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-rw-r--r--dts/Bindings/mfd/aspeed-lpc.txt2
-rw-r--r--dts/Bindings/mfd/cirrus,lochnagar.txt68
-rw-r--r--dts/Bindings/mfd/rohm,bd71837-pmic.txt17
-rw-r--r--dts/Bindings/mfd/st,stpmic1.txt61
-rw-r--r--dts/Bindings/mfd/stmpe.txt28
5 files changed, 169 insertions, 7 deletions
diff --git a/dts/Bindings/mfd/aspeed-lpc.txt b/dts/Bindings/mfd/aspeed-lpc.txt
index 34dd890..8644607 100644
--- a/dts/Bindings/mfd/aspeed-lpc.txt
+++ b/dts/Bindings/mfd/aspeed-lpc.txt
@@ -135,6 +135,8 @@ Required properties:
- clocks: contains a phandle to the syscon node describing the clocks.
There should then be one cell representing the clock to use
+Optional properties:
+
- memory-region: A phandle to a reserved_memory region to be used for the LPC
to AHB mapping
diff --git a/dts/Bindings/mfd/cirrus,lochnagar.txt b/dts/Bindings/mfd/cirrus,lochnagar.txt
new file mode 100644
index 0000000..004b015
--- /dev/null
+++ b/dts/Bindings/mfd/cirrus,lochnagar.txt
@@ -0,0 +1,68 @@
+Cirrus Logic Lochnagar Audio Development Board
+
+Lochnagar is an evaluation and development board for Cirrus Logic
+Smart CODEC and Amp devices. It allows the connection of most Cirrus
+Logic devices on mini-cards, as well as allowing connection of
+various application processor systems to provide a full evaluation
+platform. Audio system topology, clocking and power can all be
+controlled through the Lochnagar, allowing the device under test
+to be used in a variety of possible use cases.
+
+Also see these documents for generic binding information:
+ [1] GPIO : ../gpio/gpio.txt
+
+And these for relevant defines:
+ [2] include/dt-bindings/pinctrl/lochnagar.h
+ [3] include/dt-bindings/clock/lochnagar.h
+
+And these documents for the required sub-node binding details:
+ [4] Clock: ../clock/cirrus,lochnagar.txt
+ [5] Pinctrl: ../pinctrl/cirrus,lochnagar.txt
+ [6] Regulator: ../regulator/cirrus,lochnagar.txt
+
+Required properties:
+
+ - compatible : One of the following strings:
+ "cirrus,lochnagar1"
+ "cirrus,lochnagar2"
+
+ - reg : I2C slave address
+
+ - reset-gpios : Reset line to the Lochnagar, see [1].
+
+Required sub-nodes:
+
+ - lochnagar-clk : Binding for the clocking components, see [4].
+
+ - lochnagar-pinctrl : Binding for the pin control components, see [5].
+
+Optional sub-nodes:
+
+ - Bindings for the regulator components, see [6]. Only available on
+ Lochnagar 2.
+
+Optional properties:
+
+ - present-gpios : Host present line, indicating the presence of a
+ host system, see [1]. This can be omitted if the present line is
+ tied in hardware.
+
+Example:
+
+lochnagar: lochnagar@22 {
+ compatible = "cirrus,lochnagar2";
+ reg = <0x22>;
+
+ reset-gpios = <&gpio0 55 0>;
+ present-gpios = <&gpio0 60 0>;
+
+ lochnagar-clk {
+ compatible = "cirrus,lochnagar2-clk";
+ ...
+ };
+
+ lochnagar-pinctrl {
+ compatible = "cirrus,lochnagar-pinctrl";
+ ...
+ };
+};
diff --git a/dts/Bindings/mfd/rohm,bd71837-pmic.txt b/dts/Bindings/mfd/rohm,bd71837-pmic.txt
index a4b0567..d5f68ac 100644
--- a/dts/Bindings/mfd/rohm,bd71837-pmic.txt
+++ b/dts/Bindings/mfd/rohm,bd71837-pmic.txt
@@ -23,6 +23,20 @@ Required properties:
Optional properties:
- clock-output-names : Should contain name for output clock.
+- rohm,reset-snvs-powered : Transfer BD718x7 to SNVS state at reset.
+
+The BD718x7 supports two different HW states as reset target states. States
+are called as SNVS and READY. At READY state all the PMIC power outputs go
+down and OTP is reload. At the SNVS state all other logic and external
+devices apart from the SNVS power domain are shut off. Please refer to NXP
+i.MX8 documentation for further information regarding SNVS state. When a
+reset is done via SNVS state the PMIC OTP data is not reload. This causes
+power outputs that have been under SW control to stay down when reset has
+switched power state to SNVS. If reset is done via READY state the power
+outputs will be returned to HW control by OTP loading. Thus the reset
+target state is set to READY by default. If SNVS state is used the boot
+crucial regulators must have the regulator-always-on and regulator-boot-on
+properties set in regulator node.
Example:
@@ -43,6 +57,7 @@ Example:
#clock-cells = <0>;
clocks = <&osc 0>;
clock-output-names = "bd71837-32k-out";
+ rohm,reset-snvs-powered;
regulators {
buck1: BUCK1 {
@@ -50,8 +65,10 @@ Example:
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
+ regulator-always-on;
regulator-ramp-delay = <1250>;
};
+ // [...]
};
};
diff --git a/dts/Bindings/mfd/st,stpmic1.txt b/dts/Bindings/mfd/st,stpmic1.txt
new file mode 100644
index 0000000..afd45c0
--- /dev/null
+++ b/dts/Bindings/mfd/st,stpmic1.txt
@@ -0,0 +1,61 @@
+* STMicroelectronics STPMIC1 Power Management IC
+
+Required properties:
+- compatible: : "st,stpmic1"
+- reg: : The I2C slave address for the STPMIC1 chip.
+- interrupts: : The interrupt line the device is connected to.
+- #interrupt-cells: : Should be 1.
+- interrupt-controller: : Marks the device node as an interrupt controller.
+ Interrupt numbers are defined at
+ dt-bindings/mfd/st,stpmic1.h.
+
+STPMIC1 consists in a varied group of sub-devices.
+Each sub-device binding is be described in own documentation file.
+
+Device Description
+------ ------------
+st,stpmic1-onkey : Power on key, see ../input/st,stpmic1-onkey.txt
+st,stpmic1-regulators : Regulators, see ../regulator/st,stpmic1-regulator.txt
+st,stpmic1-wdt : Watchdog, see ../watchdog/st,stpmic1-wdt.txt
+
+Example:
+
+#include <dt-bindings/mfd/st,stpmic1.h>
+
+pmic: pmic@33 {
+ compatible = "st,stpmic1";
+ reg = <0x33>;
+ interrupt-parent = <&gpioa>;
+ interrupts = <0 2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ onkey {
+ compatible = "st,stpmic1-onkey";
+ interrupts = <IT_PONKEY_F 0>,<IT_PONKEY_R 1>;
+ interrupt-names = "onkey-falling", "onkey-rising";
+ power-off-time-sec = <10>;
+ };
+
+ watchdog {
+ compatible = "st,stpmic1-wdt";
+ };
+
+ regulators {
+ compatible = "st,stpmic1-regulators";
+
+ vdd_core: buck1 {
+ regulator-name = "vdd_core";
+ regulator-boot-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ vdd: buck3 {
+ regulator-name = "vdd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-pull-down;
+ };
+ };
diff --git a/dts/Bindings/mfd/stmpe.txt b/dts/Bindings/mfd/stmpe.txt
index c797c05..d4408a4 100644
--- a/dts/Bindings/mfd/stmpe.txt
+++ b/dts/Bindings/mfd/stmpe.txt
@@ -4,15 +4,29 @@ STMPE is an MFD device which may expose the following inbuilt devices: gpio,
keypad, touchscreen, adc, pwm, rotator.
Required properties:
- - compatible : "st,stmpe[610|801|811|1600|1601|2401|2403]"
- - reg : I2C/SPI address of the device
+ - compatible : "st,stmpe[610|801|811|1600|1601|2401|2403]"
+ - reg : I2C/SPI address of the device
Optional properties:
- - interrupts : The interrupt outputs from the controller
- - interrupt-controller : Marks the device node as an interrupt controller
- - wakeup-source : Marks the input device as wakable
- - st,autosleep-timeout : Valid entries (ms); 4, 16, 32, 64, 128, 256, 512 and 1024
- - irq-gpio : If present, which GPIO to use for event IRQ
+ - interrupts : The interrupt outputs from the controller
+ - interrupt-controller : Marks the device node as an interrupt controller
+ - wakeup-source : Marks the input device as wakable
+ - st,autosleep-timeout : Valid entries (ms); 4, 16, 32, 64, 128, 256, 512 and 1024
+ - irq-gpio : If present, which GPIO to use for event IRQ
+
+Optional properties for devices with touch and ADC (STMPE811|STMPE610):
+ - st,sample-time : ADC conversion time in number of clock.
+ 0 -> 36 clocks 4 -> 80 clocks (recommended)
+ 1 -> 44 clocks 5 -> 96 clocks
+ 2 -> 56 clocks 6 -> 124 clocks
+ 3 -> 64 clocks
+ - st,mod-12b : ADC Bit mode
+ 0 -> 10bit ADC 1 -> 12bit ADC
+ - st,ref-sel : ADC reference source
+ 0 -> internal 1 -> external
+ - st,adc-freq : ADC Clock speed
+ 0 -> 1.625 MHz 2 || 3 -> 6.5 MHz
+ 1 -> 3.25 MHz
Example: