diff options
Diffstat (limited to 'dts/Bindings/mfd')
25 files changed, 1585 insertions, 590 deletions
diff --git a/dts/Bindings/mfd/ac100.txt b/dts/Bindings/mfd/ac100.txt deleted file mode 100644 index dff219f074..0000000000 --- a/dts/Bindings/mfd/ac100.txt +++ /dev/null @@ -1,50 +0,0 @@ -X-Powers AC100 Codec/RTC IC Device Tree bindings - -AC100 is a audio codec and RTC subsystem combo IC. The 2 parts are -separated, including power supplies and interrupt lines, but share -a common register address space and host interface. - -Required properties: -- compatible: "x-powers,ac100" -- reg: The I2C slave address or RSB hardware address for the chip -- sub-nodes: - - codec - - compatible: "x-powers,ac100-codec" - - interrupts: SoC NMI / GPIO interrupt connected to the - IRQ_AUDIO pin - - #clock-cells: Shall be 0 - - clock-output-names: "4M_adda" - - - see clock/clock-bindings.txt for common clock bindings - - - rtc - - compatible: "x-powers,ac100-rtc" - - clocks: A phandle to the codec's "4M_adda" clock - - #clock-cells: Shall be 1 - - clock-output-names: "cko1_rtc", "cko2_rtc", "cko3_rtc" - - - see clock/clock-bindings.txt for common clock bindings - -Example: - -ac100: codec@e89 { - compatible = "x-powers,ac100"; - reg = <0xe89>; - - ac100_codec: codec { - compatible = "x-powers,ac100-codec"; - interrupt-parent = <&r_pio>; - interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */ - #clock-cells = <0>; - clock-output-names = "4M_adda"; - }; - - ac100_rtc: rtc { - compatible = "x-powers,ac100-rtc"; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - clocks = <&ac100_codec>; - #clock-cells = <1>; - clock-output-names = "cko1_rtc", "cko2_rtc", "cko3_rtc"; - }; -}; diff --git a/dts/Bindings/mfd/aspeed-lpc.txt b/dts/Bindings/mfd/aspeed-lpc.txt deleted file mode 100644 index 936aa108ea..0000000000 --- a/dts/Bindings/mfd/aspeed-lpc.txt +++ /dev/null @@ -1,157 +0,0 @@ -====================================================================== -Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller -====================================================================== - -The LPC bus is a means to bridge a host CPU to a number of low-bandwidth -peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The -primary use case of the Aspeed LPC controller is as a slave on the bus -(typically in a Baseboard Management Controller SoC), but under certain -conditions it can also take the role of bus master. - -The LPC controller is represented as a multi-function device to account for the -mix of functionality, which includes, but is not limited to: - -* An IPMI Block Transfer[2] Controller - -* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the - physical properties of some LPC pins, configuration of serial IRQs, and - APB-to-LPC bridging amonst other functions. - -* An LPC Host Interface Controller: Manages functions exposed to the host such - as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART - management and bus snoop configuration. - -* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom - hardware management protocols for handover between the host and baseboard - management controller. - -Additionally the state of the LPC controller influences the pinmux -configuration, therefore the host portion of the controller is exposed as a -syscon as a means to arbitrate access. - -[0] http://www.intel.com/design/chipsets/industry/25128901.pdf -[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4 -[2] https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf -[3] https://en.wikipedia.org/wiki/Super_I/O - -Required properties -=================== - -- compatible: One of: - "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon" - "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon" - "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon" - -- reg: contains the physical address and length values of the Aspeed - LPC memory region. - -- #address-cells: <1> -- #size-cells: <1> -- ranges: Maps 0 to the physical address and length of the LPC memory - region - -Example: - -lpc: lpc@1e789000 { - compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"; - reg = <0x1e789000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e789000 0x1000>; - - lpc_snoop: lpc-snoop@0 { - compatible = "aspeed,ast2600-lpc-snoop"; - reg = <0x0 0x80>; - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; - snoop-ports = <0x80>; - }; -}; - - -LPC Host Interface Controller -------------------- - -The LPC Host Interface Controller manages functions exposed to the host such as -LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART -management and bus snoop configuration. - -Required properties: - -- compatible: One of: - "aspeed,ast2400-lpc-ctrl"; - "aspeed,ast2500-lpc-ctrl"; - "aspeed,ast2600-lpc-ctrl"; - -- reg: contains offset/length values of the host interface controller - memory regions - -- clocks: contains a phandle to the syscon node describing the clocks. - There should then be one cell representing the clock to use - -Optional properties: - -- memory-region: A phandle to a reserved_memory region to be used for the LPC - to AHB mapping - -- flash: A phandle to the SPI flash controller containing the flash to - be exposed over the LPC to AHB mapping - -Example: - -lpc_ctrl: lpc-ctrl@80 { - compatible = "aspeed,ast2500-lpc-ctrl"; - reg = <0x80 0x80>; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - memory-region = <&flash_memory>; - flash = <&spi>; -}; - -LPC Host Controller -------------------- - -The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour -between the host and the baseboard management controller. The registers exist -in the "host" portion of the Aspeed LPC controller, which must be the parent of -the LPC host controller node. - -Required properties: - -- compatible: One of: - "aspeed,ast2400-lhc"; - "aspeed,ast2500-lhc"; - "aspeed,ast2600-lhc"; - -- reg: contains offset/length values of the LHC memory regions. In the - AST2400 and AST2500 there are two regions. - -Example: - -lhc: lhc@a0 { - compatible = "aspeed,ast2500-lhc"; - reg = <0xa0 0x24 0xc8 0x8>; -}; - -LPC reset control ------------------ - -The UARTs present in the ASPEED SoC can have their resets tied to the reset -state of the LPC bus. Some systems may chose to modify this configuration. - -Required properties: - - - compatible: One of: - "aspeed,ast2600-lpc-reset"; - "aspeed,ast2500-lpc-reset"; - "aspeed,ast2400-lpc-reset"; - - - reg: offset and length of the IP in the LHC memory region - - #reset-controller indicates the number of reset cells expected - -Example: - -lpc_reset: reset-controller@98 { - compatible = "aspeed,ast2500-lpc-reset"; - reg = <0x98 0x4>; - #reset-cells = <1>; -}; diff --git a/dts/Bindings/mfd/aspeed-lpc.yaml b/dts/Bindings/mfd/aspeed-lpc.yaml new file mode 100644 index 0000000000..750996d9a1 --- /dev/null +++ b/dts/Bindings/mfd/aspeed-lpc.yaml @@ -0,0 +1,199 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# # Copyright (c) 2021 Aspeed Tehchnology Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed Low Pin Count (LPC) Bus Controller + +maintainers: + - Andrew Jeffery <andrew@aj.id.au> + - Chia-Wei Wang <chiawei_wang@aspeedtech.com> + +description: + The LPC bus is a means to bridge a host CPU to a number of low-bandwidth + peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The + primary use case of the Aspeed LPC controller is as a slave on the bus + (typically in a Baseboard Management Controller SoC), but under certain + conditions it can also take the role of bus master. + + The LPC controller is represented as a multi-function device to account for the + mix of functionality, which includes, but is not limited to + + * An IPMI Block Transfer[2] Controller + + * An LPC Host Interface Controller manages functions exposed to the host such + as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART + management and bus snoop configuration. + + * A set of SuperIO[3] scratch registers enableing implementation of e.g. custom + hardware management protocols for handover between the host and baseboard + management controller. + + Additionally the state of the LPC controller influences the pinmux + configuration, therefore the host portion of the controller is exposed as a + syscon as a means to arbitrate access. + +properties: + compatible: + items: + - enum: + - aspeed,ast2400-lpc-v2 + - aspeed,ast2500-lpc-v2 + - aspeed,ast2600-lpc-v2 + - const: simple-mfd + - const: syscon + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +patternProperties: + "^lpc-ctrl@[0-9a-f]+$": + type: object + additionalProperties: false + + description: | + The LPC Host Interface Controller manages functions exposed to the host such as + LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management + and bus snoop configuration. + + properties: + compatible: + items: + - enum: + - aspeed,ast2400-lpc-ctrl + - aspeed,ast2500-lpc-ctrl + - aspeed,ast2600-lpc-ctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + memory-region: + maxItems: 1 + description: handle to memory reservation for the LPC to AHB mapping region + + flash: + $ref: /schemas/types.yaml#/definitions/phandle + description: The SPI flash controller containing the flash to be exposed over the LPC to AHB mapping + + required: + - compatible + - clocks + + "^reset-controller@[0-9a-f]+$": + type: object + additionalProperties: false + + description: + The UARTs present in the ASPEED SoC can have their resets tied to the reset + state of the LPC bus. Some systems may chose to modify this configuration + + properties: + compatible: + items: + - enum: + - aspeed,ast2400-lpc-reset + - aspeed,ast2500-lpc-reset + - aspeed,ast2600-lpc-reset + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + + required: + - compatible + - '#reset-cells' + + "^lpc-snoop@[0-9a-f]+$": + type: object + additionalProperties: false + + description: + The LPC snoop interface allows the BMC to listen on and record the data + bytes written by the Host to the targeted LPC I/O pots. + + properties: + compatible: + items: + - enum: + - aspeed,ast2400-lpc-snoop + - aspeed,ast2500-lpc-snoop + - aspeed,ast2600-lpc-snoop + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + snoop-ports: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: The LPC I/O ports to snoop + + required: + - compatible + - interrupts + - snoop-ports + + "^uart-routing@[0-9a-f]+$": + $ref: /schemas/soc/aspeed/uart-routing.yaml# + description: The UART routing control under LPC register space + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: + type: object + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/ast2600-clock.h> + + lpc: lpc@1e789000 { + compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"; + reg = <0x1e789000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e789000 0x1000>; + + lpc_ctrl: lpc-ctrl@80 { + compatible = "aspeed,ast2600-lpc-ctrl"; + reg = <0x80 0x80>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + memory-region = <&flash_memory>; + flash = <&spi>; + }; + + lpc_reset: reset-controller@98 { + compatible = "aspeed,ast2600-lpc-reset"; + reg = <0x98 0x4>; + #reset-cells = <1>; + }; + + lpc_snoop: lpc-snoop@90 { + compatible = "aspeed,ast2600-lpc-snoop"; + reg = <0x90 0x8>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + snoop-ports = <0x80>; + }; + }; diff --git a/dts/Bindings/mfd/axp20x.txt b/dts/Bindings/mfd/axp20x.txt deleted file mode 100644 index 2b53dcc0ea..0000000000 --- a/dts/Bindings/mfd/axp20x.txt +++ /dev/null @@ -1,273 +0,0 @@ -AXP family PMIC device tree bindings - -The axp20x family current members : -axp152 (X-Powers) -axp202 (X-Powers) -axp209 (X-Powers) -axp221 (X-Powers) -axp223 (X-Powers) -axp803 (X-Powers) -axp806 (X-Powers) -axp809 (X-Powers) -axp813 (X-Powers) - -The AXP813 is 2 chips packaged into 1. The 2 chips do not share anything -other than the packaging. Pins are routed separately. As such they should -be treated as separate entities. The other half is an AC100 RTC/codec -combo chip. Please see ./ac100.txt for its bindings. - -Required properties: -- compatible: should be one of: - * "x-powers,axp152" - * "x-powers,axp202" - * "x-powers,axp209" - * "x-powers,axp221" - * "x-powers,axp223" - * "x-powers,axp803" - * "x-powers,axp806" - * "x-powers,axp805", "x-powers,axp806" - * "x-powers,axp305", "x-powers,axp805", "x-powers,axp806" - * "x-powers,axp809" - * "x-powers,axp813" -- reg: The I2C slave address or RSB hardware address for the AXP chip -- interrupt-controller: The PMIC has its own internal IRQs -- #interrupt-cells: Should be set to 1 - -Supported common regulator properties, see ../regulator/regulator.txt for -more information: -- regulator-ramp-delay: sets the ramp up delay in uV/us - AXP20x/DCDC2: 1600, 800 - AXP20x/LDO3: 1600, 800 -- regulator-soft-start: enable the output at the lowest possible voltage and - only then set the desired voltage - AXP20x/LDO3: software-based implementation - -Optional properties: -- interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin -- x-powers,dcdc-freq: defines the work frequency of DC-DC in KHz - AXP152/20X: range: 750-1875, Default: 1.5 MHz - AXP22X/8XX: range: 1800-4050, Default: 3 MHz - -- x-powers,drive-vbus-en: boolean, set this when the N_VBUSEN pin is - used as an output pin to control an external - regulator to drive the OTG VBus, rather then - as an input pin which signals whether the - board is driving OTG VBus or not. - (axp221 / axp223 / axp803/ axp813 only) - -- x-powers,self-working-mode and - x-powers,master-mode: Boolean (axp806 only). Set either of these when the - PMIC is wired for self-working mode or master mode. - If neither is set then slave mode is assumed. - This corresponds to how the MODESET pin is wired. - -- <input>-supply: a phandle to the regulator supply node. May be omitted if - inputs are unregulated, such as using the IPSOUT output - from the PMIC. - -- regulators: A node that houses a sub-node for each regulator. Regulators - not used but preferred to be managed by the OS should be - listed as well. - See Documentation/devicetree/bindings/regulator/regulator.txt - for more information on standard regulator bindings. - -Optional properties for DCDC regulators: -- x-powers,dcdc-workmode: 1 for PWM mode, 0 for AUTO (PWM/PFM) mode - Default: Current hardware setting - The DCDC regulators work in a mixed PWM/PFM mode, - using PFM under light loads and switching to PWM - for heavier loads. Forcing PWM mode trades efficiency - under light loads for lower output noise. This - probably makes sense for HiFi audio related - applications that aren't battery constrained. - -AXP202/AXP209 regulators, type, and corresponding input supply names: - -Regulator Type Supply Name Notes ---------- ---- ----------- ----- -DCDC2 : DC-DC buck : vin2-supply -DCDC3 : DC-DC buck : vin3-supply -LDO1 : LDO : acin-supply : always on -LDO2 : LDO : ldo24in-supply : shared supply -LDO3 : LDO : ldo3in-supply -LDO4 : LDO : ldo24in-supply : shared supply -LDO5 : LDO : ldo5in-supply - -AXP221/AXP223 regulators, type, and corresponding input supply names: - -Regulator Type Supply Name Notes ---------- ---- ----------- ----- -DCDC1 : DC-DC buck : vin1-supply -DCDC2 : DC-DC buck : vin2-supply -DCDC3 : DC-DC buck : vin3-supply -DCDC4 : DC-DC buck : vin4-supply -DCDC5 : DC-DC buck : vin5-supply -DC1SW : On/Off Switch : : DCDC1 secondary output -DC5LDO : LDO : : input from DCDC5 -ALDO1 : LDO : aldoin-supply : shared supply -ALDO2 : LDO : aldoin-supply : shared supply -ALDO3 : LDO : aldoin-supply : shared supply -DLDO1 : LDO : dldoin-supply : shared supply -DLDO2 : LDO : dldoin-supply : shared supply -DLDO3 : LDO : dldoin-supply : shared supply -DLDO4 : LDO : dldoin-supply : shared supply -ELDO1 : LDO : eldoin-supply : shared supply -ELDO2 : LDO : eldoin-supply : shared supply -ELDO3 : LDO : eldoin-supply : shared supply -LDO_IO0 : LDO : ips-supply : GPIO 0 -LDO_IO1 : LDO : ips-supply : GPIO 1 -RTC_LDO : LDO : ips-supply : always on -DRIVEVBUS : Enable output : drivevbus-supply : external regulator - -AXP803 regulators, type, and corresponding input supply names: - -Regulator Type Supply Name Notes ---------- ---- ----------- ----- -DCDC1 : DC-DC buck : vin1-supply -DCDC2 : DC-DC buck : vin2-supply : poly-phase capable -DCDC3 : DC-DC buck : vin3-supply : poly-phase capable -DCDC4 : DC-DC buck : vin4-supply -DCDC5 : DC-DC buck : vin5-supply : poly-phase capable -DCDC6 : DC-DC buck : vin6-supply : poly-phase capable -DC1SW : On/Off Switch : : DCDC1 secondary output -ALDO1 : LDO : aldoin-supply : shared supply -ALDO2 : LDO : aldoin-supply : shared supply -ALDO3 : LDO : aldoin-supply : shared supply -DLDO1 : LDO : dldoin-supply : shared supply -DLDO2 : LDO : dldoin-supply : shared supply -DLDO3 : LDO : dldoin-supply : shared supply -DLDO4 : LDO : dldoin-supply : shared supply -ELDO1 : LDO : eldoin-supply : shared supply -ELDO2 : LDO : eldoin-supply : shared supply -ELDO3 : LDO : eldoin-supply : shared supply -FLDO1 : LDO : fldoin-supply : shared supply -FLDO2 : LDO : fldoin-supply : shared supply -LDO_IO0 : LDO : ips-supply : GPIO 0 -LDO_IO1 : LDO : ips-supply : GPIO 1 -RTC_LDO : LDO : ips-supply : always on -DRIVEVBUS : Enable output : drivevbus-supply : external regulator - -AXP806 regulators, type, and corresponding input supply names: - -Regulator Type Supply Name Notes ---------- ---- ----------- ----- -DCDCA : DC-DC buck : vina-supply : poly-phase capable -DCDCB : DC-DC buck : vinb-supply : poly-phase capable -DCDCC : DC-DC buck : vinc-supply : poly-phase capable -DCDCD : DC-DC buck : vind-supply : poly-phase capable -DCDCE : DC-DC buck : vine-supply : poly-phase capable -ALDO1 : LDO : aldoin-supply : shared supply -ALDO2 : LDO : aldoin-supply : shared supply -ALDO3 : LDO : aldoin-supply : shared supply -BLDO1 : LDO : bldoin-supply : shared supply -BLDO2 : LDO : bldoin-supply : shared supply -BLDO3 : LDO : bldoin-supply : shared supply -BLDO4 : LDO : bldoin-supply : shared supply -CLDO1 : LDO : cldoin-supply : shared supply -CLDO2 : LDO : cldoin-supply : shared supply -CLDO3 : LDO : cldoin-supply : shared supply -SW : On/Off Switch : swin-supply - -Additionally, the AXP806 DC-DC regulators support poly-phase arrangements -for higher output current. The possible groupings are: A+B, A+B+C, D+E. - -AXP809 regulators, type, and corresponding input supply names: - -Regulator Type Supply Name Notes ---------- ---- ----------- ----- -DCDC1 : DC-DC buck : vin1-supply -DCDC2 : DC-DC buck : vin2-supply -DCDC3 : DC-DC buck : vin3-supply -DCDC4 : DC-DC buck : vin4-supply -DCDC5 : DC-DC buck : vin5-supply -DC1SW : On/Off Switch : : DCDC1 secondary output -DC5LDO : LDO : : input from DCDC5 -ALDO1 : LDO : aldoin-supply : shared supply -ALDO2 : LDO : aldoin-supply : shared supply -ALDO3 : LDO : aldoin-supply : shared supply -DLDO1 : LDO : dldoin-supply : shared supply -DLDO2 : LDO : dldoin-supply : shared supply -ELDO1 : LDO : eldoin-supply : shared supply -ELDO2 : LDO : eldoin-supply : shared supply -ELDO3 : LDO : eldoin-supply : shared supply -LDO_IO0 : LDO : ips-supply : GPIO 0 -LDO_IO1 : LDO : ips-supply : GPIO 1 -RTC_LDO : LDO : ips-supply : always on -SW : On/Off Switch : swin-supply - -AXP813 regulators, type, and corresponding input supply names: - -Regulator Type Supply Name Notes ---------- ---- ----------- ----- -DCDC1 : DC-DC buck : vin1-supply -DCDC2 : DC-DC buck : vin2-supply : poly-phase capable -DCDC3 : DC-DC buck : vin3-supply : poly-phase capable -DCDC4 : DC-DC buck : vin4-supply -DCDC5 : DC-DC buck : vin5-supply : poly-phase capable -DCDC6 : DC-DC buck : vin6-supply : poly-phase capable -DCDC7 : DC-DC buck : vin7-supply -ALDO1 : LDO : aldoin-supply : shared supply -ALDO2 : LDO : aldoin-supply : shared supply -ALDO3 : LDO : aldoin-supply : shared supply -DLDO1 : LDO : dldoin-supply : shared supply -DLDO2 : LDO : dldoin-supply : shared supply -DLDO3 : LDO : dldoin-supply : shared supply -DLDO4 : LDO : dldoin-supply : shared supply -ELDO1 : LDO : eldoin-supply : shared supply -ELDO2 : LDO : eldoin-supply : shared supply -ELDO3 : LDO : eldoin-supply : shared supply -FLDO1 : LDO : fldoin-supply : shared supply -FLDO2 : LDO : fldoin-supply : shared supply -FLDO3 : LDO : fldoin-supply : shared supply -LDO_IO0 : LDO : ips-supply : GPIO 0 -LDO_IO1 : LDO : ips-supply : GPIO 1 -RTC_LDO : LDO : ips-supply : always on -SW : On/Off Switch : swin-supply -DRIVEVBUS : Enable output : drivevbus-supply : external regulator - -Example: - -axp209: pmic@34 { - compatible = "x-powers,axp209"; - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - - regulators { - x-powers,dcdc-freq = <1500>; - - vdd_cpu: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1450000>; - regulator-name = "vdd-cpu"; - }; - - vdd_int_dll: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-dll"; - }; - - vdd_rtc: ldo1 { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-rtc"; - }; - - avcc: ldo2 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; - }; - - ldo3 { - /* unused but preferred to be managed by OS */ - }; - }; -}; diff --git a/dts/Bindings/mfd/brcm,cru.yaml b/dts/Bindings/mfd/brcm,cru.yaml index 28ac60acf4..be4a2df71c 100644 --- a/dts/Bindings/mfd/brcm,cru.yaml +++ b/dts/Bindings/mfd/brcm,cru.yaml @@ -36,9 +36,15 @@ patternProperties: '^clock-controller@[a-f0-9]+$': $ref: ../clock/brcm,iproc-clocks.yaml + '^phy@[a-f0-9]+$': + $ref: ../phy/bcm-ns-usb2-phy.yaml + '^pin-controller@[a-f0-9]+$': $ref: ../pinctrl/brcm,ns-pinmux.yaml + '^syscon@[a-f0-9]+$': + $ref: syscon.yaml + '^thermal@[a-f0-9]+$': $ref: ../thermal/brcm,ns-thermal.yaml @@ -49,6 +55,7 @@ required: examples: - | + #include <dt-bindings/clock/bcm-nsp.h> cru-bus@1800c100 { compatible = "brcm,ns-cru", "simple-mfd"; reg = <0x1800c100 0x1d0>; @@ -73,6 +80,20 @@ examples: "iprocfast", "sata1", "sata2"; }; + phy@164 { + compatible = "brcm,ns-usb2-phy"; + reg = <0x164 0x4>; + brcm,syscon-clkset = <&clkset>; + clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; + clock-names = "phy-ref-clk"; + #phy-cells = <0>; + }; + + clkset: syscon@180 { + compatible = "brcm,cru-clkset", "syscon"; + reg = <0x180 0x4>; + }; + pin-controller@1c0 { compatible = "brcm,bcm4708-pinmux"; reg = <0x1c0 0x24>; diff --git a/dts/Bindings/mfd/brcm,misc.yaml b/dts/Bindings/mfd/brcm,misc.yaml new file mode 100644 index 0000000000..cff7d772a7 --- /dev/null +++ b/dts/Bindings/mfd/brcm,misc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/brcm,misc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom's MISC block + +maintainers: + - Rafał Miłecki <rafal@milecki.pl> + +description: | + Broadcom's MISC is a hardware block used on some SoCs (e.g. bcm63xx and + bcm4908). It's used to implement some simple functions like a watchdog, PCIe + reset, UniMAC control and more. + +properties: + compatible: + items: + - const: brcm,misc + - const: simple-mfd + + reg: + description: MISC block registers + + ranges: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + +patternProperties: + '^reset-controller@[a-f0-9]+$': + $ref: ../reset/brcm,bcm4908-misc-pcie-reset.yaml + +additionalProperties: false + +required: + - reg + - '#address-cells' + - '#size-cells' + +examples: + - | + misc@ff802600 { + compatible = "brcm,misc", "simple-mfd"; + reg = <0xff802600 0xe4>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xe4>; + + reset-controller@44 { + compatible = "brcm,bcm4908-misc-pcie-reset"; + reg = <0x44 0x4>; + #reset-cells = <1>; + }; + }; diff --git a/dts/Bindings/mfd/max14577.txt b/dts/Bindings/mfd/max14577.txt index 92070b3467..be11943a05 100644 --- a/dts/Bindings/mfd/max14577.txt +++ b/dts/Bindings/mfd/max14577.txt @@ -71,7 +71,7 @@ max14577@25 { compatible = "maxim,max14577"; reg = <0x25>; interrupt-parent = <&gpx1>; - interrupts = <5 IRQ_TYPE_NONE>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; muic: max14577-muic { compatible = "maxim,max14577-muic"; @@ -106,7 +106,7 @@ max77836@25 { compatible = "maxim,max77836"; reg = <0x25>; interrupt-parent = <&gpx1>; - interrupts = <5 IRQ_TYPE_NONE>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; muic: max77836-muic { compatible = "maxim,max77836-muic"; diff --git a/dts/Bindings/mfd/max77686.txt b/dts/Bindings/mfd/max77686.txt index 42968b7144..4447d07489 100644 --- a/dts/Bindings/mfd/max77686.txt +++ b/dts/Bindings/mfd/max77686.txt @@ -21,6 +21,6 @@ Example: max77686: pmic@9 { compatible = "maxim,max77686"; interrupt-parent = <&wakeup_eint>; - interrupts = <26 0>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; reg = <0x09>; }; diff --git a/dts/Bindings/mfd/max77693.txt b/dts/Bindings/mfd/max77693.txt index 0ced96e16c..1032df1449 100644 --- a/dts/Bindings/mfd/max77693.txt +++ b/dts/Bindings/mfd/max77693.txt @@ -139,7 +139,7 @@ Example: compatible = "maxim,max77693"; reg = <0x66>; interrupt-parent = <&gpx1>; - interrupts = <5 2>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; regulators { esafeout@1 { diff --git a/dts/Bindings/mfd/qcom,spmi-pmic.txt b/dts/Bindings/mfd/qcom,spmi-pmic.txt index 5ef79bf3d0..7a27c500ff 100644 --- a/dts/Bindings/mfd/qcom,spmi-pmic.txt +++ b/dts/Bindings/mfd/qcom,spmi-pmic.txt @@ -15,29 +15,38 @@ each. A function can consume one or more of these fixed-size register regions. Required properties: - compatible: Should contain one of: - "qcom,pm8941", - "qcom,pm8841", - "qcom,pma8084", + "qcom,pm660", + "qcom,pm660l", + "qcom,pm7325", + "qcom,pm8004", + "qcom,pm8005", "qcom,pm8019", - "qcom,pm8226", + "qcom,pm8028", "qcom,pm8110", - "qcom,pma8084", - "qcom,pmi8962", - "qcom,pmd9635", - "qcom,pm8994", - "qcom,pmi8994", - "qcom,pm8916", - "qcom,pm8004", + "qcom,pm8150", + "qcom,pm8150b", + "qcom,pm8150c", + "qcom,pm8150l", + "qcom,pm8226", + "qcom,pm8350c", + "qcom,pm8841", + "qcom,pm8901", "qcom,pm8909", + "qcom,pm8916", + "qcom,pm8941", "qcom,pm8950", - "qcom,pmi8950", + "qcom,pm8994", "qcom,pm8998", + "qcom,pma8084", + "qcom,pmd9635", + "qcom,pmi8950", + "qcom,pmi8962", + "qcom,pmi8994", "qcom,pmi8998", - "qcom,pm8005", - "qcom,pm8350c", + "qcom,pmk8002", "qcom,pmk8350", - "qcom,pm7325", "qcom,pmr735a", + "qcom,smb2351", or generalized "qcom,spmi-pmic". - reg: Specifies the SPMI USID slave address for this device. For more information see: diff --git a/dts/Bindings/mfd/qcom,tcsr.txt b/dts/Bindings/mfd/qcom,tcsr.txt index e90519d566..c5f4f0ddfc 100644 --- a/dts/Bindings/mfd/qcom,tcsr.txt +++ b/dts/Bindings/mfd/qcom,tcsr.txt @@ -6,6 +6,7 @@ registers via syscon. Required properties: - compatible: Should contain: + "qcom,tcsr-ipq6018", "syscon", "simple-mfd" for IPQ6018 "qcom,tcsr-ipq8064", "syscon" for IPQ8064 "qcom,tcsr-apq8064", "syscon" for APQ8064 "qcom,tcsr-msm8660", "syscon" for MSM8660 diff --git a/dts/Bindings/mfd/qcom-pm8xxx.yaml b/dts/Bindings/mfd/qcom-pm8xxx.yaml index 9065ec53e6..2568736701 100644 --- a/dts/Bindings/mfd/qcom-pm8xxx.yaml +++ b/dts/Bindings/mfd/qcom-pm8xxx.yaml @@ -16,6 +16,7 @@ description: | properties: compatible: enum: + - qcom,pm8018 - qcom,pm8058 - qcom,pm8821 - qcom,pm8921 diff --git a/dts/Bindings/mfd/samsung,s2mpa01.yaml b/dts/Bindings/mfd/samsung,s2mpa01.yaml new file mode 100644 index 0000000000..017befdf8a --- /dev/null +++ b/dts/Bindings/mfd/samsung,s2mpa01.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/samsung,s2mpa01.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2MPA01 Power Management IC + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + +description: | + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + The Samsung S2MPA01 is a Power Management IC which includes voltage + and current regulators, RTC, clock outputs and other sub-blocks. + +properties: + compatible: + const: samsung,s2mpa01-pmic + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + regulators: + $ref: ../regulator/samsung,s2mpa01.yaml + description: + List of child nodes that specify the regulators. + + wakeup-source: true + +required: + - compatible + - reg + - regulators + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@66 { + compatible = "samsung,s2mpa01-pmic"; + reg = <0x66>; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "VDD_ALIVE"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo2_reg: LDO2 { + regulator-name = "VDDQ_MMC2"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + // ... + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <50000>; + }; + + // ... + }; + }; + }; diff --git a/dts/Bindings/mfd/samsung,s2mps11.yaml b/dts/Bindings/mfd/samsung,s2mps11.yaml new file mode 100644 index 0000000000..771b3f16da --- /dev/null +++ b/dts/Bindings/mfd/samsung,s2mps11.yaml @@ -0,0 +1,267 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/samsung,s2mps11.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2MPS11/13/14/15 and S2MPU02 Power Management IC + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + +description: | + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + The Samsung S2MPS11/13/14/15 and S2MPU02 is a family of Power Management IC + which include voltage and current regulators, RTC, clock outputs and other + sub-blocks. + +properties: + compatible: + enum: + - samsung,s2mps11-pmic + - samsung,s2mps13-pmic + - samsung,s2mps14-pmic + - samsung,s2mps15-pmic + - samsung,s2mpu02-pmic + + clocks: + $ref: ../clock/samsung,s2mps11.yaml + description: + Child node describing clock provider. + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + regulators: + type: object + description: + List of child nodes that specify the regulators. + + samsung,s2mps11-acokb-ground: + description: | + Indicates that ACOKB pin of S2MPS11 PMIC is connected to the ground so + the PMIC must manually set PWRHOLD bit in CTRL1 register to turn off the + power. Usually the ACOKB is pulled up to VBATT so when PWRHOLD pin goes + low, the rising ACOKB will trigger power off. + type: boolean + + samsung,s2mps11-wrstbi-ground: + description: | + Indicates that WRSTBI pin of PMIC is pulled down. When the system is + suspended it will always go down thus triggerring unwanted buck warm + reset (setting buck voltages to default values). + type: boolean + + wakeup-source: true + +required: + - compatible + - reg + - regulators + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,s2mps11-pmic + then: + properties: + regulators: + $ref: ../regulator/samsung,s2mps11.yaml + samsung,s2mps11-wrstbi-ground: false + + - if: + properties: + compatible: + contains: + const: samsung,s2mps13-pmic + then: + properties: + regulators: + $ref: ../regulator/samsung,s2mps13.yaml + samsung,s2mps11-acokb-ground: false + + - if: + properties: + compatible: + contains: + const: samsung,s2mps14-pmic + then: + properties: + regulators: + $ref: ../regulator/samsung,s2mps14.yaml + samsung,s2mps11-acokb-ground: false + samsung,s2mps11-wrstbi-ground: false + + - if: + properties: + compatible: + contains: + const: samsung,s2mps15-pmic + then: + properties: + regulators: + $ref: ../regulator/samsung,s2mps15.yaml + samsung,s2mps11-acokb-ground: false + samsung,s2mps11-wrstbi-ground: false + + - if: + properties: + compatible: + contains: + const: samsung,s2mpu02-pmic + then: + properties: + regulators: + $ref: ../regulator/samsung,s2mpu02.yaml + samsung,s2mps11-acokb-ground: false + samsung,s2mps11-wrstbi-ground: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@66 { + compatible = "samsung,s2mps11-pmic"; + reg = <0x66>; + + interrupt-parent = <&gpx0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&s2mps11_irq>; + samsung,s2mps11-acokb-ground; + wakeup-source; + + clocks { + compatible = "samsung,s2mps11-clk"; + #clock-cells = <1>; + clock-output-names = "s2mps11_ap", "s2mps11_cp", "s2mps11_bt"; + }; + + regulators { + LDO1 { + regulator-name = "vdd_ldo1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + LDO4 { + regulator-name = "vdd_adc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + // .... + + BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-coupled-with = <&buck3_reg>; + regulator-coupled-max-spread = <300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + regulator-coupled-with = <&buck2_reg>; + regulator-coupled-max-spread = <300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + // ... + }; + }; + }; + + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@66 { + compatible = "samsung,s2mps14-pmic"; + reg = <0x66>; + + interrupt-parent = <&gpx0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + + clocks { + compatible = "samsung,s2mps14-clk"; + #clock-cells = <1>; + clock-output-names = "s2mps14_ap", "unused", "s2mps14_bt"; + }; + + regulators { + LDO1 { + regulator-name = "VLDO1_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + // ... + + BUCK1 { + regulator-name = "VBUCK1_1.0V"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + // ... + }; + }; + }; diff --git a/dts/Bindings/mfd/samsung,s5m8767.yaml b/dts/Bindings/mfd/samsung,s5m8767.yaml new file mode 100644 index 0000000000..5531718abd --- /dev/null +++ b/dts/Bindings/mfd/samsung,s5m8767.yaml @@ -0,0 +1,307 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/samsung,s5m8767.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S5M8767 Power Management IC + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + +description: | + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + The Samsung S5M8767 is a Power Management IC which includes voltage + and current regulators, RTC, clock outputs and other sub-blocks. + +properties: + compatible: + const: samsung,s5m8767-pmic + + clocks: + $ref: ../clock/samsung,s2mps11.yaml + description: + Child node describing clock provider. + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + regulators: + $ref: ../regulator/samsung,s5m8767.yaml + description: + List of child nodes that specify the regulators. + + s5m8767,pmic-buck2-dvs-voltage: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 8 + maxItems: 8 + description: | + A set of 8 voltage values in micro-volt (uV) units for buck2 when + changing voltage using gpio dvs. + + s5m8767,pmic-buck3-dvs-voltage: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 8 + maxItems: 8 + description: | + A set of 8 voltage values in micro-volt (uV) units for buck3 when + changing voltage using gpio dvs. + + s5m8767,pmic-buck4-dvs-voltage: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 8 + maxItems: 8 + description: | + A set of 8 voltage values in micro-volt (uV) units for buck4 when + changing voltage using gpio dvs. + + s5m8767,pmic-buck-ds-gpios: + minItems: 3 + maxItems: 3 + description: | + GPIO specifiers for three host gpio's used for selecting GPIO DVS lines. + It is one-to-one mapped to dvs gpio lines. + + s5m8767,pmic-buck2-uses-gpio-dvs: + type: boolean + description: buck2 can be controlled by gpio dvs. + + s5m8767,pmic-buck3-uses-gpio-dvs: + type: boolean + description: buck3 can be controlled by gpio dvs. + + s5m8767,pmic-buck4-uses-gpio-dvs: + type: boolean + description: buck4 can be controlled by gpio dvs. + + s5m8767,pmic-buck-default-dvs-idx: + $ref: /schemas/types.yaml#/definitions/uint32-array + minimum: 0 + maximum: 7 + default: 0 + description: | + Default voltage setting selected from the possible 8 options selectable + by the dvs gpios. The value of this property should be between 0 and 7. + If not specified or if out of range, the default value of this property + is set to 0. + + s5m8767,pmic-buck-dvs-gpios: + minItems: 3 + maxItems: 3 + description: | + GPIO specifiers for three host gpio's used for dvs. + + vinb1-supply: + description: Power supply for buck1 + vinb2-supply: + description: Power supply for buck2 + vinb3-supply: + description: Power supply for buck3 + vinb4-supply: + description: Power supply for buck4 + vinb5-supply: + description: Power supply for buck5 + vinb6-supply: + description: Power supply for buck6 + vinb7-supply: + description: Power supply for buck7 + vinb8-supply: + description: Power supply for buck8 + vinb9-supply: + description: Power supply for buck9 + + vinl1-supply: + description: Power supply for LDO3, LDO10, LDO26, LDO27 + vinl2-supply: + description: Power supply for LDO13, LDO16, LDO25, LDO28 + vinl3-supply: + description: Power supply for LDO11, LDO14 + vinl4-supply: + description: Power supply for LDO4, LDO9 + vinl5-supply: + description: Power supply for LDO12, LDO17, LDO19, LDO23 + vinl6-supply: + description: Power supply for LDO18, LDO20, LDO21, LDO24 + vinl7-supply: + description: Power supply for LDO5, LDO22 + vinl8-supply: + description: Power supply for LDO1, LDO6, LDO7, LDO8, LDO15 + vinl9-supply: + description: Power supply for LDO2 + + wakeup-source: true + +required: + - compatible + - reg + - regulators + - s5m8767,pmic-buck-ds-gpios + +dependencies: + s5m8767,pmic-buck2-dvs-voltage: [ 's5m8767,pmic-buck-dvs-gpios' ] + s5m8767,pmic-buck3-dvs-voltage: [ 's5m8767,pmic-buck-dvs-gpios' ] + s5m8767,pmic-buck4-dvs-voltage: [ 's5m8767,pmic-buck-dvs-gpios' ] + s5m8767,pmic-buck2-uses-gpio-dvs: [ 's5m8767,pmic-buck-dvs-gpios', 's5m8767,pmic-buck2-dvs-voltage' ] + s5m8767,pmic-buck3-uses-gpio-dvs: [ 's5m8767,pmic-buck-dvs-gpios', 's5m8767,pmic-buck3-dvs-voltage' ] + s5m8767,pmic-buck4-uses-gpio-dvs: [ 's5m8767,pmic-buck-dvs-gpios', 's5m8767,pmic-buck4-dvs-voltage' ] + +additionalProperties: false + +allOf: + - if: + required: + - s5m8767,pmic-buck2-uses-gpio-dvs + then: + properties: + s5m8767,pmic-buck3-uses-gpio-dvs: false + s5m8767,pmic-buck4-uses-gpio-dvs: false + + - if: + required: + - s5m8767,pmic-buck3-uses-gpio-dvs + then: + properties: + s5m8767,pmic-buck2-uses-gpio-dvs: false + s5m8767,pmic-buck4-uses-gpio-dvs: false + + - if: + required: + - s5m8767,pmic-buck4-uses-gpio-dvs + then: + properties: + s5m8767,pmic-buck2-uses-gpio-dvs: false + s5m8767,pmic-buck3-uses-gpio-dvs: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@66 { + compatible = "samsung,s5m8767-pmic"; + reg = <0x66>; + + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&s5m8767_irq &s5m8767_dvs &s5m8767_ds>; + wakeup-source; + + s5m8767,pmic-buck-default-dvs-idx = <3>; + s5m8767,pmic-buck2-uses-gpio-dvs; + + s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>, + <&gpd1 1 GPIO_ACTIVE_LOW>, + <&gpd1 2 GPIO_ACTIVE_LOW>; + + s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_LOW>, + <&gpx2 4 GPIO_ACTIVE_LOW>, + <&gpx2 5 GPIO_ACTIVE_LOW>; + + s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>, + <1250000>, <1200000>, + <1150000>, <1100000>, + <1000000>, <950000>; + + s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, + <1100000>, <1100000>, + <1000000>, <1000000>, + <1000000>, <1000000>; + + s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>; + + clocks { + compatible = "samsung,s5m8767-clk"; + #clock-cells = <1>; + clock-output-names = "en32khz_ap", "en32khz_cp", "en32khz_bt"; + }; + + regulators { + LDO1 { + regulator-name = "VDD_ALIVE"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + // ... + + BUCK1 { + regulator-name = "VDD_MIF"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + BUCK2 { + regulator-name = "VDD_ARM"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + // ... + }; + }; + }; + + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@66 { + compatible = "samsung,s5m8767-pmic"; + reg = <0x66>; + + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&s5m8767_irq &s5m8767_dvs &s5m8767_ds>; + wakeup-source; + + s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_LOW>, + <&gpx2 4 GPIO_ACTIVE_LOW>, + <&gpx2 5 GPIO_ACTIVE_LOW>; + + clocks { + compatible = "samsung,s5m8767-clk"; + #clock-cells = <1>; + clock-output-names = "en32khz_ap", "en32khz_cp", "en32khz_bt"; + }; + + regulators { + LDO1 { + regulator-name = "VDD_ALIVE"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; /* Normal Mode */ + }; + + // ... + }; + }; + }; diff --git a/dts/Bindings/mfd/samsung,sec-core.txt b/dts/Bindings/mfd/samsung,sec-core.txt deleted file mode 100644 index c68cdd3651..0000000000 --- a/dts/Bindings/mfd/samsung,sec-core.txt +++ /dev/null @@ -1,86 +0,0 @@ -Binding for Samsung S2M and S5M family multi-function device -============================================================ - -This is a part of device tree bindings for S2M and S5M family multi-function -devices. - -The Samsung S2MPA01, S2MPS11/13/14/15, S2MPU02 and S5M8767 is a family -of multi-function devices which include voltage and current regulators, RTC, -charger controller, clock outputs and other sub-blocks. It is interfaced -to the host controller using an I2C interface. Each sub-block is usually -addressed by the host system using different I2C slave addresses. - - -This document describes bindings for main device node. Optional sub-blocks -must be a sub-nodes to it. Bindings for them can be found in: - - bindings/regulator/samsung,s2mpa01.txt - - bindings/regulator/samsung,s2mps11.txt - - bindings/regulator/samsung,s5m8767.txt - - bindings/clock/samsung,s2mps11.txt - - -Required properties: - - compatible: Should be one of the following - - "samsung,s2mpa01-pmic", - - "samsung,s2mps11-pmic", - - "samsung,s2mps13-pmic", - - "samsung,s2mps14-pmic", - - "samsung,s2mps15-pmic", - - "samsung,s2mpu02-pmic", - - "samsung,s5m8767-pmic". - - reg: Specifies the I2C slave address of the pmic block. It should be 0x66. - -Optional properties: - - interrupts: Interrupt specifiers for interrupt sources. - - samsung,s2mps11-wrstbi-ground: Indicates that WRSTBI pin of PMIC is pulled - down. When the system is suspended it will always go down thus triggerring - unwanted buck warm reset (setting buck voltages to default values). - - samsung,s2mps11-acokb-ground: Indicates that ACOKB pin of S2MPS11 PMIC is - connected to the ground so the PMIC must manually set PWRHOLD bit in CTRL1 - register to turn off the power. Usually the ACOKB is pulled up to VBATT so - when PWRHOLD pin goes low, the rising ACOKB will trigger power off. - -Example: - - s2mps11_pmic@66 { - compatible = "samsung,s2mps11-pmic"; - reg = <0x66>; - - s2m_osc: clocks { - compatible = "samsung,s2mps11-clk"; - #clock-cells = <1>; - clock-output-names = "xx", "yy", "zz"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ABB_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDD_ALIVE_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <50000>; - }; - }; - }; diff --git a/dts/Bindings/mfd/st,stm32-lptimer.yaml b/dts/Bindings/mfd/st,stm32-lptimer.yaml index 8bcea8dd7d..ec7f0190f4 100644 --- a/dts/Bindings/mfd/st,stm32-lptimer.yaml +++ b/dts/Bindings/mfd/st,stm32-lptimer.yaml @@ -17,7 +17,7 @@ description: | - simple counter from IN1 input signal. maintainers: - - Fabrice Gasnier <fabrice.gasnier@st.com> + - Fabrice Gasnier <fabrice.gasnier@foss.st.com> properties: compatible: diff --git a/dts/Bindings/mfd/st,stm32-timers.yaml b/dts/Bindings/mfd/st,stm32-timers.yaml index dace35362a..10b330d429 100644 --- a/dts/Bindings/mfd/st,stm32-timers.yaml +++ b/dts/Bindings/mfd/st,stm32-timers.yaml @@ -17,8 +17,7 @@ description: | programmable prescaler. maintainers: - - Benjamin Gaignard <benjamin.gaignard@st.com> - - Fabrice Gasnier <fabrice.gasnier@st.com> + - Fabrice Gasnier <fabrice.gasnier@foss.st.com> properties: compatible: diff --git a/dts/Bindings/mfd/st,stmfx.yaml b/dts/Bindings/mfd/st,stmfx.yaml index 19e9afb385..b2a4e4aa7f 100644 --- a/dts/Bindings/mfd/st,stmfx.yaml +++ b/dts/Bindings/mfd/st,stmfx.yaml @@ -12,7 +12,7 @@ description: ST Multi-Function eXpander (STMFX) is a slave controller using I2C through VDD) and resistive touchscreen controller. maintainers: - - Amelie Delaunay <amelie.delaunay@st.com> + - Amelie Delaunay <amelie.delaunay@foss.st.com> properties: compatible: diff --git a/dts/Bindings/mfd/st,stpmic1.yaml b/dts/Bindings/mfd/st,stpmic1.yaml index 305123e74a..426658ad81 100644 --- a/dts/Bindings/mfd/st,stpmic1.yaml +++ b/dts/Bindings/mfd/st,stpmic1.yaml @@ -9,7 +9,7 @@ title: STMicroelectonics STPMIC1 Power Management IC bindings description: STMicroelectronics STPMIC1 Power Management IC maintainers: - - pascal Paillet <p.paillet@st.com> + - pascal Paillet <p.paillet@foss.st.com> properties: compatible: diff --git a/dts/Bindings/mfd/syscon.yaml b/dts/Bindings/mfd/syscon.yaml index abe3fd817e..5de16388a0 100644 --- a/dts/Bindings/mfd/syscon.yaml +++ b/dts/Bindings/mfd/syscon.yaml @@ -38,6 +38,7 @@ properties: - allwinner,sun8i-h3-system-controller - allwinner,sun8i-v3s-system-controller - allwinner,sun50i-a64-system-controller + - brcm,cru-clkset - hisilicon,dsa-subctrl - hisilicon,hi6220-sramctrl - hisilicon,pcie-sas-subctrl @@ -49,12 +50,14 @@ properties: - rockchip,rk3066-qos - rockchip,rk3228-qos - rockchip,rk3288-qos + - rockchip,rk3368-qos - rockchip,rk3399-qos - rockchip,rk3568-qos - samsung,exynos3-sysreg - samsung,exynos4-sysreg - samsung,exynos5-sysreg - samsung,exynos5433-sysreg + - samsung,exynosautov9-sysreg - const: syscon diff --git a/dts/Bindings/mfd/ti,am3359-tscadc.yaml b/dts/Bindings/mfd/ti,am3359-tscadc.yaml new file mode 100644 index 0000000000..34bf6a0143 --- /dev/null +++ b/dts/Bindings/mfd/ti,am3359-tscadc.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/ti,am3359-tscadc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI AM3359 Touchscreen controller/ADC + +maintainers: + - Miquel Raynal <miquel.raynal@bootlin.com> + +properties: + compatible: + oneOf: + - const: ti,am3359-tscadc + - items: + - const: ti,am654-tscadc + - const: ti,am3359-tscadc + - const: ti,am4372-magadc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: fck + + dmas: + items: + - description: DMA controller phandle and request line for FIFO0 + - description: DMA controller phandle and request line for FIFO1 + + dma-names: + items: + - const: fifo0 + - const: fifo1 + + adc: + type: object + description: ADC child + + tsc: + type: object + description: Touchscreen controller child + + mag: + type: object + description: Magnetic reader + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - dmas + - dma-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tscadc@0 { + compatible = "ti,am3359-tscadc"; + reg = <0x0 0x1000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&adc_tsc_fck>; + clock-names = "fck"; + dmas = <&edma 53 0>, <&edma 57 0>; + dma-names = "fifo0", "fifo1"; + + tsc { + }; + + adc { + }; + }; diff --git a/dts/Bindings/mfd/x-powers,ac100.yaml b/dts/Bindings/mfd/x-powers,ac100.yaml new file mode 100644 index 0000000000..de330c9869 --- /dev/null +++ b/dts/Bindings/mfd/x-powers,ac100.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/mfd/x-powers,ac100.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: X-Powers AC100 Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + +properties: + compatible: + const: x-powers,ac100 + + reg: + maxItems: 1 + + codec: + type: object + + properties: + "#clock-cells": + const: 0 + + compatible: + const: x-powers,ac100-codec + + interrupts: + maxItems: 1 + + clock-output-names: + maxItems: 1 + description: > + Name of the 4M_adda clock exposed by the codec + + required: + - "#clock-cells" + - compatible + - interrupts + - clock-output-names + + additionalProperties: false + + rtc: + type: object + + properties: + "#clock-cells": + const: 1 + + compatible: + const: x-powers,ac100-rtc + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: > + A phandle to the codec's "4M_adda" clock + + clock-output-names: + maxItems: 3 + description: > + Name of the cko1, cko2 and cko3 clocks exposed by the codec + + required: + - "#clock-cells" + - compatible + - interrupts + - clocks + - clock-output-names + + additionalProperties: false + +required: + - compatible + - reg + - codec + - rtc + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + rsb { + #address-cells = <1>; + #size-cells = <0>; + + codec@e89 { + compatible = "x-powers,ac100"; + reg = <0xe89>; + + ac100_codec: codec { + compatible = "x-powers,ac100-codec"; + interrupt-parent = <&r_pio>; + interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */ + #clock-cells = <0>; + clock-output-names = "4M_adda"; + }; + + ac100_rtc: rtc { + compatible = "x-powers,ac100-rtc"; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + clocks = <&ac100_codec>; + #clock-cells = <1>; + clock-output-names = "cko1_rtc", "cko2_rtc", "cko3_rtc"; + }; + }; + }; + +... diff --git a/dts/Bindings/mfd/x-powers,axp152.yaml b/dts/Bindings/mfd/x-powers,axp152.yaml new file mode 100644 index 0000000000..3a53bae611 --- /dev/null +++ b/dts/Bindings/mfd/x-powers,axp152.yaml @@ -0,0 +1,400 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/x-powers,axp152.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: X-Powers AXP PMIC Device Tree Bindings + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + +allOf: + - if: + properties: + compatible: + contains: + enum: + - x-powers,axp152 + - x-powers,axp202 + - x-powers,axp209 + + then: + properties: + regulators: + properties: + x-powers,dcdc-freq: + minimum: 750 + maximum: 1875 + default: 1500 + + else: + properties: + regulators: + properties: + x-powers,dcdc-freq: + minimum: 1800 + maximum: 4050 + default: 3000 + + - if: + properties: + compatible: + contains: + enum: + - x-powers,axp152 + - x-powers,axp202 + - x-powers,axp209 + + then: + not: + required: + - x-powers,drive-vbus-en + + - if: + not: + properties: + compatible: + contains: + const: x-powers,axp806 + + then: + allOf: + - not: + required: + - x-powers,self-working-mode + + - not: + required: + - x-powers,master-mode + + - if: + not: + properties: + compatible: + contains: + const: x-powers,axp305 + + then: + required: + - interrupts + +properties: + compatible: + oneOf: + - enum: + - x-powers,axp152 + - x-powers,axp202 + - x-powers,axp209 + - x-powers,axp221 + - x-powers,axp223 + - x-powers,axp803 + - x-powers,axp806 + - x-powers,axp809 + - x-powers,axp813 + - items: + - const: x-powers,axp805 + - const: x-powers,axp806 + - items: + - const: x-powers,axp305 + - const: x-powers,axp805 + - const: x-powers,axp806 + - items: + - const: x-powers,axp818 + - const: x-powers,axp813 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + + x-powers,drive-vbus-en: + type: boolean + description: > + Set this when the N_VBUSEN pin is used as an output pin to control an + external regulator to drive the OTG VBus, rather then as an input pin + which signals whether the board is driving OTG VBus or not. + + x-powers,self-working-mode: + type: boolean + description: > + Set this when the PMIC is wired for self-working mode through the MODESET + pin. + + x-powers,master-mode: + type: boolean + description: > + Set this when the PMIC is wired for master mode through the MODESET pin. + + vin1-supply: + description: > + DCDC1 power supply node, if present. + + vin2-supply: + description: > + DCDC2 power supply node, if present. + + vin3-supply: + description: > + DCDC3 power supply node, if present. + + vin4-supply: + description: > + DCDC4 power supply node, if present. + + vin5-supply: + description: > + DCDC5 power supply node, if present. + + vin6-supply: + description: > + DCDC6 power supply node, if present. + + vin7-supply: + description: > + DCDC7 power supply node, if present. + + vina-supply: + description: > + DCDCA power supply node, if present. + + vinb-supply: + description: > + DCDCB power supply node, if present. + + vinc-supply: + description: > + DCDCC power supply node, if present. + + vind-supply: + description: > + DCDCD power supply node, if present. + + vine-supply: + description: > + DCDCE power supply node, if present. + + acin-supply: + description: > + LDO1 power supply node, if present. + + ldo24in-supply: + description: > + LDO2 and LDO4 power supply node, if present. + + ldo3in-supply: + description: > + LDO3 power supply node, if present. + + ldo5in-supply: + description: > + LDO5 power supply node, if present. + + aldoin-supply: + description: > + ALDO* power supply node, if present. + + bldoin-supply: + description: > + BLDO* power supply node, if present. + + cldoin-supply: + description: > + CLDO* power supply node, if present. + + dldoin-supply: + description: > + DLDO* power supply node, if present. + + eldoin-supply: + description: > + ELDO* power supply node, if present. + + fldoin-supply: + description: > + FLDO* power supply node, if present. + + ips-supply: + description: > + LDO_IO0, LDO_IO1 and RTC_LDO power supply node, if present. + + drivevbus-supply: + description: > + DRIVEVBUS power supply node, if present. + + swin-supply: + description: > + SW power supply node, if present. + + adc: + $ref: /schemas/iio/adc/x-powers,axp209-adc.yaml# + + gpio: + $ref: /schemas/gpio/x-powers,axp209-gpio.yaml# + + ac-power: + $ref: /schemas/power/supply/x-powers,axp20x-ac-power-supply.yaml# + + battery-power: + $ref: /schemas/power/supply/x-powers,axp20x-battery-power-supply.yaml# + + usb-power: + $ref: /schemas/power/supply/x-powers,axp20x-usb-power-supply.yaml# + + regulators: + type: object + + properties: + x-powers,dcdc-freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + Defines the work frequency of DC-DC in kHz. + + patternProperties: + "^(([a-f])?ldo[0-9]|dcdc[0-7a-e]|ldo(_|-)io(0|1)|(dc1)?sw|rtc(_|-)ldo|drivevbus|dc5ldo)$": + $ref: /schemas/regulator/regulator.yaml# + type: object + + properties: + regulator-ramp-delay: + description: > + Only 800 and 1600 are valid for the DCDC2 and LDO3 regulators on + the AXP209. + + regulator-soft-start: + description: > + Only valid for the LDO3 regulator. + + x-powers,dcdc-workmode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: > + Only valid for DCDC regulators. Setup 1 for PWM mode, 0 + for AUTO (PWM/PFM) mode. The DCDC regulators work in a + mixed PWM/PFM mode, using PFM under light loads and + switching to PWM for heavier loads. Forcing PWM mode + trades efficiency under light loads for lower output + noise. This probably makes sense for HiFi audio related + applications that aren't battery constrained. + + additionalProperties: false + +required: + - compatible + - reg + - "#interrupt-cells" + - interrupt-controller + +additionalProperties: false + +examples: + - | + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + pmic@30 { + compatible = "x-powers,axp152"; + reg = <0x30>; + interrupts = <0>; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + + ac_power_supply: ac-power { + compatible = "x-powers,axp202-ac-power-supply"; + }; + + axp_adc: adc { + compatible = "x-powers,axp209-adc"; + #io-channel-cells = <1>; + }; + + axp_gpio: gpio { + compatible = "x-powers,axp209-gpio"; + gpio-controller; + #gpio-cells = <2>; + + gpio0-adc-pin { + pins = "GPIO0"; + function = "adc"; + }; + }; + + battery_power_supply: battery-power { + compatible = "x-powers,axp209-battery-power-supply"; + }; + + regulators { + /* Default work frequency for buck regulators */ + x-powers,dcdc-freq = <1500>; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; + }; + + reg_ldo1: ldo1 { + /* LDO1 is a fixed output regulator */ + regulator-always-on; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-rtc"; + }; + + reg_ldo2: ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; + }; + + reg_ldo3: ldo3 { + regulator-name = "ldo3"; + }; + + reg_ldo4: ldo4 { + regulator-name = "ldo4"; + }; + + reg_ldo5: ldo5 { + regulator-name = "ldo5"; + }; + }; + + usb_power_supply: usb-power { + compatible = "x-powers,axp202-usb-power-supply"; + }; + }; + }; diff --git a/dts/Bindings/mfd/xylon,logicvc.yaml b/dts/Bindings/mfd/xylon,logicvc.yaml index 8a1a6625c7..9efd49c39b 100644 --- a/dts/Bindings/mfd/xylon,logicvc.yaml +++ b/dts/Bindings/mfd/xylon,logicvc.yaml @@ -46,6 +46,9 @@ patternProperties: "^gpio@[0-9a-f]+$": $ref: /schemas/gpio/xylon,logicvc-gpio.yaml# + "^display@[0-9a-f]+$": + $ref: /schemas/display/xylon,logicvc-display.yaml# + required: - compatible - reg |