diff options
Diffstat (limited to 'dts/Bindings/mfd')
-rw-r--r-- | dts/Bindings/mfd/aspeed-lpc.txt | 8 | ||||
-rw-r--r-- | dts/Bindings/mfd/aspeed-scu.txt | 26 | ||||
-rw-r--r-- | dts/Bindings/mfd/rohm,bd71837-pmic.yaml | 6 | ||||
-rw-r--r-- | dts/Bindings/mfd/st,stm32-timers.yaml | 6 | ||||
-rw-r--r-- | dts/Bindings/mfd/st,stmfx.yaml | 3 | ||||
-rw-r--r-- | dts/Bindings/mfd/syscon.yaml | 4 |
6 files changed, 47 insertions, 6 deletions
diff --git a/dts/Bindings/mfd/aspeed-lpc.txt b/dts/Bindings/mfd/aspeed-lpc.txt index a92acf1dd4..d0a38ba8b9 100644 --- a/dts/Bindings/mfd/aspeed-lpc.txt +++ b/dts/Bindings/mfd/aspeed-lpc.txt @@ -46,6 +46,7 @@ Required properties - compatible: One of: "aspeed,ast2400-lpc", "simple-mfd" "aspeed,ast2500-lpc", "simple-mfd" + "aspeed,ast2600-lpc", "simple-mfd" - reg: contains the physical address and length values of the Aspeed LPC memory region. @@ -64,6 +65,7 @@ BMC Node - compatible: One of: "aspeed,ast2400-lpc-bmc" "aspeed,ast2500-lpc-bmc" + "aspeed,ast2600-lpc-bmc" - reg: contains the physical address and length values of the H8S/2168-compatible LPC controller memory region @@ -74,6 +76,7 @@ Host Node - compatible: One of: "aspeed,ast2400-lpc-host", "simple-mfd", "syscon" "aspeed,ast2500-lpc-host", "simple-mfd", "syscon" + "aspeed,ast2600-lpc-host", "simple-mfd", "syscon" - reg: contains the address and length values of the host-related register space for the Aspeed LPC controller @@ -128,6 +131,7 @@ Required properties: - compatible: One of: "aspeed,ast2400-lpc-ctrl"; "aspeed,ast2500-lpc-ctrl"; + "aspeed,ast2600-lpc-ctrl"; - reg: contains offset/length values of the host interface controller memory regions @@ -168,6 +172,7 @@ Required properties: - compatible: One of: "aspeed,ast2400-lhc"; "aspeed,ast2500-lhc"; + "aspeed,ast2600-lhc"; - reg: contains offset/length values of the LHC memory regions. In the AST2400 and AST2500 there are two regions. @@ -187,7 +192,8 @@ state of the LPC bus. Some systems may chose to modify this configuration. Required properties: - - compatible: "aspeed,ast2500-lpc-reset" or + - compatible: "aspeed,ast2600-lpc-reset" or + "aspeed,ast2500-lpc-reset" "aspeed,ast2400-lpc-reset" - reg: offset and length of the IP in the LHC memory region - #reset-controller indicates the number of reset cells expected diff --git a/dts/Bindings/mfd/aspeed-scu.txt b/dts/Bindings/mfd/aspeed-scu.txt index 4d92c0bb66..857ee33f73 100644 --- a/dts/Bindings/mfd/aspeed-scu.txt +++ b/dts/Bindings/mfd/aspeed-scu.txt @@ -20,3 +20,29 @@ syscon: syscon@1e6e2000 { #clock-cells = <1>; #reset-cells = <1>; }; + +Silicon ID +----------------- + +Families have unique hardware silicon identifiers within the SoC. + +Required properties: + + - compatible: "aspeed,silicon-id" or: + "aspeed,ast2400-silicon-id" or + "aspeed,ast2500-silicon-id" or + "aspeed,ast2600-silicon-id" + + - reg: offset and length of the silicon id information + optionally, a second offset and length describes the unique chip id + + The reg should be the unique silicon id register, and + not backwards compatible one in eg. the 2600. + +Example: + + +silicon-id@7c { + compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id"; + reg = <0x7c 0x4 0x150 0x8>; +}; diff --git a/dts/Bindings/mfd/rohm,bd71837-pmic.yaml b/dts/Bindings/mfd/rohm,bd71837-pmic.yaml index 65018a019e..3bfdd33702 100644 --- a/dts/Bindings/mfd/rohm,bd71837-pmic.yaml +++ b/dts/Bindings/mfd/rohm,bd71837-pmic.yaml @@ -32,9 +32,15 @@ properties: clocks: maxItems: 1 + clock-names: + const: osc + "#clock-cells": const: 0 + clock-output-names: + const: pmic_clk + # The BD718x7 supports two different HW states as reset target states. States # are called as SNVS and READY. At READY state all the PMIC power outputs go # down and OTP is reload. At the SNVS state all other logic and external diff --git a/dts/Bindings/mfd/st,stm32-timers.yaml b/dts/Bindings/mfd/st,stm32-timers.yaml index f212fc6e16..0f16c8864a 100644 --- a/dts/Bindings/mfd/st,stm32-timers.yaml +++ b/dts/Bindings/mfd/st,stm32-timers.yaml @@ -131,7 +131,7 @@ additionalProperties: false examples: - | #include <dt-bindings/clock/stm32mp1-clks.h> - timers2: timers@40000000 { + timers2: timer@40000000 { #address-cells = <1>; #size-cells = <0>; compatible = "st,stm32-timers"; @@ -149,9 +149,9 @@ examples: #pwm-cells = <3>; st,breakinput = <0 1 5>; }; - timer@0 { + timer@1 { compatible = "st,stm32-timer-trigger"; - reg = <0>; + reg = <1>; }; counter { compatible = "st,stm32-timer-counter"; diff --git a/dts/Bindings/mfd/st,stmfx.yaml b/dts/Bindings/mfd/st,stmfx.yaml index 888ab4b5df..19e9afb385 100644 --- a/dts/Bindings/mfd/st,stmfx.yaml +++ b/dts/Bindings/mfd/st,stmfx.yaml @@ -26,8 +26,7 @@ properties: drive-open-drain: true - vdd-supply: - maxItems: 1 + vdd-supply: true pinctrl: type: object diff --git a/dts/Bindings/mfd/syscon.yaml b/dts/Bindings/mfd/syscon.yaml index 8f4764a9ed..f14ae6da00 100644 --- a/dts/Bindings/mfd/syscon.yaml +++ b/dts/Bindings/mfd/syscon.yaml @@ -44,6 +44,10 @@ properties: - hisilicon,peri-subctrl - microchip,sparx5-cpu-syscon - mstar,msc313-pmsleep + - rockchip,px30-qos + - rockchip,rk3066-qos + - rockchip,rk3288-qos + - rockchip,rk3399-qos - samsung,exynos3-sysreg - samsung,exynos4-sysreg - samsung,exynos5-sysreg |