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Diffstat (limited to 'dts/Bindings/mips/cavium/ciu2.txt')
| -rw-r--r-- | dts/Bindings/mips/cavium/ciu2.txt | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/dts/Bindings/mips/cavium/ciu2.txt b/dts/Bindings/mips/cavium/ciu2.txt new file mode 100644 index 0000000000..0ec7ba8bbb --- /dev/null +++ b/dts/Bindings/mips/cavium/ciu2.txt @@ -0,0 +1,27 @@ +* Central Interrupt Unit + +Properties: +- compatible: "cavium,octeon-6880-ciu2" + + Compatibility with 68XX SOCs. + +- interrupt-controller: This is an interrupt controller. + +- reg: The base address of the CIU's register bank. + +- #interrupt-cells: Must be <2>. The first cell is the bank within + the CIU and may have a value between 0 and 63. The second cell is + the bit within the bank and may also have a value between 0 and 63. + +Example: + interrupt-controller@1070100000000 { + compatible = "cavium,octeon-6880-ciu2"; + interrupt-controller; + /* Interrupts are specified by two parts: + * 1) Controller register (0..63) + * 2) Bit within the register (0..63) + */ + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x10701 0x00000000 0x0 0x4000000>; + }; |