diff options
Diffstat (limited to 'dts/Bindings/mips')
| -rw-r--r-- | dts/Bindings/mips/brcm/bcm3384-intc.txt | 37 | ||||
| -rw-r--r-- | dts/Bindings/mips/brcm/bmips.txt | 8 | ||||
| -rw-r--r-- | dts/Bindings/mips/brcm/cm-dsl.txt | 11 | ||||
| -rw-r--r-- | dts/Bindings/mips/brcm/usb.txt | 11 | ||||
| -rw-r--r-- | dts/Bindings/mips/cpu_irq.txt | 4 |
5 files changed, 69 insertions, 2 deletions
diff --git a/dts/Bindings/mips/brcm/bcm3384-intc.txt b/dts/Bindings/mips/brcm/bcm3384-intc.txt new file mode 100644 index 0000000000..d4e0141d36 --- /dev/null +++ b/dts/Bindings/mips/brcm/bcm3384-intc.txt @@ -0,0 +1,37 @@ +* Interrupt Controller + +Properties: +- compatible: "brcm,bcm3384-intc" + + Compatibility with BCM3384 and possibly other BCM33xx/BCM63xx SoCs. + +- reg: Address/length pairs for each mask/status register set. Length must + be 8. If multiple register sets are specified, the first set will + handle IRQ offsets 0..31, the second set 32..63, and so on. + +- interrupt-controller: This is an interrupt controller. + +- #interrupt-cells: Must be <1>. Just a simple IRQ offset; no level/edge + or polarity configuration is possible with this controller. + +- interrupt-parent: This controller is cascaded from a MIPS CPU HW IRQ, or + from another INTC. + +- interrupts: The IRQ on the parent controller. + +Example: + periph_intc: periph_intc@14e00038 { + compatible = "brcm,bcm3384-intc"; + + /* + * IRQs 0..31: mask reg 0x14e00038, status reg 0x14e0003c + * IRQs 32..63: mask reg 0x14e00340, status reg 0x14e00344 + */ + reg = <0x14e00038 0x8 0x14e00340 0x8>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <4>; + }; diff --git a/dts/Bindings/mips/brcm/bmips.txt b/dts/Bindings/mips/brcm/bmips.txt new file mode 100644 index 0000000000..8ef71b4085 --- /dev/null +++ b/dts/Bindings/mips/brcm/bmips.txt @@ -0,0 +1,8 @@ +* Broadcom MIPS (BMIPS) CPUs + +Required properties: +- compatible: "brcm,bmips3300", "brcm,bmips4350", "brcm,bmips4380", + "brcm,bmips5000" + +- mips-hpt-frequency: This is common to all CPUs in the system so it lives + under the "cpus" node. diff --git a/dts/Bindings/mips/brcm/cm-dsl.txt b/dts/Bindings/mips/brcm/cm-dsl.txt new file mode 100644 index 0000000000..8a139cb3c0 --- /dev/null +++ b/dts/Bindings/mips/brcm/cm-dsl.txt @@ -0,0 +1,11 @@ +* Broadcom cable/DSL platforms + +SoCs: + +Required properties: +- compatible: "brcm,bcm3384", "brcm,bcm33843" + +Boards: + +Required properties: +- compatible: "brcm,bcm93384wvg" diff --git a/dts/Bindings/mips/brcm/usb.txt b/dts/Bindings/mips/brcm/usb.txt new file mode 100644 index 0000000000..452c45c7bf --- /dev/null +++ b/dts/Bindings/mips/brcm/usb.txt @@ -0,0 +1,11 @@ +* Broadcom USB controllers + +Required properties: +- compatible: "brcm,bcm3384-ohci", "brcm,bcm3384-ehci" + + These currently use the generic-ohci and generic-ehci drivers. On some + systems, special handling may be needed in the following cases: + + - Restoring state after systemwide power save modes + - Sharing PHYs with the USBD (UDC) hardware + - Figuring out which controllers are disabled on ASIC bondout variants diff --git a/dts/Bindings/mips/cpu_irq.txt b/dts/Bindings/mips/cpu_irq.txt index 13aa4b62c6..fc149f326d 100644 --- a/dts/Bindings/mips/cpu_irq.txt +++ b/dts/Bindings/mips/cpu_irq.txt @@ -1,6 +1,6 @@ MIPS CPU interrupt controller -On MIPS the mips_cpu_intc_init() helper can be used to initialize the 8 CPU +On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU IRQs from a devicetree file and create a irq_domain for IRQ controller. With the irq_domain in place we can describe how the 8 IRQs are wired to the @@ -36,7 +36,7 @@ Example devicetree: Example platform irq.c: static struct of_device_id __initdata of_irq_ids[] = { - { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init }, + { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init }, { .compatible = "ralink,rt2880-intc", .data = intc_of_init }, {}, }; |