diff options
Diffstat (limited to 'dts/Bindings/mmc/synopsys-dw-mshc.yaml')
| -rw-r--r-- | dts/Bindings/mmc/synopsys-dw-mshc.yaml | 43 |
1 files changed, 38 insertions, 5 deletions
diff --git a/dts/Bindings/mmc/synopsys-dw-mshc.yaml b/dts/Bindings/mmc/synopsys-dw-mshc.yaml index 240abb6f10..a6292777e3 100644 --- a/dts/Bindings/mmc/synopsys-dw-mshc.yaml +++ b/dts/Bindings/mmc/synopsys-dw-mshc.yaml @@ -4,10 +4,7 @@ $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Synopsys Designware Mobile Storage Host Controller Binding - -allOf: - - $ref: "synopsys-dw-mshc-common.yaml#" +title: Synopsys Designware Mobile Storage Host Controller maintainers: - Ulf Hansson <ulf.hansson@linaro.org> @@ -15,7 +12,10 @@ maintainers: # Everything else is described in the common file properties: compatible: - const: snps,dw-mshc + enum: + - altr,socfpga-dw-mshc + - img,pistachio-dw-mshc + - snps,dw-mshc reg: maxItems: 1 @@ -35,6 +35,39 @@ properties: - const: biu - const: ciu + iommus: + maxItems: 1 + + altr,sysmgr-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the sysmgr node + - description: register offset that controls the SDMMC clock phase + - description: register shift for the smplsel(drive in) setting + description: + This property is optional. Contains the phandle to System Manager block + that contains the SDMMC clock-phase control register. The first value is + the pointer to the sysmgr, the 2nd value is the register offset for the + SDMMC clock phase register, and the 3rd value is the bit shift for the + smplsel(drive in) setting. + +allOf: + - $ref: synopsys-dw-mshc-common.yaml# + + - if: + properties: + compatible: + contains: + const: altr,socfpga-dw-mshc + then: + properties: + altr,sysmgr-syscon: true + else: + properties: + iommus: false + altr,sysmgr-syscon: false + required: - compatible - reg |