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-rw-r--r--dts/Bindings/mmc/arasan,sdhci.txt3
-rw-r--r--dts/Bindings/mmc/fsl-imx-esdhc.txt9
-rw-r--r--dts/Bindings/mmc/k3-dw-mshc.txt28
-rw-r--r--dts/Bindings/mmc/mmc-pwrseq-simple.txt4
-rw-r--r--dts/Bindings/mmc/mmc.txt5
-rw-r--r--dts/Bindings/mmc/mtk-sd.txt32
-rw-r--r--dts/Bindings/mmc/renesas,mmcif.txt3
7 files changed, 81 insertions, 3 deletions
diff --git a/dts/Bindings/mmc/arasan,sdhci.txt b/dts/Bindings/mmc/arasan,sdhci.txt
index 98ee2abbe1..7e9490313d 100644
--- a/dts/Bindings/mmc/arasan,sdhci.txt
+++ b/dts/Bindings/mmc/arasan,sdhci.txt
@@ -8,7 +8,8 @@ Device Tree Bindings for the Arasan SDHCI Controller
[3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
Required Properties:
- - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a'
+ - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or
+ 'arasan,sdhci-4.9a'
- reg: From mmc bindings: Register location and length.
- clocks: From clock bindings: Handles to clock inputs.
- clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
diff --git a/dts/Bindings/mmc/fsl-imx-esdhc.txt b/dts/Bindings/mmc/fsl-imx-esdhc.txt
index 415c5575cb..5d0376b8f2 100644
--- a/dts/Bindings/mmc/fsl-imx-esdhc.txt
+++ b/dts/Bindings/mmc/fsl-imx-esdhc.txt
@@ -7,7 +7,14 @@ This file documents differences between the core properties described
by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
Required properties:
-- compatible : Should be "fsl,<chip>-esdhc"
+- compatible : Should be "fsl,<chip>-esdhc", the supported chips include
+ "fsl,imx25-esdhc"
+ "fsl,imx35-esdhc"
+ "fsl,imx51-esdhc"
+ "fsl,imx53-esdhc"
+ "fsl,imx6q-usdhc"
+ "fsl,imx6sl-usdhc"
+ "fsl,imx6sx-usdhc"
Optional properties:
- fsl,cd-controller : Indicate to use controller internal card detection
diff --git a/dts/Bindings/mmc/k3-dw-mshc.txt b/dts/Bindings/mmc/k3-dw-mshc.txt
index 3b35449314..df370585cb 100644
--- a/dts/Bindings/mmc/k3-dw-mshc.txt
+++ b/dts/Bindings/mmc/k3-dw-mshc.txt
@@ -13,6 +13,10 @@ Required Properties:
* compatible: should be one of the following.
- "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
+ - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
+
+Optional Properties:
+- hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
Example:
@@ -42,3 +46,27 @@ Example:
cap-mmc-highspeed;
cap-sd-highspeed;
};
+
+ /* for Hi6220 */
+
+ dwmmc_1: dwmmc1@f723e000 {
+ compatible = "hisilicon,hi6220-dw-mshc";
+ num-slots = <0x1>;
+ bus-width = <0x4>;
+ disable-wp;
+ cap-sd-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ card-detect-delay = <200>;
+ hisilicon,peripheral-syscon = <&ao_ctrl>;
+ reg = <0x0 0xf723e000 0x0 0x1000>;
+ interrupts = <0x0 0x49 0x4>;
+ clocks = <&clock_sys HI6220_MMC1_CIUCLK>, <&clock_sys HI6220_MMC1_CLK>;
+ clock-names = "ciu", "biu";
+ cd-gpios = <&gpio1 0 1>;
+ pinctrl-names = "default", "idle";
+ pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
+ pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
+ vqmmc-supply = <&ldo7>;
+ vmmc-supply = <&ldo10>;
+ };
diff --git a/dts/Bindings/mmc/mmc-pwrseq-simple.txt b/dts/Bindings/mmc/mmc-pwrseq-simple.txt
index a462c50f19..ce0e767496 100644
--- a/dts/Bindings/mmc/mmc-pwrseq-simple.txt
+++ b/dts/Bindings/mmc/mmc-pwrseq-simple.txt
@@ -21,5 +21,7 @@ Example:
sdhci0_pwrseq {
compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio1 12 0>;
+ reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+ clocks = <&clk_32768_ck>;
+ clock-names = "ext_clock";
}
diff --git a/dts/Bindings/mmc/mmc.txt b/dts/Bindings/mmc/mmc.txt
index 438899e882..0384fc3f64 100644
--- a/dts/Bindings/mmc/mmc.txt
+++ b/dts/Bindings/mmc/mmc.txt
@@ -21,6 +21,11 @@ Optional properties:
below for the case, when a GPIO is used for the CD line
- wp-inverted: when present, polarity on the WP line is inverted. See the note
below for the case, when a GPIO is used for the WP line
+- disable-wp: When set no physical WP line is present. This property should
+ only be specified when the controller has a dedicated write-protect
+ detection logic. If a GPIO is always used for the write-protect detection
+ logic it is sufficient to not specify wp-gpios property in the absence of a WP
+ line.
- max-frequency: maximum operating clock frequency
- no-1-8-v: when present, denotes that 1.8v card voltage is not supported on
this system, even if the controller claims it is.
diff --git a/dts/Bindings/mmc/mtk-sd.txt b/dts/Bindings/mmc/mtk-sd.txt
new file mode 100644
index 0000000000..a1adfa495a
--- /dev/null
+++ b/dts/Bindings/mmc/mtk-sd.txt
@@ -0,0 +1,32 @@
+* MTK MMC controller
+
+The MTK MSDC can act as a MMC controller
+to support MMC, SD, and SDIO types of memory cards.
+
+This file documents differences between the core properties in mmc.txt
+and the properties used by the msdc driver.
+
+Required properties:
+- compatible: Should be "mediatek,mt8173-mmc","mediatek,mt8135-mmc"
+- interrupts: Should contain MSDC interrupt number
+- clocks: MSDC source clock, HCLK
+- clock-names: "source", "hclk"
+- pinctrl-names: should be "default", "state_uhs"
+- pinctrl-0: should contain default/high speed pin ctrl
+- pinctrl-1: should contain uhs mode pin ctrl
+- vmmc-supply: power to the Core
+- vqmmc-supply: power to the IO
+
+Examples:
+mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc";
+ reg = <0 0x11230000 0 0x108>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
+ vmmc-supply = <&mt6397_vemc_3v3_reg>;
+ vqmmc-supply = <&mt6397_vio18_reg>;
+ clocks = <&pericfg CLK_PERI_MSDC30_0>, <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
+ clock-names = "source", "hclk";
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_default>;
+ pinctrl-1 = <&mmc0_pins_uhs>;
+};
diff --git a/dts/Bindings/mmc/renesas,mmcif.txt b/dts/Bindings/mmc/renesas,mmcif.txt
index 299081f94a..d38942f6c5 100644
--- a/dts/Bindings/mmc/renesas,mmcif.txt
+++ b/dts/Bindings/mmc/renesas,mmcif.txt
@@ -18,6 +18,8 @@ Required properties:
dma-names property.
- dma-names: must contain "tx" for the transmit DMA channel and "rx" for the
receive DMA channel.
+- max-frequency: Maximum operating clock frequency, driver uses default clock
+ frequency if it is not set.
Example: R8A7790 (R-Car H2) MMCIF0
@@ -29,4 +31,5 @@ Example: R8A7790 (R-Car H2) MMCIF0
clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
dma-names = "tx", "rx";
+ max-frequency = <97500000>;
};