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-rw-r--r--dts/Bindings/mtd/jedec,spi-nor.yaml60
1 files changed, 36 insertions, 24 deletions
diff --git a/dts/Bindings/mtd/jedec,spi-nor.yaml b/dts/Bindings/mtd/jedec,spi-nor.yaml
index ed590d7c6e..58f0cea160 100644
--- a/dts/Bindings/mtd/jedec,spi-nor.yaml
+++ b/dts/Bindings/mtd/jedec,spi-nor.yaml
@@ -10,7 +10,8 @@ maintainers:
- Rob Herring <robh@kernel.org>
allOf:
- - $ref: "mtd.yaml#"
+ - $ref: mtd.yaml#
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
properties:
compatible:
@@ -42,15 +43,14 @@ properties:
- const: jedec,spi-nor
- const: jedec,spi-nor
description:
- Must also include "jedec,spi-nor" for any SPI NOR flash that can be
- identified by the JEDEC READ ID opcode (0x9F).
+ SPI NOR flashes compatible with the JEDEC SFDP standard or which may be
+ identified with the READ ID opcode (0x9F) do not deserve a specific
+ compatible. They should instead only be matched against the generic
+ "jedec,spi-nor" compatible.
reg:
- maxItems: 1
-
- spi-max-frequency: true
- spi-rx-bus-width: true
- spi-tx-bus-width: true
+ minItems: 1
+ maxItems: 2
m25p,fast-read:
type: boolean
@@ -72,37 +72,49 @@ properties:
be used on such systems, to denote the absence of a reliable reset
mechanism.
- label: true
-
- partitions:
- type: object
-
- '#address-cells': true
- '#size-cells': true
+ no-wp:
+ type: boolean
+ description:
+ The status register write disable (SRWD) bit in status register, combined
+ with the WP# signal, provides hardware data protection for the device. When
+ the SRWD bit is set to 1, and the WP# signal is either driven LOW or hard
+ strapped to LOW, the status register nonvolatile bits become read-only and
+ the WRITE STATUS REGISTER operation will not execute. The only way to exit
+ this hardware-protected mode is to drive WP# HIGH. If the WP# signal of the
+ flash device is not connected or is wrongly tied to GND (that includes internal
+ pull-downs) then status register permanently becomes read-only as the SRWD bit
+ cannot be reset. This boolean flag can be used on such systems to avoid setting
+ the SRWD bit while writing the status register. WP# signal hard strapped to GND
+ can be a valid use case.
+
+ reset-gpios:
+ description:
+ A GPIO line connected to the RESET (active low) signal of the device.
+ If "broken-flash-reset" is present then having this property does not
+ make any difference.
-patternProperties:
- # Note: use 'partitions' node for new users
- '^partition@':
- type: object
+ spi-cpol: true
+ spi-cpha: true
- "^otp(-[0-9]+)?$":
- type: object
+dependencies:
+ spi-cpol: [ spi-cpha ]
+ spi-cpha: [ spi-cpol ]
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
+ #include <dt-bindings/gpio/gpio.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
compatible = "spansion,m25p80", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
m25p,fast-read;
+ reset-gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
};
};
...