diff options
Diffstat (limited to 'dts/Bindings/mtd/nand-controller.yaml')
-rw-r--r-- | dts/Bindings/mtd/nand-controller.yaml | 73 |
1 files changed, 16 insertions, 57 deletions
diff --git a/dts/Bindings/mtd/nand-controller.yaml b/dts/Bindings/mtd/nand-controller.yaml index bd217e6f50..359a015d4e 100644 --- a/dts/Bindings/mtd/nand-controller.yaml +++ b/dts/Bindings/mtd/nand-controller.yaml @@ -39,8 +39,6 @@ properties: ranges: true cs-gpios: - minItems: 1 - maxItems: 8 description: Array of chip-select available to the controller. The first entries are a 1:1 mapping of the available chip-select on the @@ -48,51 +46,27 @@ properties: chip-select as needed may follow and should be phandles of GPIO lines. 'reg' entries of the NAND chip subnodes become indexes of this array when this property is present. + minItems: 1 + maxItems: 8 patternProperties: "^nand@[a-f0-9]$": type: object + $ref: "nand-chip.yaml#" + properties: reg: description: - Contains the native Ready/Busy IDs. - - nand-ecc-engine: - allOf: - - $ref: /schemas/types.yaml#/definitions/phandle - description: | - A phandle on the hardware ECC engine if any. There are - basically three possibilities: - 1/ The ECC engine is part of the NAND controller, in this - case the phandle should reference the parent node. - 2/ The ECC engine is part of the NAND part (on-die), in this - case the phandle should reference the node itself. - 3/ The ECC engine is external, in this case the phandle should - reference the specific ECC engine node. - - nand-use-soft-ecc-engine: - type: boolean - description: Use a software ECC engine. - - nand-no-ecc-engine: - type: boolean - description: Do not use any ECC correction. + Contains the chip-select IDs. nand-ecc-placement: - allOf: - - $ref: /schemas/types.yaml#/definitions/string - - enum: [ oob, interleaved ] description: Location of the ECC bytes. This location is unknown by default but can be explicitly set to "oob", if all ECC bytes are known to be stored in the OOB area, or "interleaved" if ECC bytes will be interleaved with regular data in the main area. - - nand-ecc-algo: - description: - Desired ECC algorithm. $ref: /schemas/types.yaml#/definitions/string - enum: [hamming, bch, rs] + enum: [ oob, interleaved ] nand-bus-width: description: @@ -102,7 +76,6 @@ patternProperties: default: 8 nand-on-flash-bbt: - $ref: /schemas/types.yaml#/definitions/flag description: With this property, the OS will search the device for a Bad Block Table (BBT). If not found, it will create one, reserve @@ -111,21 +84,9 @@ patternProperties: few pages of all the blocks will be scanned at boot time to find Bad Block Markers (BBM). These markers will help to build a volatile BBT in RAM. - - nand-ecc-strength: - description: - Maximum number of bits that can be corrected per ECC step. - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 1 - - nand-ecc-step-size: - description: - Number of data bytes covered by a single ECC step. - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 1 + $ref: /schemas/types.yaml#/definitions/flag nand-ecc-maximize: - $ref: /schemas/types.yaml#/definitions/flag description: Whether or not the ECC strength should be maximized. The maximum ECC strength is both controller and chip @@ -134,18 +95,19 @@ patternProperties: constraint into account. This is particularly useful when only the in-band area is used by the upper layers, and you want to make your NAND as reliable as possible. + $ref: /schemas/types.yaml#/definitions/flag nand-is-boot-medium: - $ref: /schemas/types.yaml#/definitions/flag description: Whether or not the NAND chip is a boot medium. Drivers might use this information to select ECC algorithms supported by the boot ROM or similar restrictions. + $ref: /schemas/types.yaml#/definitions/flag nand-rb: - $ref: /schemas/types.yaml#/definitions/uint32-array description: Contains the native Ready/Busy IDs. + $ref: /schemas/types.yaml#/definitions/uint32-array rb-gpios: description: @@ -154,12 +116,12 @@ patternProperties: Ready/Busy pins. Active state refers to the NAND ready state and should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted. - secure-regions: - $ref: /schemas/types.yaml#/definitions/uint64-matrix + wp-gpios: description: - Regions in the NAND chip which are protected using a secure element - like Trustzone. This property contains the start address and size of - the secure regions present. + Contains one GPIO descriptor for the Write Protect pin. + Active state refers to the NAND Write Protect state and should be + set to GPIOD_ACTIVE_LOW unless the signal is inverted. + maxItems: 1 required: - reg @@ -181,10 +143,7 @@ examples: nand@0 { reg = <0>; /* Native CS */ - nand-use-soft-ecc-engine; - nand-ecc-algo = "bch"; - - /* controller specific properties */ + /* NAND chip specific properties */ }; nand@1 { |