diff options
Diffstat (limited to 'dts/Bindings/mtd')
| -rw-r--r-- | dts/Bindings/mtd/brcm,brcmnand.txt | 1 | ||||
| -rw-r--r-- | dts/Bindings/mtd/denali-nand.txt | 5 | ||||
| -rw-r--r-- | dts/Bindings/mtd/gpmc-nand.txt | 1 | ||||
| -rw-r--r-- | dts/Bindings/mtd/jedec,spi-nor.txt | 9 | ||||
| -rw-r--r-- | dts/Bindings/mtd/nand.txt | 6 | ||||
| -rw-r--r-- | dts/Bindings/mtd/nvidia-tegra20-nand.txt | 64 | ||||
| -rw-r--r-- | dts/Bindings/mtd/partition.txt | 46 | ||||
| -rw-r--r-- | dts/Bindings/mtd/partitions/brcm,trx.txt | 37 | ||||
| -rw-r--r-- | dts/Bindings/mtd/qcom_nandc.txt | 7 | ||||
| -rw-r--r-- | dts/Bindings/mtd/spear_smi.txt | 2 | ||||
| -rw-r--r-- | dts/Bindings/mtd/spi-nand.txt | 5 |
11 files changed, 174 insertions, 9 deletions
diff --git a/dts/Bindings/mtd/brcm,brcmnand.txt b/dts/Bindings/mtd/brcm,brcmnand.txt index b40f3a4928..bcda1dfc4b 100644 --- a/dts/Bindings/mtd/brcm,brcmnand.txt +++ b/dts/Bindings/mtd/brcm,brcmnand.txt @@ -42,7 +42,6 @@ Required properties: May be "nand", if the SoC has the individual NAND interrupts multiplexed behind another custom piece of hardware -- interrupt-parent : See standard interrupt bindings - #address-cells : <1> - subnodes give the chip-select number - #size-cells : <0> diff --git a/dts/Bindings/mtd/denali-nand.txt b/dts/Bindings/mtd/denali-nand.txt index 0ee8edb60e..f33da87827 100644 --- a/dts/Bindings/mtd/denali-nand.txt +++ b/dts/Bindings/mtd/denali-nand.txt @@ -8,6 +8,9 @@ Required properties: - reg : should contain registers location and length for data and reg. - reg-names: Should contain the reg names "nand_data" and "denali_reg" - interrupts : The interrupt number. + - clocks: should contain phandle of the controller core clock, the bus + interface clock, and the ECC circuit clock. + - clock-names: should contain "nand", "nand_x", "ecc" Optional properties: - nand-ecc-step-size: see nand.txt for details. If present, the value must be @@ -31,5 +34,7 @@ nand: nand@ff900000 { compatible = "altr,socfpga-denali-nand"; reg = <0xff900000 0x20>, <0xffb80000 0x1000>; reg-names = "nand_data", "denali_reg"; + clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; + clock-names = "nand", "nand_x", "ecc"; interrupts = <0 144 4>; }; diff --git a/dts/Bindings/mtd/gpmc-nand.txt b/dts/Bindings/mtd/gpmc-nand.txt index dd55904559..c059ab74ed 100644 --- a/dts/Bindings/mtd/gpmc-nand.txt +++ b/dts/Bindings/mtd/gpmc-nand.txt @@ -16,7 +16,6 @@ Required properties: - compatible: "ti,omap2-nand" - reg: range id (CS number), base offset and length of the NAND I/O space - - interrupt-parent: must point to gpmc node - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount. Optional properties: diff --git a/dts/Bindings/mtd/jedec,spi-nor.txt b/dts/Bindings/mtd/jedec,spi-nor.txt index 956bb046e5..f03be904d3 100644 --- a/dts/Bindings/mtd/jedec,spi-nor.txt +++ b/dts/Bindings/mtd/jedec,spi-nor.txt @@ -69,6 +69,15 @@ Optional properties: all chips and support for it can not be detected at runtime. Refer to your chips' datasheet to check if this is supported by your chip. +- broken-flash-reset : Some flash devices utilize stateful addressing modes + (e.g., for 32-bit addressing) which need to be managed + carefully by a system. Because these sorts of flash don't + have a standardized software reset command, and because some + systems don't toggle the flash RESET# pin upon system reset + (if the pin even exists at all), there are systems which + cannot reboot properly if the flash is left in the "wrong" + state. This boolean flag can be used on such systems, to + denote the absence of a reliable reset mechanism. Example: diff --git a/dts/Bindings/mtd/nand.txt b/dts/Bindings/mtd/nand.txt index 8bb11d8094..e949c778e9 100644 --- a/dts/Bindings/mtd/nand.txt +++ b/dts/Bindings/mtd/nand.txt @@ -25,7 +25,7 @@ Optional NAND chip properties: Deprecated values: "soft_bch": use "soft" and nand-ecc-algo instead - nand-ecc-algo: string, algorithm of NAND ECC. - Supported values are: "hamming", "bch". + Valid values are: "hamming", "bch", "rs". - nand-bus-width : 8 or 16 bus width if not present 8 - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false @@ -43,6 +43,10 @@ Optional NAND chip properties: This is particularly useful when only the in-band area is used by the upper layers, and you want to make your NAND as reliable as possible. +- nand-is-boot-medium: Whether the NAND chip is a boot medium. Drivers might use + this information to select ECC algorithms supported by + the boot ROM or similar restrictions. + - nand-rb: shall contain the native Ready/Busy ids. The ECC strength and ECC step size properties define the correction capability diff --git a/dts/Bindings/mtd/nvidia-tegra20-nand.txt b/dts/Bindings/mtd/nvidia-tegra20-nand.txt new file mode 100644 index 0000000000..b2f2ca12f9 --- /dev/null +++ b/dts/Bindings/mtd/nvidia-tegra20-nand.txt @@ -0,0 +1,64 @@ +NVIDIA Tegra NAND Flash controller + +Required properties: +- compatible: Must be one of: + - "nvidia,tegra20-nand" +- reg: MMIO address range +- interrupts: interrupt output of the NFC controller +- clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - nand +- resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names: Must include the following entries: + - nand + +Optional children nodes: +Individual NAND chips are children of the NAND controller node. Currently +only one NAND chip supported. + +Required children node properties: +- reg: An integer ranging from 1 to 6 representing the CS line to use. + +Optional children node properties: +- nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only + "hw" is supported. +- nand-ecc-algo: string, algorithm of NAND ECC. + Supported values with "hw" ECC mode are: "rs", "bch". +- nand-bus-width : See nand.txt +- nand-on-flash-bbt: See nand.txt +- nand-ecc-strength: integer representing the number of bits to correct + per ECC step (always 512). Supported strength using HW ECC + modes are: + - RS: 4, 6, 8 + - BCH: 4, 8, 14, 16 +- nand-ecc-maximize: See nand.txt +- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM + are chosen. +- wp-gpios: GPIO specifier for the write protect pin. + +Optional child node of NAND chip nodes: +Partitions: see partition.txt + + Example: + nand-controller@70008000 { + compatible = "nvidia,tegra20-nand"; + reg = <0x70008000 0x100>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; + clock-names = "nand"; + resets = <&tegra_car 13>; + reset-names = "nand"; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-bus-width = <8>; + nand-on-flash-bbt; + nand-ecc-algo = "bch"; + nand-ecc-strength = <8>; + wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; + }; + }; diff --git a/dts/Bindings/mtd/partition.txt b/dts/Bindings/mtd/partition.txt index a8f382642b..afbbd87049 100644 --- a/dts/Bindings/mtd/partition.txt +++ b/dts/Bindings/mtd/partition.txt @@ -14,6 +14,13 @@ method is used for a given flash device. To describe the method there should be a subnode of the flash device that is named 'partitions'. It must have a 'compatible' property, which is used to identify the method to use. +When a single partition is represented with a DT node (it depends on a used +format) it may also be described using above rules ('compatible' and optionally +some extra properties / subnodes). It allows describing more complex, +hierarchical (multi-level) layouts and should be used if there is some +significant relation between partitions or some partition internally uses +another partitioning method. + Available bindings are listed in the "partitions" subdirectory. @@ -109,3 +116,42 @@ flash@2 { }; }; }; + +flash@3 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootloader"; + reg = <0x000000 0x100000>; + read-only; + }; + + firmware@100000 { + label = "firmware"; + reg = <0x100000 0xe00000>; + compatible = "brcm,trx"; + }; + + calibration@f00000 { + label = "calibration"; + reg = <0xf00000 0x100000>; + compatible = "fixed-partitions"; + ranges = <0 0xf00000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "wifi0"; + reg = <0x000000 0x080000>; + }; + + partition@80000 { + label = "wifi1"; + reg = <0x080000 0x080000>; + }; + }; + }; +}; diff --git a/dts/Bindings/mtd/partitions/brcm,trx.txt b/dts/Bindings/mtd/partitions/brcm,trx.txt new file mode 100644 index 0000000000..b677147ca4 --- /dev/null +++ b/dts/Bindings/mtd/partitions/brcm,trx.txt @@ -0,0 +1,37 @@ +Broadcom TRX Container Partition +================================ + +TRX is Broadcom's official firmware format for the BCM947xx boards. It's used by +most of the vendors building devices based on Broadcom's BCM47xx SoCs and is +supported by the CFE bootloader. + +Design of the TRX format is very minimalistic. Its header contains +identification fields, CRC32 checksum and the locations of embedded partitions. +Its purpose is to store a few partitions in a format that can be distributed as +a standalone file and written in a flash memory. + +Container can hold up to 4 partitions. The first partition has to contain a +device executable binary (e.g. a kernel) as it's what the CFE bootloader starts +executing. Other partitions can be used for operating system purposes. This is +useful for systems that keep kernel and rootfs separated. + +TRX doesn't enforce any strict partition boundaries or size limits. All +partitions have to be less than the 4GiB max size limit. + +There are two existing/known TRX variants: +1) v1 which contains 3 partitions +2) v2 which contains 4 partitions + +There aren't separated compatible bindings for them as version can be trivialy +detected by a software parsing TRX header. + +Required properties: +- compatible : (required) must be "brcm,trx" + +Example: + +flash@0 { + partitions { + compatible = "brcm,trx"; + }; +}; diff --git a/dts/Bindings/mtd/qcom_nandc.txt b/dts/Bindings/mtd/qcom_nandc.txt index 73d336befa..1123cc6d56 100644 --- a/dts/Bindings/mtd/qcom_nandc.txt +++ b/dts/Bindings/mtd/qcom_nandc.txt @@ -45,11 +45,12 @@ Required properties: number (e.g., 0, 1, 2, etc.) - #address-cells: see partition.txt - #size-cells: see partition.txt -- nand-ecc-strength: see nand.txt -- nand-ecc-step-size: must be 512. see nand.txt for more details. Optional properties: - nand-bus-width: see nand.txt +- nand-ecc-strength: see nand.txt. If not specified, then ECC strength will + be used according to chip requirement and available + OOB size. Each nandcs device node may optionally contain a 'partitions' sub-node, which further contains sub-nodes describing the flash partition mapping. See @@ -77,7 +78,6 @@ nand-controller@1ac00000 { reg = <0>; nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; nand-bus-width = <8>; partitions { @@ -117,7 +117,6 @@ nand-controller@79b0000 { nand@0 { reg = <0>; nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; nand-bus-width = <8>; partitions { diff --git a/dts/Bindings/mtd/spear_smi.txt b/dts/Bindings/mtd/spear_smi.txt index 7248aadd89..c41873e92d 100644 --- a/dts/Bindings/mtd/spear_smi.txt +++ b/dts/Bindings/mtd/spear_smi.txt @@ -5,8 +5,6 @@ Required properties: - reg : Address range of the mtd chip - #address-cells, #size-cells : Must be present if the device has sub-nodes representing partitions. -- interrupt-parent: Should be the phandle for the interrupt controller - that services interrupts for this device - interrupts: Should contain the STMMAC interrupts - clock-rate : Functional clock rate of SMI in Hz diff --git a/dts/Bindings/mtd/spi-nand.txt b/dts/Bindings/mtd/spi-nand.txt new file mode 100644 index 0000000000..8b51f3b6d5 --- /dev/null +++ b/dts/Bindings/mtd/spi-nand.txt @@ -0,0 +1,5 @@ +SPI NAND flash + +Required properties: +- compatible: should be "spi-nand" +- reg: should encode the chip-select line used to access the NAND chip |