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-rw-r--r--dts/Bindings/mtd/allwinner,sun4i-a10-nand.yaml13
-rw-r--r--dts/Bindings/mtd/arasan,nand-controller.yaml63
-rw-r--r--dts/Bindings/mtd/brcm,brcmnand.txt2
-rw-r--r--dts/Bindings/mtd/denali,nand.yaml4
-rw-r--r--dts/Bindings/mtd/ingenic,jz4780-nand.txt92
-rw-r--r--dts/Bindings/mtd/ingenic,nand.yaml132
-rw-r--r--dts/Bindings/mtd/nand-controller.yaml27
-rw-r--r--dts/Bindings/mtd/partition.txt3
8 files changed, 219 insertions, 117 deletions
diff --git a/dts/Bindings/mtd/allwinner,sun4i-a10-nand.yaml b/dts/Bindings/mtd/allwinner,sun4i-a10-nand.yaml
index 5d3fa412aa..c033ac3f14 100644
--- a/dts/Bindings/mtd/allwinner,sun4i-a10-nand.yaml
+++ b/dts/Bindings/mtd/allwinner,sun4i-a10-nand.yaml
@@ -75,13 +75,12 @@ patternProperties:
allwinner,rb:
description:
Contains the native Ready/Busy IDs.
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32-array
- - minItems: 1
- maxItems: 2
- items:
- minimum: 0
- maximum: 1
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 1
+ maxItems: 2
+ items:
+ minimum: 0
+ maximum: 1
additionalProperties: false
diff --git a/dts/Bindings/mtd/arasan,nand-controller.yaml b/dts/Bindings/mtd/arasan,nand-controller.yaml
new file mode 100644
index 0000000000..cb9794edff
--- /dev/null
+++ b/dts/Bindings/mtd/arasan,nand-controller.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/arasan,nand-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arasan NAND Flash Controller with ONFI 3.1 support device tree bindings
+
+allOf:
+ - $ref: "nand-controller.yaml"
+
+maintainers:
+ - Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - xlnx,zynqmp-nand-controller
+ - enum:
+ - arasan,nfc-v3p10
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Controller clock
+ - description: NAND bus clock
+
+ clock-names:
+ items:
+ - const: controller
+ - const: bus
+
+ interrupts:
+ maxItems: 1
+
+ "#address-cells": true
+ "#size-cells": true
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+additionalProperties: true
+
+examples:
+ - |
+ nfc: nand-controller@ff100000 {
+ compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
+ reg = <0xff100000 0x1000>;
+ clock-names = "controller", "bus";
+ clocks = <&clk200>, <&clk100>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 14 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
diff --git a/dts/Bindings/mtd/brcm,brcmnand.txt b/dts/Bindings/mtd/brcm,brcmnand.txt
index 05651a654c..44335a4f8b 100644
--- a/dts/Bindings/mtd/brcm,brcmnand.txt
+++ b/dts/Bindings/mtd/brcm,brcmnand.txt
@@ -20,6 +20,8 @@ Required properties:
"brcm,brcmnand" and an appropriate version compatibility
string, like "brcm,brcmnand-v7.0"
Possible values:
+ brcm,brcmnand-v2.1
+ brcm,brcmnand-v2.2
brcm,brcmnand-v4.0
brcm,brcmnand-v5.0
brcm,brcmnand-v6.0
diff --git a/dts/Bindings/mtd/denali,nand.yaml b/dts/Bindings/mtd/denali,nand.yaml
index 46e6b6726b..c07b91592c 100644
--- a/dts/Bindings/mtd/denali,nand.yaml
+++ b/dts/Bindings/mtd/denali,nand.yaml
@@ -54,8 +54,8 @@ properties:
reg: register reset
oneOf:
- items:
- - const: nand
- - const: reg
+ - const: nand
+ - const: reg
- const: nand
- const: reg
diff --git a/dts/Bindings/mtd/ingenic,jz4780-nand.txt b/dts/Bindings/mtd/ingenic,jz4780-nand.txt
deleted file mode 100644
index c022593533..0000000000
--- a/dts/Bindings/mtd/ingenic,jz4780-nand.txt
+++ /dev/null
@@ -1,92 +0,0 @@
-* Ingenic JZ4780 NAND/ECC
-
-This file documents the device tree bindings for NAND flash devices on the
-JZ4780. NAND devices are connected to the NEMC controller (described in
-memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must
-be children of the NEMC node.
-
-Required NAND controller device properties:
-- compatible: Should be one of:
- * ingenic,jz4740-nand
- * ingenic,jz4725b-nand
- * ingenic,jz4780-nand
-- reg: For each bank with a NAND chip attached, should specify a bank number,
- an offset of 0 and a size of 0x1000000 (i.e. the whole NEMC bank).
-
-Optional NAND controller device properties:
-- ecc-engine: To make use of the hardware ECC controller, this
- property must contain a phandle for the ECC controller node. The required
- properties for this node are described below. If this is not specified,
- software ECC will be used instead.
-
-Optional children nodes:
-- Individual NAND chips are children of the NAND controller node.
-
-Required children node properties:
-- reg: An integer ranging from 1 to 6 representing the CS line to use.
-
-Optional children node properties:
-- nand-ecc-step-size: ECC block size in bytes.
-- nand-ecc-strength: ECC strength (max number of correctable bits).
-- nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by default
-- nand-on-flash-bbt: boolean to enable on flash bbt option, if not present false
-- rb-gpios: GPIO specifier for the busy pin.
-- wp-gpios: GPIO specifier for the write protect pin.
-
-Optional child node of NAND chip nodes:
-- partitions: see Documentation/devicetree/bindings/mtd/partition.txt
-
-Example:
-
-nemc: nemc@13410000 {
- ...
-
- nandc: nand-controller@1 {
- compatible = "ingenic,jz4780-nand";
- reg = <1 0 0x1000000>; /* Bank 1 */
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- ecc-engine = <&bch>;
-
- nand@1 {
- reg = <1>;
-
- nand-ecc-step-size = <1024>;
- nand-ecc-strength = <24>;
- nand-ecc-mode = "hw";
- nand-on-flash-bbt;
-
- rb-gpios = <&gpa 20 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpf 22 GPIO_ACTIVE_LOW>;
-
- partitions {
- #address-cells = <2>;
- #size-cells = <2>;
- ...
- }
- };
- };
-};
-
-The ECC controller is a separate SoC component used for error correction on
-NAND devices. The following is a description of the device properties for a
-ECC controller.
-
-Required ECC properties:
-- compatible: Should be one of:
- * ingenic,jz4740-ecc
- * ingenic,jz4725b-bch
- * ingenic,jz4780-bch
-- reg: Should specify the ECC controller registers location and length.
-- clocks: Clock for the ECC controller.
-
-Example:
-
-bch: bch@134d0000 {
- compatible = "ingenic,jz4780-bch";
- reg = <0x134d0000 0x10000>;
-
- clocks = <&cgu JZ4780_CLK_BCH>;
-};
diff --git a/dts/Bindings/mtd/ingenic,nand.yaml b/dts/Bindings/mtd/ingenic,nand.yaml
new file mode 100644
index 0000000000..8abb6d463c
--- /dev/null
+++ b/dts/Bindings/mtd/ingenic,nand.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/ingenic,nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ingenic SoCs NAND controller devicetree bindings
+
+maintainers:
+ - Paul Cercueil <paul@crapouillou.net>
+
+allOf:
+ - $ref: nand-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ingenic,jz4740-nand
+ - ingenic,jz4725b-nand
+ - ingenic,jz4780-nand
+
+ reg:
+ items:
+ - description: Bank number, offset and size of first attached NAND chip
+ - description: Bank number, offset and size of second attached NAND chip
+ - description: Bank number, offset and size of third attached NAND chip
+ - description: Bank number, offset and size of fourth attached NAND chip
+ minItems: 1
+
+ ecc-engine: true
+
+ partitions:
+ type: object
+ description:
+ Node containing description of fixed partitions.
+ See Documentation/devicetree/bindings/mtd/partition.txt
+
+patternProperties:
+ "^nand@[a-f0-9]$":
+ type: object
+ properties:
+ rb-gpios:
+ description: GPIO specifier for the busy pin.
+ maxItems: 1
+
+ wp-gpios:
+ description: GPIO specifier for the write-protect pin.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/clock/jz4780-cgu.h>
+ memory-controller@13410000 {
+ compatible = "ingenic,jz4780-nemc";
+ reg = <0x13410000 0x10000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0 0x1b000000 0x1000000>,
+ <2 0 0x1a000000 0x1000000>,
+ <3 0 0x19000000 0x1000000>,
+ <4 0 0x18000000 0x1000000>,
+ <5 0 0x17000000 0x1000000>,
+ <6 0 0x16000000 0x1000000>;
+
+ clocks = <&cgu JZ4780_CLK_NEMC>;
+
+ nand-controller@1 {
+ compatible = "ingenic,jz4780-nand";
+ reg = <1 0 0x1000000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ecc-engine = <&bch>;
+
+ ingenic,nemc-tAS = <10>;
+ ingenic,nemc-tAH = <5>;
+ ingenic,nemc-tBP = <10>;
+ ingenic,nemc-tAW = <15>;
+ ingenic,nemc-tSTRV = <100>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_nemc>;
+
+ nand@1 {
+ reg = <1>;
+
+ nand-ecc-step-size = <1024>;
+ nand-ecc-strength = <24>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_nemc_cs1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ partition@0 {
+ label = "u-boot-spl";
+ reg = <0x0 0x0 0x0 0x800000>;
+ };
+
+ partition@800000 {
+ label = "u-boot";
+ reg = <0x0 0x800000 0x0 0x200000>;
+ };
+
+ partition@a00000 {
+ label = "u-boot-env";
+ reg = <0x0 0xa00000 0x0 0x200000>;
+ };
+
+ partition@c00000 {
+ label = "boot";
+ reg = <0x0 0xc00000 0x0 0x4000000>;
+ };
+
+ partition@4c00000 {
+ label = "system";
+ reg = <0x0 0x4c00000 0x1 0xfb400000>;
+ };
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/mtd/nand-controller.yaml b/dts/Bindings/mtd/nand-controller.yaml
index d261b7096c..cde7c4d79e 100644
--- a/dts/Bindings/mtd/nand-controller.yaml
+++ b/dts/Bindings/mtd/nand-controller.yaml
@@ -47,29 +47,26 @@ patternProperties:
Contains the native Ready/Busy IDs.
nand-ecc-mode:
- allOf:
- - $ref: /schemas/types.yaml#/definitions/string
- - enum: [ none, soft, hw, hw_syndrome, hw_oob_first, on-die ]
description:
Desired ECC engine, either hardware (most of the time
embedded in the NAND controller) or software correction
(Linux will handle the calculations). soft_bch is deprecated
and should be replaced by soft and nand-ecc-algo.
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [none, soft, hw, hw_syndrome, hw_oob_first, on-die]
nand-ecc-algo:
- allOf:
- - $ref: /schemas/types.yaml#/definitions/string
- - enum: [ hamming, bch, rs ]
description:
Desired ECC algorithm.
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [hamming, bch, rs]
nand-bus-width:
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32
- - enum: [ 8, 16 ]
- - default: 8
description:
Bus width to the NAND chip
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [8, 16]
+ default: 8
nand-on-flash-bbt:
$ref: /schemas/types.yaml#/definitions/flag
@@ -83,18 +80,16 @@ patternProperties:
build a volatile BBT in RAM.
nand-ecc-strength:
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32
- - minimum: 1
description:
Maximum number of bits that can be corrected per ECC step.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
nand-ecc-step-size:
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32
- - minimum: 1
description:
Number of data bytes covered by a single ECC step.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
nand-ecc-maximize:
$ref: /schemas/types.yaml#/definitions/flag
diff --git a/dts/Bindings/mtd/partition.txt b/dts/Bindings/mtd/partition.txt
index afbbd87049..4a39698221 100644
--- a/dts/Bindings/mtd/partition.txt
+++ b/dts/Bindings/mtd/partition.txt
@@ -61,6 +61,9 @@ Optional properties:
clobbered.
- lock : Do not unlock the partition at initialization time (not supported on
all devices)
+- slc-mode: This parameter, if present, allows one to emulate SLC mode on a
+ partition attached to an MLC NAND thus making this partition immune to
+ paired-pages corruptions
Examples:
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-30 11:09:36 +0000