diff options
Diffstat (limited to 'dts/Bindings/net/renesas,ether.yaml')
| -rw-r--r-- | dts/Bindings/net/renesas,ether.yaml | 49 |
1 files changed, 32 insertions, 17 deletions
diff --git a/dts/Bindings/net/renesas,ether.yaml b/dts/Bindings/net/renesas,ether.yaml index 7f84df9790..29355ab985 100644 --- a/dts/Bindings/net/renesas,ether.yaml +++ b/dts/Bindings/net/renesas,ether.yaml @@ -10,7 +10,7 @@ allOf: - $ref: ethernet-controller.yaml# maintainers: - - Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> + - Sergei Shtylyov <sergei.shtylyov@gmail.com> properties: compatible: @@ -29,8 +29,9 @@ properties: - renesas,rcar-gen1-ether # a generic R-Car Gen1 device - items: - enum: - - renesas,ether-r8a7745 # device is a part of R8A7745 SoC + - renesas,ether-r8a7742 # device is a part of R8A7742 SoC - renesas,ether-r8a7743 # device is a part of R8A7743 SoC + - renesas,ether-r8a7745 # device is a part of R8A7745 SoC - renesas,ether-r8a7790 # device is a part of R8A7790 SoC - renesas,ether-r8a7791 # device is a part of R8A7791 SoC - renesas,ether-r8a7793 # device is a part of R8A7793 SoC @@ -40,8 +41,8 @@ properties: reg: items: - - description: E-DMAC/feLic registers - - description: TSU registers + - description: E-DMAC/feLic registers + - description: TSU registers minItems: 1 interrupts: @@ -58,9 +59,15 @@ properties: clocks: maxItems: 1 - pinctrl-0: true + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + phy-mode: true - pinctrl-names: true + phy-handle: true renesas,no-ether-link: type: boolean @@ -73,6 +80,10 @@ properties: specify when the Ether LINK signal is active-low instead of normal active-high +patternProperties: + "@[0-9a-f]$": + type: object + required: - compatible - reg @@ -82,33 +93,37 @@ required: - '#address-cells' - '#size-cells' - clocks - - pinctrl-0 + +additionalProperties: false examples: # Lager board - | - #include <dt-bindings/clock/r8a7790-clock.h> - #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/r8a7790-cpg-mssr.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/r8a7790-sysc.h> + #include <dt-bindings/gpio/gpio.h> ethernet@ee700000 { compatible = "renesas,ether-r8a7790", "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; - interrupt-parent = <&gic>; - interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7790_CLK_ETHER>; + reg = <0xee700000 0x400>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 813>; phy-mode = "rmii"; phy-handle = <&phy1>; - pinctrl-0 = <ðer_pins>; - pinctrl-names = "default"; renesas,ether-link-active-low; #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0022.1537", + "ethernet-phy-ieee802.3-c22"; reg = <1>; interrupt-parent = <&irqc0>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&phy1_pins>; - pinctrl-names = "default"; + micrel,led-mode = <1>; + reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>; }; }; |