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Diffstat (limited to 'dts/Bindings/net/ti,dp83867.txt')
| -rw-r--r-- | dts/Bindings/net/ti,dp83867.txt | 68 |
1 files changed, 0 insertions, 68 deletions
diff --git a/dts/Bindings/net/ti,dp83867.txt b/dts/Bindings/net/ti,dp83867.txt deleted file mode 100644 index 44e2a4fab2..0000000000 --- a/dts/Bindings/net/ti,dp83867.txt +++ /dev/null @@ -1,68 +0,0 @@ -* Texas Instruments - dp83867 Giga bit ethernet phy - -Required properties: - - reg - The ID number for the phy, usually a small integer - - ti,rx-internal-delay - RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h - for applicable values. Required only if interface type is - PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID - - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h - for applicable values. Required only if interface type is - PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID - -Note: If the interface type is PHY_INTERFACE_MODE_RGMII the TX/RX clock delays - will be left at their default values, as set by the PHY's pin strapping. - The default strapping will use a delay of 2.00 ns. Thus - PHY_INTERFACE_MODE_RGMII, by default, does not behave as RGMII with no - internal delay, but as PHY_INTERFACE_MODE_RGMII_ID. The device tree - should use "rgmii-id" if internal delays are desired as this may be - changed in future to cause "rgmii" mode to disable delays. - -Optional property: - - ti,min-output-impedance - MAC Interface Impedance control to set - the programmable output impedance to - minimum value (35 ohms). - - ti,max-output-impedance - MAC Interface Impedance control to set - the programmable output impedance to - maximum value (70 ohms). - - ti,dp83867-rxctrl-strap-quirk - This denotes the fact that the - board has RX_DV/RX_CTRL pin strapped in - mode 1 or 2. To ensure PHY operation, - there are specific actions that - software needs to take when this pin is - strapped in these modes. See data manual - for details. - - ti,clk-output-sel - Muxing option for CLK_OUT pin. See dt-bindings/net/ti-dp83867.h - for applicable values. The CLK_OUT pin can also - be disabled by this property. When omitted, the - PHY's default will be left as is. - - ti,sgmii-ref-clock-output-enable - This denotes which - SGMII configuration is used (4 or 6-wire modes). - Some MACs work with differential SGMII clock. - See data manual for details. - - - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h - for applicable values (deprecated) - - -tx-fifo-depth - As defined in the ethernet-controller.yaml. Values for - the depth can be found in dt-bindings/net/ti-dp83867.h - -rx-fifo-depth - As defined in the ethernet-controller.yaml. Values for - the depth can be found in dt-bindings/net/ti-dp83867.h - -Note: ti,min-output-impedance and ti,max-output-impedance are mutually - exclusive. When both properties are present ti,max-output-impedance - takes precedence. - -Default child nodes are standard Ethernet PHY device -nodes as described in Documentation/devicetree/bindings/net/phy.txt - -Example: - - ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; - tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - }; - -Datasheet can be found: -http://www.ti.com/product/DP83867IR/datasheet |