diff options
Diffstat (limited to 'dts/Bindings/net')
| -rw-r--r-- | dts/Bindings/net/broadcom-bluetooth.txt | 2 | ||||
| -rw-r--r-- | dts/Bindings/net/can/bosch,m_can.yaml | 144 | ||||
| -rw-r--r-- | dts/Bindings/net/can/can-transceiver.txt | 24 | ||||
| -rw-r--r-- | dts/Bindings/net/can/can-transceiver.yaml | 18 | ||||
| -rw-r--r-- | dts/Bindings/net/can/m_can.txt | 75 | ||||
| -rw-r--r-- | dts/Bindings/net/can/tcan4x5x.txt | 2 | ||||
| -rw-r--r-- | dts/Bindings/net/dsa/ocelot.txt | 116 | ||||
| -rw-r--r-- | dts/Bindings/net/marvell,mvusb.yaml | 64 | ||||
| -rw-r--r-- | dts/Bindings/net/mediatek-bluetooth.txt | 2 | ||||
| -rw-r--r-- | dts/Bindings/net/qca,qca7000.txt | 2 | ||||
| -rw-r--r-- | dts/Bindings/net/qcom,ipa.yaml | 198 | ||||
| -rw-r--r-- | dts/Bindings/net/qcom,ipq8064-mdio.yaml | 53 | ||||
| -rw-r--r-- | dts/Bindings/net/qualcomm-bluetooth.txt | 2 | ||||
| -rw-r--r-- | dts/Bindings/net/ti,cpsw-switch.yaml | 25 | ||||
| -rw-r--r-- | dts/Bindings/net/ti,k3-am654-cpsw-nuss.yaml | 225 | ||||
| -rw-r--r-- | dts/Bindings/net/ti-bluetooth.txt | 3 | ||||
| -rw-r--r-- | dts/Bindings/net/wireless/mediatek,mt76.txt | 29 | ||||
| -rw-r--r-- | dts/Bindings/net/wireless/qcom,ath10k.txt | 7 | ||||
| -rw-r--r-- | dts/Bindings/net/wireless/ti,wl1251.txt | 3 |
19 files changed, 877 insertions, 117 deletions
diff --git a/dts/Bindings/net/broadcom-bluetooth.txt b/dts/Bindings/net/broadcom-bluetooth.txt index dd25867463..a7d57ba5f2 100644 --- a/dts/Bindings/net/broadcom-bluetooth.txt +++ b/dts/Bindings/net/broadcom-bluetooth.txt @@ -20,7 +20,7 @@ Required properties: Optional properties: - - max-speed: see Documentation/devicetree/bindings/serial/slave-device.txt + - max-speed: see Documentation/devicetree/bindings/serial/serial.yaml - shutdown-gpios: GPIO specifier, used to enable the BT module - device-wakeup-gpios: GPIO specifier, used to wakeup the controller - host-wakeup-gpios: GPIO specifier, used to wakeup the host processor. diff --git a/dts/Bindings/net/can/bosch,m_can.yaml b/dts/Bindings/net/can/bosch,m_can.yaml new file mode 100644 index 0000000000..cccf8202c8 --- /dev/null +++ b/dts/Bindings/net/can/bosch,m_can.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/can/bosch,m_can.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bosch MCAN controller Bindings + +description: Bosch MCAN controller for CAN bus + +maintainers: + - Sriram Dash <sriram.dash@samsung.com> + +properties: + compatible: + const: bosch,m_can + + reg: + items: + - description: M_CAN registers map + - description: message RAM + + reg-names: + items: + - const: m_can + - const: message_ram + + interrupts: + items: + - description: interrupt line0 + - description: interrupt line1 + minItems: 1 + maxItems: 2 + + interrupt-names: + items: + - const: int0 + - const: int1 + minItems: 1 + maxItems: 2 + + clocks: + items: + - description: peripheral clock + - description: bus clock + + clock-names: + items: + - const: hclk + - const: cclk + + bosch,mram-cfg: + description: | + Message RAM configuration data. + Multiple M_CAN instances can share the same Message RAM + and each element(e.g Rx FIFO or Tx Buffer and etc) number + in Message RAM is also configurable, so this property is + telling driver how the shared or private Message RAM are + used by this M_CAN controller. + + The format should be as follows: + <offset sidf_elems xidf_elems rxf0_elems rxf1_elems rxb_elems txe_elems txb_elems> + The 'offset' is an address offset of the Message RAM where + the following elements start from. This is usually set to + 0x0 if you're using a private Message RAM. The remain cells + are used to specify how many elements are used for each FIFO/Buffer. + + M_CAN includes the following elements according to user manual: + 11-bit Filter 0-128 elements / 0-128 words + 29-bit Filter 0-64 elements / 0-128 words + Rx FIFO 0 0-64 elements / 0-1152 words + Rx FIFO 1 0-64 elements / 0-1152 words + Rx Buffers 0-64 elements / 0-1152 words + Tx Event FIFO 0-32 elements / 0-64 words + Tx Buffers 0-32 elements / 0-576 words + + Please refer to 2.4.1 Message RAM Configuration in Bosch + M_CAN user manual for details. + allOf: + - $ref: /schemas/types.yaml#/definitions/int32-array + - items: + items: + - description: The 'offset' is an address offset of the Message RAM + where the following elements start from. This is usually + set to 0x0 if you're using a private Message RAM. + default: 0 + - description: 11-bit Filter 0-128 elements / 0-128 words + minimum: 0 + maximum: 128 + - description: 29-bit Filter 0-64 elements / 0-128 words + minimum: 0 + maximum: 64 + - description: Rx FIFO 0 0-64 elements / 0-1152 words + minimum: 0 + maximum: 64 + - description: Rx FIFO 1 0-64 elements / 0-1152 words + minimum: 0 + maximum: 64 + - description: Rx Buffers 0-64 elements / 0-1152 words + minimum: 0 + maximum: 64 + - description: Tx Event FIFO 0-32 elements / 0-64 words + minimum: 0 + maximum: 32 + - description: Tx Buffers 0-32 elements / 0-576 words + minimum: 0 + maximum: 32 + maxItems: 1 + + can-transceiver: + $ref: can-transceiver.yaml# + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - clock-names + - bosch,mram-cfg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx6sx-clock.h> + can@20e8000 { + compatible = "bosch,m_can"; + reg = <0x020e8000 0x4000>, <0x02298000 0x4000>; + reg-names = "m_can", "message_ram"; + interrupts = <0 114 0x04>, <0 114 0x04>; + interrupt-names = "int0", "int1"; + clocks = <&clks IMX6SX_CLK_CANFD>, + <&clks IMX6SX_CLK_CANFD>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>; + + can-transceiver { + max-bitrate = <5000000>; + }; + }; + +... diff --git a/dts/Bindings/net/can/can-transceiver.txt b/dts/Bindings/net/can/can-transceiver.txt deleted file mode 100644 index 0011f53ff1..0000000000 --- a/dts/Bindings/net/can/can-transceiver.txt +++ /dev/null @@ -1,24 +0,0 @@ -Generic CAN transceiver Device Tree binding ------------------------------- - -CAN transceiver typically limits the max speed in standard CAN and CAN FD -modes. Typically these limitations are static and the transceivers themselves -provide no way to detect this limitation at runtime. For this situation, -the "can-transceiver" node can be used. - -Required Properties: - max-bitrate: a positive non 0 value that determines the max - speed that CAN/CAN-FD can run. Any other value - will be ignored. - -Examples: - -Based on Texas Instrument's TCAN1042HGV CAN Transceiver - -m_can0 { - .... - can-transceiver { - max-bitrate = <5000000>; - }; - ... -}; diff --git a/dts/Bindings/net/can/can-transceiver.yaml b/dts/Bindings/net/can/can-transceiver.yaml new file mode 100644 index 0000000000..6396977d29 --- /dev/null +++ b/dts/Bindings/net/can/can-transceiver.yaml @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/can/can-transceiver.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CAN transceiver Bindings + +description: CAN transceiver generic properties bindings + +maintainers: + - Rob Herring <robh@kernel.org> + +properties: + max-bitrate: + $ref: /schemas/types.yaml#/definitions/uint32 + description: a positive non 0 value that determines the max speed that CAN/CAN-FD can run. + minimum: 1 diff --git a/dts/Bindings/net/can/m_can.txt b/dts/Bindings/net/can/m_can.txt deleted file mode 100644 index ed614383af..0000000000 --- a/dts/Bindings/net/can/m_can.txt +++ /dev/null @@ -1,75 +0,0 @@ -Bosch MCAN controller Device Tree Bindings -------------------------------------------------- - -Required properties: -- compatible : Should be "bosch,m_can" for M_CAN controllers -- reg : physical base address and size of the M_CAN - registers map and Message RAM -- reg-names : Should be "m_can" and "message_ram" -- interrupts : Should be the interrupt number of M_CAN interrupt - line 0 and line 1, could be same if sharing - the same interrupt. -- interrupt-names : Should contain "int0" and "int1" -- clocks : Clocks used by controller, should be host clock - and CAN clock. -- clock-names : Should contain "hclk" and "cclk" -- pinctrl-<n> : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt -- pinctrl-names : Names corresponding to the numbered pinctrl states -- bosch,mram-cfg : Message RAM configuration data. - Multiple M_CAN instances can share the same Message - RAM and each element(e.g Rx FIFO or Tx Buffer and etc) - number in Message RAM is also configurable, - so this property is telling driver how the shared or - private Message RAM are used by this M_CAN controller. - - The format should be as follows: - <offset sidf_elems xidf_elems rxf0_elems rxf1_elems - rxb_elems txe_elems txb_elems> - The 'offset' is an address offset of the Message RAM - where the following elements start from. This is - usually set to 0x0 if you're using a private Message - RAM. The remain cells are used to specify how many - elements are used for each FIFO/Buffer. - - M_CAN includes the following elements according to user manual: - 11-bit Filter 0-128 elements / 0-128 words - 29-bit Filter 0-64 elements / 0-128 words - Rx FIFO 0 0-64 elements / 0-1152 words - Rx FIFO 1 0-64 elements / 0-1152 words - Rx Buffers 0-64 elements / 0-1152 words - Tx Event FIFO 0-32 elements / 0-64 words - Tx Buffers 0-32 elements / 0-576 words - - Please refer to 2.4.1 Message RAM Configuration in - Bosch M_CAN user manual for details. - -Optional Subnode: -- can-transceiver : Can-transceiver subnode describing maximum speed - that can be used for CAN/CAN-FD modes. See - Documentation/devicetree/bindings/net/can/can-transceiver.txt - for details. -Example: -SoC dtsi: -m_can1: can@20e8000 { - compatible = "bosch,m_can"; - reg = <0x020e8000 0x4000>, <0x02298000 0x4000>; - reg-names = "m_can", "message_ram"; - interrupts = <0 114 0x04>, - <0 114 0x04>; - interrupt-names = "int0", "int1"; - clocks = <&clks IMX6SX_CLK_CANFD>, - <&clks IMX6SX_CLK_CANFD>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>; -}; - -Board dts: -&m_can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_m_can1>; - status = "enabled"; - - can-transceiver { - max-bitrate = <5000000>; - }; -}; diff --git a/dts/Bindings/net/can/tcan4x5x.txt b/dts/Bindings/net/can/tcan4x5x.txt index 6bdcc3f84b..3613c2c8f7 100644 --- a/dts/Bindings/net/can/tcan4x5x.txt +++ b/dts/Bindings/net/can/tcan4x5x.txt @@ -14,7 +14,7 @@ Required properties: the interrupt. - interrupts: interrupt specification for data-ready. -See Documentation/devicetree/bindings/net/can/m_can.txt for additional +See Documentation/devicetree/bindings/net/can/bosch,m_can.yaml for additional required property details. Optional properties: diff --git a/dts/Bindings/net/dsa/ocelot.txt b/dts/Bindings/net/dsa/ocelot.txt new file mode 100644 index 0000000000..66a129fea7 --- /dev/null +++ b/dts/Bindings/net/dsa/ocelot.txt @@ -0,0 +1,116 @@ +Microchip Ocelot switch driver family +===================================== + +Felix +----- + +The VSC9959 core is currently the only switch supported by the driver, and is +found in the NXP LS1028A. It is a PCI device, part of the larger ENETC root +complex. As a result, the ethernet-switch node is a sub-node of the PCIe root +complex node and its "reg" property conforms to the parent node bindings: + +* reg: Specifies PCIe Device Number and Function Number of the endpoint device, + in this case for the Ethernet L2Switch it is PF5 (of device 0, bus 0). + +It does not require a "compatible" string. + +The interrupt line is used to signal availability of PTP TX timestamps and for +TSN frame preemption. + +For the external switch ports, depending on board configuration, "phy-mode" and +"phy-handle" are populated by board specific device tree instances. Ports 4 and +5 are fixed as internal ports in the NXP LS1028A instantiation. + +The CPU port property ("ethernet") configures the feature called "NPI port" in +the Ocelot hardware core. The CPU port in Ocelot is a set of queues, which are +connected, in the Node Processor Interface (NPI) mode, to an Ethernet port. +By default, in fsl-ls1028a.dtsi, the NPI port is assigned to the internal +2.5Gbps port@4, but can be moved to the 1Gbps port@5, depending on the specific +use case. Moving the NPI port to an external switch port is hardware possible, +but there is no platform support for the Linux system on the LS1028A chip to +operate as an entire slave DSA chip. NPI functionality (and therefore DSA +tagging) is supported on a single port at a time. + +Any port can be disabled (and in fsl-ls1028a.dtsi, they are indeed all disabled +by default, and should be enabled on a per-board basis). But if any external +switch port is enabled at all, the ENETC PF2 (enetc_port2) should be enabled as +well, regardless of whether it is configured as the DSA master or not. This is +because the Felix PHYLINK implementation accesses the MAC PCS registers, which +in hardware truly belong to the ENETC port #2 and not to Felix. + +Supported PHY interface types (appropriate SerDes protocol setting changes are +needed in the RCW binary): + +* phy_mode = "internal": on ports 4 and 5 +* phy_mode = "sgmii": on ports 0, 1, 2, 3 +* phy_mode = "qsgmii": on ports 0, 1, 2, 3 +* phy_mode = "usxgmii": on ports 0, 1, 2, 3 +* phy_mode = "2500base-x": on ports 0, 1, 2, 3 + +For the rest of the device tree binding definitions, which are standard DSA and +PCI, refer to the following documents: + +Documentation/devicetree/bindings/net/dsa/dsa.txt +Documentation/devicetree/bindings/pci/pci.txt + +Example: + +&soc { + pcie@1f0000000 { /* Integrated Endpoint Root Complex */ + ethernet-switch@0,5 { + reg = <0x000500 0 0 0 0>; + /* IEP INT_B */ + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* External ports */ + port@0 { + reg = <0>; + label = "swp0"; + }; + + port@1 { + reg = <1>; + label = "swp1"; + }; + + port@2 { + reg = <2>; + label = "swp2"; + }; + + port@3 { + reg = <3>; + label = "swp3"; + }; + + /* Tagging CPU port */ + port@4 { + reg = <4>; + ethernet = <&enetc_port2>; + phy-mode = "internal"; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + /* Non-tagging CPU port */ + port@5 { + reg = <5>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + }; +}; diff --git a/dts/Bindings/net/marvell,mvusb.yaml b/dts/Bindings/net/marvell,mvusb.yaml new file mode 100644 index 0000000000..6857376229 --- /dev/null +++ b/dts/Bindings/net/marvell,mvusb.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/marvell,mvusb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell USB to MDIO Controller + +maintainers: + - Tobias Waldekranz <tobias@waldekranz.com> + +description: |+ + This controller is mounted on development boards for Marvell's Link Street + family of Ethernet switches. It allows you to configure the switch's registers + using the standard MDIO interface. + + Since the device is connected over USB, there is no strict requirement of + having a device tree representation of the device. But in order to use it with + the mv88e6xxx driver, you need a device tree node in which to place the switch + definition. + +allOf: + - $ref: "mdio.yaml#" + +properties: + compatible: + const: usb1286,1fa4 + reg: + maxItems: 1 + description: The USB port number on the host controller + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +examples: + - | + /* USB host controller */ + usb { + #address-cells = <1>; + #size-cells = <0>; + + mdio@1 { + compatible = "usb1286,1fa4"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "marvell,mv88e6190"; + reg = <0x0>; + + ports { + /* Port definitions */ + }; + + mdio { + /* PHY definitions */ + }; + }; + }; + }; diff --git a/dts/Bindings/net/mediatek-bluetooth.txt b/dts/Bindings/net/mediatek-bluetooth.txt index 112011c51d..219bcbd0d3 100644 --- a/dts/Bindings/net/mediatek-bluetooth.txt +++ b/dts/Bindings/net/mediatek-bluetooth.txt @@ -42,7 +42,7 @@ child node of the serial node with UART. Please refer to the following documents for generic properties: - Documentation/devicetree/bindings/serial/slave-device.txt + Documentation/devicetree/bindings/serial/serial.yaml Required properties: diff --git a/dts/Bindings/net/qca,qca7000.txt b/dts/Bindings/net/qca,qca7000.txt index 21c36e5249..8f5ae0b84e 100644 --- a/dts/Bindings/net/qca,qca7000.txt +++ b/dts/Bindings/net/qca,qca7000.txt @@ -68,7 +68,7 @@ Required properties: Optional properties: - local-mac-address : see ./ethernet.txt - current-speed : current baud rate of QCA7000 which defaults to 115200 - if absent, see also ../serial/slave-device.txt + if absent, see also ../serial/serial.yaml UART Example: diff --git a/dts/Bindings/net/qcom,ipa.yaml b/dts/Bindings/net/qcom,ipa.yaml new file mode 100644 index 0000000000..140f152456 --- /dev/null +++ b/dts/Bindings/net/qcom,ipa.yaml @@ -0,0 +1,198 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/qcom,ipa.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IP Accelerator (IPA) + +maintainers: + - Alex Elder <elder@kernel.org> + +description: + This binding describes the Qualcomm IPA. The IPA is capable of offloading + certain network processing tasks (e.g. filtering, routing, and NAT) from + the main processor. + + The IPA sits between multiple independent "execution environments," + including the Application Processor (AP) and the modem. The IPA presents + a Generic Software Interface (GSI) to each execution environment. + The GSI is an integral part of the IPA, but it is logically isolated + and has a distinct interrupt and a separately-defined address space. + + See also soc/qcom/qcom,smp2p.txt and interconnect/interconnect.txt. + + - | + -------- --------- + | | | | + | AP +<---. .----+ Modem | + | +--. | | .->+ | + | | | | | | | | + -------- | | | | --------- + v | v | + --+-+---+-+-- + | GSI | + |-----------| + | | + | IPA | + | | + ------------- + +properties: + compatible: + const: "qcom,sdm845-ipa" + + reg: + items: + - description: IPA registers + - description: IPA shared memory + - description: GSI registers + + reg-names: + items: + - const: ipa-reg + - const: ipa-shared + - const: gsi + + clocks: + maxItems: 1 + + clock-names: + const: core + + interrupts: + items: + - description: IPA interrupt (hardware IRQ) + - description: GSI interrupt (hardware IRQ) + - description: Modem clock query interrupt (smp2p interrupt) + - description: Modem setup ready interrupt (smp2p interrupt) + + interrupt-names: + items: + - const: ipa + - const: gsi + - const: ipa-clock-query + - const: ipa-setup-ready + + interconnects: + items: + - description: Interconnect path between IPA and main memory + - description: Interconnect path between IPA and internal memory + - description: Interconnect path between IPA and the AP subsystem + + interconnect-names: + items: + - const: memory + - const: imem + - const: config + + qcom,smem-states: + allOf: + - $ref: /schemas/types.yaml#/definitions/phandle-array + description: State bits used in by the AP to signal the modem. + items: + - description: Whether the "ipa-clock-enabled" state bit is valid + - description: Whether the IPA clock is enabled (if valid) + + qcom,smem-state-names: + allOf: + - $ref: /schemas/types.yaml#/definitions/string-array + description: The names of the state bits used for SMP2P output + items: + - const: ipa-clock-enabled-valid + - const: ipa-clock-enabled + + modem-init: + type: boolean + description: + If present, it indicates that the modem is responsible for + performing early IPA initialization, including loading and + validating firwmare used by the GSI. + + modem-remoteproc: + $ref: /schemas/types.yaml#definitions/phandle + description: + This defines the phandle to the remoteproc node representing + the modem subsystem. This is requied so the IPA driver can + receive and act on notifications of modem up/down events. + + memory-region: + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + description: + If present, a phandle for a reserved memory area that holds + the firmware passed to Trust Zone for authentication. Required + when Trust Zone (not the modem) performs early initialization. + +required: + - compatible + - reg + - clocks + - interrupts + - interconnects + - qcom,smem-states + - modem-remoteproc + +oneOf: + - required: + - modem-init + - required: + - memory-region + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interconnect/qcom,sdm845.h> + + smp2p-mpss { + compatible = "qcom,smp2p"; + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + ipa@1e40000 { + compatible = "qcom,sdm845-ipa"; + + modem-init; + modem-remoteproc = <&mss_pil>; + + reg = <0 0x1e40000 0 0x7000>, + <0 0x1e47000 0 0x2000>, + <0 0x1e04000 0 0x2c000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>, + <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + clocks = <&rpmhcc RPMH_IPA_CLK>; + clock-names = "core"; + + interconnects = + <&rsc_hlos MASTER_IPA &rsc_hlos SLAVE_EBI1>, + <&rsc_hlos MASTER_IPA &rsc_hlos SLAVE_IMEM>, + <&rsc_hlos MASTER_APPSS_PROC &rsc_hlos SLAVE_IPA_CFG>; + interconnect-names = "memory", + "imem", + "config"; + + qcom,smem-states = <&ipa_smp2p_out 0>, + <&ipa_smp2p_out 1>; + qcom,smem-state-names = "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + }; diff --git a/dts/Bindings/net/qcom,ipq8064-mdio.yaml b/dts/Bindings/net/qcom,ipq8064-mdio.yaml new file mode 100644 index 0000000000..b9f9008104 --- /dev/null +++ b/dts/Bindings/net/qcom,ipq8064-mdio.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/qcom,ipq8064-mdio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm ipq806x MDIO bus controller + +maintainers: + - Ansuel Smith <ansuelsmth@gmail.com> + +description: + The ipq806x soc have a MDIO dedicated controller that is + used to communicate with the gmac phy connected. + +allOf: + - $ref: "mdio.yaml#" + +properties: + compatible: + const: qcom,ipq8064-mdio + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - "#address-cells" + - "#size-cells" + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-ipq806x.h> + + mdio0: mdio@37000000 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,ipq8064-mdio"; + reg = <0x37000000 0x200000>; + + clocks = <&gcc GMAC_CORE1_CLK>; + + switch@10 { + compatible = "qca,qca8337"; + /* ... */ + }; + }; diff --git a/dts/Bindings/net/qualcomm-bluetooth.txt b/dts/Bindings/net/qualcomm-bluetooth.txt index 999aceadb9..beca6466d5 100644 --- a/dts/Bindings/net/qualcomm-bluetooth.txt +++ b/dts/Bindings/net/qualcomm-bluetooth.txt @@ -31,6 +31,7 @@ Optional properties for compatible string qcom,wcn399x-bt: - max-speed: see Documentation/devicetree/bindings/serial/slave-device.txt - firmware-name: specify the name of nvm firmware to load + - clocks: clock provided to the controller Examples: @@ -57,5 +58,6 @@ serial@898000 { vddch0-supply = <&vreg_l25a_3p3>; max-speed = <3200000>; firmware-name = "crnv21.bin"; + clocks = <&rpmhcc RPMH_RF_CLK2>; }; }; diff --git a/dts/Bindings/net/ti,cpsw-switch.yaml b/dts/Bindings/net/ti,cpsw-switch.yaml index ac8c76369a..976f139bb6 100644 --- a/dts/Bindings/net/ti,cpsw-switch.yaml +++ b/dts/Bindings/net/ti,cpsw-switch.yaml @@ -37,6 +37,12 @@ properties: description: The physical base address and size of full the CPSW module IO range + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + ranges: true clocks: @@ -111,13 +117,6 @@ properties: - reg - phys - mdio: - type: object - allOf: - - $ref: "ti,davinci-mdio.yaml#" - description: - CPSW MDIO bus. - cpts: type: object description: @@ -148,6 +147,15 @@ properties: - clocks - clock-names +patternProperties: + "^mdio@": + type: object + allOf: + - $ref: "ti,davinci-mdio.yaml#" + description: + CPSW MDIO bus. + + required: - compatible - reg @@ -159,6 +167,8 @@ required: - '#address-cells' - '#size-cells' +additionalProperties: false + examples: - | #include <dt-bindings/interrupt-controller/irq.h> @@ -174,7 +184,6 @@ examples: #address-cells = <1>; #size-cells = <1>; syscon = <&scm_conf>; - inctrl-names = "default", "sleep"; interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, diff --git a/dts/Bindings/net/ti,k3-am654-cpsw-nuss.yaml b/dts/Bindings/net/ti,k3-am654-cpsw-nuss.yaml new file mode 100644 index 0000000000..78bf511e28 --- /dev/null +++ b/dts/Bindings/net/ti,k3-am654-cpsw-nuss.yaml @@ -0,0 +1,225 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: The TI AM654x/J721E SoC Gigabit Ethernet MAC (Media Access Controller) Device Tree Bindings + +maintainers: + - Grygorii Strashko <grygorii.strashko@ti.com> + - Sekhar Nori <nsekhar@ti.com> + +description: + The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports + (one external) and provides Ethernet packet communication for the device. + CPSW2G NUSS features - the Reduced Gigabit Media Independent Interface (RGMII), + Reduced Media Independent Interface (RMII), the Management Data + Input/Output (MDIO) interface for physical layer device (PHY) management, + new version of Common Platform Time Sync (CPTS), updated Address Lookup + Engine (ALE). + One external Ethernet port (port 1) with selectable RGMII/RMII interfaces and + an internal Communications Port Programming Interface (CPPI5) (Host port 0). + Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels + and one RX channels and operating by TI AM654x/J721E NAVSS Unified DMA + Peripheral Root Complex (UDMA-P) controller. + The CPSW2G NUSS is integrated into device MCU domain named MCU_CPSW0. + + Additional features + priority level Quality Of Service (QOS) support (802.1p) + Support for Audio/Video Bridging (P802.1Qav/D6.0) + Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F) + Flow Control (802.3x) Support + Time Sensitive Network Support + IEEE P902.3br/D2.0 Interspersing Express Traffic + IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic + Configurable number of addresses plus VLANs + Configurable number of classifier/policers + VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on + ingress, Auto VLAN removal on egress and auto pad to minimum frame size. + RX/TX csum offload + + Specifications can be found at + http://www.ti.com/lit/ug/spruid7e/spruid7e.pdf + http://www.ti.com/lit/ug/spruil1a/spruil1a.pdf + +properties: + "#address-cells": true + "#size-cells": true + + compatible: + oneOf: + - const: ti,am654-cpsw-nuss + - const: ti,j721e-cpsw-nuss + + reg: + maxItems: 1 + description: + The physical base address and size of full the CPSW2G NUSS IO range + + reg-names: + items: + - const: cpsw_nuss + + ranges: true + + dma-coherent: true + + clocks: + description: CPSW2G NUSS functional clock + + clock-names: + items: + - const: fck + + power-domains: + maxItems: 1 + + dmas: + maxItems: 9 + + dma-names: + items: + - const: tx0 + - const: tx1 + - const: tx2 + - const: tx3 + - const: tx4 + - const: tx5 + - const: tx6 + - const: tx7 + - const: rx + + ethernet-ports: + type: object + properties: + '#address-cells': + const: 1 + '#size-cells': + const: 0 + + patternProperties: + port@1: + type: object + description: CPSW2G NUSS external ports + + allOf: + - $ref: ethernet-controller.yaml# + + properties: + reg: + items: + - const: 1 + description: CPSW port number + + phys: + maxItems: 1 + description: phandle on phy-gmii-sel PHY + + label: + description: label associated with this port + + ti,mac-only: + $ref: /schemas/types.yaml#definitions/flag + description: + Specifies the port works in mac-only mode. + + ti,syscon-efuse: + $ref: /schemas/types.yaml#definitions/phandle-array + description: + Phandle to the system control device node which provides access + to efuse IO range with MAC addresses + + required: + - reg + - phys + + additionalProperties: false + +patternProperties: + "^mdio@[0-9a-f]+$": + type: object + allOf: + - $ref: "ti,davinci-mdio.yaml#" + description: + CPSW MDIO bus. + +required: + - compatible + - reg + - reg-names + - ranges + - clocks + - clock-names + - power-domains + - dmas + - dma-names + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/k3.h> + #include <dt-bindings/soc/ti,sci_pm_domain.h> + #include <dt-bindings/net/ti-dp83867.h> + + mcu_cpsw: ethernet@46000000 { + compatible = "ti,am654-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x46000000 0x0 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x0 0x0 0x46000000 0x0 0x200000>; + dma-coherent; + clocks = <&k3_clks 5 10>; + clock-names = "fck"; + power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + + dmas = <&mcu_udmap 0xf000>, + <&mcu_udmap 0xf001>, + <&mcu_udmap 0xf002>, + <&mcu_udmap 0xf003>, + <&mcu_udmap 0xf004>, + <&mcu_udmap 0xf005>, + <&mcu_udmap 0xf006>, + <&mcu_udmap 0xf007>, + <&mcu_udmap 0x7000>; + dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", + "rx"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + ti,syscon-efuse = <&mcu_conf 0x200>; + phys = <&phy_gmii_sel 1>; + + phy-mode = "rgmii-rxid"; + phy-handle = <&phy0>; + }; + }; + + davinci_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x0 0xf00 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 5 10>; + clock-names = "fck"; + bus_freq = <1000000>; + + phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + }; + }; + }; diff --git a/dts/Bindings/net/ti-bluetooth.txt b/dts/Bindings/net/ti-bluetooth.txt index 6d03ff8c70..f48c17b38f 100644 --- a/dts/Bindings/net/ti-bluetooth.txt +++ b/dts/Bindings/net/ti-bluetooth.txt @@ -15,8 +15,7 @@ standard BT HCI protocol with additional channels for the other functions. TI WiLink devices also have a separate WiFi interface as described in wireless/ti,wlcore.txt. -This bindings follows the UART slave device binding in -../serial/slave-device.txt. +This bindings follows the UART slave device binding in ../serial/serial.yaml. Required properties: - compatible: should be one of the following: diff --git a/dts/Bindings/net/wireless/mediatek,mt76.txt b/dts/Bindings/net/wireless/mediatek,mt76.txt index 7e675dafc2..3a76d8faaa 100644 --- a/dts/Bindings/net/wireless/mediatek,mt76.txt +++ b/dts/Bindings/net/wireless/mediatek,mt76.txt @@ -4,17 +4,27 @@ This node provides properties for configuring the MediaTek mt76xx wireless device. The node is expected to be specified as a child node of the PCI controller to which the wireless chip is connected. -Alternatively, it can specify the wireless part of the MT7628/MT7688 SoC. -For SoC, use the compatible string "mediatek,mt7628-wmac" and the following -properties: +Alternatively, it can specify the wireless part of the MT7628/MT7688 or +MT7622 SoC. For SoC, use the following compatible strings: + +compatible: +- "mediatek,mt7628-wmac" for MT7628/MT7688 +- "mediatek,mt7622-wmac" for MT7622 +properties: - reg: Address and length of the register set for the device. - interrupts: Main device interrupt +MT7622 specific properties: +- power-domains: phandle to the power domain that the WMAC is part of +- mediatek,infracfg: phandle to the infrastructure bus fabric syscon node + Optional properties: - ieee80211-freq-limit: See ieee80211.txt - mediatek,mtd-eeprom: Specify a MTD partition + offset containing EEPROM data +- big-endian: if the radio eeprom partition is written in big-endian, specify + this property The MAC address can as well be set with corresponding optional properties defined in net/ethernet.txt. @@ -31,6 +41,7 @@ Optional nodes: reg = <0x0000 0 0 0 0>; ieee80211-freq-limit = <5000000 6000000>; mediatek,mtd-eeprom = <&factory 0x8000>; + big-endian; led { led-sources = <2>; @@ -50,3 +61,15 @@ wmac: wmac@10300000 { mediatek,mtd-eeprom = <&factory 0x0000>; }; + +MT7622 example: + +wmac: wmac@18000000 { + compatible = "mediatek,mt7622-wmac"; + reg = <0 0x18000000 0 0x100000>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>; + + mediatek,infracfg = <&infracfg>; + + power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>; +}; diff --git a/dts/Bindings/net/wireless/qcom,ath10k.txt b/dts/Bindings/net/wireless/qcom,ath10k.txt index 616c87746d..71bf91f973 100644 --- a/dts/Bindings/net/wireless/qcom,ath10k.txt +++ b/dts/Bindings/net/wireless/qcom,ath10k.txt @@ -91,6 +91,11 @@ Optional properties: - qcom,msa-fixed-perm: Boolean context flag to disable SCM call for statically mapped msa region. +- qcom,coexist-support : should contain eithr "0" or "1" to indicate coex + support by the hardware. +- qcom,coexist-gpio-pin : gpio pin number information to support coex + which will be used by wifi firmware. + Example (to supply PCI based wifi block details): In this example, the node is defined as child node of the PCI controller. @@ -159,6 +164,8 @@ wifi0: wifi@a000000 { qcom,msi_addr = <0x0b006040>; qcom,msi_base = <0x40>; qcom,ath10k-pre-calibration-data = [ 01 02 03 ... ]; + qcom,coexist-support = <1>; + qcom,coexist-gpio-pin = <0x33>; }; Example (to supply wcn3990 SoC wifi block details): diff --git a/dts/Bindings/net/wireless/ti,wl1251.txt b/dts/Bindings/net/wireless/ti,wl1251.txt index f389505609..88fd28d15e 100644 --- a/dts/Bindings/net/wireless/ti,wl1251.txt +++ b/dts/Bindings/net/wireless/ti,wl1251.txt @@ -9,11 +9,12 @@ Required properties: - spi-max-frequency : Maximum SPI clocking speed of device in Hz - interrupts : Should contain interrupt line - vio-supply : phandle to regulator providing VIO -- ti,power-gpio : GPIO connected to chip's PMEN pin Optional properties: - ti,wl1251-has-eeprom : boolean, the wl1251 has an eeprom connected, which provides configuration data (calibration, MAC, ...) +- ti,power-gpio : GPIO connected to chip's PMEN pin if operated in + SPI mode - Please consult Documentation/devicetree/bindings/spi/spi-bus.txt for optional SPI connection related properties, |