diff options
Diffstat (limited to 'dts/Bindings/nvmem/nvmem.yaml')
| -rw-r--r-- | dts/Bindings/nvmem/nvmem.yaml | 71 |
1 files changed, 32 insertions, 39 deletions
diff --git a/dts/Bindings/nvmem/nvmem.yaml b/dts/Bindings/nvmem/nvmem.yaml index 3bb349c634..4fd015d402 100644 --- a/dts/Bindings/nvmem/nvmem.yaml +++ b/dts/Bindings/nvmem/nvmem.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/nvmem/nvmem.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: NVMEM (Non Volatile Memory) Device Tree Bindings +title: NVMEM (Non Volatile Memory) maintainers: - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> @@ -39,26 +39,12 @@ properties: when it's driven low (logical '0') to allow writing. maxItems: 1 -patternProperties: - "@[0-9a-f]+(,[0-7])?$": - type: object - - properties: - reg: - maxItems: 1 - description: - Offset and size in bytes within the storage device. - - bits: - $ref: /schemas/types.yaml#/definitions/uint32-array - items: - - minimum: 0 - maximum: 7 - description: - Offset in bit within the address range specified by reg. - - minimum: 1 - description: - Size in bit within the address range specified by reg. + nvmem-layout: + $ref: /schemas/nvmem/layouts/nvmem-layout.yaml + description: + Alternative to the statically defined nvmem cells, this + container may reference more advanced (dynamic) layout + parsers. additionalProperties: true @@ -67,6 +53,7 @@ examples: #include <dt-bindings/gpio/gpio.h> qfprom: eeprom@700000 { + compatible = "qcom,msm8974-qfprom", "qcom,qfprom"; #address-cells = <1>; #size-cells = <1>; reg = <0x00700000 0x100000>; @@ -75,24 +62,30 @@ examples: /* ... */ - /* Data cells */ - tsens_calibration: calib@404 { - reg = <0x404 0x10>; - }; - - tsens_calibration_bckp: calib_bckp@504 { - reg = <0x504 0x11>; - bits = <6 128>; - }; - - pvs_version: pvs-version@6 { - reg = <0x6 0x2>; - bits = <7 2>; - }; - - speed_bin: speed-bin@c{ - reg = <0xc 0x1>; - bits = <2 3>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + /* Data cells */ + tsens_calibration: calib@404 { + reg = <0x404 0x10>; + }; + + tsens_calibration_bckp: calib_bckp@504 { + reg = <0x504 0x11>; + bits = <6 128>; + }; + + pvs_version: pvs-version@6 { + reg = <0x6 0x2>; + bits = <7 2>; + }; + + speed_bin: speed-bin@c{ + reg = <0xc 0x1>; + bits = <2 3>; + }; }; }; |