summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/pci/intel-gw-pcie.yaml
diff options
context:
space:
mode:
Diffstat (limited to 'dts/Bindings/pci/intel-gw-pcie.yaml')
-rw-r--r--dts/Bindings/pci/intel-gw-pcie.yaml49
1 files changed, 15 insertions, 34 deletions
diff --git a/dts/Bindings/pci/intel-gw-pcie.yaml b/dts/Bindings/pci/intel-gw-pcie.yaml
index 48a98dae00..54e2890ae6 100644
--- a/dts/Bindings/pci/intel-gw-pcie.yaml
+++ b/dts/Bindings/pci/intel-gw-pcie.yaml
@@ -7,7 +7,18 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: PCIe RC controller on Intel Gateway SoCs
maintainers:
- - Dilip Kota <eswara.kota@linux.intel.com>
+ - Rahul Tanwar <rtanwar@maxlinear.com>
+
+select:
+ properties:
+ compatible:
+ contains:
+ const: intel,lgm-pcie
+ required:
+ - compatible
+
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie.yaml#
properties:
compatible:
@@ -15,15 +26,6 @@ properties:
- const: intel,lgm-pcie
- const: snps,dw-pcie
- device_type:
- const: pci
-
- "#address-cells":
- const: 3
-
- "#size-cells":
- const: 2
-
reg:
items:
- description: Controller control and status registers.
@@ -54,30 +56,12 @@ properties:
reset-gpios:
maxItems: 1
- linux,pci-domain: true
-
num-lanes:
maximum: 2
- description: Number of lanes to use for this port.
-
- '#interrupt-cells':
- const: 1
-
- interrupt-map-mask:
- description: Standard PCI IRQ mapping properties.
-
- interrupt-map:
- description: Standard PCI IRQ mapping properties.
max-link-speed:
- description: Specify PCI Gen for link capability.
- allOf:
- - $ref: /schemas/types.yaml#/definitions/uint32
- - enum: [ 1, 2, 3, 4 ]
- - default: 1
-
- bus-range:
- description: Range of bus numbers associated with this controller.
+ enum: [1, 2, 3, 4]
+ default: 1
reset-assert-ms:
description: |
@@ -87,9 +71,6 @@ properties:
required:
- compatible
- - device_type
- - "#address-cells"
- - "#size-cells"
- reg
- reg-names
- ranges
@@ -102,7 +83,7 @@ required:
- interrupt-map
- interrupt-map-mask
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |