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-rw-r--r--dts/Bindings/pci/microchip,pcie-host.yaml33
1 files changed, 32 insertions, 1 deletions
diff --git a/dts/Bindings/pci/microchip,pcie-host.yaml b/dts/Bindings/pci/microchip,pcie-host.yaml
index edb4f81253..f7a3c26363 100644
--- a/dts/Bindings/pci/microchip,pcie-host.yaml
+++ b/dts/Bindings/pci/microchip,pcie-host.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Microchip PCIe Root Port Bridge Controller Device Tree Bindings
+title: Microchip PCIe Root Port Bridge Controller
maintainers:
- Daire McNamara <daire.mcnamara@microchip.com>
@@ -25,6 +25,33 @@ properties:
- const: cfg
- const: apb
+ clocks:
+ description:
+ Fabric Interface Controllers, FICs, are the interface between the FPGA
+ fabric and the core complex on PolarFire SoC. The FICs require two clocks,
+ one from each side of the interface. The "FIC clocks" described by this
+ property are on the core complex side & communication through a FIC is not
+ possible unless it's corresponding clock is enabled. A clock must be
+ enabled for each of the interfaces the root port is connected through.
+ This could in theory be all 4 interfaces, one interface or any combination
+ in between.
+ minItems: 1
+ items:
+ - description: FIC0's clock
+ - description: FIC1's clock
+ - description: FIC2's clock
+ - description: FIC3's clock
+
+ clock-names:
+ description:
+ As any FIC connection combination is possible, the names should match the
+ order in the clocks property and take the form "ficN" where N is a number
+ 0-3
+ minItems: 1
+ maxItems: 4
+ items:
+ pattern: '^fic[0-3]$'
+
interrupts:
minItems: 1
items:
@@ -40,6 +67,10 @@ properties:
ranges:
maxItems: 1
+ dma-ranges:
+ minItems: 1
+ maxItems: 6
+
msi-controller:
description: Identifies the node as an MSI controller.