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-rw-r--r--dts/Bindings/pci/ti,j721e-pci-host.yaml27
1 files changed, 20 insertions, 7 deletions
diff --git a/dts/Bindings/pci/ti,j721e-pci-host.yaml b/dts/Bindings/pci/ti,j721e-pci-host.yaml
index ee7a8eade3..0880a613ec 100644
--- a/dts/Bindings/pci/ti,j721e-pci-host.yaml
+++ b/dts/Bindings/pci/ti,j721e-pci-host.yaml
@@ -15,8 +15,14 @@ allOf:
properties:
compatible:
- enum:
- - ti,j721e-pcie-host
+ oneOf:
+ - description: PCIe controller in J7200
+ items:
+ - const: ti,j7200-pcie-host
+ - const: ti,j721e-pcie-host
+ - description: PCIe controller in J721E
+ items:
+ - const: ti,j721e-pcie-host
reg:
maxItems: 4
@@ -29,9 +35,12 @@ properties:
- const: cfg
ti,syscon-pcie-ctrl:
- description: Phandle to the SYSCON entry required for configuring PCIe mode
- and link speed.
- $ref: /schemas/types.yaml#/definitions/phandle
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: Phandle to the SYSCON entry
+ - description: pcie_ctrl register offset within SYSCON
+ description: Specifier for configuring PCIe mode and link speed.
power-domains:
maxItems: 1
@@ -48,7 +57,11 @@ properties:
const: 0x104c
device-id:
- const: 0xb00d
+ oneOf:
+ - items:
+ - const: 0xb00d
+ - items:
+ - const: 0xb00f
msi-map: true
@@ -90,7 +103,7 @@ examples:
<0x00 0x0d000000 0x00 0x00800000>,
<0x00 0x10000000 0x00 0x00001000>;
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
- ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
+ ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;