diff options
Diffstat (limited to 'dts/Bindings/pci')
| -rw-r--r-- | dts/Bindings/pci/83xx-512x-pci.txt | 1 | ||||
| -rw-r--r-- | dts/Bindings/pci/amlogic,meson-pcie.txt | 2 | ||||
| -rw-r--r-- | dts/Bindings/pci/mobiveil-pcie.txt | 2 | ||||
| -rw-r--r-- | dts/Bindings/pci/nvidia,tegra20-pcie.txt | 8 | ||||
| -rw-r--r-- | dts/Bindings/pci/pci.txt | 3 | ||||
| -rw-r--r-- | dts/Bindings/pci/qcom,pcie.txt | 25 | ||||
| -rw-r--r-- | dts/Bindings/pci/rcar-pci.txt | 1 |
7 files changed, 38 insertions, 4 deletions
diff --git a/dts/Bindings/pci/83xx-512x-pci.txt b/dts/Bindings/pci/83xx-512x-pci.txt index b9165b7247..3abeecf498 100644 --- a/dts/Bindings/pci/83xx-512x-pci.txt +++ b/dts/Bindings/pci/83xx-512x-pci.txt @@ -9,7 +9,6 @@ Freescale 83xx and 512x SOCs include the same PCI bridge core. Example (MPC8313ERDB) pci0: pci@e0008500 { - cell-index = <1>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x0E -mini PCI */ diff --git a/dts/Bindings/pci/amlogic,meson-pcie.txt b/dts/Bindings/pci/amlogic,meson-pcie.txt index 12b18f82d4..efa2c8b9b8 100644 --- a/dts/Bindings/pci/amlogic,meson-pcie.txt +++ b/dts/Bindings/pci/amlogic,meson-pcie.txt @@ -3,7 +3,7 @@ Amlogic Meson AXG DWC PCIE SoC controller Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pci.txt. +Documentation/devicetree/bindings/pci/designware-pcie.txt. Additional properties are described here: diff --git a/dts/Bindings/pci/mobiveil-pcie.txt b/dts/Bindings/pci/mobiveil-pcie.txt index a618d4787d..64156993e0 100644 --- a/dts/Bindings/pci/mobiveil-pcie.txt +++ b/dts/Bindings/pci/mobiveil-pcie.txt @@ -10,8 +10,10 @@ Required properties: interrupt source. The value must be 1. - compatible: Should contain "mbvl,gpex40-pcie" - reg: Should contain PCIe registers location and length + Mandatory: "config_axi_slave": PCIe controller registers "csr_axi_slave" : Bridge config registers + Optional: "gpio_slave" : GPIO registers to control slot power "apb_csr" : MSI registers diff --git a/dts/Bindings/pci/nvidia,tegra20-pcie.txt b/dts/Bindings/pci/nvidia,tegra20-pcie.txt index 145a4f0419..7939bca478 100644 --- a/dts/Bindings/pci/nvidia,tegra20-pcie.txt +++ b/dts/Bindings/pci/nvidia,tegra20-pcie.txt @@ -65,6 +65,14 @@ Required properties: - afi - pcie_x +Optional properties: +- pinctrl-names: A list of pinctrl state names. Must contain the following + entries: + - "default": active state, puts PCIe I/O out of deep power down state + - "idle": puts PCIe I/O into deep power down state +- pinctrl-0: phandle for the default/active state of pin configurations. +- pinctrl-1: phandle for the idle state of pin configurations. + Required properties on Tegra124 and later (deprecated): - phys: Must contain an entry for each entry in phy-names. - phy-names: Must include the following entries: diff --git a/dts/Bindings/pci/pci.txt b/dts/Bindings/pci/pci.txt index 92c01db610..2a5d910240 100644 --- a/dts/Bindings/pci/pci.txt +++ b/dts/Bindings/pci/pci.txt @@ -24,6 +24,9 @@ driver implementation may support the following properties: unsupported link speed, for instance, trying to do training for unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2' for gen2, and '1' for gen1. Any other values are invalid. +- reset-gpios: + If present this property specifies PERST# GPIO. Host drivers can parse the + GPIO and apply fundamental reset to endpoints. PCI-PCI Bridge properties ------------------------- diff --git a/dts/Bindings/pci/qcom,pcie.txt b/dts/Bindings/pci/qcom,pcie.txt index 1fd703bd73..ada80b01bf 100644 --- a/dts/Bindings/pci/qcom,pcie.txt +++ b/dts/Bindings/pci/qcom,pcie.txt @@ -10,6 +10,7 @@ - "qcom,pcie-msm8996" for msm8996 or apq8096 - "qcom,pcie-ipq4019" for ipq4019 - "qcom,pcie-ipq8074" for ipq8074 + - "qcom,pcie-qcs404" for qcs404 - reg: Usage: required @@ -116,6 +117,15 @@ - "ahb" AHB clock - "aux" Auxiliary clock +- clock-names: + Usage: required for qcs404 + Value type: <stringlist> + Definition: Should contain the following entries + - "iface" AHB clock + - "aux" Auxiliary clock + - "master_bus" AXI Master clock + - "slave_bus" AXI Slave clock + - resets: Usage: required Value type: <prop-encoded-array> @@ -167,6 +177,17 @@ - "ahb" AHB Reset - "axi_m_sticky" AXI Master Sticky reset +- reset-names: + Usage: required for qcs404 + Value type: <stringlist> + Definition: Should contain the following entries + - "axi_m" AXI Master reset + - "axi_s" AXI Slave reset + - "axi_m_sticky" AXI Master Sticky reset + - "pipe_sticky" PIPE sticky reset + - "pwr" PWR reset + - "ahb" AHB reset + - power-domains: Usage: required for apq8084 and msm8996/apq8096 Value type: <prop-encoded-array> @@ -195,12 +216,12 @@ Definition: A phandle to the PCIe endpoint power supply - phys: - Usage: required for apq8084 + Usage: required for apq8084 and qcs404 Value type: <phandle> Definition: List of phandle(s) as listed in phy-names property - phy-names: - Usage: required for apq8084 + Usage: required for apq8084 and qcs404 Value type: <stringlist> Definition: Should contain "pciephy" diff --git a/dts/Bindings/pci/rcar-pci.txt b/dts/Bindings/pci/rcar-pci.txt index 6904882a0e..45bba9f88a 100644 --- a/dts/Bindings/pci/rcar-pci.txt +++ b/dts/Bindings/pci/rcar-pci.txt @@ -3,6 +3,7 @@ Required properties: compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC; "renesas,pcie-r8a7744" for the R8A7744 SoC; + "renesas,pcie-r8a774a1" for the R8A774A1 SoC; "renesas,pcie-r8a774c0" for the R8A774C0 SoC; "renesas,pcie-r8a7779" for the R8A7779 SoC; "renesas,pcie-r8a7790" for the R8A7790 SoC; |