diff options
Diffstat (limited to 'dts/Bindings/pci')
-rw-r--r-- | dts/Bindings/pci/aardvark-pci.txt | 4 | ||||
-rw-r--r-- | dts/Bindings/pci/brcm,stb-pcie.yaml | 2 | ||||
-rw-r--r-- | dts/Bindings/pci/cdns,cdns-pcie-ep.yaml | 2 | ||||
-rw-r--r-- | dts/Bindings/pci/cdns,cdns-pcie-host.yaml | 3 | ||||
-rw-r--r-- | dts/Bindings/pci/cdns-pcie-ep.yaml | 24 | ||||
-rw-r--r-- | dts/Bindings/pci/cdns-pcie-host.yaml | 12 | ||||
-rw-r--r-- | dts/Bindings/pci/cdns-pcie.yaml | 8 | ||||
-rw-r--r-- | dts/Bindings/pci/intel-gw-pcie.yaml | 7 | ||||
-rw-r--r-- | dts/Bindings/pci/loongson.yaml | 62 | ||||
-rw-r--r-- | dts/Bindings/pci/pci-ep.yaml | 9 | ||||
-rw-r--r-- | dts/Bindings/pci/pci-rcar-gen2.txt | 3 | ||||
-rw-r--r-- | dts/Bindings/pci/rcar-pci-ep.yaml | 77 | ||||
-rw-r--r-- | dts/Bindings/pci/rcar-pci.txt | 3 | ||||
-rw-r--r-- | dts/Bindings/pci/socionext,uniphier-pcie-ep.yaml | 92 |
14 files changed, 283 insertions, 25 deletions
diff --git a/dts/Bindings/pci/aardvark-pci.txt b/dts/Bindings/pci/aardvark-pci.txt index 310ef7145c..2b8ca920a7 100644 --- a/dts/Bindings/pci/aardvark-pci.txt +++ b/dts/Bindings/pci/aardvark-pci.txt @@ -19,6 +19,9 @@ contain the following properties: - interrupt-map-mask and interrupt-map: standard PCI properties to define the mapping of the PCIe interface to interrupt numbers. - bus-range: PCI bus numbers covered + - phys: the PCIe PHY handle + - max-link-speed: see pci.txt + - reset-gpios: see pci.txt In addition, the Device Tree describing an Aardvark PCIe controller must include a sub-node that describes the legacy interrupt controller @@ -48,6 +51,7 @@ Example: <0 0 0 2 &pcie_intc 1>, <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; + phys = <&comphy1 0>; pcie_intc: interrupt-controller { interrupt-controller; #interrupt-cells = <1>; diff --git a/dts/Bindings/pci/brcm,stb-pcie.yaml b/dts/Bindings/pci/brcm,stb-pcie.yaml index 77d3e81a43..8680a0f86c 100644 --- a/dts/Bindings/pci/brcm,stb-pcie.yaml +++ b/dts/Bindings/pci/brcm,stb-pcie.yaml @@ -56,6 +56,8 @@ properties: description: Indicates usage of spread-spectrum clocking. type: boolean + aspm-no-l0s: true + required: - reg - dma-ranges diff --git a/dts/Bindings/pci/cdns,cdns-pcie-ep.yaml b/dts/Bindings/pci/cdns,cdns-pcie-ep.yaml index 2996f8d477..50ce5d79d2 100644 --- a/dts/Bindings/pci/cdns,cdns-pcie-ep.yaml +++ b/dts/Bindings/pci/cdns,cdns-pcie-ep.yaml @@ -10,7 +10,7 @@ maintainers: - Tom Joseph <tjoseph@cadence.com> allOf: - - $ref: "cdns-pcie.yaml#" + - $ref: "cdns-pcie-ep.yaml#" - $ref: "pci-ep.yaml#" properties: diff --git a/dts/Bindings/pci/cdns,cdns-pcie-host.yaml b/dts/Bindings/pci/cdns,cdns-pcie-host.yaml index cabbe46ff5..84a8f095d0 100644 --- a/dts/Bindings/pci/cdns,cdns-pcie-host.yaml +++ b/dts/Bindings/pci/cdns,cdns-pcie-host.yaml @@ -45,8 +45,6 @@ examples: #size-cells = <2>; bus-range = <0x0 0xff>; linux,pci-domain = <0>; - cdns,max-outbound-regions = <16>; - cdns,no-bar-match-nbits = <32>; vendor-id = <0x17cd>; device-id = <0x0200>; @@ -57,6 +55,7 @@ examples: ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; #interrupt-cells = <0x1>; diff --git a/dts/Bindings/pci/cdns-pcie-ep.yaml b/dts/Bindings/pci/cdns-pcie-ep.yaml new file mode 100644 index 0000000000..016a5f6159 --- /dev/null +++ b/dts/Bindings/pci/cdns-pcie-ep.yaml @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/pci/cdns-pcie-ep.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence PCIe Device + +maintainers: + - Tom Joseph <tjoseph@cadence.com> + +allOf: + - $ref: "cdns-pcie.yaml#" + +properties: + cdns,max-outbound-regions: + description: maximum number of outbound regions + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 32 + default: 32 + +required: + - cdns,max-outbound-regions diff --git a/dts/Bindings/pci/cdns-pcie-host.yaml b/dts/Bindings/pci/cdns-pcie-host.yaml index ab6e43b636..303078a7b7 100644 --- a/dts/Bindings/pci/cdns-pcie-host.yaml +++ b/dts/Bindings/pci/cdns-pcie-host.yaml @@ -14,14 +14,22 @@ allOf: - $ref: "cdns-pcie.yaml#" properties: + cdns,max-outbound-regions: + description: maximum number of outbound regions + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 32 + default: 32 + deprecated: true + cdns,no-bar-match-nbits: description: Set into the no BAR match register to configure the number of least significant bits kept during inbound (PCIe -> AXI) address translations - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 64 default: 32 + deprecated: true msi-parent: true diff --git a/dts/Bindings/pci/cdns-pcie.yaml b/dts/Bindings/pci/cdns-pcie.yaml index 6887ccc339..02553d5e6c 100644 --- a/dts/Bindings/pci/cdns-pcie.yaml +++ b/dts/Bindings/pci/cdns-pcie.yaml @@ -10,14 +10,6 @@ maintainers: - Tom Joseph <tjoseph@cadence.com> properties: - cdns,max-outbound-regions: - description: maximum number of outbound regions - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 1 - maximum: 32 - default: 32 - phys: description: One per lane if more than one in the list. If only one PHY listed it must diff --git a/dts/Bindings/pci/intel-gw-pcie.yaml b/dts/Bindings/pci/intel-gw-pcie.yaml index 48a98dae00..64b2c64ca8 100644 --- a/dts/Bindings/pci/intel-gw-pcie.yaml +++ b/dts/Bindings/pci/intel-gw-pcie.yaml @@ -71,10 +71,9 @@ properties: max-link-speed: description: Specify PCI Gen for link capability. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [ 1, 2, 3, 4 ] - - default: 1 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3, 4] + default: 1 bus-range: description: Range of bus numbers associated with this controller. diff --git a/dts/Bindings/pci/loongson.yaml b/dts/Bindings/pci/loongson.yaml new file mode 100644 index 0000000000..30e7cf1aeb --- /dev/null +++ b/dts/Bindings/pci/loongson.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/loongson.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson PCI Host Controller + +maintainers: + - Jiaxun Yang <jiaxun.yang@flygoat.com> + +description: |+ + PCI host controller found on Loongson PCHs and SoCs. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + oneOf: + - const: loongson,ls2k-pci + - const: loongson,ls7a-pci + - const: loongson,rs780e-pci + + reg: + minItems: 1 + maxItems: 2 + items: + - description: CFG0 standard config space register + - description: CFG1 extended config space register + + ranges: + minItems: 1 + maxItems: 3 + + +required: + - compatible + - reg + - ranges + +examples: + - | + + bus { + #address-cells = <2>; + #size-cells = <2>; + pcie@1a000000 { + compatible = "loongson,rs780e-pci"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + // CPU_PHYSICAL(2) SIZE(2) + reg = <0x0 0x1a000000 0x0 0x2000000>; + + // BUS_ADDRESS(3) CPU_PHYSICAL(2) SIZE(2) + ranges = <0x01000000 0x0 0x00004000 0x0 0x00004000 0x0 0x00004000>, + <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>; + }; + }; +... diff --git a/dts/Bindings/pci/pci-ep.yaml b/dts/Bindings/pci/pci-ep.yaml index b3df100705..0f8e575ac0 100644 --- a/dts/Bindings/pci/pci-ep.yaml +++ b/dts/Bindings/pci/pci-ep.yaml @@ -18,21 +18,18 @@ properties: max-functions: description: Maximum number of functions that can be configured - allOf: - - $ref: /schemas/types.yaml#/definitions/uint8 + $ref: /schemas/types.yaml#/definitions/uint8 minimum: 1 default: 1 maximum: 255 max-link-speed: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 enum: [ 1, 2, 3, 4 ] num-lanes: description: maximum number of lanes - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 1 default: 1 maximum: 16 diff --git a/dts/Bindings/pci/pci-rcar-gen2.txt b/dts/Bindings/pci/pci-rcar-gen2.txt index b94078f58d..aeba38f0a3 100644 --- a/dts/Bindings/pci/pci-rcar-gen2.txt +++ b/dts/Bindings/pci/pci-rcar-gen2.txt @@ -6,7 +6,8 @@ AHB. There is one bridge instance per USB port connected to the internal OHCI and EHCI controllers. Required properties: -- compatible: "renesas,pci-r8a7743" for the R8A7743 SoC; +- compatible: "renesas,pci-r8a7742" for the R8A7742 SoC; + "renesas,pci-r8a7743" for the R8A7743 SoC; "renesas,pci-r8a7744" for the R8A7744 SoC; "renesas,pci-r8a7745" for the R8A7745 SoC; "renesas,pci-r8a7790" for the R8A7790 SoC; diff --git a/dts/Bindings/pci/rcar-pci-ep.yaml b/dts/Bindings/pci/rcar-pci-ep.yaml new file mode 100644 index 0000000000..aa483c7f27 --- /dev/null +++ b/dts/Bindings/pci/rcar-pci-ep.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car PCIe Endpoint + +maintainers: + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> + - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> + +properties: + compatible: + items: + - const: renesas,r8a774c0-pcie-ep + - const: renesas,rcar-gen3-pcie-ep + + reg: + maxItems: 5 + + reg-names: + items: + - const: apb-base + - const: memory0 + - const: memory1 + - const: memory2 + - const: memory3 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pcie + + max-functions: + minimum: 1 + maximum: 1 + +required: + - compatible + - reg + - reg-names + - resets + - power-domains + - clocks + - clock-names + - max-functions + +examples: + - | + #include <dt-bindings/clock/r8a774c0-cpg-mssr.h> + #include <dt-bindings/power/r8a774c0-sysc.h> + + pcie0_ep: pcie-ep@fe000000 { + compatible = "renesas,r8a774c0-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0xfe000000 0x80000>, + <0xfe100000 0x100000>, + <0xfe200000 0x200000>, + <0x30000000 0x8000000>, + <0x38000000 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + resets = <&cpg 319>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 319>; + clock-names = "pcie"; + max-functions = /bits/ 8 <1>; + }; diff --git a/dts/Bindings/pci/rcar-pci.txt b/dts/Bindings/pci/rcar-pci.txt index 12702c8c46..1041c44a61 100644 --- a/dts/Bindings/pci/rcar-pci.txt +++ b/dts/Bindings/pci/rcar-pci.txt @@ -11,7 +11,8 @@ compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC; "renesas,pcie-r8a7791" for the R8A7791 SoC; "renesas,pcie-r8a7793" for the R8A7793 SoC; "renesas,pcie-r8a7795" for the R8A7795 SoC; - "renesas,pcie-r8a7796" for the R8A7796 SoC; + "renesas,pcie-r8a7796" for the R8A77960 SoC; + "renesas,pcie-r8a77961" for the R8A77961 SoC; "renesas,pcie-r8a77980" for the R8A77980 SoC; "renesas,pcie-r8a77990" for the R8A77990 SoC; "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or diff --git a/dts/Bindings/pci/socionext,uniphier-pcie-ep.yaml b/dts/Bindings/pci/socionext,uniphier-pcie-ep.yaml new file mode 100644 index 0000000000..f0558b9cf9 --- /dev/null +++ b/dts/Bindings/pci/socionext,uniphier-pcie-ep.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier PCIe endpoint controller + +description: | + UniPhier PCIe endpoint controller is based on the Synopsys DesignWare + PCI core. It shares common features with the PCIe DesignWare core and + inherits common properties defined in + Documentation/devicetree/bindings/pci/designware-pcie.txt. + +maintainers: + - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> + +allOf: + - $ref: "pci-ep.yaml#" + +properties: + compatible: + const: socionext,uniphier-pro5-pcie-ep + + reg: + maxItems: 4 + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: link + - const: addr_space + + clocks: + maxItems: 2 + + clock-names: + items: + - const: gio + - const: link + + resets: + maxItems: 2 + + reset-names: + items: + - const: gio + - const: link + + num-ib-windows: + const: 16 + + num-ob-windows: + const: 16 + + num-lanes: true + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + pcie_ep: pcie-ep@66000000 { + compatible = "socionext,uniphier-pro5-pcie-ep"; + reg-names = "dbi", "dbi2", "link", "addr_space"; + reg = <0x66000000 0x1000>, <0x66001000 0x1000>, + <0x66010000 0x10000>, <0x67000000 0x400000>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 24>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 24>; + num-ib-windows = <16>; + num-ob-windows = <16>; + num-lanes = <4>; + phy-names = "pcie-phy"; + phys = <&pcie_phy>; + }; |