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-rw-r--r--dts/Bindings/perf/amlogic,g12-ddr-pmu.yaml54
-rw-r--r--dts/Bindings/perf/arm,ccn.yaml40
-rw-r--r--dts/Bindings/perf/arm,cmn.yaml24
-rw-r--r--dts/Bindings/perf/arm,dsu-pmu.yaml44
-rw-r--r--dts/Bindings/perf/arm,smmu-v3-pmcg.yaml70
-rw-r--r--dts/Bindings/perf/arm-ccn.txt23
-rw-r--r--dts/Bindings/perf/fsl-imx-ddr.yaml6
-rw-r--r--dts/Bindings/perf/marvell-cn10k-ddr.yaml37
-rw-r--r--dts/Bindings/perf/marvell-cn10k-tad.yaml63
-rw-r--r--dts/Bindings/perf/nds32v3-pmu.txt17
-rw-r--r--dts/Bindings/perf/riscv,pmu.yaml160
-rw-r--r--dts/Bindings/perf/spe-pmu.yaml40
12 files changed, 531 insertions, 47 deletions
diff --git a/dts/Bindings/perf/amlogic,g12-ddr-pmu.yaml b/dts/Bindings/perf/amlogic,g12-ddr-pmu.yaml
new file mode 100644
index 0000000000..4adab01491
--- /dev/null
+++ b/dts/Bindings/perf/amlogic,g12-ddr-pmu.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/amlogic,g12-ddr-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic G12 DDR performance monitor
+
+maintainers:
+ - Jiucheng Xu <jiucheng.xu@amlogic.com>
+
+description: |
+ Amlogic G12 series SoC integrate DDR bandwidth monitor.
+ A timer is inside and can generate interrupt when timeout.
+ The bandwidth is counted in the timer ISR. Different platform
+ has different subset of event format attribute.
+
+properties:
+ compatible:
+ enum:
+ - amlogic,g12a-ddr-pmu
+ - amlogic,g12b-ddr-pmu
+ - amlogic,sm1-ddr-pmu
+
+ reg:
+ items:
+ - description: DMC bandwidth register space.
+ - description: DMC PLL register space.
+
+ interrupts:
+ items:
+ - description: The IRQ of the inside timer timeout.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ pmu {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pmu@ff638000 {
+ compatible = "amlogic,g12a-ddr-pmu";
+ reg = <0x0 0xff638000 0x0 0x100>,
+ <0x0 0xff638c00 0x0 0x100>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
diff --git a/dts/Bindings/perf/arm,ccn.yaml b/dts/Bindings/perf/arm,ccn.yaml
new file mode 100644
index 0000000000..0b0bb20910
--- /dev/null
+++ b/dts/Bindings/perf/arm,ccn.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/arm,ccn.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM CCN (Cache Coherent Network) Performance Monitors
+
+maintainers:
+ - Robin Murphy <robin.murphy@arm.com>
+
+properties:
+ compatible:
+ enum:
+ - arm,ccn-502
+ - arm,ccn-504
+ - arm,ccn-508
+ - arm,ccn-512
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ ccn@20000000 {
+ compatible = "arm,ccn-504";
+ reg = <0x20000000 0x1000000>;
+ interrupts = <0 181 4>;
+ };
+...
diff --git a/dts/Bindings/perf/arm,cmn.yaml b/dts/Bindings/perf/arm,cmn.yaml
index e4fcc0de25..2e51072e79 100644
--- a/dts/Bindings/perf/arm,cmn.yaml
+++ b/dts/Bindings/perf/arm,cmn.yaml
@@ -12,16 +12,19 @@ maintainers:
properties:
compatible:
- const: arm,cmn-600
+ enum:
+ - arm,cmn-600
+ - arm,cmn-650
+ - arm,cmn-700
+ - arm,ci-700
reg:
items:
- description: Physical address of the base (PERIPHBASE) and
- size (up to 64MB) of the configuration address space.
+ size of the configuration address space.
interrupts:
minItems: 1
- maxItems: 4
items:
- description: Overflow interrupt for DTC0
- description: Overflow interrupt for DTC1
@@ -32,14 +35,23 @@ properties:
arm,root-node:
$ref: /schemas/types.yaml#/definitions/uint32
- description: Offset from PERIPHBASE of the configuration
- discovery node (see TRM definition of ROOTNODEBASE).
+ description: Offset from PERIPHBASE of CMN-600's configuration
+ discovery node (see TRM definition of ROOTNODEBASE). Not
+ relevant for newer CMN/CI products.
required:
- compatible
- reg
- interrupts
- - arm,root-node
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: arm,cmn-600
+then:
+ required:
+ - arm,root-node
additionalProperties: false
diff --git a/dts/Bindings/perf/arm,dsu-pmu.yaml b/dts/Bindings/perf/arm,dsu-pmu.yaml
new file mode 100644
index 0000000000..a740378ed5
--- /dev/null
+++ b/dts/Bindings/perf/arm,dsu-pmu.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2021 Arm Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
+
+maintainers:
+ - Suzuki K Poulose <suzuki.poulose@arm.com>
+ - Robin Murphy <robin.murphy@arm.com>
+
+description:
+ ARM DynamIQ Shared Unit (DSU) integrates one or more CPU cores with a shared
+ L3 memory system, control logic and external interfaces to form a multicore
+ cluster. The PMU enables gathering various statistics on the operation of the
+ DSU. The PMU provides independent 32-bit counters that can count any of the
+ supported events, along with a 64-bit cycle counter. The PMU is accessed via
+ CPU system registers and has no MMIO component.
+
+properties:
+ compatible:
+ oneOf:
+ - const: arm,dsu-pmu
+ - items:
+ - const: arm,dsu-110-pmu
+ - const: arm,dsu-pmu
+
+ interrupts:
+ items:
+ - description: nCLUSTERPMUIRQ interrupt
+
+ cpus:
+ minItems: 1
+ maxItems: 12
+ description: List of phandles for the CPUs connected to this DSU instance.
+
+required:
+ - compatible
+ - interrupts
+ - cpus
+
+additionalProperties: false
diff --git a/dts/Bindings/perf/arm,smmu-v3-pmcg.yaml b/dts/Bindings/perf/arm,smmu-v3-pmcg.yaml
new file mode 100644
index 0000000000..a4b53a6a1e
--- /dev/null
+++ b/dts/Bindings/perf/arm,smmu-v3-pmcg.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/arm,smmu-v3-pmcg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm SMMUv3 Performance Monitor Counter Group
+
+maintainers:
+ - Will Deacon <will@kernel.org>
+ - Robin Murphy <robin.murphy@arm.com>
+
+description: |
+ An SMMUv3 may have several Performance Monitor Counter Group (PMCG).
+ They are standalone performance monitoring units that support both
+ architected and IMPLEMENTATION DEFINED event counters.
+
+properties:
+ $nodename:
+ pattern: "^pmu@[0-9a-f]*"
+ compatible:
+ oneOf:
+ - items:
+ - const: arm,mmu-600-pmcg
+ - const: arm,smmu-v3-pmcg
+ - const: arm,smmu-v3-pmcg
+
+ reg:
+ items:
+ - description: Register page 0
+ - description: Register page 1, if SMMU_PMCG_CFGR.RELOC_CTRS = 1
+ minItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ msi-parent: true
+
+required:
+ - compatible
+ - reg
+
+anyOf:
+ - required:
+ - interrupts
+ - required:
+ - msi-parent
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ pmu@2b420000 {
+ compatible = "arm,smmu-v3-pmcg";
+ reg = <0x2b420000 0x1000>,
+ <0x2b430000 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>;
+ msi-parent = <&its 0xff0000>;
+ };
+
+ pmu@2b440000 {
+ compatible = "arm,smmu-v3-pmcg";
+ reg = <0x2b440000 0x1000>,
+ <0x2b450000 0x1000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>;
+ msi-parent = <&its 0xff0000>;
+ };
diff --git a/dts/Bindings/perf/arm-ccn.txt b/dts/Bindings/perf/arm-ccn.txt
deleted file mode 100644
index 1c53b5aa33..0000000000
--- a/dts/Bindings/perf/arm-ccn.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-* ARM CCN (Cache Coherent Network)
-
-Required properties:
-
-- compatible: (standard compatible string) should be one of:
- "arm,ccn-502"
- "arm,ccn-504"
- "arm,ccn-508"
- "arm,ccn-512"
-
-- reg: (standard registers property) physical address and size
- (16MB) of the configuration registers block
-
-- interrupts: (standard interrupt property) single interrupt
- generated by the control block
-
-Example:
-
- ccn@2000000000 {
- compatible = "arm,ccn-504";
- reg = <0x20 0x00000000 0 0x1000000>;
- interrupts = <0 181 4>;
- };
diff --git a/dts/Bindings/perf/fsl-imx-ddr.yaml b/dts/Bindings/perf/fsl-imx-ddr.yaml
index 80a9238536..6c96a4204e 100644
--- a/dts/Bindings/perf/fsl-imx-ddr.yaml
+++ b/dts/Bindings/perf/fsl-imx-ddr.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Freescale(NXP) IMX8 DDR performance monitor
+title: Freescale(NXP) IMX8/9 DDR performance monitor
maintainers:
- Frank Li <frank.li@nxp.com>
@@ -19,6 +19,7 @@ properties:
- fsl,imx8mm-ddr-pmu
- fsl,imx8mn-ddr-pmu
- fsl,imx8mp-ddr-pmu
+ - fsl,imx93-ddr-pmu
- items:
- enum:
- fsl,imx8mm-ddr-pmu
@@ -26,6 +27,9 @@ properties:
- fsl,imx8mq-ddr-pmu
- fsl,imx8mp-ddr-pmu
- const: fsl,imx8m-ddr-pmu
+ - items:
+ - const: fsl,imx8dxl-ddr-pmu
+ - const: fsl,imx8-ddr-pmu
reg:
maxItems: 1
diff --git a/dts/Bindings/perf/marvell-cn10k-ddr.yaml b/dts/Bindings/perf/marvell-cn10k-ddr.yaml
new file mode 100644
index 0000000000..a18dd0a8c4
--- /dev/null
+++ b/dts/Bindings/perf/marvell-cn10k-ddr.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/marvell-cn10k-ddr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell CN10K DDR performance monitor
+
+maintainers:
+ - Bharat Bhushan <bbhushan2@marvell.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - marvell,cn10k-ddr-pmu
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pmu@87e1c0000000 {
+ compatible = "marvell,cn10k-ddr-pmu";
+ reg = <0x87e1 0xc0000000 0x0 0x10000>;
+ };
+ };
diff --git a/dts/Bindings/perf/marvell-cn10k-tad.yaml b/dts/Bindings/perf/marvell-cn10k-tad.yaml
new file mode 100644
index 0000000000..3621422526
--- /dev/null
+++ b/dts/Bindings/perf/marvell-cn10k-tad.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/marvell-cn10k-tad.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell CN10K LLC-TAD performance monitor
+
+maintainers:
+ - Bhaskara Budiredla <bbudiredla@marvell.com>
+
+description: |
+ The Tag-and-Data units (TADs) maintain coherence and contain CN10K
+ shared on-chip last level cache (LLC). The tad pmu measures the
+ performance of last-level cache. Each tad pmu supports up to eight
+ counters.
+
+ The DT setup comprises of number of tad blocks, the sizes of pmu
+ regions, tad blocks and overall base address of the HW.
+
+properties:
+ compatible:
+ const: marvell,cn10k-tad-pmu
+
+ reg:
+ maxItems: 1
+
+ marvell,tad-cnt:
+ description: specifies the number of tads on the soc
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ marvell,tad-page-size:
+ description: specifies the size of each tad page
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ marvell,tad-pmu-page-size:
+ description: specifies the size of page that the pmu uses
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+required:
+ - compatible
+ - reg
+ - marvell,tad-cnt
+ - marvell,tad-page-size
+ - marvell,tad-pmu-page-size
+
+additionalProperties: false
+
+examples:
+ - |
+
+ tad {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ tad_pmu@80000000 {
+ compatible = "marvell,cn10k-tad-pmu";
+ reg = <0x87e2 0x80000000 0x0 0x1000>;
+ marvell,tad-cnt = <1>;
+ marvell,tad-page-size = <0x1000>;
+ marvell,tad-pmu-page-size = <0x1000>;
+ };
+ };
diff --git a/dts/Bindings/perf/nds32v3-pmu.txt b/dts/Bindings/perf/nds32v3-pmu.txt
deleted file mode 100644
index 1bd15785b4..0000000000
--- a/dts/Bindings/perf/nds32v3-pmu.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-* NDS32 Performance Monitor Units
-
-NDS32 core have a PMU for counting cpu and cache events like cache misses.
-The NDS32 PMU representation in the device tree should be done as under:
-
-Required properties:
-
-- compatible :
- "andestech,nds32v3-pmu"
-
-- interrupts : The interrupt number for NDS32 PMU is 13.
-
-Example:
-pmu{
- compatible = "andestech,nds32v3-pmu";
- interrupts = <13>;
-}
diff --git a/dts/Bindings/perf/riscv,pmu.yaml b/dts/Bindings/perf/riscv,pmu.yaml
new file mode 100644
index 0000000000..d01c677ad3
--- /dev/null
+++ b/dts/Bindings/perf/riscv,pmu.yaml
@@ -0,0 +1,160 @@
+# SPDX-License-Identifier: BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V SBI PMU events
+
+maintainers:
+ - Atish Patra <atishp@rivosinc.com>
+
+description: |
+ The SBI PMU extension allows supervisor software to configure, start and
+ stop any performance counter at anytime. Thus, a user can leverage all
+ capabilities of performance analysis tools, such as perf, if the SBI PMU
+ extension is enabled. The following constraints apply:
+
+ The platform must provide information about PMU event to counter mappings
+ either via device tree or another way, specific to the platform.
+ Without the event to counter mappings, the SBI PMU extension cannot be used.
+
+ Platforms should provide information about the PMU event selector values
+ that should be encoded in the expected value of MHPMEVENTx while configuring
+ MHPMCOUNTERx for that specific event. The can either be done via device tree
+ or another way, specific to the platform.
+ The exact value to be written to MHPMEVENTx is completely dependent on the
+ platform.
+
+ For information on the SBI specification see the section "Performance
+ Monitoring Unit Extension" of:
+ https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
+
+properties:
+ compatible:
+ const: riscv,pmu
+
+ riscv,event-to-mhpmevent:
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ description:
+ Represents an ONE-to-ONE mapping between a PMU event and the event
+ selector value that the platform expects to be written to the MHPMEVENTx
+ CSR for that event.
+ The mapping is encoded in an matrix format where each element represents
+ an event.
+ This property shouldn't encode any raw hardware event.
+ items:
+ items:
+ - description: event_idx, a 20-bit wide encoding of the event type and
+ code. Refer to the SBI specification for a complete description of
+ the event types and codes.
+ - description: upper 32 bits of the event selector value for MHPMEVENTx
+ - description: lower 32 bits of the event selector value for MHPMEVENTx
+
+ riscv,event-to-mhpmcounters:
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ description:
+ Represents a MANY-to-MANY mapping between a range of events and all the
+ MHPMCOUNTERx in a bitmap format that can be used to monitor these range
+ of events. The information is encoded in an matrix format where each
+ element represents a certain range of events and corresponding counters.
+ This property shouldn't encode any raw event.
+ items:
+ items:
+ - description: first event_idx of the range of events
+ - description: last event_idx of the range of events
+ - description: bitmap of MHPMCOUNTERx for this event
+
+ riscv,raw-event-to-mhpmcounters:
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ description:
+ Represents an ONE-to-MANY or MANY-to-MANY mapping between the rawevent(s)
+ and all the MHPMCOUNTERx in a bitmap format that can be used to monitor
+ that raw event.
+ The encoding of the raw events are platform specific. The information is
+ encoded in a matrix format where each element represents the specific raw
+ event(s).
+ If a platform directly encodes each raw PMU event as a unique ID, the
+ value of variant must be 0xffffffff_ffffffff.
+ items:
+ items:
+ - description:
+ upper 32 invariant bits for the range of events
+ - description:
+ lower 32 invariant bits for the range of events
+ - description:
+ upper 32 bits of the variant bit mask for the range of events
+ - description:
+ lower 32 bits of the variant bit mask for the range of events
+ - description:
+ bitmap of all MHPMCOUNTERx that can monitor the range of events
+
+dependencies:
+ riscv,event-to-mhpmevent: [ "riscv,event-to-mhpmcounters" ]
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ pmu {
+ compatible = "riscv,pmu";
+ riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
+ riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
+ <0x00002 0x00002 0x00000004>,
+ <0x00003 0x0000A 0x00000ff8>,
+ <0x10000 0x10033 0x000ff000>;
+ riscv,raw-event-to-mhpmcounters =
+ /* For event ID 0x0002 */
+ <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
+ /* For event ID 0-4 */
+ <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
+ /* For event ID 0xffffffff0000000f - 0xffffffff000000ff */
+ <0xffffffff 0x0 0xffffffff 0xffffff0f 0x00000ff0>;
+ };
+
+ - |
+ /*
+ * For HiFive Unmatched board the encodings can be found here
+ * https://sifive.cdn.prismic.io/sifive/1a82e600-1f93-4f41-b2d8-86ed8b16acba_fu740-c000-manual-v1p6.pdf
+ *
+ * This example also binds standard SBI PMU hardware IDs to U74 PMU event
+ * codes, U74 uses a bitfield for events encoding, so several U74 events
+ * can be bound to a single perf ID.
+ * See SBI PMU hardware IDs in arch/riscv/include/asm/sbi.h
+ */
+ pmu {
+ compatible = "riscv,pmu";
+ riscv,event-to-mhpmevent =
+ /* SBI_PMU_HW_CACHE_REFERENCES -> Instruction or Data cache/ITIM busy */
+ <0x00003 0x00000000 0x1801>,
+ /* SBI_PMU_HW_CACHE_MISSES -> Instruction or Data cache miss or MMIO access */
+ <0x00004 0x00000000 0x0302>,
+ /* SBI_PMU_HW_BRANCH_INSTRUCTIONS -> Conditional branch retired */
+ <0x00005 0x00000000 0x4000>,
+ /* SBI_PMU_HW_BRANCH_MISSES -> Branch or jump misprediction */
+ <0x00006 0x00000000 0x6001>,
+ /* L1D_READ_MISS -> Data cache miss or MMIO access */
+ <0x10001 0x00000000 0x0202>,
+ /* L1D_WRITE_ACCESS -> Data cache write-back */
+ <0x10002 0x00000000 0x0402>,
+ /* L1I_READ_ACCESS -> Instruction cache miss */
+ <0x10009 0x00000000 0x0102>,
+ /* LL_READ_MISS -> UTLB miss */
+ <0x10011 0x00000000 0x2002>,
+ /* DTLB_READ_MISS -> Data TLB miss */
+ <0x10019 0x00000000 0x1002>,
+ /* ITLB_READ_MISS-> Instruction TLB miss */
+ <0x10021 0x00000000 0x0802>;
+ riscv,event-to-mhpmcounters = <0x00003 0x00006 0x18>,
+ <0x10001 0x10002 0x18>,
+ <0x10009 0x10009 0x18>,
+ <0x10011 0x10011 0x18>,
+ <0x10019 0x10019 0x18>,
+ <0x10021 0x10021 0x18>;
+ riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xfc0000ff 0x18>,
+ <0x0 0x1 0xffffffff 0xfff800ff 0x18>,
+ <0x0 0x2 0xffffffff 0xffffe0ff 0x18>;
+ };
diff --git a/dts/Bindings/perf/spe-pmu.yaml b/dts/Bindings/perf/spe-pmu.yaml
new file mode 100644
index 0000000000..7d74152f43
--- /dev/null
+++ b/dts/Bindings/perf/spe-pmu.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/spe-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU)
+
+maintainers:
+ - Will Deacon <will@kernel.org>
+
+description:
+ ARMv8.2 introduces the optional Statistical Profiling Extension for collecting
+ performance sample data using an in-memory trace buffer.
+
+properties:
+ compatible:
+ const: arm,statistical-profiling-extension-v1
+
+ interrupts:
+ maxItems: 1
+ description: |
+ The PPI to signal SPE events. For heterogeneous systems where SPE is only
+ supported on a subset of the CPUs, please consult the arm,gic-v3 binding
+ for details on describing a PPI partition.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - interrupts
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ spe-pmu {
+ compatible = "arm,statistical-profiling-extension-v1";
+ interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ };