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-rw-r--r--dts/Bindings/phy/phy-tegra194-p2u.yaml21
1 files changed, 15 insertions, 6 deletions
diff --git a/dts/Bindings/phy/phy-tegra194-p2u.yaml b/dts/Bindings/phy/phy-tegra194-p2u.yaml
index 9a89d05efb..4790c6238a 100644
--- a/dts/Bindings/phy/phy-tegra194-p2u.yaml
+++ b/dts/Bindings/phy/phy-tegra194-p2u.yaml
@@ -1,10 +1,10 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: NVIDIA Tegra194 P2U binding
+title: NVIDIA Tegra194 & Tegra234 P2U
maintainers:
- Thierry Reding <treding@nvidia.com>
@@ -12,13 +12,17 @@ maintainers:
description: >
Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
Speed) each interfacing with 12 and 8 P2U instances respectively.
+ Tegra234 has three PHY bricks namely HSIO, NVHS and GBE (Gigabit Ethernet)
+ each interfacing with 8, 8 and 8 P2U instances respectively.
A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE
- interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe
- lane.
+ interface and PHY of HSIO/NVHS/GBE bricks. Each P2U instance represents one
+ PCIe lane.
properties:
compatible:
- const: nvidia,tegra194-p2u
+ enum:
+ - nvidia,tegra194-p2u
+ - nvidia,tegra234-p2u
reg:
maxItems: 1
@@ -28,6 +32,11 @@ properties:
items:
- const: ctl
+ nvidia,skip-sz-protect-en:
+ description: Should be present if two PCIe retimers are present between
+ the root port and its immediate downstream device.
+ type: boolean
+
'#phy-cells':
const: 0