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-rw-r--r--dts/Bindings/phy/samsung,exynos-pcie-phy.yaml6
1 files changed, 3 insertions, 3 deletions
diff --git a/dts/Bindings/phy/samsung,exynos-pcie-phy.yaml b/dts/Bindings/phy/samsung,exynos-pcie-phy.yaml
index ac0af40be5..41df8bb08f 100644
--- a/dts/Bindings/phy/samsung,exynos-pcie-phy.yaml
+++ b/dts/Bindings/phy/samsung,exynos-pcie-phy.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/phy/samsung,exynos-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Samsung SoC series PCIe PHY Device Tree Bindings
+title: Samsung SoC series PCIe PHY
maintainers:
- Marek Szyprowski <m.szyprowski@samsung.com>
@@ -21,12 +21,12 @@ properties:
maxItems: 1
samsung,pmu-syscon:
- $ref: '/schemas/types.yaml#/definitions/phandle'
+ $ref: /schemas/types.yaml#/definitions/phandle
description: phandle for PMU system controller interface, used to
control PMU registers bits for PCIe PHY
samsung,fsys-sysreg:
- $ref: '/schemas/types.yaml#/definitions/phandle'
+ $ref: /schemas/types.yaml#/definitions/phandle
description: phandle for FSYS sysreg interface, used to control
sysreg registers bits for PCIe PHY