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-rw-r--r--dts/Bindings/phy/cdns,dphy.txt20
-rw-r--r--dts/Bindings/phy/phy-armada38x-comphy.txt40
-rw-r--r--dts/Bindings/phy/phy-mvebu-comphy.txt65
-rw-r--r--dts/Bindings/phy/phy-mvebu-utmi.txt38
-rw-r--r--dts/Bindings/phy/phy-rockchip-inno-usb2.txt2
-rw-r--r--dts/Bindings/phy/qcom-qmp-phy.txt9
-rw-r--r--dts/Bindings/phy/qcom-qusb2-phy.txt1
-rw-r--r--dts/Bindings/phy/rcar-gen3-phy-usb2.txt2
-rw-r--r--dts/Bindings/phy/ti-phy.txt1
9 files changed, 166 insertions, 12 deletions
diff --git a/dts/Bindings/phy/cdns,dphy.txt b/dts/Bindings/phy/cdns,dphy.txt
new file mode 100644
index 0000000..1095bc4
--- /dev/null
+++ b/dts/Bindings/phy/cdns,dphy.txt
@@ -0,0 +1,20 @@
+Cadence DPHY
+============
+
+Cadence DPHY block.
+
+Required properties:
+- compatible: should be set to "cdns,dphy".
+- reg: physical base address and length of the DPHY registers.
+- clocks: DPHY reference clocks.
+- clock-names: must contain "psm" and "pll_ref".
+- #phy-cells: must be set to 0.
+
+Example:
+ dphy0: dphy@fd0e0000{
+ compatible = "cdns,dphy";
+ reg = <0x0 0xfd0e0000 0x0 0x1000>;
+ clocks = <&psm_clk>, <&pll_ref_clk>;
+ clock-names = "psm", "pll_ref";
+ #phy-cells = <0>;
+ };
diff --git a/dts/Bindings/phy/phy-armada38x-comphy.txt b/dts/Bindings/phy/phy-armada38x-comphy.txt
new file mode 100644
index 0000000..ad49e5c
--- /dev/null
+++ b/dts/Bindings/phy/phy-armada38x-comphy.txt
@@ -0,0 +1,40 @@
+mvebu armada 38x comphy driver
+------------------------------
+
+This comphy controller can be found on Marvell Armada 38x. It provides a
+number of shared PHYs used by various interfaces (network, sata, usb,
+PCIe...).
+
+Required properties:
+
+- compatible: should be "marvell,armada-380-comphy"
+- reg: should contain the comphy register location and length.
+- #address-cells: should be 1.
+- #size-cells: should be 0.
+
+A sub-node is required for each comphy lane provided by the comphy.
+
+Required properties (child nodes):
+
+- reg: comphy lane number.
+- #phy-cells : from the generic phy bindings, must be 1. Defines the
+ input port to use for a given comphy lane.
+
+Example:
+
+ comphy: phy@18300 {
+ compatible = "marvell,armada-380-comphy";
+ reg = <0x18300 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpm_comphy0: phy@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+
+ cpm_comphy1: phy@1 {
+ reg = <1>;
+ #phy-cells = <1>;
+ };
+ };
diff --git a/dts/Bindings/phy/phy-mvebu-comphy.txt b/dts/Bindings/phy/phy-mvebu-comphy.txt
index bfcf803..cf2cd86 100644
--- a/dts/Bindings/phy/phy-mvebu-comphy.txt
+++ b/dts/Bindings/phy/phy-mvebu-comphy.txt
@@ -1,16 +1,27 @@
-mvebu comphy driver
--------------------
+MVEBU comphy drivers
+--------------------
-A comphy controller can be found on Marvell Armada 7k/8k on the CP110. It
-provides a number of shared PHYs used by various interfaces (network, sata,
-usb, PCIe...).
+COMPHY controllers can be found on the following Marvell MVEBU SoCs:
+* Armada 7k/8k (on the CP110)
+* Armada 3700
+It provides a number of shared PHYs used by various interfaces (network, SATA,
+USB, PCIe...).
Required properties:
-- compatible: should be "marvell,comphy-cp110"
-- reg: should contain the comphy register location and length.
-- marvell,system-controller: should contain a phandle to the
- system controller node.
+- compatible: should be one of:
+ * "marvell,comphy-cp110" for Armada 7k/8k
+ * "marvell,comphy-a3700" for Armada 3700
+- reg: should contain the COMPHY register(s) location(s) and length(s).
+ * 1 entry for Armada 7k/8k
+ * 4 entries for Armada 3700 along with the corresponding reg-names
+ properties, memory areas are:
+ * Generic COMPHY registers
+ * Lane 1 (PCIe/GbE)
+ * Lane 0 (USB3/GbE)
+ * Lane 2 (SATA/USB3)
+- marvell,system-controller: should contain a phandle to the system
+ controller node (only for Armada 7k/8k)
- #address-cells: should be 1.
- #size-cells: should be 0.
@@ -18,11 +29,11 @@ A sub-node is required for each comphy lane provided by the comphy.
Required properties (child nodes):
-- reg: comphy lane number.
-- #phy-cells : from the generic phy bindings, must be 1. Defines the
+- reg: COMPHY lane number.
+- #phy-cells : from the generic PHY bindings, must be 1. Defines the
input port to use for a given comphy lane.
-Example:
+Examples:
cpm_comphy: phy@120000 {
compatible = "marvell,comphy-cp110";
@@ -41,3 +52,33 @@ Example:
#phy-cells = <1>;
};
};
+
+ comphy: phy@18300 {
+ compatible = "marvell,comphy-a3700";
+ reg = <0x18300 0x300>,
+ <0x1F000 0x400>,
+ <0x5C000 0x400>,
+ <0xe0178 0x8>;
+ reg-names = "comphy",
+ "lane1_pcie_gbe",
+ "lane0_usb3_gbe",
+ "lane2_sata_usb3";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+
+ comphy0: phy@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+
+ comphy1: phy@1 {
+ reg = <1>;
+ #phy-cells = <1>;
+ };
+
+ comphy2: phy@2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
+ };
diff --git a/dts/Bindings/phy/phy-mvebu-utmi.txt b/dts/Bindings/phy/phy-mvebu-utmi.txt
new file mode 100644
index 0000000..aa99cee
--- /dev/null
+++ b/dts/Bindings/phy/phy-mvebu-utmi.txt
@@ -0,0 +1,38 @@
+MVEBU A3700 UTMI PHY
+--------------------
+
+USB2 UTMI+ PHY controllers can be found on the following Marvell MVEBU SoCs:
+* Armada 3700
+
+On Armada 3700, there are two USB controllers, one is compatible with the USB2
+and USB3 specifications and supports OTG. The other one is USB2 compliant and
+only supports host mode. Both of these controllers come with a slightly
+different UTMI PHY.
+
+Required Properties:
+
+- compatible: Should be one of:
+ * "marvell,a3700-utmi-host-phy" for the PHY connected to
+ the USB2 host-only controller.
+ * "marvell,a3700-utmi-otg-phy" for the PHY connected to
+ the USB3 and USB2 OTG capable controller.
+- reg: PHY IP register range.
+- marvell,usb-misc-reg: handle on the "USB miscellaneous registers" shared
+ region covering registers related to both the host
+ controller and the PHY.
+- #phy-cells: Standard property (Documentation: phy-bindings.txt) Should be 0.
+
+
+Example:
+
+ usb2_utmi_host_phy: phy@5f000 {
+ compatible = "marvell,armada-3700-utmi-host-phy";
+ reg = <0x5f000 0x800>;
+ marvell,usb-misc-reg = <&usb2_syscon>;
+ #phy-cells = <0>;
+ };
+
+ usb2_syscon: system-controller@5f800 {
+ compatible = "marvell,armada-3700-usb2-host-misc", "syscon";
+ reg = <0x5f800 0x800>;
+ };
diff --git a/dts/Bindings/phy/phy-rockchip-inno-usb2.txt b/dts/Bindings/phy/phy-rockchip-inno-usb2.txt
index 074a7b3..00639ba 100644
--- a/dts/Bindings/phy/phy-rockchip-inno-usb2.txt
+++ b/dts/Bindings/phy/phy-rockchip-inno-usb2.txt
@@ -23,6 +23,8 @@ Optional properties:
register files". When set driver will request its
phandle as one companion-grf for some special SoCs
(e.g RV1108).
+ - extcon : phandle to the extcon device providing the cable state for
+ the otg phy.
Required nodes : a sub-node is required for each port the phy provides.
The sub-node name is used to identify host or otg port,
diff --git a/dts/Bindings/phy/qcom-qmp-phy.txt b/dts/Bindings/phy/qcom-qmp-phy.txt
index 41a1074..5d181fc 100644
--- a/dts/Bindings/phy/qcom-qmp-phy.txt
+++ b/dts/Bindings/phy/qcom-qmp-phy.txt
@@ -9,6 +9,8 @@ Required properties:
"qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
"qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
"qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
+ "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998,
+ "qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998,
"qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
"qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
"qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845.
@@ -42,6 +44,10 @@ Required properties:
"aux", "cfg_ahb", "ref".
For "qcom,msm8996-qmp-usb3-phy" must contain:
"aux", "cfg_ahb", "ref".
+ For "qcom,msm8998-qmp-usb3-phy" must contain:
+ "aux", "cfg_ahb", "ref".
+ For "qcom,msm8998-qmp-ufs-phy" must contain:
+ "ref", "ref_aux".
For "qcom,sdm845-qmp-usb3-phy" must contain:
"aux", "cfg_ahb", "ref", "com_aux".
For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
@@ -61,6 +67,9 @@ Required properties:
"phy", "common", "cfg".
For "qcom,msm8996-qmp-usb3-phy" must contain
"phy", "common".
+ For "qcom,msm8998-qmp-usb3-phy" must contain
+ "phy", "common".
+ For "qcom,msm8998-qmp-ufs-phy": no resets are listed.
For "qcom,sdm845-qmp-usb3-phy" must contain:
"phy", "common".
For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
diff --git a/dts/Bindings/phy/qcom-qusb2-phy.txt b/dts/Bindings/phy/qcom-qusb2-phy.txt
index 03025d9..fe29f9e 100644
--- a/dts/Bindings/phy/qcom-qusb2-phy.txt
+++ b/dts/Bindings/phy/qcom-qusb2-phy.txt
@@ -6,6 +6,7 @@ QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
Required properties:
- compatible: compatible list, contains
"qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996,
+ "qcom,msm8998-qusb2-phy" for 10nm PHY on msm8998,
"qcom,sdm845-qusb2-phy" for 10nm PHY on sdm845.
- reg: offset and length of the PHY register set.
diff --git a/dts/Bindings/phy/rcar-gen3-phy-usb2.txt b/dts/Bindings/phy/rcar-gen3-phy-usb2.txt
index de7b539..ad9c290 100644
--- a/dts/Bindings/phy/rcar-gen3-phy-usb2.txt
+++ b/dts/Bindings/phy/rcar-gen3-phy-usb2.txt
@@ -6,6 +6,8 @@ This file provides information on what the device node for the R-Car generation
Required properties:
- compatible: "renesas,usb2-phy-r8a774a1" if the device is a part of an R8A774A1
SoC.
+ "renesas,usb2-phy-r8a774c0" if the device is a part of an R8A774C0
+ SoC.
"renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795
SoC.
"renesas,usb2-phy-r8a7796" if the device is a part of an R8A7796
diff --git a/dts/Bindings/phy/ti-phy.txt b/dts/Bindings/phy/ti-phy.txt
index 57dfda8..8f93c3b 100644
--- a/dts/Bindings/phy/ti-phy.txt
+++ b/dts/Bindings/phy/ti-phy.txt
@@ -35,6 +35,7 @@ Required properties:
DRA7x
Should be "ti,dra7x-usb2-phy2" for the 2nd instance of USB2 PHY
in DRA7x
+ Should be "ti,am654-usb2" for the USB2 PHYs on AM654.
- reg : Address and length of the register set for the device.
- #phy-cells: determine the number of cells that should be given in the
phandle while referencing this phy.