diff options
Diffstat (limited to 'dts/Bindings/phy')
| -rw-r--r-- | dts/Bindings/phy/amlogic,axg-mipi-dphy.yaml | 70 | ||||
| -rw-r--r-- | dts/Bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml | 21 | ||||
| -rw-r--r-- | dts/Bindings/phy/brcm,sata-phy.yaml | 148 | ||||
| -rw-r--r-- | dts/Bindings/phy/brcm-sata-phy.txt | 58 | ||||
| -rw-r--r-- | dts/Bindings/phy/ingenic,phy-usb.yaml | 58 | ||||
| -rw-r--r-- | dts/Bindings/phy/intel,phy-keembay-usb.yaml | 44 | ||||
| -rw-r--r-- | dts/Bindings/phy/marvell,mmp3-hsic-phy.yaml | 9 | ||||
| -rw-r--r-- | dts/Bindings/phy/mediatek,mt7621-pci-phy.yaml | 36 | ||||
| -rw-r--r-- | dts/Bindings/phy/phy-cadence-sierra.txt | 70 | ||||
| -rw-r--r-- | dts/Bindings/phy/phy-cadence-sierra.yaml | 152 | ||||
| -rw-r--r-- | dts/Bindings/phy/phy-stm32-usbphyc.txt | 73 | ||||
| -rw-r--r-- | dts/Bindings/phy/phy-stm32-usbphyc.yaml | 138 | ||||
| -rw-r--r-- | dts/Bindings/phy/qcom,qmp-phy.yaml | 6 | ||||
| -rw-r--r-- | dts/Bindings/phy/rockchip-emmc-phy.txt | 5 | ||||
| -rw-r--r-- | dts/Bindings/phy/samsung,exynos-pcie-phy.yaml | 51 | ||||
| -rw-r--r-- | dts/Bindings/phy/samsung-phy.txt | 1 | ||||
| -rw-r--r-- | dts/Bindings/phy/ti,omap-usb2.yaml | 4 |
17 files changed, 725 insertions, 219 deletions
diff --git a/dts/Bindings/phy/amlogic,axg-mipi-dphy.yaml b/dts/Bindings/phy/amlogic,axg-mipi-dphy.yaml new file mode 100644 index 0000000000..be485f5008 --- /dev/null +++ b/dts/Bindings/phy/amlogic,axg-mipi-dphy.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 BayLibre, SAS +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/amlogic,axg-mipi-dphy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic AXG MIPI D-PHY + +maintainers: + - Neil Armstrong <narmstrong@baylibre.com> + +properties: + compatible: + enum: + - amlogic,axg-mipi-dphy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pclk + + resets: + maxItems: 1 + + reset-names: + items: + - const: phy + + "#phy-cells": + const: 0 + + phys: + maxItems: 1 + + phy-names: + items: + - const: analog + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - phys + - phy-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@ff640000 { + compatible = "amlogic,axg-mipi-dphy"; + reg = <0xff640000 0x100>; + clocks = <&clk_mipi_dsi_phy>; + clock-names = "pclk"; + resets = <&reset_phy>; + reset-names = "phy"; + phys = <&mipi_pcie_analog_dphy>; + phy-names = "analog"; + #phy-cells = <0>; + }; diff --git a/dts/Bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml b/dts/Bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml index 18c1ec5e19..4d01f3124e 100644 --- a/dts/Bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml +++ b/dts/Bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml @@ -9,27 +9,32 @@ title: Amlogic AXG shared MIPI/PCIE analog PHY maintainers: - Remi Pommarel <repk@triplefau.lt> +description: |+ + The Everything-Else Power Domains node should be the child of a syscon + node with the required property: + + - compatible: Should be the following: + "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon" + + Refer to the the bindings described in + Documentation/devicetree/bindings/mfd/syscon.yaml + properties: compatible: const: amlogic,axg-mipi-pcie-analog-phy - reg: - maxItems: 1 - "#phy-cells": - const: 1 + const: 0 required: - compatible - - reg - "#phy-cells" additionalProperties: false examples: - | - mpphy: phy@0 { + mpphy: phy { compatible = "amlogic,axg-mipi-pcie-analog-phy"; - reg = <0x0 0xc>; - #phy-cells = <1>; + #phy-cells = <0>; }; diff --git a/dts/Bindings/phy/brcm,sata-phy.yaml b/dts/Bindings/phy/brcm,sata-phy.yaml new file mode 100644 index 0000000000..58c3ef8004 --- /dev/null +++ b/dts/Bindings/phy/brcm,sata-phy.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/brcm,sata-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Broadcom SATA3 PHY + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + +properties: + $nodename: + pattern: "^sata[-|_]phy(@.*)?$" + + compatible: + oneOf: + - items: + - enum: + - brcm,bcm7216-sata-phy + - brcm,bcm7425-sata-phy + - brcm,bcm7445-sata-phy + - brcm,bcm63138-sata-phy + - const: brcm,phy-sata3 + - items: + - const: brcm,iproc-nsp-sata-phy + - items: + - const: brcm,iproc-ns2-sata-phy + - items: + - const: brcm,iproc-sr-sata-phy + + reg: + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + maxItems: 2 + items: + - const: phy + - const: phy-ctrl + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^sata-phy@[0-9]+$": + type: object + description: | + Each port's PHY should be represented as a sub-node. + + properties: + reg: + description: The SATA PHY port number + maxItems: 1 + + "#phy-cells": + const: 0 + + "brcm,enable-ssc": + $ref: /schemas/types.yaml#/definitions/flag + description: | + Use spread spectrum clocking (SSC) on this port + This property is not applicable for "brcm,iproc-ns2-sata-phy", + "brcm,iproc-nsp-sata-phy" and "brcm,iproc-sr-sata-phy". + + "brcm,rxaeq-mode": + $ref: /schemas/types.yaml#/definitions/string + description: + String that indicates the desired RX equalizer mode. + enum: + - off + - auto + - manual + + "brcm,rxaeq-value": + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + When 'brcm,rxaeq-mode' is set to "manual", provides the RX + equalizer value that should be used. + minimum: 0 + maximum: 63 + + "brcm,tx-amplitude-millivolt": + description: | + Transmit amplitude voltage in millivolt. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [400, 500, 600, 800] + + required: + - reg + - "#phy-cells" + + additionalProperties: false + +if: + properties: + compatible: + items: + const: brcm,iproc-ns2-sata-phy +then: + properties: + reg: + maxItems: 2 + reg-names: + items: + - const: "phy" + - const: "phy-ctrl" +else: + properties: + reg: + maxItems: 1 + reg-names: + maxItems: 1 + items: + - const: "phy" + +required: + - compatible + - "#address-cells" + - "#size-cells" + - reg + - reg-names + +additionalProperties: false + +examples: + - | + sata_phy@f0458100 { + compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3"; + reg = <0xf0458100 0x1e00>; + reg-names = "phy"; + #address-cells = <1>; + #size-cells = <0>; + + sata-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + sata-phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; diff --git a/dts/Bindings/phy/brcm-sata-phy.txt b/dts/Bindings/phy/brcm-sata-phy.txt deleted file mode 100644 index c03ad21984..0000000000 --- a/dts/Bindings/phy/brcm-sata-phy.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Broadcom SATA3 PHY - -Required properties: -- compatible: should be one or more of - "brcm,bcm7216-sata-phy" - "brcm,bcm7425-sata-phy" - "brcm,bcm7445-sata-phy" - "brcm,iproc-ns2-sata-phy" - "brcm,iproc-nsp-sata-phy" - "brcm,phy-sata3" - "brcm,iproc-sr-sata-phy" - "brcm,bcm63138-sata-phy" -- address-cells: should be 1 -- size-cells: should be 0 -- reg: register ranges for the PHY PCB interface -- reg-names: should be "phy" and "phy-ctrl" - The "phy-ctrl" registers are only required for - "brcm,iproc-ns2-sata-phy" and "brcm,iproc-sr-sata-phy". - -Sub-nodes: - Each port's PHY should be represented as a sub-node. - -Sub-nodes required properties: -- reg: the PHY number -- phy-cells: generic PHY binding; must be 0 - -Sub-nodes optional properties: -- brcm,enable-ssc: use spread spectrum clocking (SSC) on this port - This property is not applicable for "brcm,iproc-ns2-sata-phy", - "brcm,iproc-nsp-sata-phy" and "brcm,iproc-sr-sata-phy". - -- brcm,rxaeq-mode: string that indicates the desired RX equalizer - mode, possible values are: - "off" (equivalent to not specifying the property) - "auto" - "manual" (brcm,rxaeq-value is used in that case) - -- brcm,rxaeq-value: when 'rxaeq-mode' is set to "manual", provides the RX - equalizer value that should be used. Allowed range is 0..63. - -Example - sata-phy@f0458100 { - compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3"; - reg = <0xf0458100 0x1e00>, <0xf045804c 0x10>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - - sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - - sata-phy@1 { - reg = <1>; - #phy-cells = <0>; - }; - }; diff --git a/dts/Bindings/phy/ingenic,phy-usb.yaml b/dts/Bindings/phy/ingenic,phy-usb.yaml new file mode 100644 index 0000000000..0fd93d71fe --- /dev/null +++ b/dts/Bindings/phy/ingenic,phy-usb.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/ingenic,phy-usb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic SoCs USB PHY devicetree bindings + +maintainers: + - Paul Cercueil <paul@crapouillou.net> + - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> + +properties: + $nodename: + pattern: '^usb-phy@.*' + + compatible: + enum: + - ingenic,jz4770-phy + - ingenic,jz4775-phy + - ingenic,jz4780-phy + - ingenic,x1000-phy + - ingenic,x1830-phy + - ingenic,x2000-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + vcc-supply: + description: VCC power supply + + '#phy-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - vcc-supply + - '#phy-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/jz4770-cgu.h> + otg_phy: usb-phy@3c { + compatible = "ingenic,jz4770-phy"; + reg = <0x3c 0x10>; + + vcc-supply = <&vcc>; + clocks = <&cgu JZ4770_CLK_OTG_PHY>; + + #phy-cells = <0>; + }; diff --git a/dts/Bindings/phy/intel,phy-keembay-usb.yaml b/dts/Bindings/phy/intel,phy-keembay-usb.yaml new file mode 100644 index 0000000000..a217bb8ac5 --- /dev/null +++ b/dts/Bindings/phy/intel,phy-keembay-usb.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/intel,phy-keembay-usb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay USB PHY bindings + +maintainers: + - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> + +properties: + compatible: + const: intel,keembay-usb-phy + + reg: + items: + - description: USB APB CPR (clock, power, reset) register + - description: USB APB slave register + + reg-names: + items: + - const: cpr-apb-base + - const: slv-apb-base + + '#phy-cells': + const: 0 + +required: + - compatible + - reg + - '#phy-cells' + +additionalProperties: false + +examples: + - | + usb-phy@20400000 { + compatible = "intel,keembay-usb-phy"; + reg = <0x20400000 0x1c>, + <0x20480000 0xd0>; + reg-names = "cpr-apb-base", "slv-apb-base"; + #phy-cells = <0>; + }; diff --git a/dts/Bindings/phy/marvell,mmp3-hsic-phy.yaml b/dts/Bindings/phy/marvell,mmp3-hsic-phy.yaml index 00609ace67..ff255aa4cc 100644 --- a/dts/Bindings/phy/marvell,mmp3-hsic-phy.yaml +++ b/dts/Bindings/phy/marvell,mmp3-hsic-phy.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0-or-later +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) # Copyright 2019 Lubomir Rintel <lkundrak@v3.sk> %YAML 1.2 --- @@ -18,27 +18,20 @@ properties: maxItems: 1 description: base address of the device - reset-gpios: - maxItems: 1 - description: GPIO connected to reset - "#phy-cells": const: 0 required: - compatible - reg - - reset-gpios - "#phy-cells" additionalProperties: false examples: - | - #include <dt-bindings/gpio/gpio.h> hsic-phy@f0001800 { compatible = "marvell,mmp3-hsic-phy"; reg = <0xf0001800 0x40>; - reset-gpios = <&gpio 63 GPIO_ACTIVE_HIGH>; #phy-cells = <0>; }; diff --git a/dts/Bindings/phy/mediatek,mt7621-pci-phy.yaml b/dts/Bindings/phy/mediatek,mt7621-pci-phy.yaml new file mode 100644 index 0000000000..0ccaded3f2 --- /dev/null +++ b/dts/Bindings/phy/mediatek,mt7621-pci-phy.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/mediatek,mt7621-pci-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Mediatek Mt7621 PCIe PHY Device Tree Bindings + +maintainers: + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +properties: + compatible: + const: mediatek,mt7621-pci-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 1 + description: selects if the phy is dual-ported + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + pcie0_phy: pcie-phy@1e149000 { + compatible = "mediatek,mt7621-pci-phy"; + reg = <0x1e149000 0x0700>; + #phy-cells = <1>; + }; diff --git a/dts/Bindings/phy/phy-cadence-sierra.txt b/dts/Bindings/phy/phy-cadence-sierra.txt deleted file mode 100644 index 03f5939d3d..0000000000 --- a/dts/Bindings/phy/phy-cadence-sierra.txt +++ /dev/null @@ -1,70 +0,0 @@ -Cadence Sierra PHY ------------------------ - -Required properties: -- compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform - Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC. -- resets: Must contain an entry for each in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include "sierra_reset" and "sierra_apb". - "sierra_reset" must control the reset line to the PHY. - "sierra_apb" must control the reset line to the APB PHY - interface ("sierra_apb" is optional). -- reg: register range for the PHY. -- #address-cells: Must be 1 -- #size-cells: Must be 0 - -Optional properties: -- clocks: Must contain an entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must contain "cmn_refclk_dig_div" and - "cmn_refclk1_dig_div" for configuring the frequency of - the clock to the lanes. "phy_clk" is deprecated. -- cdns,autoconf: A boolean property whose presence indicates that the - PHY registers will be configured by hardware. If not - present, all sub-node optional properties must be - provided. - -Sub-nodes: - Each group of PHY lanes with a single master lane should be represented as - a sub-node. Note that the actual configuration of each lane is determined by - hardware strapping, and must match the configuration specified here. - -Sub-node required properties: -- #phy-cells: Generic PHY binding; must be 0. -- reg: The master lane number. This is the lowest numbered lane - in the lane group. -- resets: Must contain one entry which controls the reset line for the - master lane of the sub-node. - See ../reset/reset.txt for details. - -Sub-node optional properties: -- cdns,num-lanes: Number of lanes in this group. From 1 to 4. The - group is made up of consecutive lanes. -- cdns,phy-type: Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on - configuration of lanes. - -Example: - pcie_phy4: pcie-phy@fd240000 { - compatible = "cdns,sierra-phy-t0"; - reg = <0x0 0xfd240000 0x0 0x40000>; - resets = <&phyrst 0>, <&phyrst 1>; - reset-names = "sierra_reset", "sierra_apb"; - clocks = <&phyclock>; - clock-names = "phy_clk"; - #address-cells = <1>; - #size-cells = <0>; - pcie0_phy0: pcie-phy@0 { - reg = <0>; - resets = <&phyrst 2>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_PCIE>; - }; - pcie0_phy1: pcie-phy@2 { - reg = <2>; - resets = <&phyrst 4>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_PCIE>; - }; diff --git a/dts/Bindings/phy/phy-cadence-sierra.yaml b/dts/Bindings/phy/phy-cadence-sierra.yaml new file mode 100644 index 0000000000..d210843863 --- /dev/null +++ b/dts/Bindings/phy/phy-cadence-sierra.yaml @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence Sierra PHY binding + +description: + This binding describes the Cadence Sierra PHY. Sierra PHY supports multilink + multiprotocol combinations including protocols such as PCIe, USB etc. + +maintainers: + - Swapnil Jakhade <sjakhade@cadence.com> + - Yuti Amonkar <yamonkar@cadence.com> + +properties: + compatible: + enum: + - cdns,sierra-phy-t0 + - ti,sierra-phy-t0 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + resets: + minItems: 1 + maxItems: 2 + items: + - description: Sierra PHY reset. + - description: Sierra APB reset. This is optional. + + reset-names: + minItems: 1 + maxItems: 2 + items: + - const: sierra_reset + - const: sierra_apb + + reg: + maxItems: 1 + description: + Offset of the Sierra PHY configuration registers. + + reg-names: + const: serdes + + clocks: + maxItems: 2 + + clock-names: + items: + - const: cmn_refclk_dig_div + - const: cmn_refclk1_dig_div + + cdns,autoconf: + type: boolean + description: + A boolean property whose presence indicates that the PHY registers will be + configured by hardware. If not present, all sub-node optional properties + must be provided. + +patternProperties: + '^phy@[0-9a-f]$': + type: object + description: + Each group of PHY lanes with a single master lane should be represented as + a sub-node. Note that the actual configuration of each lane is determined + by hardware strapping, and must match the configuration specified here. + properties: + reg: + description: + The master lane number. This is the lowest numbered lane in the lane group. + minimum: 0 + maximum: 15 + + resets: + minItems: 1 + maxItems: 4 + description: + Contains list of resets, one per lane, to get all the link lanes out of reset. + + "#phy-cells": + const: 0 + + cdns,phy-type: + description: + Specifies the type of PHY for which the group of PHY lanes is used. + Refer include/dt-bindings/phy/phy.h. Constants from the header should be used. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [2, 4] + + cdns,num-lanes: + description: + Number of lanes in this group. The group is made up of consecutive lanes. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 16 + + required: + - reg + - resets + - "#phy-cells" + + additionalProperties: false + +required: + - compatible + - "#address-cells" + - "#size-cells" + - reg + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/phy/phy.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + + sierra-phy@fd240000 { + compatible = "cdns,sierra-phy-t0"; + reg = <0x0 0xfd240000 0x0 0x40000>; + resets = <&phyrst 0>, <&phyrst 1>; + reset-names = "sierra_reset", "sierra_apb"; + clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>; + clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; + #address-cells = <1>; + #size-cells = <0>; + pcie0_phy0: phy@0 { + reg = <0>; + resets = <&phyrst 2>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + }; + pcie0_phy1: phy@2 { + reg = <2>; + resets = <&phyrst 4>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + }; + }; + }; diff --git a/dts/Bindings/phy/phy-stm32-usbphyc.txt b/dts/Bindings/phy/phy-stm32-usbphyc.txt deleted file mode 100644 index 725ae71ae6..0000000000 --- a/dts/Bindings/phy/phy-stm32-usbphyc.txt +++ /dev/null @@ -1,73 +0,0 @@ -STMicroelectronics STM32 USB HS PHY controller - -The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI -switch. It controls PHY configuration and status, and the UTMI+ switch that -selects either OTG or HOST controller for the second PHY port. It also sets -PLL configuration. - -USBPHYC - |_ PLL - | - |_ PHY port#1 _________________ HOST controller - | _ | - | / 1|________________| - |_ PHY port#2 ----| |________________ - | \_0| | - |_ UTMI switch_______| OTG controller - - -Phy provider node -================= - -Required properties: -- compatible: must be "st,stm32mp1-usbphyc" -- reg: address and length of the usb phy control register set -- clocks: phandle + clock specifier for the PLL phy clock -- #address-cells: number of address cells for phys sub-nodes, must be <1> -- #size-cells: number of size cells for phys sub-nodes, must be <0> - -Optional properties: -- assigned-clocks: phandle + clock specifier for the PLL phy clock -- assigned-clock-parents: the PLL phy clock parent -- resets: phandle + reset specifier - -Required nodes: one sub-node per port the controller provides. - -Phy sub-nodes -============== - -Required properties: -- reg: phy port index -- phy-supply: phandle to the regulator providing 3V3 power to the PHY, - see phy-bindings.txt in the same directory. -- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY -- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY -- #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY - port#1 and must be <1> for PHY port#2, to select USB controller - - -Example: - usbphyc: usb-phy@5a006000 { - compatible = "st,stm32mp1-usbphyc"; - reg = <0x5a006000 0x1000>; - clocks = <&rcc_clk USBPHY_K>; - resets = <&rcc_rst USBPHY_R>; - #address-cells = <1>; - #size-cells = <0>; - - usbphyc_port0: usb-phy@0 { - reg = <0>; - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18> - #phy-cells = <0>; - }; - - usbphyc_port1: usb-phy@1 { - reg = <1>; - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18> - #phy-cells = <1>; - }; - }; diff --git a/dts/Bindings/phy/phy-stm32-usbphyc.yaml b/dts/Bindings/phy/phy-stm32-usbphyc.yaml new file mode 100644 index 0000000000..0ba61979b9 --- /dev/null +++ b/dts/Bindings/phy/phy-stm32-usbphyc.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 USB HS PHY controller binding + +description: + + The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI + switch. It controls PHY configuration and status, and the UTMI+ switch that + selects either OTG or HOST controller for the second PHY port. It also sets + PLL configuration. + + USBPHYC + |_ PLL + | + |_ PHY port#1 _________________ HOST controller + | __ | + | / 1|________________| + |_ PHY port#2 ----| |________________ + | \_0| | + |_ UTMI switch_______| OTG controller + +maintainers: + - Amelie Delaunay <amelie.delaunay@st.com> + +properties: + compatible: + const: st,stm32mp1-usbphyc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +#Required child nodes: + +patternProperties: + "^usb-phy@[0|1]$": + type: object + description: + Each port the controller provides must be represented as a sub-node. + + properties: + reg: + description: phy port index. + maxItems: 1 + + phy-supply: + description: regulator providing 3V3 power supply to the PHY. + + vdda1v1-supply: + description: regulator providing 1V1 power supply to the PLL block + + vdda1v8-supply: + description: regulator providing 1V8 power supply to the PLL block + + "#phy-cells": + enum: [ 0x0, 0x1 ] + + allOf: + - if: + properties: + reg: + const: 0 + then: + properties: + "#phy-cells": + const: 0 + else: + properties: + "#phy-cells": + const: 1 + description: + The value is used to select UTMI switch output. + 0 for OTG controller and 1 for Host controller. + + required: + - reg + - phy-supply + - vdda1v1-supply + - vdda1v8-supply + - "#phy-cells" + + additionalProperties: false + +required: + - compatible + - reg + - clocks + - "#address-cells" + - "#size-cells" + - usb-phy@0 + - usb-phy@1 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/stm32mp1-clks.h> + #include <dt-bindings/reset/stm32mp1-resets.h> + usbphyc: usbphyc@5a006000 { + compatible = "st,stm32mp1-usbphyc"; + reg = <0x5a006000 0x1000>; + clocks = <&rcc USBPHY_K>; + resets = <&rcc USBPHY_R>; + #address-cells = <1>; + #size-cells = <0>; + + usbphyc_port0: usb-phy@0 { + reg = <0>; + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; + #phy-cells = <0>; + }; + + usbphyc_port1: usb-phy@1 { + reg = <1>; + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; + #phy-cells = <1>; + }; + }; +... diff --git a/dts/Bindings/phy/qcom,qmp-phy.yaml b/dts/Bindings/phy/qcom,qmp-phy.yaml index 185cdea9cf..ec05db3746 100644 --- a/dts/Bindings/phy/qcom,qmp-phy.yaml +++ b/dts/Bindings/phy/qcom,qmp-phy.yaml @@ -31,6 +31,9 @@ properties: - qcom,sdm845-qmp-usb3-uni-phy - qcom,sm8150-qmp-ufs-phy - qcom,sm8250-qmp-ufs-phy + - qcom,sm8250-qmp-gen3x1-pcie-phy + - qcom,sm8250-qmp-gen3x2-pcie-phy + - qcom,sm8250-qmp-modem-pcie-phy reg: items: @@ -259,6 +262,9 @@ allOf: enum: - qcom,sdm845-qhp-pcie-phy - qcom,sdm845-qmp-pcie-phy + - qcom,sm8250-qmp-gen3x1-pcie-phy + - qcom,sm8250-qmp-gen3x2-pcie-phy + - qcom,sm8250-qmp-modem-pcie-phy then: properties: clocks: diff --git a/dts/Bindings/phy/rockchip-emmc-phy.txt b/dts/Bindings/phy/rockchip-emmc-phy.txt index e728786f21..00aa2d349e 100644 --- a/dts/Bindings/phy/rockchip-emmc-phy.txt +++ b/dts/Bindings/phy/rockchip-emmc-phy.txt @@ -16,6 +16,11 @@ Optional properties: - drive-impedance-ohm: Specifies the drive impedance in Ohm. Possible values are 33, 40, 50, 66 and 100. If not set, the default value of 50 will be applied. + - enable-strobe-pulldown: Enable internal pull-down for the strobe line. + If not set, pull-down is not used. + - output-tapdelay-select: Specifies the phyctrl_otapdlysec register. + If not set, the register defaults to 0x4. + Maximum value 0xf. Example: diff --git a/dts/Bindings/phy/samsung,exynos-pcie-phy.yaml b/dts/Bindings/phy/samsung,exynos-pcie-phy.yaml new file mode 100644 index 0000000000..ac0af40be5 --- /dev/null +++ b/dts/Bindings/phy/samsung,exynos-pcie-phy.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/samsung,exynos-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SoC series PCIe PHY Device Tree Bindings + +maintainers: + - Marek Szyprowski <m.szyprowski@samsung.com> + - Jaehoon Chung <jh80.chung@samsung.com> + +properties: + "#phy-cells": + const: 0 + + compatible: + const: samsung,exynos5433-pcie-phy + + reg: + maxItems: 1 + + samsung,pmu-syscon: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle for PMU system controller interface, used to + control PMU registers bits for PCIe PHY + + samsung,fsys-sysreg: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle for FSYS sysreg interface, used to control + sysreg registers bits for PCIe PHY + +required: + - "#phy-cells" + - compatible + - reg + - samsung,pmu-syscon + - samsung,fsys-sysreg + +additionalProperties: false + +examples: + - | + pcie_phy: pcie-phy@15680000 { + compatible = "samsung,exynos5433-pcie-phy"; + reg = <0x15680000 0x1000>; + samsung,pmu-syscon = <&pmu_system_controller>; + samsung,fsys-sysreg = <&syscon_fsys>; + #phy-cells = <0>; + }; +... diff --git a/dts/Bindings/phy/samsung-phy.txt b/dts/Bindings/phy/samsung-phy.txt index 7510830a79..8f51aee911 100644 --- a/dts/Bindings/phy/samsung-phy.txt +++ b/dts/Bindings/phy/samsung-phy.txt @@ -47,6 +47,7 @@ Required properties: - "samsung,exynos4210-usb2-phy" - "samsung,exynos4x12-usb2-phy" - "samsung,exynos5250-usb2-phy" + - "samsung,exynos5420-usb2-phy" - "samsung,s5pv210-usb2-phy" - reg : a list of registers used by phy driver - first and obligatory is the location of phy modules registers diff --git a/dts/Bindings/phy/ti,omap-usb2.yaml b/dts/Bindings/phy/ti,omap-usb2.yaml index 83d5d0aceb..cbbf5e8b11 100644 --- a/dts/Bindings/phy/ti,omap-usb2.yaml +++ b/dts/Bindings/phy/ti,omap-usb2.yaml @@ -44,13 +44,13 @@ properties: - const: refclk syscon-phy-power: - $ref: /schemas/types.yaml#definitions/phandle-array + $ref: /schemas/types.yaml#/definitions/phandle-array description: phandle/offset pair. Phandle to the system control module and register offset to power on/off the PHY. ctrl-module: - $ref: /schemas/types.yaml#definitions/phandle + $ref: /schemas/types.yaml#/definitions/phandle description: (deprecated) phandle of the control module used by PHY driver to power on the PHY. Use syscon-phy-power instead. |