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-rw-r--r--dts/Bindings/pinctrl/renesas,rzn1-pinctrl.yaml9
1 files changed, 4 insertions, 5 deletions
diff --git a/dts/Bindings/pinctrl/renesas,rzn1-pinctrl.yaml b/dts/Bindings/pinctrl/renesas,rzn1-pinctrl.yaml
index 4a43af0d6e..816688580e 100644
--- a/dts/Bindings/pinctrl/renesas,rzn1-pinctrl.yaml
+++ b/dts/Bindings/pinctrl/renesas,rzn1-pinctrl.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/N1 Pin Controller
maintainers:
- - Gareth Williams <gareth.williams.jx@renesas.com>
+ - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
- Geert Uytterhoeven <geert+renesas@glider.be>
properties:
@@ -31,6 +31,9 @@ properties:
description:
The bus clock, sometimes described as pclk, for register accesses.
+allOf:
+ - $ref: pinctrl.yaml#
+
required:
- compatible
- reg
@@ -71,7 +74,6 @@ additionalProperties:
offset by 10. Additional identifiers are provided to specify the
MDIO source peripheral.
- phandle: true
bias-disable: true
bias-pull-up:
description: Pull up the pin with 50 kOhm
@@ -88,9 +90,6 @@ additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
- type: object
- properties:
- phandle: true
-
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"