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-rw-r--r--dts/Bindings/powerpc/4xx/akebono.txt2
-rw-r--r--dts/Bindings/powerpc/4xx/hsta.txt1
-rw-r--r--dts/Bindings/powerpc/4xx/ppc440spe-adma.txt2
-rw-r--r--dts/Bindings/powerpc/fsl/dcsr.txt7
-rw-r--r--dts/Bindings/powerpc/fsl/diu.txt2
-rw-r--r--dts/Bindings/powerpc/fsl/dma.txt4
-rw-r--r--dts/Bindings/powerpc/fsl/ecm.txt4
-rw-r--r--dts/Bindings/powerpc/fsl/mcm.txt4
-rw-r--r--dts/Bindings/powerpc/fsl/mpc5121-psc.txt4
-rw-r--r--dts/Bindings/powerpc/fsl/msi-pic.txt5
-rw-r--r--dts/Bindings/powerpc/fsl/pamu.txt2
-rw-r--r--dts/Bindings/powerpc/nintendo/wii.txt1
12 files changed, 0 insertions, 38 deletions
diff --git a/dts/Bindings/powerpc/4xx/akebono.txt b/dts/Bindings/powerpc/4xx/akebono.txt
index db93921..940fd78 100644
--- a/dts/Bindings/powerpc/4xx/akebono.txt
+++ b/dts/Bindings/powerpc/4xx/akebono.txt
@@ -19,7 +19,6 @@ The IBM Akebono board is a development board for the PPC476GTR SoC.
- compatible : should be "ibm,476gtr-sdhci","generic-sdhci".
- reg : should contain the SDHCI registers location and length.
- - interrupt-parent : a phandle for the interrupt controller.
- interrupts : should contain the SDHCI interrupt.
1.b) The Advanced Host Controller Interface (AHCI) SATA node
@@ -30,7 +29,6 @@ The IBM Akebono board is a development board for the PPC476GTR SoC.
- compatible : should be "ibm,476gtr-ahci".
- reg : should contain the AHCI registers location and length.
- - interrupt-parent : a phandle for the interrupt controller.
- interrupts : should contain the AHCI interrupt.
1.c) The FPGA node
diff --git a/dts/Bindings/powerpc/4xx/hsta.txt b/dts/Bindings/powerpc/4xx/hsta.txt
index c737c83..66dbd9f 100644
--- a/dts/Bindings/powerpc/4xx/hsta.txt
+++ b/dts/Bindings/powerpc/4xx/hsta.txt
@@ -13,7 +13,6 @@ device tree entries:
Require properties:
- compatible : "ibm,476gtr-hsta-msi", "ibm,hsta-msi"
- reg : register mapping for the HSTA MSI space
-- interrupt-parent : parent controller for mapping interrupts
- interrupts : ordered interrupt mapping for each MSI in the register
space. The first interrupt should be associated with a
register offset of 0x00, the second to 0x10, etc.
diff --git a/dts/Bindings/powerpc/4xx/ppc440spe-adma.txt b/dts/Bindings/powerpc/4xx/ppc440spe-adma.txt
index 515ebcf..de6a5f7 100644
--- a/dts/Bindings/powerpc/4xx/ppc440spe-adma.txt
+++ b/dts/Bindings/powerpc/4xx/ppc440spe-adma.txt
@@ -38,7 +38,6 @@ DMA devices.
2 sources: DMAx CS FIFO Needs Service IRQ (on UIC0)
and DMA Error IRQ (on UIC1). The latter is common
for both DMA engines>.
- - interrupt-parent : needed for interrupt mapping
Example:
@@ -65,7 +64,6 @@ DMA devices.
- compatible : "amcc,xor-accelerator";
- reg : <registers mapping>
- interrupts : <interrupt mapping for XOR interrupt source>
- - interrupt-parent : for interrupt mapping
Example:
diff --git a/dts/Bindings/powerpc/fsl/dcsr.txt b/dts/Bindings/powerpc/fsl/dcsr.txt
index 18a8810..4b01e1a 100644
--- a/dts/Bindings/powerpc/fsl/dcsr.txt
+++ b/dts/Bindings/powerpc/fsl/dcsr.txt
@@ -84,13 +84,6 @@ PROPERTIES
Interrupt numbers are listed in order (perfmon, event0, event1).
- - interrupt-parent
- Usage: required
- Value type: <phandle>
- Definition: A single <phandle> value that points
- to the interrupt parent to which the child domain
- is being mapped. Value must be "&mpic"
-
- reg
Usage: required
Value type: <prop-encoded-array>
diff --git a/dts/Bindings/powerpc/fsl/diu.txt b/dts/Bindings/powerpc/fsl/diu.txt
index b66cb6d..eb45db1 100644
--- a/dts/Bindings/powerpc/fsl/diu.txt
+++ b/dts/Bindings/powerpc/fsl/diu.txt
@@ -8,8 +8,6 @@ Required properties:
- reg : should contain at least address and length of the DIU register
set.
- interrupts : one DIU interrupt should be described here.
-- interrupt-parent : the phandle for the interrupt controller that
- services interrupts for this device.
Optional properties:
- edid : verbatim EDID data block describing attached display.
diff --git a/dts/Bindings/powerpc/fsl/dma.txt b/dts/Bindings/powerpc/fsl/dma.txt
index 7fc1b01..c11ad5c 100644
--- a/dts/Bindings/powerpc/fsl/dma.txt
+++ b/dts/Bindings/powerpc/fsl/dma.txt
@@ -13,7 +13,6 @@ Required properties:
DMA channels and the address space of the DMA controller
- cell-index : controller index. 0 for controller @ 0x8100
- interrupts : interrupt specifier for DMA IRQ
-- interrupt-parent : optional, if needed for interrupt mapping
- DMA channel nodes:
- compatible : must include "fsl,elo-dma-channel"
@@ -25,7 +24,6 @@ Optional properties:
- interrupts : interrupt specifier for DMA channel IRQ
(on 83xx this is expected to be identical to
the interrupts property of the parent node)
- - interrupt-parent : optional, if needed for interrupt mapping
Example:
dma@82a8 {
@@ -88,7 +86,6 @@ Required properties:
- cell-index : DMA channel index starts at 0.
- reg : DMA channel specific registers
- interrupts : interrupt specifier for DMA channel IRQ
- - interrupt-parent : optional, if needed for interrupt mapping
Example:
dma@21300 {
@@ -146,7 +143,6 @@ Required properties:
- compatible : must include "fsl,eloplus-dma-channel"
- reg : DMA channel specific registers
- interrupts : interrupt specifier for DMA channel IRQ
- - interrupt-parent : optional, if needed for interrupt mapping
Example:
dma@100300 {
diff --git a/dts/Bindings/powerpc/fsl/ecm.txt b/dts/Bindings/powerpc/fsl/ecm.txt
index f514f29..76dc547 100644
--- a/dts/Bindings/powerpc/fsl/ecm.txt
+++ b/dts/Bindings/powerpc/fsl/ecm.txt
@@ -57,8 +57,4 @@ PROPERTIES
Usage: required
Value type: <prop-encoded-array>
- - interrupt-parent
- Usage: required
- Value type: <phandle>
-
=====================================================================
diff --git a/dts/Bindings/powerpc/fsl/mcm.txt b/dts/Bindings/powerpc/fsl/mcm.txt
index 4ceda9b..a5dae6b 100644
--- a/dts/Bindings/powerpc/fsl/mcm.txt
+++ b/dts/Bindings/powerpc/fsl/mcm.txt
@@ -57,8 +57,4 @@ PROPERTIES
Usage: required
Value type: <prop-encoded-array>
- - interrupt-parent
- Usage: required
- Value type: <phandle>
-
=====================================================================
diff --git a/dts/Bindings/powerpc/fsl/mpc5121-psc.txt b/dts/Bindings/powerpc/fsl/mpc5121-psc.txt
index 6478175..5dfd68f 100644
--- a/dts/Bindings/powerpc/fsl/mpc5121-psc.txt
+++ b/dts/Bindings/powerpc/fsl/mpc5121-psc.txt
@@ -18,8 +18,6 @@ Required properties :
- interrupts : <a b> where a is the interrupt number of the
PSC FIFO Controller and b is a field that represents an
encoding of the sense and level information for the interrupt.
- - interrupt-parent : the phandle for the interrupt controller that
- services interrupts for this device.
Recommended properties :
- fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4)
@@ -45,8 +43,6 @@ Required properties :
- interrupts : <a b> where a is the interrupt number of the
PSC FIFO Controller and b is a field that represents an
encoding of the sense and level information for the interrupt.
- - interrupt-parent : the phandle for the interrupt controller that
- services interrupts for this device.
Recommended properties :
- clocks : specifies the clock needed to operate the fifo controller
diff --git a/dts/Bindings/powerpc/fsl/msi-pic.txt b/dts/Bindings/powerpc/fsl/msi-pic.txt
index 82dd5b6..f8d2b7f 100644
--- a/dts/Bindings/powerpc/fsl/msi-pic.txt
+++ b/dts/Bindings/powerpc/fsl/msi-pic.txt
@@ -21,11 +21,6 @@ Required properties:
be set as edge sensitive. If msi-available-ranges is present, only
the interrupts that correspond to available ranges shall be present.
-- interrupt-parent: the phandle for the interrupt controller
- that services interrupts for this device. for 83xx cpu, the interrupts
- are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed
- to MPIC.
-
Optional properties:
- msi-available-ranges: use <start count> style section to define which
msi interrupt can be used in the 256 msi interrupts. This property is
diff --git a/dts/Bindings/powerpc/fsl/pamu.txt b/dts/Bindings/powerpc/fsl/pamu.txt
index c2b2899..b21ab85 100644
--- a/dts/Bindings/powerpc/fsl/pamu.txt
+++ b/dts/Bindings/powerpc/fsl/pamu.txt
@@ -32,8 +32,6 @@ Optional properties:
A standard property. It represents the CCSR registers of
all child PAMUs combined. Include it to provide support
for legacy drivers.
-- interrupt-parent : <phandle>
- Phandle to interrupt controller
- fsl,portid-mapping : <u32>
The Coherency Subdomain ID Port Mapping Registers and
Snoop ID Port Mapping registers, which are part of the
diff --git a/dts/Bindings/powerpc/nintendo/wii.txt b/dts/Bindings/powerpc/nintendo/wii.txt
index a3dc4b9..c4d78f2 100644
--- a/dts/Bindings/powerpc/nintendo/wii.txt
+++ b/dts/Bindings/powerpc/nintendo/wii.txt
@@ -148,7 +148,6 @@ Nintendo Wii device tree
- reg : should contain the controller registers location and length
- interrupt-controller
- interrupts : should contain the cascade interrupt of the "flipper" pic
- - interrupt-parent: should contain the phandle of the "flipper" pic
1.l) The General Purpose I/O (GPIO) controller node