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-rw-r--r--dts/Bindings/pwm/pwm-sifive.yaml6
1 files changed, 3 insertions, 3 deletions
diff --git a/dts/Bindings/pwm/pwm-sifive.yaml b/dts/Bindings/pwm/pwm-sifive.yaml
index 84e66913d0..bae9931289 100644
--- a/dts/Bindings/pwm/pwm-sifive.yaml
+++ b/dts/Bindings/pwm/pwm-sifive.yaml
@@ -8,8 +8,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiFive PWM controller
maintainers:
- - Yash Shah <yash.shah@sifive.com>
- - Sagar Kadam <sagar.kadam@sifive.com>
- Paul Walmsley <paul.walmsley@sifive.com>
description:
@@ -22,6 +20,9 @@ description:
https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
+allOf:
+ - $ref: pwm.yaml#
+
properties:
compatible:
items:
@@ -55,7 +56,6 @@ required:
- compatible
- reg
- clocks
- - "#pwm-cells"
- interrupts
additionalProperties: false