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-rw-r--r--dts/Bindings/rtc/atmel,at91rm9200-rtc.txt15
-rw-r--r--dts/Bindings/rtc/dw-apb.txt32
-rw-r--r--dts/Bindings/rtc/haoyu,hym8563.txt27
-rw-r--r--dts/Bindings/rtc/imxdi-rtc.txt17
-rw-r--r--dts/Bindings/rtc/lpc32xx-rtc.txt15
-rw-r--r--dts/Bindings/rtc/maxim,ds1742.txt12
-rw-r--r--dts/Bindings/rtc/moxa,moxart-rtc.txt17
-rw-r--r--dts/Bindings/rtc/nvidia,tegra20-rtc.txt22
-rw-r--r--dts/Bindings/rtc/olpc-xo1-rtc.txt5
-rw-r--r--dts/Bindings/rtc/orion-rtc.txt18
-rw-r--r--dts/Bindings/rtc/pxa-rtc.txt14
-rw-r--r--dts/Bindings/rtc/rtc-cmos.txt28
-rw-r--r--dts/Bindings/rtc/rtc-omap.txt21
-rw-r--r--dts/Bindings/rtc/rtc-palmas.txt33
-rw-r--r--dts/Bindings/rtc/s3c-rtc.txt20
-rw-r--r--dts/Bindings/rtc/sa1100-rtc.txt17
-rw-r--r--dts/Bindings/rtc/snvs-rtc.txt1
-rw-r--r--dts/Bindings/rtc/spear-rtc.txt17
-rw-r--r--dts/Bindings/rtc/stmp3xxx-rtc.txt16
-rw-r--r--dts/Bindings/rtc/sunxi-rtc.txt17
-rw-r--r--dts/Bindings/rtc/twl-rtc.txt12
-rw-r--r--dts/Bindings/rtc/via,vt8500-rtc.txt15
22 files changed, 391 insertions, 0 deletions
diff --git a/dts/Bindings/rtc/atmel,at91rm9200-rtc.txt b/dts/Bindings/rtc/atmel,at91rm9200-rtc.txt
new file mode 100644
index 0000000000..34c1505774
--- /dev/null
+++ b/dts/Bindings/rtc/atmel,at91rm9200-rtc.txt
@@ -0,0 +1,15 @@
+Atmel AT91RM9200 Real Time Clock
+
+Required properties:
+- compatible: should be: "atmel,at91rm9200-rtc" or "atmel,at91sam9x5-rtc"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: rtc alarm/event interrupt
+
+Example:
+
+rtc@fffffe00 {
+ compatible = "atmel,at91rm9200-rtc";
+ reg = <0xfffffe00 0x100>;
+ interrupts = <1 4 7>;
+};
diff --git a/dts/Bindings/rtc/dw-apb.txt b/dts/Bindings/rtc/dw-apb.txt
new file mode 100644
index 0000000000..c703d51abb
--- /dev/null
+++ b/dts/Bindings/rtc/dw-apb.txt
@@ -0,0 +1,32 @@
+* Designware APB timer
+
+Required properties:
+- compatible: One of:
+ "snps,dw-apb-timer"
+ "snps,dw-apb-timer-sp" <DEPRECATED>
+ "snps,dw-apb-timer-osc" <DEPRECATED>
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: IRQ line for the timer.
+- either clocks+clock-names or clock-frequency properties
+
+Optional properties:
+- clocks : list of clock specifiers, corresponding to entries in
+ the clock-names property;
+- clock-names : should contain "timer" and "pclk" entries, matching entries
+ in the clocks property.
+- clock-frequency: The frequency in HZ of the timer.
+- clock-freq: For backwards compatibility with picoxcell
+
+If using the clock specifiers, the pclk clock is optional, as not all
+systems may use one.
+
+
+Example:
+ timer@ffe00000 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 170 4>;
+ reg = <0xffe00000 0x1000>;
+ clocks = <&timer_clk>, <&timer_pclk>;
+ clock-names = "timer", "pclk";
+ };
diff --git a/dts/Bindings/rtc/haoyu,hym8563.txt b/dts/Bindings/rtc/haoyu,hym8563.txt
new file mode 100644
index 0000000000..31406fd4a4
--- /dev/null
+++ b/dts/Bindings/rtc/haoyu,hym8563.txt
@@ -0,0 +1,27 @@
+Haoyu Microelectronics HYM8563 Real Time Clock
+
+The HYM8563 provides basic rtc and alarm functionality
+as well as a clock output of up to 32kHz.
+
+Required properties:
+- compatible: should be: "haoyu,hym8563"
+- reg: i2c address
+- interrupts: rtc alarm/event interrupt
+- #clock-cells: the value should be 0
+
+Example:
+
+hym8563: hym8563@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+
+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+
+ #clock-cells = <0>;
+};
+
+device {
+...
+ clocks = <&hym8563>;
+...
+};
diff --git a/dts/Bindings/rtc/imxdi-rtc.txt b/dts/Bindings/rtc/imxdi-rtc.txt
new file mode 100644
index 0000000000..c9d80d7da1
--- /dev/null
+++ b/dts/Bindings/rtc/imxdi-rtc.txt
@@ -0,0 +1,17 @@
+* i.MX25 Real Time Clock controller
+
+This binding supports the following chips: i.MX25, i.MX53
+
+Required properties:
+- compatible: should be: "fsl,imx25-rtc"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: rtc alarm interrupt
+
+Example:
+
+rtc@80056000 {
+ compatible = "fsl,imx53-rtc", "fsl,imx25-rtc";
+ reg = <0x80056000 2000>;
+ interrupts = <29>;
+};
diff --git a/dts/Bindings/rtc/lpc32xx-rtc.txt b/dts/Bindings/rtc/lpc32xx-rtc.txt
new file mode 100644
index 0000000000..a87a1e9bc0
--- /dev/null
+++ b/dts/Bindings/rtc/lpc32xx-rtc.txt
@@ -0,0 +1,15 @@
+* NXP LPC32xx SoC Real Time Clock controller
+
+Required properties:
+- compatible: must be "nxp,lpc3220-rtc"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: The RTC interrupt
+
+Example:
+
+ rtc@40024000 {
+ compatible = "nxp,lpc3220-rtc";
+ reg = <0x40024000 0x1000>;
+ interrupts = <52 0>;
+ };
diff --git a/dts/Bindings/rtc/maxim,ds1742.txt b/dts/Bindings/rtc/maxim,ds1742.txt
new file mode 100644
index 0000000000..d0f937c355
--- /dev/null
+++ b/dts/Bindings/rtc/maxim,ds1742.txt
@@ -0,0 +1,12 @@
+* Maxim (Dallas) DS1742/DS1743 Real Time Clock
+
+Required properties:
+- compatible: Should contain "maxim,ds1742".
+- reg: Physical base address of the RTC and length of memory
+ mapped region.
+
+Example:
+ rtc: rtc@10000000 {
+ compatible = "maxim,ds1742";
+ reg = <0x10000000 0x800>;
+ };
diff --git a/dts/Bindings/rtc/moxa,moxart-rtc.txt b/dts/Bindings/rtc/moxa,moxart-rtc.txt
new file mode 100644
index 0000000000..c9d3ac1477
--- /dev/null
+++ b/dts/Bindings/rtc/moxa,moxart-rtc.txt
@@ -0,0 +1,17 @@
+MOXA ART real-time clock
+
+Required properties:
+
+- compatible : Should be "moxa,moxart-rtc"
+- gpio-rtc-sclk : RTC sclk gpio, with zero flags
+- gpio-rtc-data : RTC data gpio, with zero flags
+- gpio-rtc-reset : RTC reset gpio, with zero flags
+
+Example:
+
+ rtc: rtc {
+ compatible = "moxa,moxart-rtc";
+ gpio-rtc-sclk = <&gpio 5 0>;
+ gpio-rtc-data = <&gpio 6 0>;
+ gpio-rtc-reset = <&gpio 7 0>;
+ };
diff --git a/dts/Bindings/rtc/nvidia,tegra20-rtc.txt b/dts/Bindings/rtc/nvidia,tegra20-rtc.txt
new file mode 100644
index 0000000000..652d1ff2e8
--- /dev/null
+++ b/dts/Bindings/rtc/nvidia,tegra20-rtc.txt
@@ -0,0 +1,22 @@
+NVIDIA Tegra20 real-time clock
+
+The Tegra RTC maintains seconds and milliseconds counters, and five alarm
+registers. The alarms and other interrupts may wake the system from low-power
+state.
+
+Required properties:
+
+- compatible : should be "nvidia,tegra20-rtc".
+- reg : Specifies base physical address and size of the registers.
+- interrupts : A single interrupt specifier.
+- clocks : Must contain one entry, for the module clock.
+ See ../clocks/clock-bindings.txt for details.
+
+Example:
+
+timer {
+ compatible = "nvidia,tegra20-rtc";
+ reg = <0x7000e000 0x100>;
+ interrupts = <0 2 0x04>;
+ clocks = <&tegra_car 4>;
+};
diff --git a/dts/Bindings/rtc/olpc-xo1-rtc.txt b/dts/Bindings/rtc/olpc-xo1-rtc.txt
new file mode 100644
index 0000000000..a2891ceb63
--- /dev/null
+++ b/dts/Bindings/rtc/olpc-xo1-rtc.txt
@@ -0,0 +1,5 @@
+OLPC XO-1 RTC
+~~~~~~~~~~~~~
+
+Required properties:
+ - compatible : "olpc,xo1-rtc"
diff --git a/dts/Bindings/rtc/orion-rtc.txt b/dts/Bindings/rtc/orion-rtc.txt
new file mode 100644
index 0000000000..3bf63ffa51
--- /dev/null
+++ b/dts/Bindings/rtc/orion-rtc.txt
@@ -0,0 +1,18 @@
+* Mvebu Real Time Clock
+
+RTC controller for the Kirkwood, the Dove, the Armada 370 and the
+Armada XP SoCs
+
+Required properties:
+- compatible : Should be "marvell,orion-rtc"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: IRQ line for the RTC.
+
+Example:
+
+rtc@10300 {
+ compatible = "marvell,orion-rtc";
+ reg = <0xd0010300 0x20>;
+ interrupts = <50>;
+};
diff --git a/dts/Bindings/rtc/pxa-rtc.txt b/dts/Bindings/rtc/pxa-rtc.txt
new file mode 100644
index 0000000000..8c6672a1b7
--- /dev/null
+++ b/dts/Bindings/rtc/pxa-rtc.txt
@@ -0,0 +1,14 @@
+* PXA RTC
+
+PXA specific RTC driver.
+
+Required properties:
+- compatible : Should be "marvell,pxa-rtc"
+
+Examples:
+
+rtc@40900000 {
+ compatible = "marvell,pxa-rtc";
+ reg = <0x40900000 0x3c>;
+ interrupts = <30 31>;
+};
diff --git a/dts/Bindings/rtc/rtc-cmos.txt b/dts/Bindings/rtc/rtc-cmos.txt
new file mode 100644
index 0000000000..7382989b30
--- /dev/null
+++ b/dts/Bindings/rtc/rtc-cmos.txt
@@ -0,0 +1,28 @@
+ Motorola mc146818 compatible RTC
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Required properties:
+ - compatible : "motorola,mc146818"
+ - reg : should contain registers location and length.
+
+Optional properties:
+ - interrupts : should contain interrupt.
+ - interrupt-parent : interrupt source phandle.
+ - ctrl-reg : Contains the initial value of the control register also
+ called "Register B".
+ - freq-reg : Contains the initial value of the frequency register also
+ called "Regsiter A".
+
+"Register A" and "B" are usually initialized by the firmware (BIOS for
+instance). If this is not done, it can be performed by the driver.
+
+ISA Example:
+
+ rtc@70 {
+ compatible = "motorola,mc146818";
+ interrupts = <8 3>;
+ interrupt-parent = <&ioapic1>;
+ ctrl-reg = <2>;
+ freq-reg = <0x26>;
+ reg = <1 0x70 2>;
+ };
diff --git a/dts/Bindings/rtc/rtc-omap.txt b/dts/Bindings/rtc/rtc-omap.txt
new file mode 100644
index 0000000000..5a0f02d34d
--- /dev/null
+++ b/dts/Bindings/rtc/rtc-omap.txt
@@ -0,0 +1,21 @@
+TI Real Time Clock
+
+Required properties:
+- compatible:
+ - "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family.
+ - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family.
+ This RTC IP has special WAKE-EN Register to enable
+ Wakeup generation for event Alarm.
+- reg: Address range of rtc register set
+- interrupts: rtc timer, alarm interrupts in order
+- interrupt-parent: phandle for the interrupt controller
+
+Example:
+
+rtc@1c23000 {
+ compatible = "ti,da830-rtc";
+ reg = <0x23000 0x1000>;
+ interrupts = <19
+ 19>;
+ interrupt-parent = <&intc>;
+};
diff --git a/dts/Bindings/rtc/rtc-palmas.txt b/dts/Bindings/rtc/rtc-palmas.txt
new file mode 100644
index 0000000000..adbccc0a51
--- /dev/null
+++ b/dts/Bindings/rtc/rtc-palmas.txt
@@ -0,0 +1,33 @@
+Palmas RTC controller bindings
+
+Required properties:
+- compatible:
+ - "ti,palmas-rtc" for palma series of the RTC controller
+- interrupt-parent: Parent interrupt device, must be handle of palmas node.
+- interrupts: Interrupt number of RTC submodule on device.
+
+Optional properties:
+
+- ti,backup-battery-chargeable: The Palmas series device like TPS65913 or
+ TPS80036 supports the backup battery for powering the RTC when main
+ battery is removed or in very low power state. The backup battery
+ can be chargeable or non-chargeable. This flag will tells whether
+ battery is chargeable or not. If charging battery then driver can
+ enable the charging.
+- ti,backup-battery-charge-high-current: Enable high current charging in
+ backup battery. Device supports the < 100mA and > 100mA charging.
+ The high current will be > 100mA. Absence of this property will
+ charge battery to lower current i.e. < 100mA.
+
+Example:
+ palmas: tps65913@58 {
+ ...
+ palmas_rtc: rtc {
+ compatible = "ti,palmas-rtc";
+ interrupt-parent = <&palmas>;
+ interrupts = <8 0>;
+ ti,backup-battery-chargeable;
+ ti,backup-battery-charge-high-current;
+ };
+ ...
+ };
diff --git a/dts/Bindings/rtc/s3c-rtc.txt b/dts/Bindings/rtc/s3c-rtc.txt
new file mode 100644
index 0000000000..7ac7259fe9
--- /dev/null
+++ b/dts/Bindings/rtc/s3c-rtc.txt
@@ -0,0 +1,20 @@
+* Samsung's S3C Real Time Clock controller
+
+Required properties:
+- compatible: should be one of the following.
+ * "samsung,s3c2410-rtc" - for controllers compatible with s3c2410 rtc.
+ * "samsung,s3c6410-rtc" - for controllers compatible with s3c6410 rtc.
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: Two interrupt numbers to the cpu should be specified. First
+ interrupt number is the rtc alarm interrupt and second interrupt number
+ is the rtc tick interrupt. The number of cells representing a interrupt
+ depends on the parent interrupt controller.
+
+Example:
+
+ rtc@10070000 {
+ compatible = "samsung,s3c6410-rtc";
+ reg = <0x10070000 0x100>;
+ interrupts = <44 0 45 0>;
+ };
diff --git a/dts/Bindings/rtc/sa1100-rtc.txt b/dts/Bindings/rtc/sa1100-rtc.txt
new file mode 100644
index 0000000000..0cda19ad48
--- /dev/null
+++ b/dts/Bindings/rtc/sa1100-rtc.txt
@@ -0,0 +1,17 @@
+* Marvell Real Time Clock controller
+
+Required properties:
+- compatible: should be "mrvl,sa1100-rtc"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: Should be two. The first interrupt number is the rtc alarm
+ interrupt and the second interrupt number is the rtc hz interrupt.
+- interrupt-names: Assign name of irq resource.
+
+Example:
+ rtc: rtc@d4010000 {
+ compatible = "mrvl,mmp-rtc";
+ reg = <0xd4010000 0x1000>;
+ interrupts = <5>, <6>;
+ interrupt-name = "rtc 1Hz", "rtc alarm";
+ };
diff --git a/dts/Bindings/rtc/snvs-rtc.txt b/dts/Bindings/rtc/snvs-rtc.txt
new file mode 100644
index 0000000000..fb61ed77ad
--- /dev/null
+++ b/dts/Bindings/rtc/snvs-rtc.txt
@@ -0,0 +1 @@
+See Documentation/devicetree/bindings/crypto/fsl-sec4.txt for details.
diff --git a/dts/Bindings/rtc/spear-rtc.txt b/dts/Bindings/rtc/spear-rtc.txt
new file mode 100644
index 0000000000..ca67ac6210
--- /dev/null
+++ b/dts/Bindings/rtc/spear-rtc.txt
@@ -0,0 +1,17 @@
+* SPEAr RTC
+
+Required properties:
+- compatible : "st,spear600-rtc"
+- reg : Address range of the rtc registers
+- interrupt-parent: Should be the phandle for the interrupt controller
+ that services interrupts for this device
+- interrupt: Should contain the rtc interrupt number
+
+Example:
+
+ rtc@fc000000 {
+ compatible = "st,spear600-rtc";
+ reg = <0xfc000000 0x1000>;
+ interrupt-parent = <&vic1>;
+ interrupts = <12>;
+ };
diff --git a/dts/Bindings/rtc/stmp3xxx-rtc.txt b/dts/Bindings/rtc/stmp3xxx-rtc.txt
new file mode 100644
index 0000000000..b800070fe6
--- /dev/null
+++ b/dts/Bindings/rtc/stmp3xxx-rtc.txt
@@ -0,0 +1,16 @@
+* STMP3xxx/i.MX28 Time Clock controller
+
+Required properties:
+- compatible: should be one of the following.
+ * "fsl,stmp3xxx-rtc"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: rtc alarm interrupt
+
+Example:
+
+rtc@80056000 {
+ compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
+ reg = <0x80056000 2000>;
+ interrupts = <29>;
+};
diff --git a/dts/Bindings/rtc/sunxi-rtc.txt b/dts/Bindings/rtc/sunxi-rtc.txt
new file mode 100644
index 0000000000..6983aad376
--- /dev/null
+++ b/dts/Bindings/rtc/sunxi-rtc.txt
@@ -0,0 +1,17 @@
+* sun4i/sun7i Real Time Clock
+
+RTC controller for the Allwinner A10/A20
+
+Required properties:
+- compatible : Should be "allwinner,sun4i-a10-rtc" or "allwinner,sun7i-a20-rtc"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: IRQ line for the RTC.
+
+Example:
+
+rtc: rtc@01c20d00 {
+ compatible = "allwinner,sun4i-a10-rtc";
+ reg = <0x01c20d00 0x20>;
+ interrupts = <24>;
+};
diff --git a/dts/Bindings/rtc/twl-rtc.txt b/dts/Bindings/rtc/twl-rtc.txt
new file mode 100644
index 0000000000..596e0c97be
--- /dev/null
+++ b/dts/Bindings/rtc/twl-rtc.txt
@@ -0,0 +1,12 @@
+* TI twl RTC
+
+The TWL family (twl4030/6030) contains a RTC.
+
+Required properties:
+- compatible : Should be twl4030-rtc
+
+Examples:
+
+rtc@0 {
+ compatible = "ti,twl4030-rtc";
+};
diff --git a/dts/Bindings/rtc/via,vt8500-rtc.txt b/dts/Bindings/rtc/via,vt8500-rtc.txt
new file mode 100644
index 0000000000..3c0484c495
--- /dev/null
+++ b/dts/Bindings/rtc/via,vt8500-rtc.txt
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 Realtime Clock Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-rtc"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : alarm interrupt
+
+Example:
+
+ rtc@d8100000 {
+ compatible = "via,vt8500-rtc";
+ reg = <0xd8100000 0x10000>;
+ interrupts = <48>;
+ };
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-25 15:26:41 +0000