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-rw-r--r--dts/Bindings/serial/cdns,uart.yaml31
1 files changed, 21 insertions, 10 deletions
diff --git a/dts/Bindings/serial/cdns,uart.yaml b/dts/Bindings/serial/cdns,uart.yaml
index fcdbe6f87e..e35ad1109e 100644
--- a/dts/Bindings/serial/cdns,uart.yaml
+++ b/dts/Bindings/serial/cdns,uart.yaml
@@ -4,13 +4,10 @@
$id: http://devicetree.org/schemas/serial/cdns,uart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Cadence UART Controller Device Tree Bindings
+title: Cadence UART Controller
maintainers:
- - Michal Simek <michal.simek@xilinx.com>
-
-allOf:
- - $ref: /schemas/serial.yaml#
+ - Michal Simek <michal.simek@amd.com>
properties:
compatible:
@@ -46,6 +43,9 @@ properties:
port does not use this pin.
type: boolean
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- reg
@@ -53,14 +53,25 @@ required:
- clocks
- clock-names
+allOf:
+ - $ref: serial.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: cdns,uart-r1p8
+ then:
+ properties:
+ power-domains: false
+
unevaluatedProperties: false
examples:
- |
uart0: serial@e0000000 {
- compatible = "xlnx,xuartps", "cdns,uart-r1p8";
- clocks = <&clkc 23>, <&clkc 40>;
- clock-names = "uart_clk", "pclk";
- reg = <0xE0000000 0x1000>;
- interrupts = <0 27 4>;
+ compatible = "xlnx,xuartps", "cdns,uart-r1p8";
+ clocks = <&clkc 23>, <&clkc 40>;
+ clock-names = "uart_clk", "pclk";
+ reg = <0xe0000000 0x1000>;
+ interrupts = <0 27 4>;
};