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-rw-r--r--dts/Bindings/serial/8250.txt1
-rw-r--r--dts/Bindings/serial/ingenic,uart.txt3
-rw-r--r--dts/Bindings/serial/milbeaut-uart.txt21
-rw-r--r--dts/Bindings/serial/nvidia,tegra194-tcu.txt35
-rw-r--r--dts/Bindings/serial/omap_serial.txt2
-rw-r--r--dts/Bindings/serial/pl011.txt51
-rw-r--r--dts/Bindings/serial/pl011.yaml126
-rw-r--r--dts/Bindings/serial/renesas,rzn1-uart.txt10
-rw-r--r--dts/Bindings/serial/renesas,sci-serial.txt2
-rw-r--r--dts/Bindings/serial/snps-dw-apb-uart.txt76
-rw-r--r--dts/Bindings/serial/snps-dw-apb-uart.yaml140
11 files changed, 329 insertions, 138 deletions
diff --git a/dts/Bindings/serial/8250.txt b/dts/Bindings/serial/8250.txt
index da50321..3cba12f 100644
--- a/dts/Bindings/serial/8250.txt
+++ b/dts/Bindings/serial/8250.txt
@@ -21,6 +21,7 @@ Required properties:
- "altr,16550-FIFO128"
- "fsl,16550-FIFO64"
- "fsl,ns16550"
+ - "intel,xscale-uart"
- "ti,da830-uart"
- "aspeed,ast2400-vuart"
- "aspeed,ast2500-vuart"
diff --git a/dts/Bindings/serial/ingenic,uart.txt b/dts/Bindings/serial/ingenic,uart.txt
index c3c6406..24ed876 100644
--- a/dts/Bindings/serial/ingenic,uart.txt
+++ b/dts/Bindings/serial/ingenic,uart.txt
@@ -6,7 +6,8 @@ Required properties:
- "ingenic,jz4760-uart",
- "ingenic,jz4770-uart",
- "ingenic,jz4775-uart",
- - "ingenic,jz4780-uart".
+ - "ingenic,jz4780-uart",
+ - "ingenic,x1000-uart".
- reg : offset and length of the register set for the device.
- interrupts : should contain uart interrupt.
- clocks : phandles to the module & baud clocks.
diff --git a/dts/Bindings/serial/milbeaut-uart.txt b/dts/Bindings/serial/milbeaut-uart.txt
new file mode 100644
index 0000000..3d2fb1a
--- /dev/null
+++ b/dts/Bindings/serial/milbeaut-uart.txt
@@ -0,0 +1,21 @@
+Socionext Milbeaut UART controller
+
+Required properties:
+- compatible: should be "socionext,milbeaut-usio-uart".
+- reg: offset and length of the register set for the device.
+- interrupts: two interrupts specifier.
+- interrupt-names: should be "rx", "tx".
+- clocks: phandle to the input clock.
+
+Optional properties:
+- auto-flow-control: flow control enable.
+
+Example:
+ usio1: usio_uart@1e700010 {
+ compatible = "socionext,milbeaut-usio-uart";
+ reg = <0x1e700010 0x10>;
+ interrupts = <0 141 0x4>, <0 149 0x4>;
+ interrupt-names = "rx", "tx";
+ clocks = <&clk 2>;
+ auto-flow-control;
+ };
diff --git a/dts/Bindings/serial/nvidia,tegra194-tcu.txt b/dts/Bindings/serial/nvidia,tegra194-tcu.txt
new file mode 100644
index 0000000..085a859
--- /dev/null
+++ b/dts/Bindings/serial/nvidia,tegra194-tcu.txt
@@ -0,0 +1,35 @@
+NVIDIA Tegra Combined UART (TCU)
+
+The TCU is a system for sharing a hardware UART instance among multiple
+systems within the Tegra SoC. It is implemented through a mailbox-
+based protocol where each "virtual UART" has a pair of mailboxes, one
+for transmitting and one for receiving, that is used to communicate
+with the hardware implementing the TCU.
+
+Required properties:
+- name : Should be tcu
+- compatible
+ Array of strings
+ One of:
+ - "nvidia,tegra194-tcu"
+- mbox-names:
+ "rx" - Mailbox for receiving data from hardware UART
+ "tx" - Mailbox for transmitting data to hardware UART
+- mboxes: Mailboxes corresponding to the mbox-names.
+
+This node is a mailbox consumer. See the following files for details of
+the mailbox subsystem, and the specifiers implemented by the relevant
+provider(s):
+
+- .../mailbox/mailbox.txt
+- .../mailbox/nvidia,tegra186-hsp.txt
+
+Example bindings:
+-----------------
+
+tcu: tcu {
+ compatible = "nvidia,tegra194-tcu";
+ mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>,
+ <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>;
+ mbox-names = "rx", "tx";
+};
diff --git a/dts/Bindings/serial/omap_serial.txt b/dts/Bindings/serial/omap_serial.txt
index c35d5ec..0a9b544 100644
--- a/dts/Bindings/serial/omap_serial.txt
+++ b/dts/Bindings/serial/omap_serial.txt
@@ -22,6 +22,8 @@ Optional properties:
- dma-names : "rx" for receive channel, "tx" for transmit channel.
- rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt
- rs485-rts-active-high: drive RTS high when sending (default is low).
+- clocks: phandle to the functional clock as per
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
Example:
diff --git a/dts/Bindings/serial/pl011.txt b/dts/Bindings/serial/pl011.txt
deleted file mode 100644
index 77863ae..0000000
--- a/dts/Bindings/serial/pl011.txt
+++ /dev/null
@@ -1,51 +0,0 @@
-* ARM AMBA Primecell PL011 serial UART
-
-Required properties:
-- compatible: must be "arm,primecell", "arm,pl011", "zte,zx296702-uart"
-- reg: exactly one register range with length 0x1000
-- interrupts: exactly one interrupt specifier
-
-Optional properties:
-- pinctrl:
- When present, must have one state named "default",
- and may contain a second name named "sleep". The former
- state sets up pins for ordinary operation whereas
- the latter state will put the associated pins to sleep
- when the UART is unused
-- clocks:
- When present, the first clock listed must correspond to
- the clock named UARTCLK on the IP block, i.e. the clock
- to the external serial line, whereas the second clock
- must correspond to the PCLK clocking the internal logic
- of the block. Just listing one clock (the first one) is
- deprecated.
-- clock-names:
- When present, the first clock listed must be named
- "uartclk" and the second clock listed must be named
- "apb_pclk"
-- dmas:
- When present, may have one or two dma channels.
- The first one must be named "rx", the second one
- must be named "tx".
-- auto-poll:
- Enables polling when using RX DMA.
-- poll-rate-ms:
- Rate at which poll occurs when auto-poll is set,
- default 100ms.
-- poll-timeout-ms:
- Poll timeout when auto-poll is set, default
- 3000ms.
-
-See also bindings/arm/primecell.txt
-
-Example:
-
-uart@80120000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0x80120000 0x1000>;
- interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dma 13 0 0x2>, <&dma 13 0 0x0>;
- dma-names = "rx", "tx";
- clocks = <&foo_clk>, <&bar_clk>;
- clock-names = "uartclk", "apb_pclk";
-};
diff --git a/dts/Bindings/serial/pl011.yaml b/dts/Bindings/serial/pl011.yaml
new file mode 100644
index 0000000..1a64d59
--- /dev/null
+++ b/dts/Bindings/serial/pl011.yaml
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/pl011.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM AMBA Primecell PL011 serial UART
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+allOf:
+ - $ref: /schemas/serial.yaml#
+
+# Need a custom select here or 'arm,primecell' will match on lots of nodes
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - arm,pl011
+ - zte,zx296702-uart
+ required:
+ - compatible
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: arm,pl011
+ - const: arm,primecell
+ - items:
+ - const: zte,zx296702-uart
+ - const: arm,primecell
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ pinctrl-0: true
+ pinctrl-1: true
+
+ pinctrl-names:
+ description:
+ When present, must have one state named "default",
+ and may contain a second name named "sleep". The former
+ state sets up pins for ordinary operation whereas
+ the latter state will put the associated pins to sleep
+ when the UART is unused
+ minItems: 1
+ items:
+ - const: default
+ - const: sleep
+
+ clocks:
+ description:
+ When present, the first clock listed must correspond to
+ the clock named UARTCLK on the IP block, i.e. the clock
+ to the external serial line, whereas the second clock
+ must correspond to the PCLK clocking the internal logic
+ of the block. Just listing one clock (the first one) is
+ deprecated.
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: uartclk
+ - const: apb_pclk
+
+ dmas:
+ minItems: 1
+ maxItems: 2
+
+ dma-names:
+ minItems: 1
+ items:
+ - const: rx
+ - const: tx
+
+ auto-poll:
+ description:
+ Enables polling when using RX DMA.
+ type: boolean
+
+ poll-rate-ms:
+ description:
+ Rate at which poll occurs when auto-poll is set.
+ default 100ms.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - default: 100
+
+ poll-timeout-ms:
+ description:
+ Poll timeout when auto-poll is set, default
+ 3000ms.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - default: 3000
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+dependencies:
+ poll-rate-ms: [ auto-poll ]
+ poll-timeout-ms: [ auto-poll ]
+
+additionalProperties: false
+
+examples:
+ - |
+ serial@80120000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x80120000 0x1000>;
+ interrupts = <0 11 4>;
+ dmas = <&dma 13 0 0x2>, <&dma 13 0 0x0>;
+ dma-names = "rx", "tx";
+ clocks = <&foo_clk>, <&bar_clk>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+...
diff --git a/dts/Bindings/serial/renesas,rzn1-uart.txt b/dts/Bindings/serial/renesas,rzn1-uart.txt
deleted file mode 100644
index 8b9e0d4..0000000
--- a/dts/Bindings/serial/renesas,rzn1-uart.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-Renesas RZ/N1 UART
-
-This controller is based on the Synopsys DesignWare ABP UART and inherits all
-properties defined in snps-dw-apb-uart.txt except for the compatible property.
-
-Required properties:
-- compatible : The device specific string followed by the generic RZ/N1 string.
- Therefore it must be one of:
- "renesas,r9a06g032-uart", "renesas,rzn1-uart"
- "renesas,r9a06g033-uart", "renesas,rzn1-uart"
diff --git a/dts/Bindings/serial/renesas,sci-serial.txt b/dts/Bindings/serial/renesas,sci-serial.txt
index 20232ad..dd63151 100644
--- a/dts/Bindings/serial/renesas,sci-serial.txt
+++ b/dts/Bindings/serial/renesas,sci-serial.txt
@@ -29,7 +29,9 @@ Required properties:
- "renesas,scif-r8a774c0" for R8A774C0 (RZ/G2E) SCIF compatible UART.
- "renesas,hscif-r8a774c0" for R8A774C0 (RZ/G2E) HSCIF compatible UART.
- "renesas,scif-r8a7778" for R8A7778 (R-Car M1) SCIF compatible UART.
+ - "renesas,hscif-r8a7778" for R8A7778 (R-Car M1) HSCIF compatible UART.
- "renesas,scif-r8a7779" for R8A7779 (R-Car H1) SCIF compatible UART.
+ - "renesas,hscif-r8a7779" for R8A7779 (R-Car H1) HSCIF compatible UART.
- "renesas,scif-r8a7790" for R8A7790 (R-Car H2) SCIF compatible UART.
- "renesas,scifa-r8a7790" for R8A7790 (R-Car H2) SCIFA compatible UART.
- "renesas,scifb-r8a7790" for R8A7790 (R-Car H2) SCIFB compatible UART.
diff --git a/dts/Bindings/serial/snps-dw-apb-uart.txt b/dts/Bindings/serial/snps-dw-apb-uart.txt
deleted file mode 100644
index 12bbe9f..0000000
--- a/dts/Bindings/serial/snps-dw-apb-uart.txt
+++ /dev/null
@@ -1,76 +0,0 @@
-* Synopsys DesignWare ABP UART
-
-Required properties:
-- compatible : "snps,dw-apb-uart"
-- reg : offset and length of the register set for the device.
-- interrupts : should contain uart interrupt.
-
-Clock handling:
-The clock rate of the input clock needs to be supplied by one of
-- clock-frequency : the input clock frequency for the UART.
-- clocks : phandle to the input clock
-
-The supplying peripheral clock can also be handled, needing a second property
-- clock-names: tuple listing input clock names.
- Required elements: "baudclk", "apb_pclk"
-
-Optional properties:
-- snps,uart-16550-compatible : reflects the value of UART_16550_COMPATIBLE
- configuration parameter. Define this if your UART does not implement the busy
- functionality.
-- resets : phandle to the parent reset controller.
-- reg-shift : quantity to shift the register offsets by. If this property is
- not present then the register offsets are not shifted.
-- reg-io-width : the size (in bytes) of the IO accesses that should be
- performed on the device. If this property is not present then single byte
- accesses are used.
-- dcd-override : Override the DCD modem status signal. This signal will always
- be reported as active instead of being obtained from the modem status
- register. Define this if your serial port does not use this pin.
-- dsr-override : Override the DTS modem status signal. This signal will always
- be reported as active instead of being obtained from the modem status
- register. Define this if your serial port does not use this pin.
-- cts-override : Override the CTS modem status signal. This signal will always
- be reported as active instead of being obtained from the modem status
- register. Define this if your serial port does not use this pin.
-- ri-override : Override the RI modem status signal. This signal will always be
- reported as inactive instead of being obtained from the modem status register.
- Define this if your serial port does not use this pin.
-
-Example:
-
- uart@80230000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x80230000 0x100>;
- clock-frequency = <3686400>;
- interrupts = <10>;
- reg-shift = <2>;
- reg-io-width = <4>;
- dcd-override;
- dsr-override;
- cts-override;
- ri-override;
- };
-
-Example with one clock:
-
- uart@80230000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x80230000 0x100>;
- clocks = <&baudclk>;
- interrupts = <10>;
- reg-shift = <2>;
- reg-io-width = <4>;
- };
-
-Example with two clocks:
-
- uart@80230000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x80230000 0x100>;
- clocks = <&baudclk>, <&apb_pclk>;
- clock-names = "baudclk", "apb_pclk";
- interrupts = <10>;
- reg-shift = <2>;
- reg-io-width = <4>;
- };
diff --git a/dts/Bindings/serial/snps-dw-apb-uart.yaml b/dts/Bindings/serial/snps-dw-apb-uart.yaml
new file mode 100644
index 0000000..b420025
--- /dev/null
+++ b/dts/Bindings/serial/snps-dw-apb-uart.yaml
@@ -0,0 +1,140 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare ABP UART
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+allOf:
+ - $ref: /schemas/serial.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - renesas,r9a06g032-uart
+ - renesas,r9a06g033-uart
+ - const: renesas,rzn1-uart
+ - items:
+ - enum:
+ - rockchip,px30-uart
+ - rockchip,rk3036-uart
+ - rockchip,rk3066-uart
+ - rockchip,rk3188-uart
+ - rockchip,rk3288-uart
+ - rockchip,rk3328-uart
+ - rockchip,rk3368-uart
+ - rockchip,rk3399-uart
+ - rockchip,rv1108-uart
+ - const: snps,dw-apb-uart
+ - items:
+ - enum:
+ - brcm,bcm11351-dw-apb-uart
+ - brcm,bcm21664-dw-apb-uart
+ - const: snps,dw-apb-uart
+ - const: snps,dw-apb-uart
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clock-frequency: true
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: baudclk
+ - const: apb_pclk
+
+ snps,uart-16550-compatible:
+ description: reflects the value of UART_16550_COMPATIBLE configuration
+ parameter. Define this if your UART does not implement the busy functionality.
+ type: boolean
+
+ resets:
+ maxItems: 1
+
+ reg-shift: true
+
+ reg-io-width: true
+
+ dcd-override:
+ description: Override the DCD modem status signal. This signal will
+ always be reported as active instead of being obtained from the modem
+ status register. Define this if your serial port does not use this
+ pin.
+ type: boolean
+
+ dsr-override:
+ description: Override the DTS modem status signal. This signal will
+ always be reported as active instead of being obtained from the modem
+ status register. Define this if your serial port does not use this
+ pin.
+ type: boolean
+
+ cts-override:
+ description: Override the CTS modem status signal. This signal will
+ always be reported as active instead of being obtained from the modem
+ status register. Define this if your serial port does not use this
+ pin.
+ type: boolean
+
+ ri-override:
+ description: Override the RI modem status signal. This signal will always
+ be reported as inactive instead of being obtained from the modem status
+ register. Define this if your serial port does not use this pin.
+ type: boolean
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+examples:
+ - |
+ serial@80230000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x80230000 0x100>;
+ clock-frequency = <3686400>;
+ interrupts = <10>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dcd-override;
+ dsr-override;
+ cts-override;
+ ri-override;
+ };
+
+ - |
+ // Example with one clock:
+ serial@80230000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x80230000 0x100>;
+ clocks = <&baudclk>;
+ interrupts = <10>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+
+ - |
+ // Example with two clocks:
+ serial@80230000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x80230000 0x100>;
+ clocks = <&baudclk>, <&apb_pclk>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <10>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+...