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-rw-r--r--dts/Bindings/serial/fsl-imx-uart.txt6
-rw-r--r--dts/Bindings/serial/maxim,max310x.txt2
-rw-r--r--dts/Bindings/serial/mtk-uart.txt1
-rw-r--r--dts/Bindings/serial/nxp,sc16is7xx.txt4
-rw-r--r--dts/Bindings/serial/omap_serial.txt1
-rw-r--r--dts/Bindings/serial/qca,ar9330-uart.txt3
-rw-r--r--dts/Bindings/serial/renesas,rzn1-uart.txt10
-rw-r--r--dts/Bindings/serial/renesas,sci-serial.txt19
-rw-r--r--dts/Bindings/serial/xlnx,opb-uartlite.txt23
9 files changed, 57 insertions, 12 deletions
diff --git a/dts/Bindings/serial/fsl-imx-uart.txt b/dts/Bindings/serial/fsl-imx-uart.txt
index afcfbc3..35957cb 100644
--- a/dts/Bindings/serial/fsl-imx-uart.txt
+++ b/dts/Bindings/serial/fsl-imx-uart.txt
@@ -9,7 +9,11 @@ Optional properties:
- fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
in DCE mode by default.
- rs485-rts-delay, rs485-rts-active-low, rs485-rx-during-tx,
- linux,rs485-enabled-at-boot-time: see rs485.txt
+ linux,rs485-enabled-at-boot-time: see rs485.txt. Note that for RS485
+ you must enable either the "uart-has-rtscts" or the "rts-gpios"
+ properties. In case you use "uart-has-rtscts" the signal that controls
+ the transceiver is actually CTS_B, not RTS_B. CTS_B is always output,
+ and RTS_B is input, regardless of dte-mode.
Please check Documentation/devicetree/bindings/serial/serial.txt
for the complete list of generic properties.
diff --git a/dts/Bindings/serial/maxim,max310x.txt b/dts/Bindings/serial/maxim,max310x.txt
index 823f77d..79e10a0 100644
--- a/dts/Bindings/serial/maxim,max310x.txt
+++ b/dts/Bindings/serial/maxim,max310x.txt
@@ -7,8 +7,6 @@ Required properties:
- "maxim,max3109" for Maxim MAX3109,
- "maxim,max14830" for Maxim MAX14830.
- reg: SPI chip select number.
-- interrupt-parent: The phandle for the interrupt controller that
- services interrupts for this IC.
- interrupts: Specifies the interrupt source of the parent interrupt
controller. The format of the interrupt specifier depends on the
parent interrupt controller.
diff --git a/dts/Bindings/serial/mtk-uart.txt b/dts/Bindings/serial/mtk-uart.txt
index f73abff..742cb47 100644
--- a/dts/Bindings/serial/mtk-uart.txt
+++ b/dts/Bindings/serial/mtk-uart.txt
@@ -8,6 +8,7 @@ Required properties:
* "mediatek,mt6582-uart" for MT6582 compatible UARTS
* "mediatek,mt6589-uart" for MT6589 compatible UARTS
* "mediatek,mt6755-uart" for MT6755 compatible UARTS
+ * "mediatek,mt6765-uart" for MT6765 compatible UARTS
* "mediatek,mt6795-uart" for MT6795 compatible UARTS
* "mediatek,mt6797-uart" for MT6797 compatible UARTS
* "mediatek,mt7622-uart" for MT7622 compatible UARTS
diff --git a/dts/Bindings/serial/nxp,sc16is7xx.txt b/dts/Bindings/serial/nxp,sc16is7xx.txt
index fbfe536..e7921a8 100644
--- a/dts/Bindings/serial/nxp,sc16is7xx.txt
+++ b/dts/Bindings/serial/nxp,sc16is7xx.txt
@@ -10,8 +10,6 @@ Required properties:
- "nxp,sc16is760" for NXP SC16IS760,
- "nxp,sc16is762" for NXP SC16IS762.
- reg: I2C address of the SC16IS7xx device.
-- interrupt-parent: The phandle for the interrupt controller that
- services interrupts for this IC.
- interrupts: Should contain the UART interrupt
- clocks: Reference to the IC source clock.
@@ -44,8 +42,6 @@ Required properties:
- "nxp,sc16is760" for NXP SC16IS760,
- "nxp,sc16is762" for NXP SC16IS762.
- reg: SPI chip select number.
-- interrupt-parent: The phandle for the interrupt controller that
- services interrupts for this IC.
- interrupts: Specifies the interrupt source of the parent interrupt
controller. The format of the interrupt specifier depends on the
parent interrupt controller.
diff --git a/dts/Bindings/serial/omap_serial.txt b/dts/Bindings/serial/omap_serial.txt
index 4b0f05a..c35d5ec 100644
--- a/dts/Bindings/serial/omap_serial.txt
+++ b/dts/Bindings/serial/omap_serial.txt
@@ -1,6 +1,7 @@
OMAP UART controller
Required properties:
+- compatible : should be "ti,am654-uart" for AM654 controllers
- compatible : should be "ti,omap2-uart" for OMAP2 controllers
- compatible : should be "ti,omap3-uart" for OMAP3 controllers
- compatible : should be "ti,omap4-uart" for OMAP4 controllers
diff --git a/dts/Bindings/serial/qca,ar9330-uart.txt b/dts/Bindings/serial/qca,ar9330-uart.txt
index c5e032c..7d65126 100644
--- a/dts/Bindings/serial/qca,ar9330-uart.txt
+++ b/dts/Bindings/serial/qca,ar9330-uart.txt
@@ -7,9 +7,6 @@ Required properties:
- reg: Specifies the physical base address of the controller and
the length of the memory mapped region.
-- interrupt-parent: The phandle for the interrupt controller that
- services interrupts for this device.
-
- interrupts: Specifies the interrupt source of the parent interrupt
controller. The format of the interrupt specifier depends on the
parent interrupt controller.
diff --git a/dts/Bindings/serial/renesas,rzn1-uart.txt b/dts/Bindings/serial/renesas,rzn1-uart.txt
new file mode 100644
index 0000000..8b9e0d4
--- /dev/null
+++ b/dts/Bindings/serial/renesas,rzn1-uart.txt
@@ -0,0 +1,10 @@
+Renesas RZ/N1 UART
+
+This controller is based on the Synopsys DesignWare ABP UART and inherits all
+properties defined in snps-dw-apb-uart.txt except for the compatible property.
+
+Required properties:
+- compatible : The device specific string followed by the generic RZ/N1 string.
+ Therefore it must be one of:
+ "renesas,r9a06g032-uart", "renesas,rzn1-uart"
+ "renesas,r9a06g033-uart", "renesas,rzn1-uart"
diff --git a/dts/Bindings/serial/renesas,sci-serial.txt b/dts/Bindings/serial/renesas,sci-serial.txt
index 106808b..eaca9da 100644
--- a/dts/Bindings/serial/renesas,sci-serial.txt
+++ b/dts/Bindings/serial/renesas,sci-serial.txt
@@ -5,6 +5,7 @@ Required properties:
- compatible: Must contain one or more of the following:
- "renesas,scif-r7s72100" for R7S72100 (RZ/A1H) SCIF compatible UART.
+ - "renesas,scif-r7s9210" for R7S9210 (RZ/A2) SCIF compatible UART.
- "renesas,scifa-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFA compatible UART.
- "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART.
- "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART.
@@ -72,7 +73,21 @@ Required properties:
family-specific and/or generic versions.
- reg: Base address and length of the I/O registers used by the UART.
- - interrupts: Must contain an interrupt-specifier for the SCIx interrupt.
+ - interrupts: Must contain one or more interrupt-specifiers for the SCIx.
+ If a single interrupt is expressed, then all events are
+ multiplexed into this single interrupt.
+
+ If multiple interrupts are provided by the hardware, the order
+ in which the interrupts are listed must match order below. Note
+ that some HW interrupt events may be muxed together resulting
+ in duplicate entries.
+ The interrupt order is as follows:
+ 1. Error (ERI)
+ 2. Receive buffer full (RXI)
+ 3. Transmit buffer empty (TXI)
+ 4. Break (BRI)
+ 5. Data Ready (DRI)
+ 6. Transmit End (TEI)
- clocks: Must contain a phandle and clock-specifier pair for each entry
in clock-names.
@@ -89,7 +104,7 @@ Required properties:
- "scif_clk" for the optional external clock source for the frequency
divider (SCIF_CLK).
-Note: Each enabled SCIx UART should have an alias correctly numbered in the
+Note: Each enabled SCIx UART may have an optional "serialN" alias in the
"aliases" node.
Optional properties:
diff --git a/dts/Bindings/serial/xlnx,opb-uartlite.txt b/dts/Bindings/serial/xlnx,opb-uartlite.txt
new file mode 100644
index 0000000..c37deb4
--- /dev/null
+++ b/dts/Bindings/serial/xlnx,opb-uartlite.txt
@@ -0,0 +1,23 @@
+Xilinx Axi Uartlite controller Device Tree Bindings
+---------------------------------------------------------
+
+Required properties:
+- compatible : Can be either of
+ "xlnx,xps-uartlite-1.00.a"
+ "xlnx,opb-uartlite-1.00.b"
+- reg : Physical base address and size of the Axi Uartlite
+ registers map.
+- interrupts : Should contain the UART controller interrupt.
+
+Optional properties:
+- port-number : Set Uart port number
+- clock-names : Should be "s_axi_aclk"
+- clocks : Input clock specifier. Refer to common clock bindings.
+
+Example:
+serial@800c0000 {
+ compatible = "xlnx,xps-uartlite-1.00.a";
+ reg = <0x0 0x800c0000 0x10000>;
+ interrupts = <0x0 0x6e 0x1>;
+ port-number = <0>;
+};