summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/serial
diff options
context:
space:
mode:
Diffstat (limited to 'dts/Bindings/serial')
-rw-r--r--dts/Bindings/serial/cirrus,clps711x-uart.txt7
-rw-r--r--dts/Bindings/serial/mtk-uart.txt22
-rw-r--r--dts/Bindings/serial/of-serial.txt2
-rw-r--r--dts/Bindings/serial/via,vt8500-uart.txt17
-rw-r--r--dts/Bindings/serial/vt8500-uart.txt3
5 files changed, 30 insertions, 21 deletions
diff --git a/dts/Bindings/serial/cirrus,clps711x-uart.txt b/dts/Bindings/serial/cirrus,clps711x-uart.txt
index 12f3cf834d..caaeb25835 100644
--- a/dts/Bindings/serial/cirrus,clps711x-uart.txt
+++ b/dts/Bindings/serial/cirrus,clps711x-uart.txt
@@ -8,7 +8,8 @@ Required properties:
- syscon: Phandle to SYSCON node, which contain UART control bits.
Optional properties:
-- uart-use-ms: Indicate the UART has modem signal (DCD, DSR, CTS).
+- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
+ line respectively.
Note: Each UART port should have an alias correctly numbered
in "aliases" node.
@@ -24,5 +25,7 @@ Example:
interrupts = <12 13>;
clocks = <&clks 11>;
syscon = <&syscon1>;
- uart-use-ms;
+ cts-gpios = <&sysgpio 0 GPIO_ACTIVE_LOW>;
+ dsr-gpios = <&sysgpio 1 GPIO_ACTIVE_LOW>;
+ dcd-gpios = <&sysgpio 2 GPIO_ACTIVE_LOW>;
};
diff --git a/dts/Bindings/serial/mtk-uart.txt b/dts/Bindings/serial/mtk-uart.txt
new file mode 100644
index 0000000000..48358a33ea
--- /dev/null
+++ b/dts/Bindings/serial/mtk-uart.txt
@@ -0,0 +1,22 @@
+* Mediatek Universal Asynchronous Receiver/Transmitter (UART)
+
+Required properties:
+- compatible should contain:
+ * "mediatek,mt6589-uart" for MT6589 compatible UARTS
+ * "mediatek,mt6582-uart" for MT6582 compatible UARTS
+ * "mediatek,mt6577-uart" for all compatible UARTS (MT6589, MT6582, MT6577)
+
+- reg: The base address of the UART register bank.
+
+- interrupts: A single interrupt specifier.
+
+- clocks: Clock driving the hardware.
+
+Example:
+
+ uart0: serial@11006000 {
+ compatible = "mediatek,mt6589-uart", "mediatek,mt6577-uart";
+ reg = <0x11006000 0x400>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&uart_clk>;
+ };
diff --git a/dts/Bindings/serial/of-serial.txt b/dts/Bindings/serial/of-serial.txt
index 77054772a8..8c4fd03320 100644
--- a/dts/Bindings/serial/of-serial.txt
+++ b/dts/Bindings/serial/of-serial.txt
@@ -14,6 +14,7 @@ Required properties:
- "altr,16550-FIFO32"
- "altr,16550-FIFO64"
- "altr,16550-FIFO128"
+ - "fsl,16550-FIFO64"
- "serial" if the port type is unknown.
- reg : offset and length of the register set for the device.
- interrupts : should contain uart interrupt.
@@ -37,7 +38,6 @@ Optional properties:
- auto-flow-control: one way to enable automatic flow control support. The
driver is allowed to detect support for the capability even without this
property.
-- has-hw-flow-control: the hardware has flow control capability.
Example:
diff --git a/dts/Bindings/serial/via,vt8500-uart.txt b/dts/Bindings/serial/via,vt8500-uart.txt
deleted file mode 100644
index 5feef1ef16..0000000000
--- a/dts/Bindings/serial/via,vt8500-uart.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-VIA/Wondermedia VT8500 UART Controller
------------------------------------------------------
-
-Required properties:
-- compatible : "via,vt8500-uart"
-- reg : Should contain 1 register ranges(address and length)
-- interrupts : UART interrupt
-- clocks : phandle to the uart source clock (usually a 24Mhz fixed clock)
-
-Example:
-
- uart@d8210000 {
- compatible = "via,vt8500-uart";
- reg = <0xd8210000 0x1040>;
- interrupts = <47>;
- clocks = <&ref24>;
- };
diff --git a/dts/Bindings/serial/vt8500-uart.txt b/dts/Bindings/serial/vt8500-uart.txt
index 795c393d09..2b64e6107f 100644
--- a/dts/Bindings/serial/vt8500-uart.txt
+++ b/dts/Bindings/serial/vt8500-uart.txt
@@ -1,7 +1,8 @@
* VIA VT8500 and WonderMedia WM8xxx UART Controller
Required properties:
-- compatible: should be "via,vt8500-uart"
+- compatible: should be "via,vt8500-uart" (for VIA/WonderMedia chips up to and
+ including WM8850/WM8950), or "wm,wm8880-uart" (for WM8880 and later)
- reg: base physical address of the controller and length of memory mapped
region.