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-rw-r--r--dts/Bindings/serial/arm_sbsa_uart.txt10
-rw-r--r--dts/Bindings/serial/ingenic,uart.txt22
-rw-r--r--dts/Bindings/serial/mtk-uart.txt12
-rw-r--r--dts/Bindings/serial/nxp,lpc1850-uart.txt28
-rw-r--r--dts/Bindings/serial/nxp,sc16is7xx.txt37
-rw-r--r--dts/Bindings/serial/pl011.txt2
-rw-r--r--dts/Bindings/serial/renesas,sci-serial.txt8
-rw-r--r--dts/Bindings/serial/sirf-uart.txt15
-rw-r--r--dts/Bindings/serial/uniphier-uart.txt23
9 files changed, 140 insertions, 17 deletions
diff --git a/dts/Bindings/serial/arm_sbsa_uart.txt b/dts/Bindings/serial/arm_sbsa_uart.txt
new file mode 100644
index 0000000000..4163e7eb77
--- /dev/null
+++ b/dts/Bindings/serial/arm_sbsa_uart.txt
@@ -0,0 +1,10 @@
+* ARM SBSA defined generic UART
+This UART uses a subset of the PL011 registers and consequently lives
+in the PL011 driver. It's baudrate and other communication parameters
+cannot be adjusted at runtime, so it lacks a clock specifier here.
+
+Required properties:
+- compatible: must be "arm,sbsa-uart"
+- reg: exactly one register range
+- interrupts: exactly one interrupt specifier
+- current-speed: the (fixed) baud rate set by the firmware
diff --git a/dts/Bindings/serial/ingenic,uart.txt b/dts/Bindings/serial/ingenic,uart.txt
new file mode 100644
index 0000000000..c2d3b3abe7
--- /dev/null
+++ b/dts/Bindings/serial/ingenic,uart.txt
@@ -0,0 +1,22 @@
+* Ingenic SoC UART
+
+Required properties:
+- compatible : "ingenic,jz4740-uart" or "ingenic,jz4780-uart"
+- reg : offset and length of the register set for the device.
+- interrupts : should contain uart interrupt.
+- clocks : phandles to the module & baud clocks.
+- clock-names: tuple listing input clock names.
+ Required elements: "baud", "module"
+
+Example:
+
+uart0: serial@10030000 {
+ compatible = "ingenic,jz4740-uart";
+ reg = <0x10030000 0x100>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <9>;
+
+ clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
+ clock-names = "baud", "module";
+};
diff --git a/dts/Bindings/serial/mtk-uart.txt b/dts/Bindings/serial/mtk-uart.txt
index 44152261e5..8d63f1da07 100644
--- a/dts/Bindings/serial/mtk-uart.txt
+++ b/dts/Bindings/serial/mtk-uart.txt
@@ -14,7 +14,14 @@ Required properties:
- interrupts: A single interrupt specifier.
-- clocks: Clock driving the hardware.
+- clocks : Must contain an entry for each entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+- clock-names:
+ - "baud": The clock the baudrate is derived from
+ - "bus": The bus clock for register accesses (optional)
+
+For compatibility with older device trees an unnamed clock is used for the
+baud clock if the baudclk does not exist. Do not use this for new designs.
Example:
@@ -22,5 +29,6 @@ Example:
compatible = "mediatek,mt6589-uart", "mediatek,mt6577-uart";
reg = <0x11006000 0x400>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&uart_clk>, <&bus_clk>;
+ clock-names = "baud", "bus";
};
diff --git a/dts/Bindings/serial/nxp,lpc1850-uart.txt b/dts/Bindings/serial/nxp,lpc1850-uart.txt
new file mode 100644
index 0000000000..04e23e63ee
--- /dev/null
+++ b/dts/Bindings/serial/nxp,lpc1850-uart.txt
@@ -0,0 +1,28 @@
+* NXP LPC1850 UART
+
+Required properties:
+- compatible : "nxp,lpc1850-uart", "ns16550a".
+- reg : offset and length of the register set for the device.
+- interrupts : should contain uart interrupt.
+- clocks : phandle to the input clocks.
+- clock-names : required elements: "uartclk", "reg".
+
+Optional properties:
+- dmas : Two or more DMA channel specifiers following the
+ convention outlined in bindings/dma/dma.txt
+- dma-names : Names for the dma channels, if present. There must
+ be at least one channel named "tx" for transmit
+ and named "rx" for receive.
+
+Since it's also possible to also use the of_serial.c driver all
+parameters from 8250.txt also apply but are optional.
+
+Example:
+uart0: serial@40081000 {
+ compatible = "nxp,lpc1850-uart", "ns16550a";
+ reg = <0x40081000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <24>;
+ clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
+ clock-names = "uartclk", "reg";
+};
diff --git a/dts/Bindings/serial/nxp,sc16is7xx.txt b/dts/Bindings/serial/nxp,sc16is7xx.txt
index 246c795668..fbfe53635a 100644
--- a/dts/Bindings/serial/nxp,sc16is7xx.txt
+++ b/dts/Bindings/serial/nxp,sc16is7xx.txt
@@ -1,4 +1,5 @@
* NXP SC16IS7xx advanced Universal Asynchronous Receiver-Transmitter (UART)
+* i2c as bus
Required properties:
- compatible: Should be one of the following:
@@ -31,3 +32,39 @@ Example:
gpio-controller;
#gpio-cells = <2>;
};
+
+* spi as bus
+
+Required properties:
+- compatible: Should be one of the following:
+ - "nxp,sc16is740" for NXP SC16IS740,
+ - "nxp,sc16is741" for NXP SC16IS741,
+ - "nxp,sc16is750" for NXP SC16IS750,
+ - "nxp,sc16is752" for NXP SC16IS752,
+ - "nxp,sc16is760" for NXP SC16IS760,
+ - "nxp,sc16is762" for NXP SC16IS762.
+- reg: SPI chip select number.
+- interrupt-parent: The phandle for the interrupt controller that
+ services interrupts for this IC.
+- interrupts: Specifies the interrupt source of the parent interrupt
+ controller. The format of the interrupt specifier depends on the
+ parent interrupt controller.
+- clocks: phandle to the IC source clock.
+
+Optional properties:
+- gpio-controller: Marks the device node as a GPIO controller.
+- #gpio-cells: Should be two. The first cell is the GPIO number and
+ the second cell is used to specify the GPIO polarity:
+ 0 = active high,
+ 1 = active low.
+
+Example:
+ sc16is750: sc16is750@0 {
+ compatible = "nxp,sc16is750";
+ reg = <0>;
+ clocks = <&clk20m>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
diff --git a/dts/Bindings/serial/pl011.txt b/dts/Bindings/serial/pl011.txt
index ba3ecb8cb5..cbae3d9a02 100644
--- a/dts/Bindings/serial/pl011.txt
+++ b/dts/Bindings/serial/pl011.txt
@@ -1,7 +1,7 @@
* ARM AMBA Primecell PL011 serial UART
Required properties:
-- compatible: must be "arm,primecell", "arm,pl011"
+- compatible: must be "arm,primecell", "arm,pl011", "zte,zx296702-uart"
- reg: exactly one register range with length 0x1000
- interrupts: exactly one interrupt specifier
diff --git a/dts/Bindings/serial/renesas,sci-serial.txt b/dts/Bindings/serial/renesas,sci-serial.txt
index ae73bb0e9a..e84b13a8ed 100644
--- a/dts/Bindings/serial/renesas,sci-serial.txt
+++ b/dts/Bindings/serial/renesas,sci-serial.txt
@@ -29,6 +29,7 @@ Required properties:
- "renesas,scifa" for generic SCIFA compatible UART.
- "renesas,scifb" for generic SCIFB compatible UART.
- "renesas,hscif" for generic HSCIF compatible UART.
+ - "renesas,sci" for generic SCI compatible UART.
When compatible with the generic version, nodes must list the
SoC-specific version corresponding to the platform first followed by the
@@ -44,6 +45,11 @@ Required properties:
Note: Each enabled SCIx UART should have an alias correctly numbered in the
"aliases" node.
+Optional properties:
+ - dmas: Must contain a list of two references to DMA specifiers, one for
+ transmission, and one for reception.
+ - dma-names: Must contain a list of two DMA names, "tx" and "rx".
+
Example:
aliases {
serial0 = &scifa0;
@@ -56,4 +62,6 @@ Example:
interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
clock-names = "sci_ick";
+ dmas = <&dmac0 0x21>, <&dmac0 0x22>;
+ dma-names = "tx", "rx";
};
diff --git a/dts/Bindings/serial/sirf-uart.txt b/dts/Bindings/serial/sirf-uart.txt
index f0c39261c5..67e2a0aeb0 100644
--- a/dts/Bindings/serial/sirf-uart.txt
+++ b/dts/Bindings/serial/sirf-uart.txt
@@ -2,8 +2,7 @@
Required properties:
- compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart",
- "sirf,atlas7-uart" or "sirf,atlas7-bt-uart" which means
- uart located in BT module and used for BT.
+ "sirf,atlas7-uart" or "sirf,atlas7-usp-uart".
- reg : Offset and length of the register set for the device
- interrupts : Should contain uart interrupt
- fifosize : Should define hardware rx/tx fifo size
@@ -33,15 +32,3 @@ usp@b0090000 {
rts-gpios = <&gpio 15 0>;
cts-gpios = <&gpio 46 0>;
};
-
-for uart use in BT module,
-uart6: uart@11000000 {
- cell-index = <6>;
- compatible = "sirf,atlas7-bt-uart", "sirf,atlas7-uart";
- reg = <0x11000000 0x1000>;
- interrupts = <0 100 0>;
- clocks = <&clks 138>, <&clks 140>, <&clks 141>;
- clock-names = "uart", "general", "noc";
- fifosize = <128>;
- status = "disabled";
-}
diff --git a/dts/Bindings/serial/uniphier-uart.txt b/dts/Bindings/serial/uniphier-uart.txt
new file mode 100644
index 0000000000..0b3892a7a5
--- /dev/null
+++ b/dts/Bindings/serial/uniphier-uart.txt
@@ -0,0 +1,23 @@
+UniPhier UART controller
+
+Required properties:
+- compatible: should be "socionext,uniphier-uart".
+- reg: offset and length of the register set for the device.
+- interrupts: a single interrupt specifier.
+- clocks: phandle to the input clock.
+
+Optional properties:
+- fifo-size: the RX/TX FIFO size. Defaults to 64 if not specified.
+
+Example:
+ aliases {
+ serial0 = &serial0;
+ };
+
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ clocks = <&uart_clk>;
+ fifo-size = <64>;
+ };