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Diffstat (limited to 'dts/Bindings/soc/xilinx/xlnx,vcu.txt')
| -rw-r--r-- | dts/Bindings/soc/xilinx/xlnx,vcu.txt | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/dts/Bindings/soc/xilinx/xlnx,vcu.txt b/dts/Bindings/soc/xilinx/xlnx,vcu.txt new file mode 100644 index 0000000000..6786d6715d --- /dev/null +++ b/dts/Bindings/soc/xilinx/xlnx,vcu.txt @@ -0,0 +1,31 @@ +LogicoreIP designed compatible with Xilinx ZYNQ family. +------------------------------------------------------- + +General concept +--------------- + +LogicoreIP design to provide the isolation between processing system +and programmable logic. Also provides the list of register set to configure +the frequency. + +Required properties: +- compatible: shall be one of: + "xlnx,vcu" + "xlnx,vcu-logicoreip-1.0" +- reg, reg-names: There are two sets of registers need to provide. + 1. vcu slcr + 2. Logicore + reg-names should contain name for the each register sequence. +- clocks: phandle for aclk and pll_ref clocksource +- clock-names: The identification string, "aclk", is always required for + the axi clock. "pll_ref" is required for pll. +Example: + + xlnx_vcu: vcu@a0040000 { + compatible = "xlnx,vcu-logicoreip-1.0"; + reg = <0x0 0xa0040000 0x0 0x1000>, + <0x0 0xa0041000 0x0 0x1000>; + reg-names = "vcu_slcr", "logicore"; + clocks = <&si570_1>, <&clkc 71>; + clock-names = "pll_ref", "aclk"; + }; |