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-rw-r--r--dts/Bindings/spi/nvidia,tegra210-quad.yaml69
1 files changed, 25 insertions, 44 deletions
diff --git a/dts/Bindings/spi/nvidia,tegra210-quad.yaml b/dts/Bindings/spi/nvidia,tegra210-quad.yaml
index 0296edd1de..48e97e2402 100644
--- a/dts/Bindings/spi/nvidia,tegra210-quad.yaml
+++ b/dts/Bindings/spi/nvidia,tegra210-quad.yaml
@@ -11,7 +11,7 @@ maintainers:
- Jonathan Hunter <jonathanh@nvidia.com>
allOf:
- - $ref: "spi-controller.yaml#"
+ - $ref: spi-controller.yaml#
properties:
compatible:
@@ -20,6 +20,7 @@ properties:
- nvidia,tegra186-qspi
- nvidia,tegra194-qspi
- nvidia,tegra234-qspi
+ - nvidia,tegra241-qspi
reg:
maxItems: 1
@@ -47,8 +48,9 @@ properties:
- const: tx
patternProperties:
- "@[0-9a-f]+":
+ "@[0-9a-f]+$":
type: object
+ additionalProperties: true
properties:
spi-rx-bus-width:
@@ -57,27 +59,6 @@ patternProperties:
spi-tx-bus-width:
enum: [1, 2, 4]
- nvidia,tx-clk-tap-delay:
- description:
- Delays the clock going out to device with this tap value.
- Tap value varies based on platform design trace lengths from Tegra
- QSPI to corresponding slave device.
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 0
- maximum: 31
-
- nvidia,rx-clk-tap-delay:
- description:
- Delays the clock coming in from the device with this tap value.
- Tap value varies based on platform design trace lengths from Tegra
- QSPI to corresponding slave device.
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 0
- maximum: 255
-
- required:
- - reg
-
required:
- compatible
- reg
@@ -94,25 +75,25 @@ examples:
#include <dt-bindings/reset/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
spi@70410000 {
- compatible = "nvidia,tegra210-qspi";
- reg = <0x70410000 0x1000>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car TEGRA210_CLK_QSPI>,
- <&tegra_car TEGRA210_CLK_QSPI_PM>;
- clock-names = "qspi", "qspi_out";
- resets = <&tegra_car 211>;
- dmas = <&apbdma 5>, <&apbdma 5>;
- dma-names = "rx", "tx";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <104000000>;
- spi-tx-bus-width = <2>;
- spi-rx-bus-width = <2>;
- nvidia,tx-clk-tap-delay = <0>;
- nvidia,rx-clk-tap-delay = <0>;
- };
+ compatible = "nvidia,tegra210-qspi";
+ reg = <0x70410000 0x1000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA210_CLK_QSPI>,
+ <&tegra_car TEGRA210_CLK_QSPI_PM>;
+ clock-names = "qspi", "qspi_out";
+ resets = <&tegra_car 211>;
+ dmas = <&apbdma 5>, <&apbdma 5>;
+ dma-names = "rx", "tx";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <104000000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ nvidia,tx-clk-tap-delay = <0>;
+ nvidia,rx-clk-tap-delay = <0>;
+ };
};