diff options
Diffstat (limited to 'dts/Bindings/spi')
| -rw-r--r-- | dts/Bindings/spi/fsl-spi.txt | 2 | ||||
| -rw-r--r-- | dts/Bindings/spi/sh-hspi.txt | 2 | ||||
| -rw-r--r-- | dts/Bindings/spi/sh-msiof.txt | 2 | ||||
| -rw-r--r-- | dts/Bindings/spi/snps,dw-apb-ssi.txt | 6 | ||||
| -rw-r--r-- | dts/Bindings/spi/spi-cadence.txt | 1 | ||||
| -rw-r--r-- | dts/Bindings/spi/spi-fsl-lpspi.txt | 1 | ||||
| -rw-r--r-- | dts/Bindings/spi/spi-rockchip.txt | 1 | ||||
| -rw-r--r-- | dts/Bindings/spi/spi-rspi.txt | 2 | ||||
| -rw-r--r-- | dts/Bindings/spi/spi-uniphier.txt | 22 | ||||
| -rw-r--r-- | dts/Bindings/spi/spi-xilinx.txt | 1 | ||||
| -rw-r--r-- | dts/Bindings/spi/spi-xlp.txt | 1 | ||||
| -rw-r--r-- | dts/Bindings/spi/spi-zynqmp-qspi.txt | 1 |
12 files changed, 27 insertions, 15 deletions
diff --git a/dts/Bindings/spi/fsl-spi.txt b/dts/Bindings/spi/fsl-spi.txt index a233137206..8854004a1d 100644 --- a/dts/Bindings/spi/fsl-spi.txt +++ b/dts/Bindings/spi/fsl-spi.txt @@ -12,8 +12,6 @@ Required properties: information for the interrupt. This should be encoded based on the information in section 2) depending on the type of interrupt controller you have. -- interrupt-parent : the phandle for the interrupt controller that - services interrupts for this device. - clock-frequency : input clock frequency to non FSL_SOC cores Optional properties: diff --git a/dts/Bindings/spi/sh-hspi.txt b/dts/Bindings/spi/sh-hspi.txt index 585fed9037..b9d1e4d11a 100644 --- a/dts/Bindings/spi/sh-hspi.txt +++ b/dts/Bindings/spi/sh-hspi.txt @@ -6,8 +6,6 @@ Required properties: - "renesas,hspi-r8a7778" (R-Car M1) - "renesas,hspi-r8a7779" (R-Car H1) - reg : Offset and length of the register set for the device -- interrupt-parent : The phandle for the interrupt controller that - services interrupts for this device - interrupts : Interrupt specifier - #address-cells : Must be <1> - #size-cells : Must be <0> diff --git a/dts/Bindings/spi/sh-msiof.txt b/dts/Bindings/spi/sh-msiof.txt index 39806329c1..bfbc2035fb 100644 --- a/dts/Bindings/spi/sh-msiof.txt +++ b/dts/Bindings/spi/sh-msiof.txt @@ -29,8 +29,6 @@ Required properties: If two register sets are present, the first is to be used by the CPU, and the second is to be used by the DMA engine. -- interrupt-parent : The phandle for the interrupt controller that - services interrupts for this device - interrupts : Interrupt specifier - #address-cells : Must be <1> - #size-cells : Must be <0> diff --git a/dts/Bindings/spi/snps,dw-apb-ssi.txt b/dts/Bindings/spi/snps,dw-apb-ssi.txt index 204b311e04..642d3fb1ef 100644 --- a/dts/Bindings/spi/snps,dw-apb-ssi.txt +++ b/dts/Bindings/spi/snps,dw-apb-ssi.txt @@ -1,8 +1,10 @@ Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface. Required properties: -- compatible : "snps,dw-apb-ssi" -- reg : The register base for the controller. +- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or + "jaguar2" +- reg : The register base for the controller. For "mscc,<soc>-spi", a second + register set is required (named ICPU_CFG:SPI_MST) - interrupts : One interrupt, used by the controller. - #address-cells : <1>, as required by generic SPI binding. - #size-cells : <0>, also as required by generic SPI binding. diff --git a/dts/Bindings/spi/spi-cadence.txt b/dts/Bindings/spi/spi-cadence.txt index 94f09141a4..05a2ef9456 100644 --- a/dts/Bindings/spi/spi-cadence.txt +++ b/dts/Bindings/spi/spi-cadence.txt @@ -6,7 +6,6 @@ Required properties: - reg : Physical base address and size of SPI registers map. - interrupts : Property with a value describing the interrupt number. -- interrupt-parent : Must be core interrupt controller - clock-names : List of input clock names - "ref_clk", "pclk" (See clock bindings for details). - clocks : Clock phandles (see clock bindings for details). diff --git a/dts/Bindings/spi/spi-fsl-lpspi.txt b/dts/Bindings/spi/spi-fsl-lpspi.txt index 225ace1d0c..4af132606b 100644 --- a/dts/Bindings/spi/spi-fsl-lpspi.txt +++ b/dts/Bindings/spi/spi-fsl-lpspi.txt @@ -4,7 +4,6 @@ Required properties: - compatible : - "fsl,imx7ulp-spi" for LPSPI compatible with the one integrated on i.MX7ULP soc - reg : address and length of the lpspi master registers -- interrupt-parent : core interrupt controller - interrupts : lpspi interrupt - clocks : lpspi clock specifier diff --git a/dts/Bindings/spi/spi-rockchip.txt b/dts/Bindings/spi/spi-rockchip.txt index 6e3ffacbba..a0edac12d8 100644 --- a/dts/Bindings/spi/spi-rockchip.txt +++ b/dts/Bindings/spi/spi-rockchip.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: should be one of the following. "rockchip,rv1108-spi" for rv1108 SoCs. + "rockchip,px30-spi", "rockchip,rk3066-spi" for px30 SoCs. "rockchip,rk3036-spi" for rk3036 SoCS. "rockchip,rk3066-spi" for rk3066 SoCs. "rockchip,rk3188-spi" for rk3188 SoCs. diff --git a/dts/Bindings/spi/spi-rspi.txt b/dts/Bindings/spi/spi-rspi.txt index 3b02b3a7cf..96fd58548f 100644 --- a/dts/Bindings/spi/spi-rspi.txt +++ b/dts/Bindings/spi/spi-rspi.txt @@ -28,8 +28,6 @@ Required properties: - "rx" for SPRI, - "tx" to SPTI, - "mux" for a single muxed interrupt. -- interrupt-parent : The phandle for the interrupt controller that - services interrupts for this device. - num-cs : Number of chip selects. Some RSPI cores have more than 1. - #address-cells : Must be <1> - #size-cells : Must be <0> diff --git a/dts/Bindings/spi/spi-uniphier.txt b/dts/Bindings/spi/spi-uniphier.txt new file mode 100644 index 0000000000..504a4ecfc7 --- /dev/null +++ b/dts/Bindings/spi/spi-uniphier.txt @@ -0,0 +1,22 @@ +Socionext UniPhier SPI controller driver + +UniPhier SoCs have SCSSI which supports SPI single channel. + +Required properties: + - compatible: should be "socionext,uniphier-scssi" + - reg: address and length of the spi master registers + - #address-cells: must be <1>, see spi-bus.txt + - #size-cells: must be <0>, see spi-bus.txt + - clocks: A phandle to the clock for the device. + - resets: A phandle to the reset control for the device. + +Example: + +spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; +}; diff --git a/dts/Bindings/spi/spi-xilinx.txt b/dts/Bindings/spi/spi-xilinx.txt index 7bf61efc66..dc924a5f71 100644 --- a/dts/Bindings/spi/spi-xilinx.txt +++ b/dts/Bindings/spi/spi-xilinx.txt @@ -6,7 +6,6 @@ Required properties: - reg : Physical base address and size of SPI registers map. - interrupts : Property with a value describing the interrupt number. -- interrupt-parent : Must be core interrupt controller Optional properties: - xlnx,num-ss-bits : Number of chip selects used. diff --git a/dts/Bindings/spi/spi-xlp.txt b/dts/Bindings/spi/spi-xlp.txt index 40e82d51ef..f4925ec0ed 100644 --- a/dts/Bindings/spi/spi-xlp.txt +++ b/dts/Bindings/spi/spi-xlp.txt @@ -13,7 +13,6 @@ Required properties: - reg : Should contain register location and length. - clocks : Phandle of the spi clock - interrupts : Interrupt number used by this controller. -- interrupt-parent : Phandle of the parent interrupt controller. SPI slave nodes must be children of the SPI master node and can contain properties described in Documentation/devicetree/bindings/spi/spi-bus.txt. diff --git a/dts/Bindings/spi/spi-zynqmp-qspi.txt b/dts/Bindings/spi/spi-zynqmp-qspi.txt index c8f50e5cf7..0f6d37ff54 100644 --- a/dts/Bindings/spi/spi-zynqmp-qspi.txt +++ b/dts/Bindings/spi/spi-zynqmp-qspi.txt @@ -6,7 +6,6 @@ Required properties: - reg : Physical base address and size of GQSPI registers map. - interrupts : Property with a value describing the interrupt number. -- interrupt-parent : Must be core interrupt controller. - clock-names : List of input clock names - "ref_clk", "pclk" (See clock bindings for details). - clocks : Clock phandles (see clock bindings for details). |