diff options
Diffstat (limited to 'dts/Bindings/watchdog/ti,rti-wdt.yaml')
| -rw-r--r-- | dts/Bindings/watchdog/ti,rti-wdt.yaml | 32 |
1 files changed, 26 insertions, 6 deletions
diff --git a/dts/Bindings/watchdog/ti,rti-wdt.yaml b/dts/Bindings/watchdog/ti,rti-wdt.yaml index 054584d754..62ddc284a5 100644 --- a/dts/Bindings/watchdog/ti,rti-wdt.yaml +++ b/dts/Bindings/watchdog/ti,rti-wdt.yaml @@ -18,7 +18,7 @@ description: to directly reset the SoC. allOf: - - $ref: "watchdog.yaml#" + - $ref: watchdog.yaml# properties: compatible: @@ -34,11 +34,19 @@ properties: power-domains: maxItems: 1 - assigned-clocks: - maxItems: 1 - - assigned-clocks-parents: + memory-region: maxItems: 1 + description: + Contains the watchdog reserved memory. It is optional. + In the reserved memory, the specified values, which are + PON_REASON_SOF_NUM(0xBBBBCCCC), PON_REASON_MAGIC_NUM(0xDDDDDDDD), + and PON_REASON_EOF_NUM(0xCCCCBBBB), are pre-stored at the first + 3 * 4 bytes to tell that last boot was caused by watchdog reset. + Once the PON reason is captured by driver(rti_wdt.c), the driver + is supposed to wipe the whole memory region. Surely, if this + property is set, at least 12 bytes reserved memory starting from + specific memory address(0xa220000) should be set. More please + refer to example. required: - compatible @@ -53,7 +61,18 @@ examples: /* * RTI WDT in main domain on J721e SoC. Assigned clocks are used to * select the source clock for the watchdog, forcing it to tick with - * a 32kHz clock in this case. + * a 32kHz clock in this case. Add a reserved memory(optional) to keep + * the watchdog reset cause persistent, which was be written in 12 bytes + * starting from 0xa2200000 by RTI Watchdog Firmware, then make it + * possible to get watchdog reset cause in driver. + * + * Reserved memory should be defined as follows: + * reserved-memory { + * wdt_reset_memory_region: wdt-memory@a2200000 { + * reg = <0x00 0xa2200000 0x00 0x1000>; + * no-map; + * }; + * } */ #include <dt-bindings/soc/ti,sci_pm_domain.h> @@ -64,4 +83,5 @@ examples: power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; assigned-clocks = <&k3_clks 252 1>; assigned-clock-parents = <&k3_clks 252 5>; + memory-region = <&wdt_reset_memory_region>; }; |