diff options
Diffstat (limited to 'dts/Bindings')
982 files changed, 16937 insertions, 5559 deletions
diff --git a/dts/Bindings/Makefile b/dts/Bindings/Makefile index 1eaccf135b..bf2d8a8ced 100644 --- a/dts/Bindings/Makefile +++ b/dts/Bindings/Makefile @@ -75,3 +75,6 @@ always-$(CHECK_DT_BINDING) += $(patsubst $(srctree)/$(src)/%.yaml,%.example.dtb, # build artifacts here before they are processed by scripts/Makefile.clean clean-files = $(shell find $(obj) \( -name '*.example.dts' -o \ -name '*.example.dtb' \) -delete 2>/dev/null) + +dt_compatible_check: $(obj)/processed-schema.json + $(Q)$(srctree)/scripts/dtc/dt-extract-compatibles $(srctree) | xargs dt-check-compatible -v -s $< diff --git a/dts/Bindings/arm/actions.yaml b/dts/Bindings/arm/actions.yaml index 02dc72c976..e012f612f0 100644 --- a/dts/Bindings/arm/actions.yaml +++ b/dts/Bindings/arm/actions.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/actions.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Actions Semi platforms device tree bindings +title: Actions Semi platforms maintainers: - Andreas Färber <afaerber@suse.de> diff --git a/dts/Bindings/arm/airoha.yaml b/dts/Bindings/arm/airoha.yaml index fc19b1a6f3..3292c669ee 100644 --- a/dts/Bindings/arm/airoha.yaml +++ b/dts/Bindings/arm/airoha.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/airoha.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Airoha SoC based Platforms Device Tree Bindings +title: Airoha SoC based Platforms maintainers: - Felix Fietkau <nbd@nbd.name> diff --git a/dts/Bindings/arm/altera.yaml b/dts/Bindings/arm/altera.yaml index e6de1d7f51..3eee03aa93 100644 --- a/dts/Bindings/arm/altera.yaml +++ b/dts/Bindings/arm/altera.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/altera.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Altera's SoCFPGA platform device tree bindings +title: Altera's SoCFPGA platform maintainers: - Dinh Nguyen <dinguyen@kernel.org> diff --git a/dts/Bindings/arm/amazon,al.yaml b/dts/Bindings/arm/amazon,al.yaml index 0f03135d91..37dbb4768e 100644 --- a/dts/Bindings/arm/amazon,al.yaml +++ b/dts/Bindings/arm/amazon,al.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/amazon,al.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Amazon's Annapurna Labs Alpine Platform Device Tree Bindings +title: Amazon's Annapurna Labs Alpine Platform maintainers: - Hanna Hawa <hhhawa@amazon.com> diff --git a/dts/Bindings/arm/amlogic.yaml b/dts/Bindings/arm/amlogic.yaml index 61a6cabb37..9fda2436c6 100644 --- a/dts/Bindings/arm/amlogic.yaml +++ b/dts/Bindings/arm/amlogic.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/amlogic.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Amlogic MesonX device tree bindings +title: Amlogic MesonX maintainers: - Kevin Hilman <khilman@baylibre.com> @@ -120,6 +120,7 @@ properties: - enum: - amlogic,q200 - amlogic,q201 + - azw,gt1-ultimate - khadas,vim2 - kingnovel,r-box-pro - libretech,aml-s912-pc @@ -136,6 +137,7 @@ properties: - enum: - amlogic,s400 - jethome,jethub-j100 + - jethome,jethub-j110 - const: amlogic,a113d - const: amlogic,meson-axg diff --git a/dts/Bindings/arm/apple.yaml b/dts/Bindings/arm/apple.yaml index 8d93e8a6cc..7262f3c098 100644 --- a/dts/Bindings/arm/apple.yaml +++ b/dts/Bindings/arm/apple.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/apple.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Apple ARM Machine Device Tree Bindings +title: Apple ARM Machine maintainers: - Hector Martin <marcan@marcan.st> diff --git a/dts/Bindings/arm/arm,cci-400.yaml b/dts/Bindings/arm/arm,cci-400.yaml index 1706134b75..d28303d909 100644 --- a/dts/Bindings/arm/arm,cci-400.yaml +++ b/dts/Bindings/arm/arm,cci-400.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ARM CCI Cache Coherent Interconnect Device Tree Binding +title: ARM CCI Cache Coherent Interconnect maintainers: - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> diff --git a/dts/Bindings/arm/arm,coresight-catu.yaml b/dts/Bindings/arm/arm,coresight-catu.yaml index d783d92761..2bae06eed6 100644 --- a/dts/Bindings/arm/arm,coresight-catu.yaml +++ b/dts/Bindings/arm/arm,coresight-catu.yaml @@ -61,6 +61,9 @@ properties: maxItems: 1 description: Address translation error interrupt + power-domains: + maxItems: 1 + in-ports: $ref: /schemas/graph.yaml#/properties/ports additionalProperties: false diff --git a/dts/Bindings/arm/arm,coresight-cti.yaml b/dts/Bindings/arm/arm,coresight-cti.yaml index 72ffe4d1e9..0c5b875cb6 100644 --- a/dts/Bindings/arm/arm,coresight-cti.yaml +++ b/dts/Bindings/arm/arm,coresight-cti.yaml @@ -98,6 +98,9 @@ properties: base cti node if compatible string arm,coresight-cti-v8-arch is used, or may appear in a trig-conns child node when appropriate. + power-domains: + maxItems: 1 + arm,cti-ctm-id: $ref: /schemas/types.yaml#/definitions/uint32 description: diff --git a/dts/Bindings/arm/arm,coresight-dynamic-funnel.yaml b/dts/Bindings/arm/arm,coresight-dynamic-funnel.yaml index 1eeedc2285..44a1041cb0 100644 --- a/dts/Bindings/arm/arm,coresight-dynamic-funnel.yaml +++ b/dts/Bindings/arm/arm,coresight-dynamic-funnel.yaml @@ -54,6 +54,9 @@ properties: - const: apb_pclk - const: atclk + power-domains: + maxItems: 1 + in-ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/dts/Bindings/arm/arm,coresight-dynamic-replicator.yaml b/dts/Bindings/arm/arm,coresight-dynamic-replicator.yaml index a26ed9214e..03792e9bd9 100644 --- a/dts/Bindings/arm/arm,coresight-dynamic-replicator.yaml +++ b/dts/Bindings/arm/arm,coresight-dynamic-replicator.yaml @@ -54,6 +54,9 @@ properties: - const: apb_pclk - const: atclk + power-domains: + maxItems: 1 + qcom,replicator-loses-context: type: boolean description: diff --git a/dts/Bindings/arm/arm,coresight-etb10.yaml b/dts/Bindings/arm/arm,coresight-etb10.yaml index fd06ede26c..90679788e0 100644 --- a/dts/Bindings/arm/arm,coresight-etb10.yaml +++ b/dts/Bindings/arm/arm,coresight-etb10.yaml @@ -54,6 +54,9 @@ properties: - const: apb_pclk - const: atclk + power-domains: + maxItems: 1 + in-ports: $ref: /schemas/graph.yaml#/properties/ports additionalProperties: false diff --git a/dts/Bindings/arm/arm,coresight-etm.yaml b/dts/Bindings/arm/arm,coresight-etm.yaml index e0377ce485..01200f6750 100644 --- a/dts/Bindings/arm/arm,coresight-etm.yaml +++ b/dts/Bindings/arm/arm,coresight-etm.yaml @@ -73,6 +73,9 @@ properties: - const: apb_pclk - const: atclk + power-domains: + maxItems: 1 + arm,coresight-loses-context-with-cpu: type: boolean description: diff --git a/dts/Bindings/arm/arm,coresight-static-funnel.yaml b/dts/Bindings/arm/arm,coresight-static-funnel.yaml index 374083956b..cc8c3baa79 100644 --- a/dts/Bindings/arm/arm,coresight-static-funnel.yaml +++ b/dts/Bindings/arm/arm,coresight-static-funnel.yaml @@ -27,6 +27,9 @@ properties: compatible: const: arm,coresight-static-funnel + power-domains: + maxItems: 1 + in-ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/dts/Bindings/arm/arm,coresight-static-replicator.yaml b/dts/Bindings/arm/arm,coresight-static-replicator.yaml index a34d858383..1892a091ac 100644 --- a/dts/Bindings/arm/arm,coresight-static-replicator.yaml +++ b/dts/Bindings/arm/arm,coresight-static-replicator.yaml @@ -27,6 +27,9 @@ properties: compatible: const: arm,coresight-static-replicator + power-domains: + maxItems: 1 + in-ports: $ref: /schemas/graph.yaml#/properties/ports additionalProperties: false diff --git a/dts/Bindings/arm/arm,coresight-stm.yaml b/dts/Bindings/arm/arm,coresight-stm.yaml index 905008faa0..378380c3f5 100644 --- a/dts/Bindings/arm/arm,coresight-stm.yaml +++ b/dts/Bindings/arm/arm,coresight-stm.yaml @@ -61,6 +61,9 @@ properties: - const: apb_pclk - const: atclk + power-domains: + maxItems: 1 + out-ports: $ref: /schemas/graph.yaml#/properties/ports additionalProperties: false diff --git a/dts/Bindings/arm/arm,coresight-tmc.yaml b/dts/Bindings/arm/arm,coresight-tmc.yaml index 3463b6e53a..cb8dceaca7 100644 --- a/dts/Bindings/arm/arm,coresight-tmc.yaml +++ b/dts/Bindings/arm/arm,coresight-tmc.yaml @@ -55,6 +55,12 @@ properties: - const: apb_pclk - const: atclk + iommus: + maxItems: 1 + + power-domains: + maxItems: 1 + arm,buffer-size: $ref: /schemas/types.yaml#/definitions/uint32 deprecated: true diff --git a/dts/Bindings/arm/arm,coresight-tpiu.yaml b/dts/Bindings/arm/arm,coresight-tpiu.yaml index e80d48200c..61a0cdc277 100644 --- a/dts/Bindings/arm/arm,coresight-tpiu.yaml +++ b/dts/Bindings/arm/arm,coresight-tpiu.yaml @@ -54,6 +54,9 @@ properties: - const: apb_pclk - const: atclk + power-domains: + maxItems: 1 + in-ports: $ref: /schemas/graph.yaml#/properties/ports additionalProperties: false diff --git a/dts/Bindings/arm/arm,corstone1000.yaml b/dts/Bindings/arm/arm,corstone1000.yaml index a77f882238..693f3fe7be 100644 --- a/dts/Bindings/arm/arm,corstone1000.yaml +++ b/dts/Bindings/arm/arm,corstone1000.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ARM Corstone1000 Device Tree Bindings +title: ARM Corstone1000 maintainers: - Vishnu Banavath <vishnu.banavath@arm.com> diff --git a/dts/Bindings/arm/arm,embedded-trace-extension.yaml b/dts/Bindings/arm/arm,embedded-trace-extension.yaml index 5f07fb166c..108460627d 100644 --- a/dts/Bindings/arm/arm,embedded-trace-extension.yaml +++ b/dts/Bindings/arm/arm,embedded-trace-extension.yaml @@ -33,6 +33,9 @@ properties: Handle to the cpu this ETE is bound to. $ref: /schemas/types.yaml#/definitions/phandle + power-domains: + maxItems: 1 + out-ports: description: | Output connections from the ETE to legacy CoreSight trace bus. diff --git a/dts/Bindings/arm/arm,integrator.yaml b/dts/Bindings/arm/arm,integrator.yaml index 528eee6429..98ff5698ae 100644 --- a/dts/Bindings/arm/arm,integrator.yaml +++ b/dts/Bindings/arm/arm,integrator.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/arm,integrator.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ARM Integrator Boards Device Tree Bindings +title: ARM Integrator Boards maintainers: - Linus Walleij <linus.walleij@linaro.org> diff --git a/dts/Bindings/arm/arm,realview.yaml b/dts/Bindings/arm/arm,realview.yaml index 4f9b21f49e..8d3ed2e4ed 100644 --- a/dts/Bindings/arm/arm,realview.yaml +++ b/dts/Bindings/arm/arm,realview.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/arm,realview.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ARM RealView Boards Device Tree Bindings +title: ARM RealView Boards maintainers: - Linus Walleij <linus.walleij@linaro.org> diff --git a/dts/Bindings/arm/arm,versatile-sysreg.yaml b/dts/Bindings/arm/arm,versatile-sysreg.yaml new file mode 100644 index 0000000000..491eef1e1b --- /dev/null +++ b/dts/Bindings/arm/arm,versatile-sysreg.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,versatile-sysreg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm Versatile system registers + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +description: + This is a system control registers block, providing multiple low level + platform functions like board detection and identification, software + interrupt generation, MMC and NOR Flash control, etc. + +properties: + compatible: + items: + - const: arm,versatile-sysreg + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + panel: + type: object + +required: + - compatible + - reg + +additionalProperties: false +... diff --git a/dts/Bindings/arm/arm,versatile.yaml b/dts/Bindings/arm/arm,versatile.yaml index 34b437c727..13e52ba920 100644 --- a/dts/Bindings/arm/arm,versatile.yaml +++ b/dts/Bindings/arm/arm,versatile.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/arm,versatile.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ARM Versatile Boards Device Tree Bindings +title: ARM Versatile Boards maintainers: - Linus Walleij <linus.walleij@linaro.org> diff --git a/dts/Bindings/arm/arm,vexpress-juno.yaml b/dts/Bindings/arm/arm,vexpress-juno.yaml index a4b4452afc..eec190a962 100644 --- a/dts/Bindings/arm/arm,vexpress-juno.yaml +++ b/dts/Bindings/arm/arm,vexpress-juno.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ARM Versatile Express and Juno Boards Device Tree Bindings +title: ARM Versatile Express and Juno Boards maintainers: - Sudeep Holla <sudeep.holla@arm.com> diff --git a/dts/Bindings/arm/aspeed/aspeed.yaml b/dts/Bindings/arm/aspeed/aspeed.yaml index 1895ce9de4..217a1d6748 100644 --- a/dts/Bindings/arm/aspeed/aspeed.yaml +++ b/dts/Bindings/arm/aspeed/aspeed.yaml @@ -29,6 +29,7 @@ properties: - description: AST2500 based boards items: - enum: + - amd,daytonax-bmc - amd,ethanolx-bmc - ampere,mtjade-bmc - aspeed,ast2500-evb @@ -69,6 +70,7 @@ properties: - description: AST2600 based boards items: - enum: + - ampere,mtmitchell-bmc - aspeed,ast2600-evb - aspeed,ast2600-evb-a1 - facebook,bletchley-bmc diff --git a/dts/Bindings/arm/atmel-at91.yaml b/dts/Bindings/arm/atmel-at91.yaml index 2b7848bb77..2224b18801 100644 --- a/dts/Bindings/arm/atmel-at91.yaml +++ b/dts/Bindings/arm/atmel-at91.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/atmel-at91.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Atmel AT91 device tree bindings. +title: Atmel AT91. maintainers: - Alexandre Belloni <alexandre.belloni@bootlin.com> @@ -127,6 +127,13 @@ properties: - const: atmel,sama5d3 - const: atmel,sama5 + - description: Microchip SAMA5D3 Ethernet Development System Board + items: + - const: microchip,sama5d3-eds + - const: atmel,sama5d36 + - const: atmel,sama5d3 + - const: atmel,sama5 + - description: CalAmp LMU5000 board items: - const: calamp,lmu5000 diff --git a/dts/Bindings/arm/axxia.yaml b/dts/Bindings/arm/axxia.yaml index e0d2bb71cf..d60907e43e 100644 --- a/dts/Bindings/arm/axxia.yaml +++ b/dts/Bindings/arm/axxia.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/axxia.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Axxia AXM55xx device tree bindings +title: Axxia AXM55xx maintainers: - Anders Berg <anders.berg@lsi.com> diff --git a/dts/Bindings/arm/bcm/brcm,bcm4908.yaml b/dts/Bindings/arm/bcm/brcm,bcm4908.yaml deleted file mode 100644 index 9b745531ff..0000000000 --- a/dts/Bindings/arm/bcm/brcm,bcm4908.yaml +++ /dev/null @@ -1,42 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm4908.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Broadcom BCM4908 device tree bindings - -description: - Broadcom BCM4906 / BCM4908 / BCM49408 Wi-Fi/network SoCs with Brahma CPUs. - -maintainers: - - Rafał Miłecki <rafal@milecki.pl> - -properties: - $nodename: - const: '/' - compatible: - oneOf: - - description: BCM4906 based boards - items: - - enum: - - netgear,r8000p - - tplink,archer-c2300-v1 - - const: brcm,bcm4906 - - const: brcm,bcm4908 - - - description: BCM4908 based boards - items: - - enum: - - asus,gt-ac5300 - - netgear,raxe500 - - const: brcm,bcm4908 - - - description: BCM49408 based boards - items: - - const: brcm,bcm49408 - - const: brcm,bcm4908 - -additionalProperties: true - -... diff --git a/dts/Bindings/arm/bcm/brcm,bcmbca.yaml b/dts/Bindings/arm/bcm/brcm,bcmbca.yaml index 324e591043..84866e29ca 100644 --- a/dts/Bindings/arm/bcm/brcm,bcmbca.yaml +++ b/dts/Bindings/arm/bcm/brcm,bcmbca.yaml @@ -15,6 +15,7 @@ maintainers: - William Zhang <william.zhang@broadcom.com> - Anand Gore <anand.gore@broadcom.com> - Kursad Oney <kursad.oney@broadcom.com> + - Rafał Miłecki <rafal@milecki.pl> properties: $nodename: @@ -28,6 +29,30 @@ properties: - const: brcm,bcm47622 - const: brcm,bcmbca + - description: BCM4906 based boards + items: + - enum: + - netgear,r8000p + - tplink,archer-c2300-v1 + - const: brcm,bcm4906 + - const: brcm,bcm4908 + - const: brcm,bcmbca + + - description: BCM4908 based boards + items: + - enum: + - asus,gt-ac5300 + - brcm,bcm94908 + - netgear,raxe500 + - const: brcm,bcm4908 + - const: brcm,bcmbca + + - description: BCM49408 based boards + items: + - const: brcm,bcm49408 + - const: brcm,bcm4908 + - const: brcm,bcmbca + - description: BCM4912 based boards items: - enum: diff --git a/dts/Bindings/arm/bcm/brcm,brcmstb.txt b/dts/Bindings/arm/bcm/brcm,brcmstb.txt index 104cc9b41d..071421dbc4 100644 --- a/dts/Bindings/arm/bcm/brcm,brcmstb.txt +++ b/dts/Bindings/arm/bcm/brcm,brcmstb.txt @@ -187,15 +187,8 @@ Required properties: Sequencer DRAM parameters and control registers. Used for Self-Refresh Power-Down (SRPD), among other things. -Required properties: -- compatible : should contain one of these - "brcm,brcmstb-memc-ddr-rev-b.2.1" - "brcm,brcmstb-memc-ddr-rev-b.2.2" - "brcm,brcmstb-memc-ddr-rev-b.2.3" - "brcm,brcmstb-memc-ddr-rev-b.3.0" - "brcm,brcmstb-memc-ddr-rev-b.3.1" - "brcm,brcmstb-memc-ddr" -- reg : the MEMC DDR register range +See Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml for a +full list of supported compatible strings and properties. Example: diff --git a/dts/Bindings/arm/bitmain.yaml b/dts/Bindings/arm/bitmain.yaml index 90ba02be48..55a5a570b5 100644 --- a/dts/Bindings/arm/bitmain.yaml +++ b/dts/Bindings/arm/bitmain.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/bitmain.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Bitmain platform device tree bindings +title: Bitmain platform maintainers: - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> diff --git a/dts/Bindings/arm/calxeda.yaml b/dts/Bindings/arm/calxeda.yaml index 46f78addeb..3e9f5e1d86 100644 --- a/dts/Bindings/arm/calxeda.yaml +++ b/dts/Bindings/arm/calxeda.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/calxeda.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Calxeda Platforms Device Tree Bindings +title: Calxeda Platforms maintainers: - Rob Herring <robh@kernel.org> diff --git a/dts/Bindings/arm/cpus.yaml b/dts/Bindings/arm/cpus.yaml index a07c5bac7c..5c13b73e4d 100644 --- a/dts/Bindings/arm/cpus.yaml +++ b/dts/Bindings/arm/cpus.yaml @@ -174,6 +174,7 @@ properties: - nvidia,tegra194-carmel - qcom,krait - qcom,kryo + - qcom,kryo240 - qcom,kryo250 - qcom,kryo260 - qcom,kryo280 diff --git a/dts/Bindings/arm/digicolor.yaml b/dts/Bindings/arm/digicolor.yaml index a35de3c9e2..0cf9ddaa52 100644 --- a/dts/Bindings/arm/digicolor.yaml +++ b/dts/Bindings/arm/digicolor.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/digicolor.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Conexant Digicolor Platforms Device Tree Bindings +title: Conexant Digicolor Platforms maintainers: - Baruch Siach <baruch@tkos.co.il> diff --git a/dts/Bindings/arm/fsl.yaml b/dts/Bindings/arm/fsl.yaml index 7431579ab0..fbfc4f99c0 100644 --- a/dts/Bindings/arm/fsl.yaml +++ b/dts/Bindings/arm/fsl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/fsl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Freescale i.MX Platforms Device Tree Bindings +title: Freescale i.MX Platforms maintainers: - Shawn Guo <shawnguo@kernel.org> @@ -554,8 +554,7 @@ properties: - engicam,imx6ul-isiot # Engicam Is.IoT MX6UL eMMC/NAND Starter kit - fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board - karo,imx6ul-tx6ul # Ka-Ro electronics TXUL-0010 Module - - kontron,imx6ul-n6310-som # Kontron N6310 SOM - - kontron,imx6ul-n6311-som # Kontron N6311 SOM + - kontron,sl-imx6ul # Kontron SL i.MX6UL SoM - prt,prti6g # Protonic PRTI6G Board - technexion,imx6ul-pico-dwarf # TechNexion i.MX6UL Pico-Dwarf - technexion,imx6ul-pico-hobbit # TechNexion i.MX6UL Pico-Hobbit @@ -591,23 +590,17 @@ properties: - const: phytec,imx6ul-pcl063 # PHYTEC phyCORE-i.MX 6UL - const: fsl,imx6ul - - description: Kontron N6310 S Board + - description: Kontron BL i.MX6UL (N631X S) Board items: - - const: kontron,imx6ul-n6310-s - - const: kontron,imx6ul-n6310-som + - const: kontron,bl-imx6ul # Kontron BL i.MX6UL Carrier Board + - const: kontron,sl-imx6ul # Kontron SL i.MX6UL SoM - const: fsl,imx6ul - - description: Kontron N6311 S Board + - description: Kontron BL i.MX6UL 43 (N631X S 43) Board items: - - const: kontron,imx6ul-n6311-s - - const: kontron,imx6ul-n6311-som - - const: fsl,imx6ul - - - description: Kontron N6310 S 43 Board - items: - - const: kontron,imx6ul-n6310-s-43 - - const: kontron,imx6ul-n6310-s - - const: kontron,imx6ul-n6310-som + - const: kontron,bl-imx6ul-43 # Kontron BL i.MX6UL Carrier Board with 4.3" Display + - const: kontron,bl-imx6ul # Kontron BL i.MX6UL Carrier Board + - const: kontron,sl-imx6ul # Kontron SL i.MX6UL SoM - const: fsl,imx6ul - description: TQ-Systems TQMa6UL1 SoM on MBa6ULx board @@ -637,7 +630,7 @@ properties: - enum: - fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board - joz,jozacp # JOZ Access Point - - kontron,imx6ull-n6411-som # Kontron N6411 SOM + - kontron,sl-imx6ull # Kontron SL i.MX6ULL SoM - myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board - toradex,colibri-imx6ull # Colibri iMX6ULL Modules - toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module @@ -698,10 +691,10 @@ properties: - const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module - const: fsl,imx6ull - - description: Kontron N6411 S Board + - description: Kontron BL i.MX6ULL (N6411 S) Board items: - - const: kontron,imx6ull-n6411-s - - const: kontron,imx6ull-n6411-som + - const: kontron,bl-imx6ull # Kontron BL i.MX6ULL Carrier Board + - const: kontron,sl-imx6ull # Kontron SL i.MX6ULL SoM - const: fsl,imx6ull - description: TQ Systems TQMa6ULLx SoM on MBa6ULx board @@ -825,13 +818,15 @@ properties: - emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base - fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board - fsl,imx8mm-evk # i.MX8MM EVK Board + - gateworks,imx8mm-gw7904 - gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit - gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit - gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit - gw,imx8mm-gw7901 # i.MX8MM Gateworks Board - gw,imx8mm-gw7902 # i.MX8MM Gateworks Board - gw,imx8mm-gw7903 # i.MX8MM Gateworks Board - - kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM + - kontron,imx8mm-sl # i.MX8MM Kontron SL (N801X) SOM + - kontron,imx8mm-osm-s # i.MX8MM Kontron OSM-S (N802X) SOM - menlo,mx8menlo # i.MX8MM Menlo board with Verdin SoM - toradex,verdin-imx8mm # Verdin iMX8M Mini Modules - toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT @@ -850,8 +845,14 @@ properties: - description: Kontron BL i.MX8MM (N801X S) Board items: - - const: kontron,imx8mm-n801x-s - - const: kontron,imx8mm-n801x-som + - const: kontron,imx8mm-bl + - const: kontron,imx8mm-sl + - const: fsl,imx8mm + + - description: Kontron BL i.MX8MM OSM-S (N802X S) Board + items: + - const: kontron,imx8mm-bl-osm-s + - const: kontron,imx8mm-osm-s - const: fsl,imx8mm - description: Toradex Boards with Verdin iMX8M Mini Modules @@ -936,6 +937,13 @@ properties: - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules - const: fsl,imx8mp + - description: Avnet (MSC Branded) Boards with SM2S i.MX8M Plus Modules + items: + - const: avnet,sm2s-imx8mp-14N0600E-ep1 # SM2S-IMX8PLUS-14N0600E on SM2-MB-EP1 Carrier Board + - const: avnet,sm2s-imx8mp-14N0600E # 14N0600E variant of SM2S-IMX8PLUS SoM + - const: avnet,sm2s-imx8mp # SM2S-IMX8PLUS SoM + - const: fsl,imx8mp + - description: Engicam i.Core MX8M Plus SoM based boards items: - enum: @@ -1034,6 +1042,12 @@ properties: - toradex,colibri-imx8x # Colibri iMX8X Modules - const: fsl,imx8qxp + - description: i.MX8DXL based Boards + items: + - enum: + - fsl,imx8dxl-evk # i.MX8DXL EVK Board + - const: fsl,imx8dxl + - description: i.MX8QXP Boards with Toradex Coilbri iMX8X Modules items: - enum: diff --git a/dts/Bindings/arm/intel,keembay.yaml b/dts/Bindings/arm/intel,keembay.yaml index 107e686ab2..53d2ce02b2 100644 --- a/dts/Bindings/arm/intel,keembay.yaml +++ b/dts/Bindings/arm/intel,keembay.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/intel,keembay.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Keem Bay platform device tree bindings +title: Keem Bay platform maintainers: - Paul J. Murphy <paul.j.murphy@intel.com> diff --git a/dts/Bindings/arm/intel,socfpga.yaml b/dts/Bindings/arm/intel,socfpga.yaml index 61a454a40e..4b4dcf551e 100644 --- a/dts/Bindings/arm/intel,socfpga.yaml +++ b/dts/Bindings/arm/intel,socfpga.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/intel,socfpga.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Intel SoCFPGA platform device tree bindings +title: Intel SoCFPGA platform maintainers: - Dinh Nguyen <dinguyen@kernel.org> diff --git a/dts/Bindings/arm/intel-ixp4xx.yaml b/dts/Bindings/arm/intel-ixp4xx.yaml index 230bffeec0..553dcbc70e 100644 --- a/dts/Bindings/arm/intel-ixp4xx.yaml +++ b/dts/Bindings/arm/intel-ixp4xx.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/intel-ixp4xx.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Intel IXP4xx Device Tree Bindings +title: Intel IXP4xx maintainers: - Linus Walleij <linus.walleij@linaro.org> diff --git a/dts/Bindings/arm/marvell/armada-37xx.txt b/dts/Bindings/arm/marvell/armada-37xx.txt index f6d6642d81..29fa93dad5 100644 --- a/dts/Bindings/arm/marvell/armada-37xx.txt +++ b/dts/Bindings/arm/marvell/armada-37xx.txt @@ -1,21 +1,3 @@ -Marvell Armada 37xx Platforms Device Tree Bindings --------------------------------------------------- - -Boards using a SoC of the Marvell Armada 37xx family must carry the -following root node property: - - - compatible: must contain "marvell,armada3710" - -In addition, boards using the Marvell Armada 3720 SoC shall have the -following property before the previous one: - - - compatible: must contain "marvell,armada3720" - -Example: - -compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710"; - - Power management ---------------- @@ -48,11 +30,3 @@ avs: avs@11500 { compatible = "marvell,armada-3700-avs", "syscon"; reg = <0x11500 0x40>; } - - -CZ.NIC's Turris Mox SOHO router Device Tree Bindings ----------------------------------------------------- - -Required root node property: - - - compatible: must contain "cznic,turris-mox" diff --git a/dts/Bindings/arm/marvell/armada-37xx.yaml b/dts/Bindings/arm/marvell/armada-37xx.yaml new file mode 100644 index 0000000000..6905d29f31 --- /dev/null +++ b/dts/Bindings/arm/marvell/armada-37xx.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/armada-37xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 37xx Platforms + +maintainers: + - Robert Marko <robert.marko@sartura.hr> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Armada 3720 SoC boards + items: + - enum: + - cznic,turris-mox + - globalscale,espressobin + - marvell,armada-3720-db + - methode,edpu + - methode,udpu + - const: marvell,armada3720 + - const: marvell,armada3710 + + - description: Globalscale Espressobin boards + items: + - enum: + - globalscale,espressobin-emmc + - globalscale,espressobin-ultra + - globalscale,espressobin-v7 + - const: globalscale,espressobin + - const: marvell,armada3720 + - const: marvell,armada3710 + + - description: Globalscale Espressobin V7 boards + items: + - enum: + - globalscale,espressobin-v7-emmc + - const: globalscale,espressobin-v7 + - const: globalscale,espressobin + - const: marvell,armada3720 + - const: marvell,armada3710 + +additionalProperties: true diff --git a/dts/Bindings/arm/mediatek.yaml b/dts/Bindings/arm/mediatek.yaml index 07c0ea94e8..d76ce4c381 100644 --- a/dts/Bindings/arm/mediatek.yaml +++ b/dts/Bindings/arm/mediatek.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/mediatek.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: MediaTek SoC based Platforms Device Tree Bindings +title: MediaTek SoC based Platforms maintainers: - Sean Wang <sean.wang@mediatek.com> diff --git a/dts/Bindings/arm/mediatek/mediatek,infracfg.yaml b/dts/Bindings/arm/mediatek/mediatek,infracfg.yaml index 8681b785ed..1d7c837d93 100644 --- a/dts/Bindings/arm/mediatek/mediatek,infracfg.yaml +++ b/dts/Bindings/arm/mediatek/mediatek,infracfg.yaml @@ -23,6 +23,7 @@ properties: - mediatek,mt2701-infracfg - mediatek,mt2712-infracfg - mediatek,mt6765-infracfg + - mediatek,mt6795-infracfg - mediatek,mt6779-infracfg_ao - mediatek,mt6797-infracfg - mediatek,mt7622-infracfg @@ -60,6 +61,7 @@ if: enum: - mediatek,mt2701-infracfg - mediatek,mt2712-infracfg + - mediatek,mt6795-infracfg - mediatek,mt7622-infracfg - mediatek,mt7986-infracfg - mediatek,mt8135-infracfg diff --git a/dts/Bindings/arm/mediatek/mediatek,mmsys.yaml b/dts/Bindings/arm/mediatek/mediatek,mmsys.yaml index 6ad023eec1..eb451bec23 100644 --- a/dts/Bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/dts/Bindings/arm/mediatek/mediatek,mmsys.yaml @@ -25,6 +25,7 @@ properties: - mediatek,mt2712-mmsys - mediatek,mt6765-mmsys - mediatek,mt6779-mmsys + - mediatek,mt6795-mmsys - mediatek,mt6797-mmsys - mediatek,mt8167-mmsys - mediatek,mt8173-mmsys @@ -52,7 +53,8 @@ properties: description: Using mailbox to communicate with GCE, it should have this property and list of phandle, mailbox specifiers. See - Documentation/devicetree/bindings/mailbox/mtk-gce.txt for details. + Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml + for details. $ref: /schemas/types.yaml#/definitions/phandle-array mediatek,gce-client-reg: diff --git a/dts/Bindings/arm/mediatek/mediatek,mt7622-wed.yaml b/dts/Bindings/arm/mediatek/mediatek,mt7622-wed.yaml index 787d6673f9..84fb0a146b 100644 --- a/dts/Bindings/arm/mediatek/mediatek,mt7622-wed.yaml +++ b/dts/Bindings/arm/mediatek/mediatek,mt7622-wed.yaml @@ -20,6 +20,7 @@ properties: items: - enum: - mediatek,mt7622-wed + - mediatek,mt7986-wed - const: syscon reg: diff --git a/dts/Bindings/arm/mediatek/mediatek,mt7986-wed-pcie.yaml b/dts/Bindings/arm/mediatek/mediatek,mt7986-wed-pcie.yaml new file mode 100644 index 0000000000..96221f51c1 --- /dev/null +++ b/dts/Bindings/arm/mediatek/mediatek,mt7986-wed-pcie.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wed-pcie.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek PCIE WED Controller for MT7986 + +maintainers: + - Lorenzo Bianconi <lorenzo@kernel.org> + - Felix Fietkau <nbd@nbd.name> + +description: + The mediatek WED PCIE provides a configuration interface for PCIE + controller on MT7986 soc. + +properties: + compatible: + items: + - enum: + - mediatek,mt7986-wed-pcie + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + wed_pcie: wed-pcie@10003000 { + compatible = "mediatek,mt7986-wed-pcie", + "syscon"; + reg = <0 0x10003000 0 0x10>; + }; + }; diff --git a/dts/Bindings/arm/mediatek/mediatek,pericfg.yaml b/dts/Bindings/arm/mediatek/mediatek,pericfg.yaml index 8585f6f18f..ef62cbb135 100644 --- a/dts/Bindings/arm/mediatek/mediatek,pericfg.yaml +++ b/dts/Bindings/arm/mediatek/mediatek,pericfg.yaml @@ -21,6 +21,7 @@ properties: - mediatek,mt2701-pericfg - mediatek,mt2712-pericfg - mediatek,mt6765-pericfg + - mediatek,mt6795-pericfg - mediatek,mt7622-pericfg - mediatek,mt7629-pericfg - mediatek,mt8135-pericfg diff --git a/dts/Bindings/arm/microchip,sparx5.yaml b/dts/Bindings/arm/microchip,sparx5.yaml index 6193388c63..9a0d54e979 100644 --- a/dts/Bindings/arm/microchip,sparx5.yaml +++ b/dts/Bindings/arm/microchip,sparx5.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/microchip,sparx5.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Microchip Sparx5 Boards Device Tree Bindings +title: Microchip Sparx5 Boards maintainers: - Lars Povlsen <lars.povlsen@microchip.com> diff --git a/dts/Bindings/arm/moxart.yaml b/dts/Bindings/arm/moxart.yaml index 670d24ce8e..4256528091 100644 --- a/dts/Bindings/arm/moxart.yaml +++ b/dts/Bindings/arm/moxart.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/moxart.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: MOXA ART device tree bindings +title: MOXA ART maintainers: - Jonas Jensen <jonas.jensen@gmail.com> diff --git a/dts/Bindings/arm/nvidia,tegra194-ccplex.yaml b/dts/Bindings/arm/nvidia,tegra194-ccplex.yaml index c9675c4cdc..b6f57d79a7 100644 --- a/dts/Bindings/arm/nvidia,tegra194-ccplex.yaml +++ b/dts/Bindings/arm/nvidia,tegra194-ccplex.yaml @@ -4,7 +4,7 @@ $id: "http://devicetree.org/schemas/arm/nvidia,tegra194-ccplex.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: NVIDIA Tegra194 CPU Complex device tree bindings +title: NVIDIA Tegra194 CPU Complex maintainers: - Thierry Reding <thierry.reding@gmail.com> diff --git a/dts/Bindings/arm/psci.yaml b/dts/Bindings/arm/psci.yaml index dd83ef278a..3a2c908ff2 100644 --- a/dts/Bindings/arm/psci.yaml +++ b/dts/Bindings/arm/psci.yaml @@ -43,29 +43,24 @@ properties: - description: For implementations complying to PSCI 0.2. - const: arm,psci-0.2 - - - description: - For implementations complying to PSCI 0.2. Function IDs are not required and should be ignored by an OS with PSCI 0.2 support, but are permitted to be present for compatibility with existing software when "arm,psci" is later in the compatible list. + minItems: 1 items: - const: arm,psci-0.2 - const: arm,psci - description: For implementations complying to PSCI 1.0. - const: arm,psci-1.0 - - - description: - For implementations complying to PSCI 1.0. PSCI 1.0 is backward compatible with PSCI 0.2 with minor specification updates, as defined in the PSCI specification[2]. + minItems: 1 items: - const: arm,psci-1.0 - const: arm,psci-0.2 + - const: arm,psci method: description: The method of calling the PSCI firmware. diff --git a/dts/Bindings/arm/qcom.yaml b/dts/Bindings/arm/qcom.yaml index fb1d00bcc8..1b5ac6b02b 100644 --- a/dts/Bindings/arm/qcom.yaml +++ b/dts/Bindings/arm/qcom.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/qcom.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: QCOM device tree bindings +title: QCOM maintainers: - Bjorn Andersson <bjorn.andersson@linaro.org> @@ -176,6 +176,9 @@ properties: - longcheer,l8910 - samsung,a3u-eur - samsung,a5u-eur + - samsung,e5 + - samsung,e7 + - samsung,grandmax - samsung,j5 - samsung,serranove - wingtech,wt88047 @@ -450,6 +453,7 @@ properties: - description: Google Pazquel with LTE and Parade (newest rev) items: + - const: google,pazquel-sku6 - const: google,pazquel-sku4 - const: qcom,sc7180 @@ -550,6 +554,7 @@ properties: - description: Qualcomm Technologies, Inc. sc7280 CRD platform (newest rev) items: + - const: google,zoglin - const: google,hoglin - const: qcom,sc7280 @@ -565,16 +570,31 @@ properties: - const: google,piglin - const: qcom,sc7280 + - description: Google Evoker (newest rev) + items: + - const: google,evoker + - const: qcom,sc7280 + - description: Google Herobrine (newest rev) items: - const: google,herobrine - const: qcom,sc7280 + - description: Google Villager (rev0) + items: + - const: google,villager-rev0 + - const: qcom,sc7280 + - description: Google Villager (newest rev) items: - const: google,villager - const: qcom,sc7280 + - description: Google Villager with LTE (newest rev) + items: + - const: google,villager-sku512 + - const: qcom,sc7280 + - items: - enum: - lenovo,flex-5g @@ -716,6 +736,7 @@ properties: - enum: - qcom,sm8450-hdk - qcom,sm8450-qrd + - sony,pdx223 - const: qcom,sm8450 additionalProperties: true diff --git a/dts/Bindings/arm/rda.yaml b/dts/Bindings/arm/rda.yaml index a5c0444aa2..09241ea1d2 100644 --- a/dts/Bindings/arm/rda.yaml +++ b/dts/Bindings/arm/rda.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/rda.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: RDA Micro platforms device tree bindings +title: RDA Micro platforms maintainers: - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> diff --git a/dts/Bindings/arm/realtek.yaml b/dts/Bindings/arm/realtek.yaml index 9fb0297fe1..ddd9a85099 100644 --- a/dts/Bindings/arm/realtek.yaml +++ b/dts/Bindings/arm/realtek.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/realtek.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Realtek platforms device tree bindings +title: Realtek platforms maintainers: - Andreas Färber <afaerber@suse.de> diff --git a/dts/Bindings/arm/renesas.yaml b/dts/Bindings/arm/renesas.yaml index ff80152f09..f51464a08a 100644 --- a/dts/Bindings/arm/renesas.yaml +++ b/dts/Bindings/arm/renesas.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/renesas.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings +title: Renesas SH-Mobile, R-Mobile, and R-Car Platform maintainers: - Geert Uytterhoeven <geert+renesas@glider.be> @@ -264,6 +264,7 @@ properties: - renesas,r8a779m4 - renesas,r8a779m5 - renesas,r8a779m8 + - renesas,r8a779mb - enum: - renesas,r8a7795 - renesas,r8a77961 @@ -291,6 +292,13 @@ properties: - renesas,v3hsk # V3HSK (Y-ASK-RCAR-V3H-WS10) - const: renesas,r8a77980 + - description: R-Car V3H2 (R8A77980A) + items: + - enum: + - renesas,condor-i # Condor-I (RTP0RC77980SEBS012SA01) + - const: renesas,r8a77980a + - const: renesas,r8a77980 + - description: R-Car E3 (R8A77990) items: - enum: @@ -409,6 +417,14 @@ properties: - const: renesas,r8a779m8 - const: renesas,r8a7795 + - description: R-Car H3Ne-1.7G (R8A779MB) + items: + - enum: + - renesas,h3ulcb # H3ULCB (R-Car Starter Kit Premier) + - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version) + - const: renesas,r8a779mb + - const: renesas,r8a7795 + - description: RZ/N1D (R9A06G032) items: - enum: diff --git a/dts/Bindings/arm/rockchip.yaml b/dts/Bindings/arm/rockchip.yaml index 7811ba6414..c6c69a4e37 100644 --- a/dts/Bindings/arm/rockchip.yaml +++ b/dts/Bindings/arm/rockchip.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/rockchip.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Rockchip platforms device tree bindings +title: Rockchip platforms maintainers: - Heiko Stuebner <heiko@sntech.de> @@ -30,6 +30,16 @@ properties: - const: amarula,vyasa-rk3288 - const: rockchip,rk3288 + - description: Anbernic RG353P + items: + - const: anbernic,rg353p + - const: rockchip,rk3566 + + - description: Anbernic RG503 + items: + - const: anbernic,rg503 + - const: rockchip,rk3566 + - description: Asus Tinker board items: - const: asus,rk3288-tinker @@ -151,6 +161,7 @@ properties: - friendlyarm,nanopi-m4b - friendlyarm,nanopi-neo4 - friendlyarm,nanopi-r4s + - friendlyarm,nanopi-r4s-enterprise - const: rockchip,rk3399 - description: GeekBuying GeekBox @@ -363,30 +374,55 @@ properties: - const: google,gru - const: rockchip,rk3399 - - description: Google Scarlet - Innolux display (Acer Chromebook Tab 10) + - description: | + Google Scarlet - Innolux display (Acer Chromebook Tab 10 and more) items: + - const: google,scarlet-rev15-sku2 + - const: google,scarlet-rev15-sku4 - const: google,scarlet-rev15-sku6 - const: google,scarlet-rev15 + - const: google,scarlet-rev14-sku2 + - const: google,scarlet-rev14-sku4 - const: google,scarlet-rev14-sku6 - const: google,scarlet-rev14 + - const: google,scarlet-rev13-sku2 + - const: google,scarlet-rev13-sku4 - const: google,scarlet-rev13-sku6 - const: google,scarlet-rev13 + - const: google,scarlet-rev12-sku2 + - const: google,scarlet-rev12-sku4 - const: google,scarlet-rev12-sku6 - const: google,scarlet-rev12 + - const: google,scarlet-rev11-sku2 + - const: google,scarlet-rev11-sku4 - const: google,scarlet-rev11-sku6 - const: google,scarlet-rev11 + - const: google,scarlet-rev10-sku2 + - const: google,scarlet-rev10-sku4 - const: google,scarlet-rev10-sku6 - const: google,scarlet-rev10 + - const: google,scarlet-rev9-sku2 + - const: google,scarlet-rev9-sku4 - const: google,scarlet-rev9-sku6 - const: google,scarlet-rev9 + - const: google,scarlet-rev8-sku2 + - const: google,scarlet-rev8-sku4 - const: google,scarlet-rev8-sku6 - const: google,scarlet-rev8 + - const: google,scarlet-rev7-sku2 + - const: google,scarlet-rev7-sku4 - const: google,scarlet-rev7-sku6 - const: google,scarlet-rev7 + - const: google,scarlet-rev6-sku2 + - const: google,scarlet-rev6-sku4 - const: google,scarlet-rev6-sku6 - const: google,scarlet-rev6 + - const: google,scarlet-rev5-sku2 + - const: google,scarlet-rev5-sku4 - const: google,scarlet-rev5-sku6 - const: google,scarlet-rev5 + - const: google,scarlet-rev4-sku2 + - const: google,scarlet-rev4-sku4 - const: google,scarlet-rev4-sku6 - const: google,scarlet-rev4 - const: google,scarlet @@ -470,6 +506,11 @@ properties: - const: netxeon,r89 - const: rockchip,rk3288 + - description: OPEN AI LAB EAIDK-610 + items: + - const: openailab,eaidk-610 + - const: rockchip,rk3399 + - description: Orange Pi RK3399 board items: - const: rockchip,rk3399-orangepi @@ -494,6 +535,11 @@ properties: - const: pine64,pinenote - const: rockchip,rk3566 + - description: Pine64 PinePhonePro + items: + - const: pine64,pinephone-pro + - const: rockchip,rk3399 + - description: Pine64 Rock64 items: - const: pine64,rock64 @@ -537,6 +583,11 @@ properties: - const: radxa,rockpi4 - const: rockchip,rk3399 + - description: Radxa ROCK 4C+ + items: + - const: radxa,rock-4c-plus + - const: rockchip,rk3399 + - description: Radxa ROCK Pi E items: - const: radxa,rockpi-e diff --git a/dts/Bindings/arm/rockchip/pmu.yaml b/dts/Bindings/arm/rockchip/pmu.yaml index 5ece38065e..8c73bc7f40 100644 --- a/dts/Bindings/arm/rockchip/pmu.yaml +++ b/dts/Bindings/arm/rockchip/pmu.yaml @@ -21,10 +21,12 @@ select: enum: - rockchip,px30-pmu - rockchip,rk3066-pmu + - rockchip,rk3128-pmu - rockchip,rk3288-pmu - rockchip,rk3368-pmu - rockchip,rk3399-pmu - rockchip,rk3568-pmu + - rockchip,rk3588-pmu required: - compatible @@ -35,10 +37,12 @@ properties: - enum: - rockchip,px30-pmu - rockchip,rk3066-pmu + - rockchip,rk3128-pmu - rockchip,rk3288-pmu - rockchip,rk3368-pmu - rockchip,rk3399-pmu - rockchip,rk3568-pmu + - rockchip,rk3588-pmu - const: syscon - const: simple-mfd diff --git a/dts/Bindings/arm/socionext/socionext,uniphier-system-cache.yaml b/dts/Bindings/arm/socionext/socionext,uniphier-system-cache.yaml index 7ca5375f27..6096c082d5 100644 --- a/dts/Bindings/arm/socionext/socionext,uniphier-system-cache.yaml +++ b/dts/Bindings/arm/socionext/socionext,uniphier-system-cache.yaml @@ -22,7 +22,6 @@ properties: description: | should contain 3 regions: control register, revision register, operation register, in this order. - minItems: 3 maxItems: 3 interrupts: diff --git a/dts/Bindings/arm/spear.yaml b/dts/Bindings/arm/spear.yaml index 605ad3f882..a465c9eca7 100644 --- a/dts/Bindings/arm/spear.yaml +++ b/dts/Bindings/arm/spear.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/spear.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ST SPEAr Platforms Device Tree Bindings +title: ST SPEAr Platforms maintainers: - Viresh Kumar <vireshk@kernel.org> diff --git a/dts/Bindings/arm/sti.yaml b/dts/Bindings/arm/sti.yaml index a41cd87648..3ca054c643 100644 --- a/dts/Bindings/arm/sti.yaml +++ b/dts/Bindings/arm/sti.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/sti.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ST STi Platforms Device Tree Bindings +title: ST STi Platforms maintainers: - Patrice Chotard <patrice.chotard@foss.st.com> diff --git a/dts/Bindings/arm/sunxi.yaml b/dts/Bindings/arm/sunxi.yaml index 0c23567782..3ad1cd50e3 100644 --- a/dts/Bindings/arm/sunxi.yaml +++ b/dts/Bindings/arm/sunxi.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/sunxi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner platforms device tree bindings +title: Allwinner platforms maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/arm/tegra.yaml b/dts/Bindings/arm/tegra.yaml index 49841ca272..1f62253f94 100644 --- a/dts/Bindings/arm/tegra.yaml +++ b/dts/Bindings/arm/tegra.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/tegra.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: NVIDIA Tegra device tree bindings +title: NVIDIA Tegra maintainers: - Thierry Reding <thierry.reding@gmail.com> diff --git a/dts/Bindings/arm/tesla.yaml b/dts/Bindings/arm/tesla.yaml index 09856da657..d670a0d562 100644 --- a/dts/Bindings/arm/tesla.yaml +++ b/dts/Bindings/arm/tesla.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/tesla.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Tesla Full Self Driving(FSD) platforms device tree bindings +title: Tesla Full Self Driving(FSD) platforms maintainers: - Alim Akhtar <alim.akhtar@samsung.com> diff --git a/dts/Bindings/arm/ti/k3.yaml b/dts/Bindings/arm/ti/k3.yaml index 61c6ab4f52..28b8232e1c 100644 --- a/dts/Bindings/arm/ti/k3.yaml +++ b/dts/Bindings/arm/ti/k3.yaml @@ -19,32 +19,11 @@ properties: compatible: oneOf: - - description: K3 AM654 SoC + - description: K3 AM62A7 SoC items: - enum: - - ti,am654-evm - - siemens,iot2050-basic - - siemens,iot2050-basic-pg2 - - siemens,iot2050-advanced - - siemens,iot2050-advanced-pg2 - - const: ti,am654 - - - description: K3 J721E SoC - oneOf: - - const: ti,j721e - - items: - - enum: - - ti,j721e-evm - - ti,j721e-sk - - const: ti,j721e - - - description: K3 J7200 SoC - oneOf: - - const: ti,j7200 - - items: - - enum: - - ti,j7200-evm - - const: ti,j7200 + - ti,am62a7-sk + - const: ti,am62a7 - description: K3 AM625 SoC items: @@ -59,6 +38,33 @@ properties: - ti,am642-sk - const: ti,am642 + - description: K3 AM654 SoC + items: + - enum: + - siemens,iot2050-advanced + - siemens,iot2050-advanced-pg2 + - siemens,iot2050-basic + - siemens,iot2050-basic-pg2 + - ti,am654-evm + - const: ti,am654 + + - description: K3 J7200 SoC + oneOf: + - const: ti,j7200 + - items: + - enum: + - ti,j7200-evm + - const: ti,j7200 + + - description: K3 J721E SoC + oneOf: + - const: ti,j721e + - items: + - enum: + - ti,j721e-evm + - ti,j721e-sk + - const: ti,j721e + - description: K3 J721s2 SoC items: - enum: diff --git a/dts/Bindings/arm/toshiba.yaml b/dts/Bindings/arm/toshiba.yaml index 9c1cacbdc9..716ba4a3ca 100644 --- a/dts/Bindings/arm/toshiba.yaml +++ b/dts/Bindings/arm/toshiba.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/toshiba.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Toshiba Visconti Platform Device Tree Bindings +title: Toshiba Visconti Platform maintainers: - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> diff --git a/dts/Bindings/arm/ux500.yaml b/dts/Bindings/arm/ux500.yaml index 17accb31bc..b42d20fa43 100644 --- a/dts/Bindings/arm/ux500.yaml +++ b/dts/Bindings/arm/ux500.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/ux500.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Ux500 platforms device tree bindings +title: Ux500 platforms maintainers: - Linus Walleij <linus.walleij@linaro.org> diff --git a/dts/Bindings/arm/versatile-sysreg.txt b/dts/Bindings/arm/versatile-sysreg.txt deleted file mode 100644 index a4f15262d7..0000000000 --- a/dts/Bindings/arm/versatile-sysreg.txt +++ /dev/null @@ -1,10 +0,0 @@ -ARM Versatile system registers --------------------------------------- - -This is a system control registers block, providing multiple low level -platform functions like board detection and identification, software -interrupt generation, MMC and NOR Flash control etc. - -Required node properties: -- compatible value : = "arm,versatile-sysreg", "syscon" -- reg : physical base address and the size of the registers window diff --git a/dts/Bindings/arm/vt8500.yaml b/dts/Bindings/arm/vt8500.yaml index 7b762bfc11..5d5ad5a604 100644 --- a/dts/Bindings/arm/vt8500.yaml +++ b/dts/Bindings/arm/vt8500.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/vt8500.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: VIA/Wondermedia VT8500 Platforms Device Tree Bindings +title: VIA/Wondermedia VT8500 Platforms maintainers: - Tony Prisk <linux@prisktech.co.nz> diff --git a/dts/Bindings/arm/xilinx.yaml b/dts/Bindings/arm/xilinx.yaml index 4dc0e01959..969cfe6dc4 100644 --- a/dts/Bindings/arm/xilinx.yaml +++ b/dts/Bindings/arm/xilinx.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/arm/xilinx.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Xilinx Zynq Platforms Device Tree Bindings +title: Xilinx Zynq Platforms maintainers: - Michal Simek <michal.simek@xilinx.com> diff --git a/dts/Bindings/ata/ahci-common.yaml b/dts/Bindings/ata/ahci-common.yaml new file mode 100644 index 0000000000..94d72aeaad --- /dev/null +++ b/dts/Bindings/ata/ahci-common.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/ahci-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common Properties for Serial ATA AHCI controllers + +maintainers: + - Hans de Goede <hdegoede@redhat.com> + - Damien Le Moal <damien.lemoal@opensource.wdc.com> + +description: + This document defines device tree properties for a common AHCI SATA + controller implementation. It's hardware interface is supposed to + conform to the technical standard defined by Intel (see Serial ATA + Advanced Host Controller Interface specification for details). The + document doesn't constitute a DT-node binding by itself but merely + defines a set of common properties for the AHCI-compatible devices. + +select: false + +allOf: + - $ref: sata-common.yaml# + +properties: + reg: + description: + Generic AHCI registers space conforming to the Serial ATA AHCI + specification. + + reg-names: + description: CSR space IDs + contains: + const: ahci + + interrupts: + description: + Generic AHCI state change interrupt. Can be implemented either as a + single line attached to the controller or as a set of the signals + indicating the particular port events. + minItems: 1 + maxItems: 32 + + ahci-supply: + description: Power regulator for AHCI controller + + target-supply: + description: Power regulator for SATA target device + + phy-supply: + description: Power regulator for SATA PHY + + phys: + description: Reference to the SATA PHY node + maxItems: 1 + + phy-names: + const: sata-phy + + hba-cap: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + Bitfield of the HBA generic platform capabilities like Staggered + Spin-up or Mechanical Presence Switch support. It can be used to + appropriately initialize the HWinit fields of the HBA CAP register + in case if the system firmware hasn't done it. + + ports-implemented: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + Mask that indicates which ports the HBA supports. Useful if PI is not + programmed by the BIOS, which is true for some embedded SoC's. + +patternProperties: + "^sata-port@[0-9a-f]+$": + $ref: '#/$defs/ahci-port' + description: + It is optionally possible to describe the ports as sub-nodes so + to enable each port independently when dealing with multiple PHYs. + +required: + - reg + - interrupts + +additionalProperties: true + +$defs: + ahci-port: + $ref: /schemas/ata/sata-common.yaml#/$defs/sata-port + + properties: + reg: + description: + AHCI SATA port identifier. By design AHCI controller can't have + more than 32 ports due to the CAP.NP fields and PI register size + constraints. + minimum: 0 + maximum: 31 + + phys: + description: Individual AHCI SATA port PHY + maxItems: 1 + + phy-names: + description: AHCI SATA port PHY ID + const: sata-phy + + target-supply: + description: Power regulator for SATA port target device + + hba-port-cap: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + Bitfield of the HBA port-specific platform capabilities like Hot + plugging, eSATA, FIS-based Switching, etc (see AHCI specification + for details). It can be used to initialize the HWinit fields of + the PxCMD register in case if the system firmware hasn't done it. + + required: + - reg + +... diff --git a/dts/Bindings/ata/ahci-platform.yaml b/dts/Bindings/ata/ahci-platform.yaml index c146ab8e14..7dc2a2e8f5 100644 --- a/dts/Bindings/ata/ahci-platform.yaml +++ b/dts/Bindings/ata/ahci-platform.yaml @@ -30,14 +30,11 @@ select: - marvell,armada-3700-ahci - marvell,armada-8k-ahci - marvell,berlin2q-ahci - - snps,dwc-ahci - - snps,spear-ahci required: - compatible allOf: - - $ref: "sata-common.yaml#" - + - $ref: "ahci-common.yaml#" properties: compatible: @@ -49,17 +46,11 @@ properties: - marvell,berlin2-ahci - marvell,berlin2q-ahci - const: generic-ahci - - items: - - enum: - - rockchip,rk3568-dwc-ahci - - const: snps,dwc-ahci - enum: - cavium,octeon-7130-ahci - hisilicon,hisi-ahci - ibm,476gtr-ahci - marvell,armada-3700-ahci - - snps,dwc-ahci - - snps,spear-ahci reg: minItems: 1 @@ -69,92 +60,37 @@ properties: maxItems: 1 clocks: - description: - Clock IDs array as required by the controller. minItems: 1 maxItems: 3 clock-names: - description: - Names of clocks corresponding to IDs in the clock property. minItems: 1 maxItems: 3 interrupts: maxItems: 1 - ahci-supply: - description: - regulator for AHCI controller - - dma-coherent: true - - phy-supply: - description: - regulator for PHY power - - phys: - description: - List of all PHYs on this controller - maxItems: 1 - - phy-names: - description: - Name specifier for the PHYs - maxItems: 1 - - ports-implemented: - $ref: '/schemas/types.yaml#/definitions/uint32' - description: | - Mask that indicates which ports that the HBA supports - are available for software to use. Useful if PORTS_IMPL - is not programmed by the BIOS, which is true with - some embedded SoCs. - maximum: 0x1f - power-domains: maxItems: 1 resets: maxItems: 1 - target-supply: - description: - regulator for SATA target power - -required: - - compatible - - reg - - interrupts - patternProperties: "^sata-port@[0-9a-f]+$": - type: object - additionalProperties: false - description: - Subnode with configuration of the Ports. - - properties: - reg: - maxItems: 1 - - phys: - maxItems: 1 - - phy-names: - maxItems: 1 - - target-supply: - description: - regulator for SATA target power - - required: - - reg + $ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port anyOf: - required: [ phys ] - required: [ target-supply ] + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + unevaluatedProperties: false examples: @@ -167,6 +103,8 @@ examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/berlin2q.h> + #include <dt-bindings/ata/ahci.h> + sata@f7e90000 { compatible = "marvell,berlin2q-ahci", "generic-ahci"; reg = <0xf7e90000 0x1000>; @@ -175,15 +113,23 @@ examples: #address-cells = <1>; #size-cells = <0>; + hba-cap = <HBA_SMPS>; + sata0: sata-port@0 { reg = <0>; + phys = <&sata_phy 0>; target-supply = <®_sata0>; + + hba-port-cap = <(HBA_PORT_FBSCP | HBA_PORT_ESP)>; }; sata1: sata-port@1 { reg = <1>; + phys = <&sata_phy 1>; target-supply = <®_sata1>; + + hba-port-cap = <(HBA_PORT_HPCP | HBA_PORT_MPSP | HBA_PORT_FBSCP)>; }; }; diff --git a/dts/Bindings/ata/baikal,bt1-ahci.yaml b/dts/Bindings/ata/baikal,bt1-ahci.yaml new file mode 100644 index 0000000000..9b7ca4759b --- /dev/null +++ b/dts/Bindings/ata/baikal,bt1-ahci.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 SoC AHCI SATA controller + +maintainers: + - Serge Semin <fancer.lancer@gmail.com> + +description: + AHCI SATA controller embedded into the Baikal-T1 SoC is based on the + DWC AHCI SATA v4.10a IP-core. + +allOf: + - $ref: snps,dwc-ahci-common.yaml# + +properties: + compatible: + const: baikal,bt1-ahci + + clocks: + items: + - description: Peripheral APB bus clock + - description: Application AXI BIU clock + - description: SATA Ports reference clock + + clock-names: + items: + - const: pclk + - const: aclk + - const: ref + + resets: + items: + - description: Application AXI BIU domain reset + - description: SATA Ports clock domain reset + + reset-names: + items: + - const: arst + - const: ref + + ports-implemented: + maximum: 0x3 + +patternProperties: + "^sata-port@[0-1]$": + $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port + + properties: + reg: + minimum: 0 + maximum: 1 + + snps,tx-ts-max: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Due to having AXI3 bus interface utilized the maximum Tx DMA + transaction size can't exceed 16 beats (AxLEN[3:0]). + enum: [ 1, 2, 4, 8, 16 ] + + snps,rx-ts-max: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Due to having AXI3 bus interface utilized the maximum Rx DMA + transaction size can't exceed 16 beats (AxLEN[3:0]). + enum: [ 1, 2, 4, 8, 16 ] + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + +unevaluatedProperties: false + +examples: + - | + sata@1f050000 { + compatible = "baikal,bt1-ahci"; + reg = <0x1f050000 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + + interrupts = <0 64 4>; + + clocks = <&ccu_sys 1>, <&ccu_axi 2>, <&sata_ref_clk>; + clock-names = "pclk", "aclk", "ref"; + + resets = <&ccu_axi 2>, <&ccu_sys 0>; + reset-names = "arst", "ref"; + + ports-implemented = <0x3>; + + sata-port@0 { + reg = <0>; + + snps,tx-ts-max = <4>; + snps,rx-ts-max = <4>; + }; + + sata-port@1 { + reg = <1>; + + snps,tx-ts-max = <4>; + snps,rx-ts-max = <4>; + }; + }; +... diff --git a/dts/Bindings/ata/brcm,sata-brcm.yaml b/dts/Bindings/ata/brcm,sata-brcm.yaml index 235a93ac86..fe7f091e74 100644 --- a/dts/Bindings/ata/brcm,sata-brcm.yaml +++ b/dts/Bindings/ata/brcm,sata-brcm.yaml @@ -14,7 +14,7 @@ maintainers: - Florian Fainelli <f.fainelli@gmail.com> allOf: - - $ref: sata-common.yaml# + - $ref: ahci-common.yaml# properties: compatible: @@ -30,7 +30,6 @@ properties: - const: brcm,bcm-nsp-ahci reg: - minItems: 2 maxItems: 2 reg-names: @@ -41,8 +40,6 @@ properties: interrupts: maxItems: 1 - dma-coherent: true - if: properties: compatible: diff --git a/dts/Bindings/ata/cortina,gemini-sata-bridge.yaml b/dts/Bindings/ata/cortina,gemini-sata-bridge.yaml index 21a9097559..5290936665 100644 --- a/dts/Bindings/ata/cortina,gemini-sata-bridge.yaml +++ b/dts/Bindings/ata/cortina,gemini-sata-bridge.yaml @@ -22,7 +22,6 @@ properties: maxItems: 1 resets: - minItems: 2 maxItems: 2 description: phandles to the reset lines for both SATA bridges @@ -32,7 +31,6 @@ properties: - const: sata1 clocks: - minItems: 2 maxItems: 2 description: phandles to the compulsory peripheral clocks diff --git a/dts/Bindings/ata/sata-common.yaml b/dts/Bindings/ata/sata-common.yaml index 7ac77b1c58..58c9342b99 100644 --- a/dts/Bindings/ata/sata-common.yaml +++ b/dts/Bindings/ata/sata-common.yaml @@ -31,22 +31,27 @@ properties: "#size-cells": const: 0 + dma-coherent: true + patternProperties: "^sata-port@[0-9a-e]$": + $ref: '#/$defs/sata-port' description: | DT nodes for ports connected on the SATA host. The SATA port nodes will be named "sata-port". + +additionalProperties: true + +$defs: + sata-port: type: object properties: reg: minimum: 0 - maximum: 14 description: - The ID number of the drive port SATA can potentially use a port - multiplier making it possible to connect up to 15 disks to a single - SATA port. - -additionalProperties: true + The ID number of the SATA port. Aside with being directly used, + each port can have a Port Multiplier attached thus allowing to + access more than one drive by means of a single SATA port. ... diff --git a/dts/Bindings/ata/sata_highbank.yaml b/dts/Bindings/ata/sata_highbank.yaml index 49679b5804..f23f26a8f2 100644 --- a/dts/Bindings/ata/sata_highbank.yaml +++ b/dts/Bindings/ata/sata_highbank.yaml @@ -52,7 +52,6 @@ properties: minItems: 1 maxItems: 8 items: - minItems: 2 maxItems: 2 calxeda,tx-atten: diff --git a/dts/Bindings/ata/snps,dwc-ahci-common.yaml b/dts/Bindings/ata/snps,dwc-ahci-common.yaml new file mode 100644 index 0000000000..c145791052 --- /dev/null +++ b/dts/Bindings/ata/snps,dwc-ahci-common.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DWC AHCI SATA controller properties + +maintainers: + - Serge Semin <fancer.lancer@gmail.com> + +description: + This document defines device tree schema for the generic Synopsys DWC + AHCI controller properties. + +select: false + +allOf: + - $ref: ahci-common.yaml# + +properties: + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + description: + Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock, + PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx) + clock, etc. + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + items: + oneOf: + - description: Application APB/AHB/AXI BIU clock + enum: + - pclk + - aclk + - hclk + - sata + - description: Power Module keep-alive clock + const: pmalive + - description: RxOOB detection clock + const: rxoob + - description: SATA Ports reference clock + const: ref + + resets: + description: + At least basic application and reference clock domains resets are + normally supported by the DWC AHCI SATA controller. + minItems: 1 + maxItems: 4 + + reset-names: + minItems: 1 + maxItems: 4 + items: + oneOf: + - description: Application AHB/AXI BIU clock domain reset control + enum: + - arst + - hrst + - description: Power Module keep-alive clock domain reset control + const: pmalive + - description: RxOOB detection clock domain reset control + const: rxoob + - description: Reference clock domain reset control + const: ref + +patternProperties: + "^sata-port@[0-9a-e]$": + $ref: '#/$defs/dwc-ahci-port' + +additionalProperties: true + +$defs: + dwc-ahci-port: + $ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port + + properties: + reg: + minimum: 0 + maximum: 7 + + snps,tx-ts-max: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Maximal size of Tx DMA transactions in FIFO words + enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ] + + snps,rx-ts-max: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Maximal size of Rx DMA transactions in FIFO words + enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ] + +... diff --git a/dts/Bindings/ata/snps,dwc-ahci.yaml b/dts/Bindings/ata/snps,dwc-ahci.yaml new file mode 100644 index 0000000000..5afa4b57ce --- /dev/null +++ b/dts/Bindings/ata/snps,dwc-ahci.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DWC AHCI SATA controller + +maintainers: + - Serge Semin <fancer.lancer@gmail.com> + +description: + This document defines device tree bindings for the generic Synopsys DWC + implementation of the AHCI SATA controller. + +allOf: + - $ref: snps,dwc-ahci-common.yaml# + +properties: + compatible: + oneOf: + - description: Synopsys AHCI SATA-compatible devices + const: snps,dwc-ahci + - description: SPEAr1340 AHCI SATA device + const: snps,spear-ahci + - description: Rockhip RK3568 AHCI controller + items: + - const: rockchip,rk3568-dwc-ahci + - const: snps,dwc-ahci + +patternProperties: + "^sata-port@[0-9a-e]$": + $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/ata/ahci.h> + + sata@122f0000 { + compatible = "snps,dwc-ahci"; + reg = <0x122F0000 0x1ff>; + #address-cells = <1>; + #size-cells = <0>; + + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&clock1>, <&clock2>; + clock-names = "aclk", "ref"; + + phys = <&sata_phy>; + phy-names = "sata-phy"; + + ports-implemented = <0x1>; + + sata-port@0 { + reg = <0>; + + hba-port-cap = <HBA_PORT_FBSCP>; + + snps,tx-ts-max = <512>; + snps,rx-ts-max = <512>; + }; + }; + +... diff --git a/dts/Bindings/bus/allwinner,sun50i-a64-de2.yaml b/dts/Bindings/bus/allwinner,sun50i-a64-de2.yaml index ad313ccaaa..85c4a979ae 100644 --- a/dts/Bindings/bus/allwinner,sun50i-a64-de2.yaml +++ b/dts/Bindings/bus/allwinner,sun50i-a64-de2.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/bus/allwinner,sun50i-a64-de2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A64 Display Engine Bus Device Tree Bindings +title: Allwinner A64 Display Engine Bus maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/bus/allwinner,sun8i-a23-rsb.yaml b/dts/Bindings/bus/allwinner,sun8i-a23-rsb.yaml index 3d719f468a..bee5f53f83 100644 --- a/dts/Bindings/bus/allwinner,sun8i-a23-rsb.yaml +++ b/dts/Bindings/bus/allwinner,sun8i-a23-rsb.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/bus/allwinner,sun8i-a23-rsb.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A23 RSB Device Tree Bindings +title: Allwinner A23 RSB maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/bus/palmbus.yaml b/dts/Bindings/bus/palmbus.yaml index f5cbfaf52d..30fa6526cf 100644 --- a/dts/Bindings/bus/palmbus.yaml +++ b/dts/Bindings/bus/palmbus.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/bus/palmbus.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Ralink PalmBus Device Tree Bindings +title: Ralink PalmBus maintainers: - Sergio Paracuellos <sergio.paracuellos@gmail.com> diff --git a/dts/Bindings/clock/airoha,en7523-scu.yaml b/dts/Bindings/clock/airoha,en7523-scu.yaml index d60e746548..79b0752faa 100644 --- a/dts/Bindings/clock/airoha,en7523-scu.yaml +++ b/dts/Bindings/clock/airoha,en7523-scu.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/airoha,en7523-scu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: EN7523 Clock Device Tree Bindings +title: EN7523 Clock maintainers: - Felix Fietkau <nbd@nbd.name> diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-ahb-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-ahb-clk.yaml index 558db4b6ed..93587b7004 100644 --- a/dts/Bindings/clock/allwinner,sun4i-a10-ahb-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun4i-a10-ahb-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ahb-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 AHB Clock Device Tree Bindings +title: Allwinner A10 AHB Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-apb0-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-apb0-clk.yaml index b1e3d739be..e14e1aad9f 100644 --- a/dts/Bindings/clock/allwinner,sun4i-a10-apb0-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun4i-a10-apb0-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-apb0-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 APB0 Bus Clock Device Tree Bindings +title: Allwinner A10 APB0 Bus Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-apb1-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-apb1-clk.yaml index 51b7a6d4ea..8a4747ebe0 100644 --- a/dts/Bindings/clock/allwinner,sun4i-a10-apb1-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun4i-a10-apb1-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-apb1-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 APB1 Bus Clock Device Tree Bindings +title: Allwinner A10 APB1 Bus Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-axi-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-axi-clk.yaml index d801158e15..aa08dd49dd 100644 --- a/dts/Bindings/clock/allwinner,sun4i-a10-axi-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun4i-a10-axi-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-axi-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 AXI Clock Device Tree Bindings +title: Allwinner A10 AXI Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml index 15ed64d352..1690b9d99c 100644 --- a/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml +++ b/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ccu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner Clock Control Unit Device Tree Bindings +title: Allwinner Clock Control Unit maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-cpu-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-cpu-clk.yaml index 0dfafba1a1..08d073520c 100644 --- a/dts/Bindings/clock/allwinner,sun4i-a10-cpu-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun4i-a10-cpu-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-cpu-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 CPU Clock Device Tree Bindings +title: Allwinner A10 CPU Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-display-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-display-clk.yaml index 7484a7ab7d..e665e50c17 100644 --- a/dts/Bindings/clock/allwinner,sun4i-a10-display-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun4i-a10-display-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-display-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Display Clock Device Tree Bindings +title: Allwinner A10 Display Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-gates-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-gates-clk.yaml index 9a37a357cb..c4714d0fbe 100644 --- a/dts/Bindings/clock/allwinner,sun4i-a10-gates-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun4i-a10-gates-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-gates-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Bus Gates Clock Device Tree Bindings +title: Allwinner A10 Bus Gates Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-mbus-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-mbus-clk.yaml index 18f131e262..e824e33489 100644 --- a/dts/Bindings/clock/allwinner,sun4i-a10-mbus-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun4i-a10-mbus-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mbus-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 MBUS Clock Device Tree Bindings +title: Allwinner A10 MBUS Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-mmc-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-mmc-clk.yaml index 5199285a66..c612f94bef 100644 --- a/dts/Bindings/clock/allwinner,sun4i-a10-mmc-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun4i-a10-mmc-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mmc-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Module 1 Clock Device Tree Bindings +title: Allwinner A10 Module 1 Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-mod0-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-mod0-clk.yaml index 3e2abe3e67..80ae3a7a58 100644 --- a/dts/Bindings/clock/allwinner,sun4i-a10-mod0-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun4i-a10-mod0-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mod0-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Module 0 Clock Device Tree Bindings +title: Allwinner A10 Module 0 Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-mod1-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-mod1-clk.yaml index 7ddb55c75c..4f9a8d44d4 100644 --- a/dts/Bindings/clock/allwinner,sun4i-a10-mod1-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun4i-a10-mod1-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mod1-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Module 1 Clock Device Tree Bindings +title: Allwinner A10 Module 1 Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-osc-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-osc-clk.yaml index c604822cda..52a7b6e712 100644 --- a/dts/Bindings/clock/allwinner,sun4i-a10-osc-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun4i-a10-osc-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-osc-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Gatable Oscillator Clock Device Tree Bindings +title: Allwinner A10 Gatable Oscillator Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml index e5d9d45dab..b13a1f21d5 100644 --- a/dts/Bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll1-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 CPU PLL Device Tree Bindings +title: Allwinner A10 CPU PLL maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-pll3-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-pll3-clk.yaml index 4b80a42fb3..418d207d23 100644 --- a/dts/Bindings/clock/allwinner,sun4i-a10-pll3-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun4i-a10-pll3-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll3-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Video PLL Device Tree Bindings +title: Allwinner A10 Video PLL maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-pll5-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-pll5-clk.yaml index 415bd77de5..76ef3f0c7f 100644 --- a/dts/Bindings/clock/allwinner,sun4i-a10-pll5-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun4i-a10-pll5-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll5-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 DRAM PLL Device Tree Bindings +title: Allwinner A10 DRAM PLL maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-pll6-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-pll6-clk.yaml index ec5652f760..a94c93c90e 100644 --- a/dts/Bindings/clock/allwinner,sun4i-a10-pll6-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun4i-a10-pll6-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll6-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Peripheral PLL Device Tree Bindings +title: Allwinner A10 Peripheral PLL maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml index 0a335c615e..6646b2a99f 100644 --- a/dts/Bindings/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 TCON Channel 0 Clock Device Tree Bindings +title: Allwinner A10 TCON Channel 0 Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-usb-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-usb-clk.yaml index cd95d25bfe..5103b675e4 100644 --- a/dts/Bindings/clock/allwinner,sun4i-a10-usb-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun4i-a10-usb-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-usb-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 USB Clock Device Tree Bindings +title: Allwinner A10 USB Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-ve-clk.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-ve-clk.yaml index 5dfd0c1c27..80337e38d6 100644 --- a/dts/Bindings/clock/allwinner,sun4i-a10-ve-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun4i-a10-ve-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ve-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Video Engine Clock Device Tree Bindings +title: Allwinner A10 Video Engine Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun5i-a13-ahb-clk.yaml b/dts/Bindings/clock/allwinner,sun5i-a13-ahb-clk.yaml index 99add7991c..c6a6fbb686 100644 --- a/dts/Bindings/clock/allwinner,sun5i-a13-ahb-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun5i-a13-ahb-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun5i-a13-ahb-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A13 AHB Clock Device Tree Bindings +title: Allwinner A13 AHB Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun6i-a31-pll6-clk.yaml b/dts/Bindings/clock/allwinner,sun6i-a31-pll6-clk.yaml index 5f377205af..7d6a6a34d2 100644 --- a/dts/Bindings/clock/allwinner,sun6i-a31-pll6-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun6i-a31-pll6-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun6i-a31-pll6-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A31 Peripheral PLL Device Tree Bindings +title: Allwinner A31 Peripheral PLL maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun7i-a20-gmac-clk.yaml b/dts/Bindings/clock/allwinner,sun7i-a20-gmac-clk.yaml index 59e5dce1b6..b6202de357 100644 --- a/dts/Bindings/clock/allwinner,sun7i-a20-gmac-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun7i-a20-gmac-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun7i-a20-gmac-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A20 GMAC TX Clock Device Tree Bindings +title: Allwinner A20 GMAC TX Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun7i-a20-out-clk.yaml b/dts/Bindings/clock/allwinner,sun7i-a20-out-clk.yaml index c745733bcf..fde7f7dc3d 100644 --- a/dts/Bindings/clock/allwinner,sun7i-a20-out-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun7i-a20-out-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun7i-a20-out-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A20 Output Clock Device Tree Bindings +title: Allwinner A20 Output Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml b/dts/Bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml index 17caf78f0c..70369bd633 100644 --- a/dts/Bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun8i-a83t-de2-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A83t Display Engine 2/3 Clock Controller Device Tree Bindings +title: Allwinner A83t Display Engine 2/3 Clock Controller maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun8i-h3-bus-gates-clk.yaml b/dts/Bindings/clock/allwinner,sun8i-h3-bus-gates-clk.yaml index 3eb2bf65b2..45b9e2c7c1 100644 --- a/dts/Bindings/clock/allwinner,sun8i-h3-bus-gates-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun8i-h3-bus-gates-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun8i-h3-bus-gates-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Bus Gates Clock Device Tree Bindings +title: Allwinner A10 Bus Gates Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun9i-a80-ahb-clk.yaml b/dts/Bindings/clock/allwinner,sun9i-a80-ahb-clk.yaml index d178da90aa..f0f65af8ae 100644 --- a/dts/Bindings/clock/allwinner,sun9i-a80-ahb-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun9i-a80-ahb-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-ahb-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A80 AHB Clock Device Tree Bindings +title: Allwinner A80 AHB Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun9i-a80-apb0-clk.yaml b/dts/Bindings/clock/allwinner,sun9i-a80-apb0-clk.yaml index 0351c79bd2..e9f9bc8f57 100644 --- a/dts/Bindings/clock/allwinner,sun9i-a80-apb0-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun9i-a80-apb0-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-apb0-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A80 APB0 Bus Clock Device Tree Bindings +title: Allwinner A80 APB0 Bus Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun9i-a80-cpus-clk.yaml b/dts/Bindings/clock/allwinner,sun9i-a80-cpus-clk.yaml index 24d5b2f1a3..c48db2d493 100644 --- a/dts/Bindings/clock/allwinner,sun9i-a80-cpus-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun9i-a80-cpus-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-cpus-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A80 CPUS Clock Device Tree Bindings +title: Allwinner A80 CPUS Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun9i-a80-de-clks.yaml b/dts/Bindings/clock/allwinner,sun9i-a80-de-clks.yaml index a82c7c7e94..e9f81a343b 100644 --- a/dts/Bindings/clock/allwinner,sun9i-a80-de-clks.yaml +++ b/dts/Bindings/clock/allwinner,sun9i-a80-de-clks.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-de-clks.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A80 Display Engine Clock Controller Device Tree Bindings +title: Allwinner A80 Display Engine Clock Controller maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun9i-a80-gt-clk.yaml b/dts/Bindings/clock/allwinner,sun9i-a80-gt-clk.yaml index 43963c3062..d3ce5eb18d 100644 --- a/dts/Bindings/clock/allwinner,sun9i-a80-gt-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun9i-a80-gt-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-gt-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A80 GT Bus Clock Device Tree Bindings +title: Allwinner A80 GT Bus Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun9i-a80-mmc-config-clk.yaml b/dts/Bindings/clock/allwinner,sun9i-a80-mmc-config-clk.yaml index 20dc115fa2..65ee5afe83 100644 --- a/dts/Bindings/clock/allwinner,sun9i-a80-mmc-config-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun9i-a80-mmc-config-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-mmc-config-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A80 MMC Configuration Clock Device Tree Bindings +title: Allwinner A80 MMC Configuration Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun9i-a80-pll4-clk.yaml b/dts/Bindings/clock/allwinner,sun9i-a80-pll4-clk.yaml index b76bab6a30..261264a8ae 100644 --- a/dts/Bindings/clock/allwinner,sun9i-a80-pll4-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun9i-a80-pll4-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-pll4-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A80 Peripheral PLL Device Tree Bindings +title: Allwinner A80 Peripheral PLL maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun9i-a80-usb-clks.yaml b/dts/Bindings/clock/allwinner,sun9i-a80-usb-clks.yaml index 6532fb6821..515c15d5f6 100644 --- a/dts/Bindings/clock/allwinner,sun9i-a80-usb-clks.yaml +++ b/dts/Bindings/clock/allwinner,sun9i-a80-usb-clks.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-usb-clks.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A80 USB Clock Controller Device Tree Bindings +title: Allwinner A80 USB Clock Controller maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun9i-a80-usb-mod-clk.yaml b/dts/Bindings/clock/allwinner,sun9i-a80-usb-mod-clk.yaml index 15218d10e7..3f7b8d9511 100644 --- a/dts/Bindings/clock/allwinner,sun9i-a80-usb-mod-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun9i-a80-usb-mod-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-usb-mod-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A80 USB Module Clock Device Tree Bindings +title: Allwinner A80 USB Module Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/allwinner,sun9i-a80-usb-phy-clk.yaml b/dts/Bindings/clock/allwinner,sun9i-a80-usb-phy-clk.yaml index 2569041684..0d49072d47 100644 --- a/dts/Bindings/clock/allwinner,sun9i-a80-usb-phy-clk.yaml +++ b/dts/Bindings/clock/allwinner,sun9i-a80-usb-phy-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-usb-phy-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A80 USB PHY Clock Device Tree Bindings +title: Allwinner A80 USB PHY Clock maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/clock/amlogic,meson8-ddr-clkc.yaml b/dts/Bindings/clock/amlogic,meson8-ddr-clkc.yaml index 4b8669f870..d98d95d8e8 100644 --- a/dts/Bindings/clock/amlogic,meson8-ddr-clkc.yaml +++ b/dts/Bindings/clock/amlogic,meson8-ddr-clkc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Amlogic DDR Clock Controller Device Tree Bindings +title: Amlogic DDR Clock Controller maintainers: - Martin Blumenstingl <martin.blumenstingl@googlemail.com> diff --git a/dts/Bindings/clock/brcm,bcm2711-dvp.yaml b/dts/Bindings/clock/brcm,bcm2711-dvp.yaml index 08543ecbe3..2d40df2d34 100644 --- a/dts/Bindings/clock/brcm,bcm2711-dvp.yaml +++ b/dts/Bindings/clock/brcm,bcm2711-dvp.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/brcm,bcm2711-dvp.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Broadcom BCM2711 HDMI DVP Device Tree Bindings +title: Broadcom BCM2711 HDMI DVP maintainers: - Maxime Ripard <mripard@kernel.org> diff --git a/dts/Bindings/clock/canaan,k210-clk.yaml b/dts/Bindings/clock/canaan,k210-clk.yaml index 7f5cf4001f..998e5cce65 100644 --- a/dts/Bindings/clock/canaan,k210-clk.yaml +++ b/dts/Bindings/clock/canaan,k210-clk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/canaan,k210-clk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Canaan Kendryte K210 Clock Device Tree Bindings +title: Canaan Kendryte K210 Clock maintainers: - Damien Le Moal <damien.lemoal@wdc.com> diff --git a/dts/Bindings/clock/cirrus,cs2000-cp.yaml b/dts/Bindings/clock/cirrus,cs2000-cp.yaml index 0abd6ba82d..82836086ca 100644 --- a/dts/Bindings/clock/cirrus,cs2000-cp.yaml +++ b/dts/Bindings/clock/cirrus,cs2000-cp.yaml @@ -23,7 +23,6 @@ properties: clocks: description: Common clock binding for CLK_IN, XTI/REF_CLK - minItems: 2 maxItems: 2 clock-names: diff --git a/dts/Bindings/clock/gpio-gate-clock.txt b/dts/Bindings/clock/gpio-gate-clock.txt deleted file mode 100644 index d3379ff9b8..0000000000 --- a/dts/Bindings/clock/gpio-gate-clock.txt +++ /dev/null @@ -1,21 +0,0 @@ -Binding for simple gpio gated clock. - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "gpio-gate-clock". -- #clock-cells : from common clock binding; shall be set to 0. -- enable-gpios : GPIO reference for enabling and disabling the clock. - -Optional properties: -- clocks: Maximum of one parent clock is supported. - -Example: - clock { - compatible = "gpio-gate-clock"; - clocks = <&parentclk>; - #clock-cells = <0>; - enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; - }; diff --git a/dts/Bindings/clock/gpio-gate-clock.yaml b/dts/Bindings/clock/gpio-gate-clock.yaml new file mode 100644 index 0000000000..d09d0e3f0c --- /dev/null +++ b/dts/Bindings/clock/gpio-gate-clock.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/gpio-gate-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Simple GPIO clock gate + +maintainers: + - Jyri Sarha <jsarha@ti.com> + +properties: + compatible: + const: gpio-gate-clock + + clocks: + maxItems: 1 + + '#clock-cells': + const: 0 + + enable-gpios: + description: GPIO reference for enabling and disabling the clock. + maxItems: 1 + +required: + - compatible + - '#clock-cells' + - enable-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + clock { + compatible = "gpio-gate-clock"; + clocks = <&parentclk>; + #clock-cells = <0>; + enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; + }; diff --git a/dts/Bindings/clock/idt,versaclock5.yaml b/dts/Bindings/clock/idt,versaclock5.yaml index 7c331bfbe3..f9ba9864d8 100644 --- a/dts/Bindings/clock/idt,versaclock5.yaml +++ b/dts/Bindings/clock/idt,versaclock5.yaml @@ -56,6 +56,7 @@ properties: - idt,5p49v5935 - idt,5p49v6901 - idt,5p49v6965 + - idt,5p49v6975 reg: description: I2C device address @@ -108,7 +109,7 @@ patternProperties: properties: idt,mode: description: - The output drive mode. Values defined in dt-bindings/clk/versaclock.h + The output drive mode. Values defined in dt-bindings/clock/versaclock.h $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 6 @@ -134,6 +135,7 @@ allOf: enum: - idt,5p49v5933 - idt,5p49v5935 + - idt,5p49v6975 then: # Devices with builtin crystal + optional external input properties: @@ -151,7 +153,7 @@ additionalProperties: false examples: - | - #include <dt-bindings/clk/versaclock.h> + #include <dt-bindings/clock/versaclock.h> /* 25MHz reference crystal */ ref25: ref25m { diff --git a/dts/Bindings/clock/mediatek,apmixedsys.yaml b/dts/Bindings/clock/mediatek,apmixedsys.yaml index 770546195f..731bfe0408 100644 --- a/dts/Bindings/clock/mediatek,apmixedsys.yaml +++ b/dts/Bindings/clock/mediatek,apmixedsys.yaml @@ -34,6 +34,7 @@ properties: - mediatek,mt2712-apmixedsys - mediatek,mt6765-apmixedsys - mediatek,mt6779-apmixedsys + - mediatek,mt6795-apmixedsys - mediatek,mt7629-apmixedsys - mediatek,mt8167-apmixedsys - mediatek,mt8183-apmixedsys diff --git a/dts/Bindings/clock/mediatek,mt6795-clock.yaml b/dts/Bindings/clock/mediatek,mt6795-clock.yaml new file mode 100644 index 0000000000..04469eabc8 --- /dev/null +++ b/dts/Bindings/clock/mediatek,mt6795-clock.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt6795-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Functional Clock Controller for MT6795 + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + - Chun-Jie Chen <chun-jie.chen@mediatek.com> + +description: | + The clock architecture in MediaTek like below + PLLs --> + dividers --> + muxes + --> + clock gate + + The devices provide clock gate control in different IP blocks. + +properties: + compatible: + enum: + - mediatek,mt6795-mfgcfg + - mediatek,mt6795-vdecsys + - mediatek,mt6795-vencsys + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + mfgcfg: clock-controller@13000000 { + compatible = "mediatek,mt6795-mfgcfg"; + reg = <0 0x13000000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: clock-controller@16000000 { + compatible = "mediatek,mt6795-vdecsys"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: clock-controller@18000000 { + compatible = "mediatek,mt6795-vencsys"; + reg = <0 0x18000000 0 0x1000>; + #clock-cells = <1>; + }; + }; diff --git a/dts/Bindings/clock/mediatek,mt6795-sys-clock.yaml b/dts/Bindings/clock/mediatek,mt6795-sys-clock.yaml new file mode 100644 index 0000000000..378b761237 --- /dev/null +++ b/dts/Bindings/clock/mediatek,mt6795-sys-clock.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt6795-sys-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek System Clock Controller for MT6795 + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + - Chun-Jie Chen <chun-jie.chen@mediatek.com> + +description: + The Mediatek system clock controller provides various clocks and system + configuration like reset and bus protection on MT6795. + +properties: + compatible: + items: + - enum: + - mediatek,mt6795-apmixedsys + - mediatek,mt6795-infracfg + - mediatek,mt6795-pericfg + - mediatek,mt6795-topckgen + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + topckgen: clock-controller@10000000 { + compatible = "mediatek,mt6795-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + }; diff --git a/dts/Bindings/clock/mediatek,mt7621-sysc.yaml b/dts/Bindings/clock/mediatek,mt7621-sysc.yaml index 0c0b0ae5e2..b42f0f5c11 100644 --- a/dts/Bindings/clock/mediatek,mt7621-sysc.yaml +++ b/dts/Bindings/clock/mediatek,mt7621-sysc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: MT7621 Clock Device Tree Bindings +title: MT7621 Clock maintainers: - Sergio Paracuellos <sergio.paracuellos@gmail.com> diff --git a/dts/Bindings/clock/mediatek,mt8365-clock.yaml b/dts/Bindings/clock/mediatek,mt8365-clock.yaml new file mode 100644 index 0000000000..b327ecb4e5 --- /dev/null +++ b/dts/Bindings/clock/mediatek,mt8365-clock.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt8365-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Functional Clock Controller for MT8365 + +maintainers: + - Markus Schneider-Pargmann <msp@baylibre.com> + +properties: + compatible: + items: + - enum: + - mediatek,mt8365-apu + - mediatek,mt8365-imgsys + - mediatek,mt8365-mfgcfg + - mediatek,mt8365-vdecsys + - mediatek,mt8365-vencsys + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + apu: clock-controller@19020000 { + compatible = "mediatek,mt8365-apu", "syscon"; + reg = <0x19020000 0x1000>; + #clock-cells = <1>; + }; diff --git a/dts/Bindings/clock/mediatek,mt8365-sys-clock.yaml b/dts/Bindings/clock/mediatek,mt8365-sys-clock.yaml new file mode 100644 index 0000000000..643f84660c --- /dev/null +++ b/dts/Bindings/clock/mediatek,mt8365-sys-clock.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt8365-sys-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek System Clock Controller for MT8365 + +maintainers: + - Markus Schneider-Pargmann <msp@baylibre.com> + +description: + The apmixedsys module provides most of PLLs which generated from SoC 26m. + The topckgen provides dividers and muxes which provides the clock source to other IP blocks. + The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks. + +properties: + compatible: + items: + - enum: + - mediatek,mt8365-topckgen + - mediatek,mt8365-infracfg + - mediatek,mt8365-apmixedsys + - mediatek,mt8365-pericfg + - mediatek,mt8365-mcucfg + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + topckgen: clock-controller@10000000 { + compatible = "mediatek,mt8365-topckgen", "syscon"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + }; diff --git a/dts/Bindings/clock/mediatek,topckgen.yaml b/dts/Bindings/clock/mediatek,topckgen.yaml index 5b8b37a2e5..81531b5b0d 100644 --- a/dts/Bindings/clock/mediatek,topckgen.yaml +++ b/dts/Bindings/clock/mediatek,topckgen.yaml @@ -33,6 +33,7 @@ properties: - mediatek,mt2712-topckgen - mediatek,mt6765-topckgen - mediatek,mt6779-topckgen + - mediatek,mt6795-topckgen - mediatek,mt7629-topckgen - mediatek,mt7986-topckgen - mediatek,mt8167-topckgen diff --git a/dts/Bindings/clock/microchip,mpfs-ccc.yaml b/dts/Bindings/clock/microchip,mpfs-ccc.yaml new file mode 100644 index 0000000000..f177036079 --- /dev/null +++ b/dts/Bindings/clock/microchip,mpfs-ccc.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry + +maintainers: + - Conor Dooley <conor.dooley@microchip.com> + +description: | + Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of + these blocks contains two PLLs and 2 DLLs & are located in the four corners of + the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at: + https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html + +properties: + compatible: + const: microchip,mpfs-ccc + + reg: + items: + - description: PLL0's control registers + - description: PLL1's control registers + - description: DLL0's control registers + - description: DLL1's control registers + + clocks: + description: + The CCC PLL's have two input clocks. It is required that even if the input + clocks are identical that both are provided. + minItems: 2 + items: + - description: PLL0's refclk0 + - description: PLL0's refclk1 + - description: PLL1's refclk0 + - description: PLL1's refclk1 + - description: DLL0's refclk + - description: DLL1's refclk + + clock-names: + minItems: 2 + items: + - const: pll0_ref0 + - const: pll0_ref1 + - const: pll1_ref0 + - const: pll1_ref1 + - const: dll0_ref + - const: dll1_ref + + '#clock-cells': + const: 1 + description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of + PolarFire clock IDs. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@38100000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x38010000 0x1000>, <0x38020000 0x1000>, + <0x39010000 0x1000>, <0x39020000 0x1000>; + #clock-cells = <1>; + clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, + <&refclk_ccc>, <&refclk_ccc>; + clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", + "dll0_ref", "dll1_ref"; + }; diff --git a/dts/Bindings/clock/microchip,mpfs.yaml b/dts/Bindings/clock/microchip,mpfs-clkcfg.yaml index 016a4f378b..b2ce787222 100644 --- a/dts/Bindings/clock/microchip,mpfs.yaml +++ b/dts/Bindings/clock/microchip,mpfs-clkcfg.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/clock/microchip,mpfs.yaml# +$id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Microchip PolarFire Clock Control Module Binding @@ -40,8 +40,21 @@ properties: const: 1 description: | The clock consumer should specify the desired clock by having the clock - ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h - for the full list of PolarFire clock IDs. + ID in its "clocks" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of + PolarFire clock IDs. + + resets: + maxItems: 1 + + '#reset-cells': + description: + The AHB/AXI peripherals on the PolarFire SoC have reset support, so from + CLK_ENVM to CLK_CFM. The reset consumer should specify the desired + peripheral via the clock ID in its "resets" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of + PolarFire clock IDs. + const: 1 required: - compatible diff --git a/dts/Bindings/clock/qcom,a53pll.yaml b/dts/Bindings/clock/qcom,a53pll.yaml index fbd758470b..fe6ca4f68b 100644 --- a/dts/Bindings/clock/qcom,a53pll.yaml +++ b/dts/Bindings/clock/qcom,a53pll.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm A53 PLL Binding maintainers: - - Sivaprakash Murugesan <sivaprak@codeaurora.org> + - Bjorn Andersson <andersson@kernel.org> description: The A53 PLL on few Qualcomm platforms is the main CPU PLL used used for @@ -17,6 +17,7 @@ properties: compatible: enum: - qcom,ipq6018-a53pll + - qcom,ipq8074-a53pll - qcom,msm8916-a53pll - qcom,msm8939-a53pll diff --git a/dts/Bindings/clock/qcom,gcc-apq8064.yaml b/dts/Bindings/clock/qcom,gcc-apq8064.yaml index 3cf404c932..6b4efd64c1 100644 --- a/dts/Bindings/clock/qcom,gcc-apq8064.yaml +++ b/dts/Bindings/clock/qcom,gcc-apq8064.yaml @@ -38,6 +38,15 @@ properties: description: child tsens device $ref: /schemas/thermal/qcom-tsens.yaml# + clocks: + maxItems: 3 + + clock-names: + items: + - const: cxo + - const: pxo + - const: pll4 + nvmem-cells: minItems: 1 maxItems: 2 diff --git a/dts/Bindings/clock/qcom,gcc-msm8660.yaml b/dts/Bindings/clock/qcom,gcc-msm8660.yaml new file mode 100644 index 0000000000..09b2ea60d3 --- /dev/null +++ b/dts/Bindings/clock/qcom,gcc-msm8660.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8660.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for MSM8660 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module which supports the clocks and resets on + MSM8660 + + See also: + - dt-bindings/clock/qcom,gcc-msm8660.h + - dt-bindings/reset/qcom,gcc-msm8660.h + +allOf: + - $ref: "qcom,gcc.yaml#" + +properties: + compatible: + enum: + - qcom,gcc-msm8660 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: pxo + - const: cxo + +required: + - compatible + +unevaluatedProperties: false + +examples: + # Example for GCC for MSM8974: + - | + clock-controller@900000 { + compatible = "qcom,gcc-msm8660"; + reg = <0x900000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&pxo_board>, <&cxo_board>; + clock-names = "pxo", "cxo"; + }; +... diff --git a/dts/Bindings/clock/qcom,gcc-msm8909.yaml b/dts/Bindings/clock/qcom,gcc-msm8909.yaml new file mode 100644 index 0000000000..2272ea5f78 --- /dev/null +++ b/dts/Bindings/clock/qcom,gcc-msm8909.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8909.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for MSM8909 + +maintainers: + - Stephan Gerhold <stephan@gerhold.net> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on MSM8909. + + See also: + - dt-bindings/clock/qcom,gcc-msm8909.h + +properties: + compatible: + const: qcom,gcc-msm8909 + + clocks: + items: + - description: XO source + - description: Sleep clock source + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + + clock-names: + items: + - const: xo + - const: sleep_clk + - const: dsi0pll + - const: dsi0pllbyte + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-msm8909"; + reg = <0x01800000 0x80000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&xo_board>, <&sleep_clk>, <&dsi0_phy 1>, <&dsi0_phy 0>; + clock-names = "xo", "sleep_clk", "dsi0pll", "dsi0pllbyte"; + }; +... diff --git a/dts/Bindings/clock/qcom,gcc-msm8916.yaml b/dts/Bindings/clock/qcom,gcc-msm8916.yaml new file mode 100644 index 0000000000..2ceb1e501e --- /dev/null +++ b/dts/Bindings/clock/qcom,gcc-msm8916.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8916.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for MSM8916 and MSM8939 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on MSM8916 or MSM8939. + + See also: + - dt-bindings/clock/qcom,gcc-msm8916.h + - dt-bindings/clock/qcom,gcc-msm8939.h + - dt-bindings/reset/qcom,gcc-msm8916.h + - dt-bindings/reset/qcom,gcc-msm8939.h + +properties: + compatible: + enum: + - qcom,gcc-msm8916 + - qcom,gcc-msm8939 + + clocks: + items: + - description: XO source + - description: Sleep clock source + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + - description: External MCLK clock + - description: External Primary I2S clock + - description: External Secondary I2S clock + + clock-names: + items: + - const: xo + - const: sleep_clk + - const: dsi0pll + - const: dsi0pllbyte + - const: ext_mclk + - const: ext_pri_i2s + - const: ext_sec_i2s + +required: + - compatible + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + clock-controller@300000 { + compatible = "qcom,gcc-msm8916"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x300000 0x90000>; + }; +... diff --git a/dts/Bindings/clock/qcom,gcc-msm8976.yaml b/dts/Bindings/clock/qcom,gcc-msm8976.yaml index f3430b159c..4b7d695183 100644 --- a/dts/Bindings/clock/qcom,gcc-msm8976.yaml +++ b/dts/Bindings/clock/qcom,gcc-msm8976.yaml @@ -45,29 +45,16 @@ properties: description: Phandle to voltage regulator providing power to the GX domain. - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - compatible - - reg - clocks - clock-names - vdd_gfx-supply - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/clock/qcom,gcc-msm8994.yaml b/dts/Bindings/clock/qcom,gcc-msm8994.yaml index 22e67b238b..7b9fef6d9b 100644 --- a/dts/Bindings/clock/qcom,gcc-msm8994.yaml +++ b/dts/Bindings/clock/qcom,gcc-msm8994.yaml @@ -32,28 +32,15 @@ properties: - const: xo - const: sleep - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/clock/qcom,gcc-msm8996.yaml b/dts/Bindings/clock/qcom,gcc-msm8996.yaml index 005e0edd46..dfc5165db9 100644 --- a/dts/Bindings/clock/qcom,gcc-msm8996.yaml +++ b/dts/Bindings/clock/qcom,gcc-msm8996.yaml @@ -49,30 +49,13 @@ properties: - const: ufs_rx_symbol_1_clk_src - const: ufs_tx_symbol_0_clk_src - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/clock/qcom,gcc-msm8998.yaml b/dts/Bindings/clock/qcom,gcc-msm8998.yaml index 8151c0a056..544a2335cf 100644 --- a/dts/Bindings/clock/qcom,gcc-msm8998.yaml +++ b/dts/Bindings/clock/qcom,gcc-msm8998.yaml @@ -37,32 +37,15 @@ properties: - const: core_bi_pll_test_se # Optional clock minItems: 2 - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/clock/qcom,gcc-other.yaml b/dts/Bindings/clock/qcom,gcc-other.yaml index 6c78df0c46..76988e04c7 100644 --- a/dts/Bindings/clock/qcom,gcc-other.yaml +++ b/dts/Bindings/clock/qcom,gcc-other.yaml @@ -18,11 +18,7 @@ description: | - dt-bindings/clock/qcom,gcc-ipq4019.h - dt-bindings/clock/qcom,gcc-ipq6018.h - dt-bindings/reset/qcom,gcc-ipq6018.h - - dt-bindings/clock/qcom,gcc-msm8939.h - dt-bindings/clock/qcom,gcc-msm8953.h - - dt-bindings/reset/qcom,gcc-msm8939.h - - dt-bindings/clock/qcom,gcc-msm8660.h - - dt-bindings/reset/qcom,gcc-msm8660.h - dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974) - dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974) - dt-bindings/clock/qcom,gcc-mdm9607.h @@ -40,9 +36,6 @@ properties: - qcom,gcc-ipq6018 - qcom,gcc-mdm9607 - qcom,gcc-msm8226 - - qcom,gcc-msm8660 - - qcom,gcc-msm8916 - - qcom,gcc-msm8939 - qcom,gcc-msm8953 - qcom,gcc-msm8974 - qcom,gcc-msm8974pro diff --git a/dts/Bindings/clock/qcom,gcc-qcm2290.yaml b/dts/Bindings/clock/qcom,gcc-qcm2290.yaml index 5de9c82631..aec37e3f5e 100644 --- a/dts/Bindings/clock/qcom,gcc-qcm2290.yaml +++ b/dts/Bindings/clock/qcom,gcc-qcm2290.yaml @@ -30,32 +30,15 @@ properties: - const: bi_tcxo - const: sleep_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/clock/qcom,gcc-sc7180.yaml b/dts/Bindings/clock/qcom,gcc-sc7180.yaml index a404c8fbee..e4d490e65d 100644 --- a/dts/Bindings/clock/qcom,gcc-sc7180.yaml +++ b/dts/Bindings/clock/qcom,gcc-sc7180.yaml @@ -33,32 +33,15 @@ properties: - const: bi_tcxo_ao - const: sleep_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/clock/qcom,gcc-sc7280.yaml b/dts/Bindings/clock/qcom,gcc-sc7280.yaml index 5693b89975..ea61367e5a 100644 --- a/dts/Bindings/clock/qcom,gcc-sc7280.yaml +++ b/dts/Bindings/clock/qcom,gcc-sc7280.yaml @@ -44,28 +44,15 @@ properties: - const: ufs_phy_tx_symbol_0_clk - const: usb3_phy_wrapper_gcc_usb30_pipe_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/clock/qcom,gcc-sc8180x.yaml b/dts/Bindings/clock/qcom,gcc-sc8180x.yaml index f03ef96e57..30b5d1215f 100644 --- a/dts/Bindings/clock/qcom,gcc-sc8180x.yaml +++ b/dts/Bindings/clock/qcom,gcc-sc8180x.yaml @@ -32,32 +32,15 @@ properties: - const: bi_tcxo_ao - const: sleep_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/clock/qcom,gcc-sc8280xp.yaml b/dts/Bindings/clock/qcom,gcc-sc8280xp.yaml index 0bcdc69c6f..b1bf768530 100644 --- a/dts/Bindings/clock/qcom,gcc-sc8280xp.yaml +++ b/dts/Bindings/clock/qcom,gcc-sc8280xp.yaml @@ -33,7 +33,7 @@ properties: - description: Primary USB SuperSpeed pipe clock - description: USB4 PHY pipegmux clock source - description: USB4 PHY DP gmux clock source - - description: USB4 PHY sys piegmux clock source + - description: USB4 PHY sys pipegmux clock source - description: USB4 PHY PCIe pipe clock - description: USB4 PHY router max pipe clock - description: Primary USB4 RX0 clock @@ -46,7 +46,7 @@ properties: - description: Second USB4 PHY router max pipe clock - description: Secondary USB4 RX0 clock - description: Secondary USB4 RX1 clock - - description: Multiport USB first SupserSpeed pipe clock + - description: Multiport USB first SuperSpeed pipe clock - description: Multiport USB second SuperSpeed pipe clock - description: PCIe 2a pipe clock - description: PCIe 2b pipe clock @@ -56,30 +56,17 @@ properties: - description: First EMAC controller reference clock - description: Second EMAC controller reference clock - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - protected-clocks: maxItems: 389 required: - compatible - clocks - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/clock/qcom,gcc-sdm845.yaml b/dts/Bindings/clock/qcom,gcc-sdm845.yaml index daf7906ebc..e169d46c78 100644 --- a/dts/Bindings/clock/qcom,gcc-sdm845.yaml +++ b/dts/Bindings/clock/qcom,gcc-sdm845.yaml @@ -19,51 +19,67 @@ description: | properties: compatible: - const: qcom,gcc-sdm845 + enum: + - qcom,gcc-sdm670 + - qcom,gcc-sdm845 clocks: - items: - - description: Board XO source - - description: Board active XO source - - description: Sleep clock source - - description: PCIE 0 Pipe clock source - - description: PCIE 1 Pipe clock source + minItems: 3 + maxItems: 5 clock-names: - items: - - const: bi_tcxo - - const: bi_tcxo_ao - - const: sleep_clk - - const: pcie_0_pipe_clk - - const: pcie_1_pipe_clk - - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 + minItems: 3 + maxItems: 5 power-domains: maxItems: 1 - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + - if: + properties: + compatible: + contains: + const: qcom,gcc-sdm670 + then: + properties: + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + + - if: + properties: + compatible: + contains: + const: qcom,gcc-sdm845 + then: + properties: + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source + - description: PCIE 1 Pipe clock source + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + - const: pcie_0_pipe_clk + - const: pcie_1_pipe_clk + +unevaluatedProperties: false examples: # Example for GCC for SDM845: diff --git a/dts/Bindings/clock/qcom,gcc-sdx55.yaml b/dts/Bindings/clock/qcom,gcc-sdx55.yaml index b0d1c65aa3..13ffa16e08 100644 --- a/dts/Bindings/clock/qcom,gcc-sdx55.yaml +++ b/dts/Bindings/clock/qcom,gcc-sdx55.yaml @@ -35,28 +35,15 @@ properties: - const: core_bi_pll_test_se # Optional clock minItems: 2 - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/clock/qcom,gcc-sdx65.yaml b/dts/Bindings/clock/qcom,gcc-sdx65.yaml index 16c4cdc7b4..8a1419c4d4 100644 --- a/dts/Bindings/clock/qcom,gcc-sdx65.yaml +++ b/dts/Bindings/clock/qcom,gcc-sdx65.yaml @@ -20,9 +20,6 @@ properties: compatible: const: qcom,gcc-sdx65 - reg: - maxItems: 1 - clocks: items: - description: Board XO source @@ -43,25 +40,15 @@ properties: - const: core_bi_pll_test_se # Optional clock minItems: 5 - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - required: - compatible - - reg - clocks - clock-names - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/clock/qcom,gcc-sm6115.yaml b/dts/Bindings/clock/qcom,gcc-sm6115.yaml index 26050da844..bb81a27a1b 100644 --- a/dts/Bindings/clock/qcom,gcc-sm6115.yaml +++ b/dts/Bindings/clock/qcom,gcc-sm6115.yaml @@ -30,32 +30,15 @@ properties: - const: bi_tcxo - const: sleep_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/clock/qcom,gcc-sm6125.yaml b/dts/Bindings/clock/qcom,gcc-sm6125.yaml index ab12b391ef..03e84e1581 100644 --- a/dts/Bindings/clock/qcom,gcc-sm6125.yaml +++ b/dts/Bindings/clock/qcom,gcc-sm6125.yaml @@ -30,32 +30,15 @@ properties: - const: bi_tcxo - const: sleep_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/clock/qcom,gcc-sm6350.yaml b/dts/Bindings/clock/qcom,gcc-sm6350.yaml index 20926cd829..cbe98c01c0 100644 --- a/dts/Bindings/clock/qcom,gcc-sm6350.yaml +++ b/dts/Bindings/clock/qcom,gcc-sm6350.yaml @@ -32,32 +32,15 @@ properties: - const: bi_tcxo_ao - const: sleep_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/clock/qcom,gcc-sm8150.yaml b/dts/Bindings/clock/qcom,gcc-sm8150.yaml index 12766a8666..0333ccb07d 100644 --- a/dts/Bindings/clock/qcom,gcc-sm8150.yaml +++ b/dts/Bindings/clock/qcom,gcc-sm8150.yaml @@ -31,32 +31,15 @@ properties: - const: bi_tcxo - const: sleep_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/clock/qcom,gcc-sm8250.yaml b/dts/Bindings/clock/qcom,gcc-sm8250.yaml index 80bd6caf5b..4e2a9cac0a 100644 --- a/dts/Bindings/clock/qcom,gcc-sm8250.yaml +++ b/dts/Bindings/clock/qcom,gcc-sm8250.yaml @@ -31,32 +31,15 @@ properties: - const: bi_tcxo - const: sleep_clk - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/clock/qcom,gcc-sm8350.yaml b/dts/Bindings/clock/qcom,gcc-sm8350.yaml index 1122700dcc..3edbeca70a 100644 --- a/dts/Bindings/clock/qcom,gcc-sm8350.yaml +++ b/dts/Bindings/clock/qcom,gcc-sm8350.yaml @@ -54,28 +54,15 @@ properties: - const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock minItems: 2 - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - compatible - clocks - clock-names - - reg - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/clock/qcom,gcc-sm8450.yaml b/dts/Bindings/clock/qcom,gcc-sm8450.yaml index 58d98a766d..102ce6862e 100644 --- a/dts/Bindings/clock/qcom,gcc-sm8450.yaml +++ b/dts/Bindings/clock/qcom,gcc-sm8450.yaml @@ -46,28 +46,15 @@ properties: - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock minItems: 2 - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - required: - compatible - - reg - clocks - clock-names - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/clock/qcom,gpucc.yaml b/dts/Bindings/clock/qcom,gpucc.yaml index 9ebcb1943b..a7d0af1bd9 100644 --- a/dts/Bindings/clock/qcom,gpucc.yaml +++ b/dts/Bindings/clock/qcom,gpucc.yaml @@ -17,6 +17,7 @@ description: | dt-bindings/clock/qcom,gpucc-sdm845.h dt-bindings/clock/qcom,gpucc-sc7180.h dt-bindings/clock/qcom,gpucc-sc7280.h + dt-bindings/clock/qcom,gpucc-sc8280xp.h dt-bindings/clock/qcom,gpucc-sm6350.h dt-bindings/clock/qcom,gpucc-sm8150.h dt-bindings/clock/qcom,gpucc-sm8250.h @@ -28,6 +29,7 @@ properties: - qcom,sc7180-gpucc - qcom,sc7280-gpucc - qcom,sc8180x-gpucc + - qcom,sc8280xp-gpucc - qcom,sm6350-gpucc - qcom,sm8150-gpucc - qcom,sm8250-gpucc diff --git a/dts/Bindings/clock/qcom,mmcc.yaml b/dts/Bindings/clock/qcom,mmcc.yaml index 32e87014bb..03faab5b6a 100644 --- a/dts/Bindings/clock/qcom,mmcc.yaml +++ b/dts/Bindings/clock/qcom,mmcc.yaml @@ -31,30 +31,12 @@ properties: - qcom,mmcc-sdm660 clocks: - items: - - description: Board XO source - - description: Board sleep source - - description: Global PLL 0 clock - - description: DSI phy instance 0 dsi clock - - description: DSI phy instance 0 byte clock - - description: DSI phy instance 1 dsi clock - - description: DSI phy instance 1 byte clock - - description: HDMI phy PLL clock - - description: DisplayPort phy PLL vco clock - - description: DisplayPort phy PLL link clock + minItems: 8 + maxItems: 10 clock-names: - items: - - const: xo - - const: sleep - - const: gpll0 - - const: dsi0dsi - - const: dsi0byte - - const: dsi1dsi - - const: dsi1byte - - const: hdmipll - - const: dpvco - - const: dplink + minItems: 8 + maxItems: 10 '#clock-cells': const: 1 @@ -85,16 +67,179 @@ required: additionalProperties: false -if: - properties: - compatible: - contains: - const: qcom,mmcc-msm8998 - -then: - required: - - clocks - - clock-names +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,mmcc-apq8064 + - qcom,mmcc-msm8960 + then: + properties: + clocks: + items: + - description: Board PXO source + - description: PLL 3 clock + - description: PLL 3 Vote clock + - description: DSI phy instance 1 dsi clock + - description: DSI phy instance 1 byte clock + - description: DSI phy instance 2 dsi clock + - description: DSI phy instance 2 byte clock + - description: HDMI phy PLL clock + + clock-names: + items: + - const: pxo + - const: pll3 + - const: pll8_vote + - const: dsi1pll + - const: dsi1pllbyte + - const: dsi2pll + - const: dsi2pllbyte + - const: hdmipll + + - if: + properties: + compatible: + contains: + enum: + - qcom,mmcc-msm8994 + - qcom,mmcc-msm8998 + - qcom,mmcc-sdm630 + - qcom,mmcc-sdm660 + then: + required: + - clocks + - clock-names + + - if: + properties: + compatible: + contains: + const: qcom,mmcc-msm8994 + then: + properties: + clocks: + items: + - description: Board XO source + - description: Global PLL 0 clock + - description: MMSS NoC AHB clock + - description: GFX3D clock + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + - description: DSI phy instance 1 dsi clock + - description: DSI phy instance 1 byte clock + - description: HDMI phy PLL clock + + clock-names: + items: + - const: xo + - const: gpll0 + - const: mmssnoc_ahb + - const: oxili_gfx3d_clk_src + - const: dsi0pll + - const: dsi0pllbyte + - const: dsi1pll + - const: dsi1pllbyte + - const: hdmipll + + - if: + properties: + compatible: + contains: + const: qcom,mmcc-msm8996 + then: + properties: + clocks: + items: + - description: Board XO source + - description: Global PLL 0 clock + - description: MMSS NoC AHB clock + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + - description: DSI phy instance 1 dsi clock + - description: DSI phy instance 1 byte clock + - description: HDMI phy PLL clock + + clock-names: + items: + - const: xo + - const: gpll0 + - const: gcc_mmss_noc_cfg_ahb_clk + - const: dsi0pll + - const: dsi0pllbyte + - const: dsi1pll + - const: dsi1pllbyte + - const: hdmipll + + - if: + properties: + compatible: + contains: + const: qcom,mmcc-msm8998 + then: + properties: + clocks: + items: + - description: Board XO source + - description: Global PLL 0 clock + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + - description: DSI phy instance 1 dsi clock + - description: DSI phy instance 1 byte clock + - description: HDMI phy PLL clock + - description: DisplayPort phy PLL link clock + - description: DisplayPort phy PLL vco clock + - description: Test clock + + clock-names: + items: + - const: xo + - const: gpll0 + - const: dsi0dsi + - const: dsi0byte + - const: dsi1dsi + - const: dsi1byte + - const: hdmipll + - const: dplink + - const: dpvco + - const: core_bi_pll_test_se + + - if: + properties: + compatible: + contains: + enum: + - qcom,mmcc-sdm630 + - qcom,mmcc-sdm660 + then: + properties: + clocks: + items: + - description: Board XO source + - description: Board sleep source + - description: Global PLL 0 clock + - description: Global PLL 0 DIV clock + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + - description: DSI phy instance 1 dsi clock + - description: DSI phy instance 1 byte clock + - description: DisplayPort phy PLL link clock + - description: DisplayPort phy PLL vco clock + + clock-names: + items: + - const: xo + - const: sleep_clk + - const: gpll0 + - const: gpll0_div + - const: dsi0pll + - const: dsi0pllbyte + - const: dsi1pll + - const: dsi1pllbyte + - const: dp_link_2x_clk_divsel_five + - const: dp_vco_divided_clk_src_mux examples: # Example for MMCC for MSM8960: diff --git a/dts/Bindings/clock/qcom,msm8996-apcc.yaml b/dts/Bindings/clock/qcom,msm8996-apcc.yaml index a20cb10636..c4971234fe 100644 --- a/dts/Bindings/clock/qcom,msm8996-apcc.yaml +++ b/dts/Bindings/clock/qcom,msm8996-apcc.yaml @@ -26,22 +26,18 @@ properties: clocks: items: - - description: Primary PLL clock for power cluster (little) - - description: Primary PLL clock for perf cluster (big) - - description: Alternate PLL clock for power cluster (little) - - description: Alternate PLL clock for perf cluster (big) + - description: XO source clock-names: items: - - const: pwrcl_pll - - const: perfcl_pll - - const: pwrcl_alt_pll - - const: perfcl_alt_pll + - const: xo required: - compatible - reg - '#clock-cells' + - clocks + - clock-names additionalProperties: false @@ -51,4 +47,7 @@ examples: compatible = "qcom,msm8996-apcc"; reg = <0x6400000 0x90000>; #clock-cells = <1>; + + clocks = <&xo_board>; + clock-names = "xo"; }; diff --git a/dts/Bindings/clock/qcom,rpmcc.yaml b/dts/Bindings/clock/qcom,rpmcc.yaml index d63b45ad06..2a95bf8664 100644 --- a/dts/Bindings/clock/qcom,rpmcc.yaml +++ b/dts/Bindings/clock/qcom,rpmcc.yaml @@ -29,6 +29,7 @@ properties: - qcom,rpmcc-mdm9607 - qcom,rpmcc-msm8226 - qcom,rpmcc-msm8660 + - qcom,rpmcc-msm8909 - qcom,rpmcc-msm8916 - qcom,rpmcc-msm8936 - qcom,rpmcc-msm8953 @@ -43,6 +44,7 @@ properties: - qcom,rpmcc-sdm660 - qcom,rpmcc-sm6115 - qcom,rpmcc-sm6125 + - qcom,rpmcc-sm6375 - const: qcom,rpmcc '#clock-cells': diff --git a/dts/Bindings/clock/qcom,rpmhcc.yaml b/dts/Bindings/clock/qcom,rpmhcc.yaml index 8fcaf418f8..437a34b930 100644 --- a/dts/Bindings/clock/qcom,rpmhcc.yaml +++ b/dts/Bindings/clock/qcom,rpmhcc.yaml @@ -21,6 +21,7 @@ properties: - qcom,sc7280-rpmh-clk - qcom,sc8180x-rpmh-clk - qcom,sc8280xp-rpmh-clk + - qcom,sdm670-rpmh-clk - qcom,sdm845-rpmh-clk - qcom,sdx55-rpmh-clk - qcom,sdx65-rpmh-clk diff --git a/dts/Bindings/clock/qcom,sc7280-lpasscc.yaml b/dts/Bindings/clock/qcom,sc7280-lpasscc.yaml index 47028d7b98..633887dc2f 100644 --- a/dts/Bindings/clock/qcom,sc7280-lpasscc.yaml +++ b/dts/Bindings/clock/qcom,sc7280-lpasscc.yaml @@ -36,13 +36,11 @@ properties: items: - description: LPASS qdsp6ss register - description: LPASS top-cc register - - description: LPASS cc register reg-names: items: - const: qdsp6ss - const: top_cc - - const: cc required: - compatible @@ -59,8 +57,8 @@ examples: #include <dt-bindings/clock/qcom,lpass-sc7280.h> clock-controller@3000000 { compatible = "qcom,sc7280-lpasscc"; - reg = <0x03000000 0x40>, <0x03c04000 0x4>, <0x03389000 0x24>; - reg-names = "qdsp6ss", "top_cc", "cc"; + reg = <0x03000000 0x40>, <0x03c04000 0x4>; + reg-names = "qdsp6ss", "top_cc"; clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; clock-names = "iface"; #clock-cells = <1>; diff --git a/dts/Bindings/clock/qcom,sc7280-lpasscorecc.yaml b/dts/Bindings/clock/qcom,sc7280-lpasscorecc.yaml index bad9135489..f50e284e5f 100644 --- a/dts/Bindings/clock/qcom,sc7280-lpasscorecc.yaml +++ b/dts/Bindings/clock/qcom,sc7280-lpasscorecc.yaml @@ -22,6 +22,8 @@ properties: clock-names: true + reg: true + compatible: enum: - qcom,sc7280-lpassaoncc @@ -38,8 +40,14 @@ properties: '#power-domain-cells': const: 1 - reg: - maxItems: 1 + '#reset-cells': + const: 1 + + qcom,adsp-pil-mode: + description: + Indicates if the LPASS would be brought out of reset using + peripheral loader. + type: boolean required: - compatible @@ -69,6 +77,11 @@ allOf: items: - const: bi_tcxo - const: lpass_aon_cc_main_rcg_clk_src + + reg: + items: + - description: lpass core cc register + - description: lpass audio csr register - if: properties: compatible: @@ -90,6 +103,8 @@ allOf: - const: bi_tcxo_ao - const: iface + reg: + maxItems: 1 - if: properties: compatible: @@ -108,6 +123,8 @@ allOf: items: - const: bi_tcxo + reg: + maxItems: 1 examples: - | #include <dt-bindings/clock/qcom,rpmh.h> @@ -116,13 +133,15 @@ examples: #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> lpass_audiocc: clock-controller@3300000 { compatible = "qcom,sc7280-lpassaudiocc"; - reg = <0x3300000 0x30000>; + reg = <0x3300000 0x30000>, + <0x32a9000 0x1000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; #clock-cells = <1>; #power-domain-cells = <1>; + #reset-cells = <1>; }; - | @@ -165,6 +184,7 @@ examples: clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&lpasscore LPASS_CORE_CC_CORE_CLK>; clock-names = "bi_tcxo", "bi_tcxo_ao","iface"; + qcom,adsp-pil-mode; #clock-cells = <1>; #power-domain-cells = <1>; }; diff --git a/dts/Bindings/clock/qcom,sm6115-dispcc.yaml b/dts/Bindings/clock/qcom,sm6115-dispcc.yaml new file mode 100644 index 0000000000..6660ff16ad --- /dev/null +++ b/dts/Bindings/clock/qcom,sm6115-dispcc.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6115-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock Controller for SM6115 + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: | + Qualcomm display clock control module which supports the clocks and + power domains on SM6115. + + See also: + include/dt-bindings/clock/qcom,sm6115-dispcc.h + +properties: + compatible: + enum: + - qcom,sm6115-dispcc + + clocks: + items: + - description: Board XO source + - description: Board sleep clock + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: GPLL0 DISP DIV clock from GCC + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/clock/qcom,gcc-sm6115.h> + clock-controller@5f00000 { + compatible = "qcom,sm6115-dispcc"; + reg = <0x5f00000 0x20000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/dts/Bindings/clock/qcom,sm6375-gcc.yaml b/dts/Bindings/clock/qcom,sm6375-gcc.yaml new file mode 100644 index 0000000000..3c573e1a12 --- /dev/null +++ b/dts/Bindings/clock/qcom,sm6375-gcc.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6375-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for SM6375 + +maintainers: + - Konrad Dybcio <konrad.dybcio@somainline.org> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on SM6375 + + See also: + - dt-bindings/clock/qcom,sm6375-gcc.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,sm6375-gcc + + clocks: + items: + - description: Board XO source + - description: Board XO Active-Only source + - description: Sleep clock source + +required: + - compatible + - clocks + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + clock-controller@1400000 { + compatible = "qcom,sm6375-gcc"; + reg = <0x01400000 0x1f0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&sleep_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/dts/Bindings/clock/qcom,sm8450-dispcc.yaml b/dts/Bindings/clock/qcom,sm8450-dispcc.yaml new file mode 100644 index 0000000000..1cc2457f82 --- /dev/null +++ b/dts/Bindings/clock/qcom,sm8450-dispcc.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8450-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller for SM8450 + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +description: | + Qualcomm display clock control module which supports the clocks, resets and + power domains on SM8450. + + See also: + include/dt-bindings/clock/qcom,sm8450-dispcc.h + +properties: + compatible: + enum: + - qcom,sm8450-dispcc + + clocks: + minItems: 3 + items: + - description: Board XO source + - description: Board Always On XO source + - description: Display's AHB clock + - description: sleep clock + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY1 + - description: Pixel clock from DSI PHY1 + - description: Link clock from DP PHY0 + - description: VCO DIV clock from DP PHY0 + - description: Link clock from DP PHY1 + - description: VCO DIV clock from DP PHY1 + - description: Link clock from DP PHY2 + - description: VCO DIV clock from DP PHY2 + - description: Link clock from DP PHY3 + - description: VCO DIV clock from DP PHY3 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sm8450.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + clock-controller@af00000 { + compatible = "qcom,sm8450-dispcc"; + reg = <0x0af00000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + power-domains = <&rpmhpd SM8450_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + }; +... diff --git a/dts/Bindings/clock/renesas,rcar-usb2-clock-sel.yaml b/dts/Bindings/clock/renesas,rcar-usb2-clock-sel.yaml index 6eaabb4d82..81f09df714 100644 --- a/dts/Bindings/clock/renesas,rcar-usb2-clock-sel.yaml +++ b/dts/Bindings/clock/renesas,rcar-usb2-clock-sel.yaml @@ -47,7 +47,6 @@ properties: maxItems: 1 clocks: - minItems: 4 maxItems: 4 clock-names: @@ -64,7 +63,6 @@ properties: maxItems: 1 resets: - minItems: 2 maxItems: 2 reset-names: diff --git a/dts/Bindings/clock/renesas,rzg2l-cpg.yaml b/dts/Bindings/clock/renesas,rzg2l-cpg.yaml index d036675e07..487f74cdc7 100644 --- a/dts/Bindings/clock/renesas,rzg2l-cpg.yaml +++ b/dts/Bindings/clock/renesas,rzg2l-cpg.yaml @@ -24,7 +24,7 @@ description: | properties: compatible: enum: - - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} + - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five - renesas,r9a07g044-cpg # RZ/G2{L,LC} - renesas,r9a07g054-cpg # RZ/V2L - renesas,r9a09g011-cpg # RZ/V2M diff --git a/dts/Bindings/clock/renesas,versaclock7.yaml b/dts/Bindings/clock/renesas,versaclock7.yaml new file mode 100644 index 0000000000..8d4eb4475f --- /dev/null +++ b/dts/Bindings/clock/renesas,versaclock7.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,versaclock7.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Versaclock7 Programmable Clock Device Tree Bindings + +maintainers: + - Alex Helms <alexander.helms.jy@renesas.com> + +description: | + Renesas Versaclock7 is a family of configurable clock generator and + jitter attenuator ICs with fractional and integer dividers. + +properties: + '#clock-cells': + const: 1 + + compatible: + enum: + - renesas,rc21008a + + reg: + maxItems: 1 + + clocks: + items: + - description: External crystal or oscillator + + clock-names: + items: + - const: xin + +required: + - '#clock-cells' + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + vc7_xin: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <49152000>; + }; + + i2c@0 { + reg = <0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + + vc7: clock-controller@9 { + compatible = "renesas,rc21008a"; + reg = <0x9>; + #clock-cells = <1>; + clocks = <&vc7_xin>; + clock-names = "xin"; + }; + }; diff --git a/dts/Bindings/clock/rockchip,px30-cru.yaml b/dts/Bindings/clock/rockchip,px30-cru.yaml index 3eec381c7c..0f0f64b6f8 100644 --- a/dts/Bindings/clock/rockchip,px30-cru.yaml +++ b/dts/Bindings/clock/rockchip,px30-cru.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/rockchip,px30-cru.yaml# diff --git a/dts/Bindings/clock/rockchip,rk3036-cru.yaml b/dts/Bindings/clock/rockchip,rk3036-cru.yaml index 1376230fed..ba5b454643 100644 --- a/dts/Bindings/clock/rockchip,rk3036-cru.yaml +++ b/dts/Bindings/clock/rockchip,rk3036-cru.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/rockchip,rk3036-cru.yaml# diff --git a/dts/Bindings/clock/rockchip,rk3128-cru.txt b/dts/Bindings/clock/rockchip,rk3128-cru.txt deleted file mode 100644 index 6f8744fd30..0000000000 --- a/dts/Bindings/clock/rockchip,rk3128-cru.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Rockchip RK3126/RK3128 Clock and Reset Unit - -The RK3126/RK3128 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3126-cru" or "rockchip,rk3128-cru" - "rockchip,rk3126-cru" - controller compatible with RK3126 SoC. - "rockchip,rk3128-cru" - controller compatible with RK3128 SoC. -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "ext_i2s" - external I2S clock - optional, - - "gmac_clkin" - external GMAC clock - optional - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3128-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart2: serial@20068000 { - compatible = "rockchip,serial"; - reg = <0x20068000 0x100>; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "sclk_uart", "pclk_uart"; - }; diff --git a/dts/Bindings/clock/rockchip,rk3128-cru.yaml b/dts/Bindings/clock/rockchip,rk3128-cru.yaml new file mode 100644 index 0000000000..b3d9c8eca9 --- /dev/null +++ b/dts/Bindings/clock/rockchip,rk3128-cru.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3128-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3126/RK3128 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The RK3126/RK3128 clock controller generates and supplies clock to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + +properties: + compatible: + enum: + - rockchip,rk3126-cru + - rockchip,rk3128-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + minItems: 1 + items: + - const: xin24m + - enum: + - ext_i2s + - gmac_clkin + - enum: + - ext_i2s + - gmac_clkin + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@20000000 { + compatible = "rockchip,rk3128-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/dts/Bindings/clock/rockchip,rk3228-cru.yaml b/dts/Bindings/clock/rockchip,rk3228-cru.yaml index cf7dc01d94..1050fff72a 100644 --- a/dts/Bindings/clock/rockchip,rk3228-cru.yaml +++ b/dts/Bindings/clock/rockchip,rk3228-cru.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/rockchip,rk3228-cru.yaml# diff --git a/dts/Bindings/clock/rockchip,rk3288-cru.yaml b/dts/Bindings/clock/rockchip,rk3288-cru.yaml index 96bc05749e..6655e97d52 100644 --- a/dts/Bindings/clock/rockchip,rk3288-cru.yaml +++ b/dts/Bindings/clock/rockchip,rk3288-cru.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/rockchip,rk3288-cru.yaml# diff --git a/dts/Bindings/clock/rockchip,rk3308-cru.yaml b/dts/Bindings/clock/rockchip,rk3308-cru.yaml index 523ee578a5..fec37f5b80 100644 --- a/dts/Bindings/clock/rockchip,rk3308-cru.yaml +++ b/dts/Bindings/clock/rockchip,rk3308-cru.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/rockchip,rk3308-cru.yaml# diff --git a/dts/Bindings/clock/rockchip,rk3368-cru.yaml b/dts/Bindings/clock/rockchip,rk3368-cru.yaml index adb6787772..90af242b41 100644 --- a/dts/Bindings/clock/rockchip,rk3368-cru.yaml +++ b/dts/Bindings/clock/rockchip,rk3368-cru.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/rockchip,rk3368-cru.yaml# diff --git a/dts/Bindings/clock/rockchip,rk3399-cru.yaml b/dts/Bindings/clock/rockchip,rk3399-cru.yaml index 54da1e31ea..0b758e015e 100644 --- a/dts/Bindings/clock/rockchip,rk3399-cru.yaml +++ b/dts/Bindings/clock/rockchip,rk3399-cru.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0-only +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/rockchip,rk3399-cru.yaml# diff --git a/dts/Bindings/clock/rockchip,rv1108-cru.yaml b/dts/Bindings/clock/rockchip,rv1108-cru.yaml index 20421c22f1..4611d920b8 100644 --- a/dts/Bindings/clock/rockchip,rv1108-cru.yaml +++ b/dts/Bindings/clock/rockchip,rv1108-cru.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/rockchip,rv1108-cru.yaml# diff --git a/dts/Bindings/clock/rockchip,rv1126-cru.yaml b/dts/Bindings/clock/rockchip,rv1126-cru.yaml new file mode 100644 index 0000000000..0998f8b922 --- /dev/null +++ b/dts/Bindings/clock/rockchip,rv1126-cru.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rv1126-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RV1126 Clock and Reset Unit + +maintainers: + - Jagan Teki <jagan@edgeble.ai> + - Finley Xiao <finley.xiao@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: + The RV1126 clock controller generates the clock and also implements a + reset controller for SoC peripherals. + +properties: + compatible: + enum: + - rockchip,rv1126-cru + - rockchip,rv1126-pmucru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@ff490000 { + compatible = "rockchip,rv1126-cru"; + reg = <0xff490000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/dts/Bindings/clock/samsung,exynos850-clock.yaml b/dts/Bindings/clock/samsung,exynos850-clock.yaml index aa11815ad3..141cf173f8 100644 --- a/dts/Bindings/clock/samsung,exynos850-clock.yaml +++ b/dts/Bindings/clock/samsung,exynos850-clock.yaml @@ -33,10 +33,13 @@ properties: enum: - samsung,exynos850-cmu-top - samsung,exynos850-cmu-apm + - samsung,exynos850-cmu-aud - samsung,exynos850-cmu-cmgp - samsung,exynos850-cmu-core - samsung,exynos850-cmu-dpu - samsung,exynos850-cmu-hsi + - samsung,exynos850-cmu-is + - samsung,exynos850-cmu-mfcmscl - samsung,exynos850-cmu-peri clocks: @@ -92,6 +95,24 @@ allOf: properties: compatible: contains: + const: samsung,exynos850-cmu-aud + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: AUD clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_aud + + - if: + properties: + compatible: + contains: const: samsung,exynos850-cmu-cmgp then: @@ -176,6 +197,54 @@ allOf: properties: compatible: contains: + const: samsung,exynos850-cmu-is + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_IS bus clock (from CMU_TOP) + - description: Image Texture Processing core clock (from CMU_TOP) + - description: Visual Recognition Accelerator clock (from CMU_TOP) + - description: Geometric Distortion Correction clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_is_bus + - const: dout_is_itp + - const: dout_is_vra + - const: dout_is_gdc + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-mfcmscl + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: Multi-Format Codec clock (from CMU_TOP) + - description: Memory to Memory Scaler clock (from CMU_TOP) + - description: Multi-Channel Scaler clock (from CMU_TOP) + - description: JPEG codec clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_mfcmscl_mfc + - const: dout_mfcmscl_m2m + - const: dout_mfcmscl_mcsc + - const: dout_mfcmscl_jpeg + + - if: + properties: + compatible: + contains: const: samsung,exynos850-cmu-peri then: diff --git a/dts/Bindings/clock/samsung,exynosautov9-clock.yaml b/dts/Bindings/clock/samsung,exynosautov9-clock.yaml index eafc715d2d..2ab4642679 100644 --- a/dts/Bindings/clock/samsung,exynosautov9-clock.yaml +++ b/dts/Bindings/clock/samsung,exynosautov9-clock.yaml @@ -35,6 +35,8 @@ properties: - samsung,exynosautov9-cmu-top - samsung,exynosautov9-cmu-busmc - samsung,exynosautov9-cmu-core + - samsung,exynosautov9-cmu-fsys0 + - samsung,exynosautov9-cmu-fsys1 - samsung,exynosautov9-cmu-fsys2 - samsung,exynosautov9-cmu-peric0 - samsung,exynosautov9-cmu-peric1 @@ -111,6 +113,48 @@ allOf: properties: compatible: contains: + const: samsung,exynosautov9-cmu-fsys0 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_FSYS0 bus clock (from CMU_TOP) + - description: CMU_FSYS0 pcie clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_fsys0_bus + - const: dout_clkcmu_fsys0_pcie + + - if: + properties: + compatible: + contains: + const: samsung,exynosautov9-cmu-fsys1 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_FSYS1 bus clock (from CMU_TOP) + - description: CMU_FSYS1 mmc card clock (from CMU_TOP) + - description: CMU_FSYS1 usb clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_fsys1_bus + - const: dout_clkcmu_fsys1_mmc_card + - const: dout_clkcmu_fsys1_usbdrd + + - if: + properties: + compatible: + contains: const: samsung,exynosautov9-cmu-fsys2 then: diff --git a/dts/Bindings/clock/samsung,s2mps11.yaml b/dts/Bindings/clock/samsung,s2mps11.yaml index 9248bfc16d..d5296e6053 100644 --- a/dts/Bindings/clock/samsung,s2mps11.yaml +++ b/dts/Bindings/clock/samsung,s2mps11.yaml @@ -34,7 +34,6 @@ properties: const: 1 clock-output-names: - minItems: 3 maxItems: 3 description: Names for AP, CP and BT clocks. diff --git a/dts/Bindings/clock/sprd,sc9863a-clk.yaml b/dts/Bindings/clock/sprd,sc9863a-clk.yaml index 47e1ab08c9..785a12797a 100644 --- a/dts/Bindings/clock/sprd,sc9863a-clk.yaml +++ b/dts/Bindings/clock/sprd,sc9863a-clk.yaml @@ -5,7 +5,7 @@ $id: "http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: SC9863A Clock Control Unit Device Tree Bindings +title: SC9863A Clock Control Unit maintainers: - Orson Zhai <orsonzhai@gmail.com> diff --git a/dts/Bindings/clock/ti/gate.txt b/dts/Bindings/clock/ti/gate.txt index b4820b1de4..4982615c01 100644 --- a/dts/Bindings/clock/ti/gate.txt +++ b/dts/Bindings/clock/ti/gate.txt @@ -10,7 +10,7 @@ will be controlled instead and the corresponding hw-ops for that is used. [1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.txt +[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml [3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt Required properties: diff --git a/dts/Bindings/clock/ti/interface.txt b/dts/Bindings/clock/ti/interface.txt index 94ec77dc3c..d3eb5ca92a 100644 --- a/dts/Bindings/clock/ti/interface.txt +++ b/dts/Bindings/clock/ti/interface.txt @@ -9,7 +9,7 @@ companion clock finding (match corresponding functional gate clock) and hardware autoidle enable / disable. [1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.txt +[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml Required properties: - compatible : shall be one of: diff --git a/dts/Bindings/clock/toshiba,tmpv770x-pipllct.yaml b/dts/Bindings/clock/toshiba,tmpv770x-pipllct.yaml index 7b7300ce96..d36558aa39 100644 --- a/dts/Bindings/clock/toshiba,tmpv770x-pipllct.yaml +++ b/dts/Bindings/clock/toshiba,tmpv770x-pipllct.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pipllct.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Toshiba Visconti5 TMPV770X PLL Controller Device Tree Bindings +title: Toshiba Visconti5 TMPV770X PLL Controller maintainers: - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> diff --git a/dts/Bindings/clock/toshiba,tmpv770x-pismu.yaml b/dts/Bindings/clock/toshiba,tmpv770x-pismu.yaml index ed79f16fe6..081f85b1eb 100644 --- a/dts/Bindings/clock/toshiba,tmpv770x-pismu.yaml +++ b/dts/Bindings/clock/toshiba,tmpv770x-pismu.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pismu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Toshiba Visconti5 TMPV770x SMU controller Device Tree Bindings +title: Toshiba Visconti5 TMPV770x SMU controller maintainers: - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> diff --git a/dts/Bindings/clock/xlnx,clocking-wizard.yaml b/dts/Bindings/clock/xlnx,clocking-wizard.yaml new file mode 100644 index 0000000000..634b7b9646 --- /dev/null +++ b/dts/Bindings/clock/xlnx,clocking-wizard.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Xilinx clocking wizard + +maintainers: + - Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> + +description: + The clocking wizard is a soft ip clocking block of Xilinx versal. It + reads required input clock frequencies from the devicetree and acts as clock + clock output. + +properties: + compatible: + enum: + - xlnx,clocking-wizard + - xlnx,clocking-wizard-v5.2 + - xlnx,clocking-wizard-v6.0 + + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + items: + - description: clock input + - description: axi clock + + clock-names: + items: + - const: clk_in1 + - const: s_axi_aclk + + + xlnx,speed-grade: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3] + description: + Speed grade of the device. Higher the speed grade faster is the FPGA device. + + xlnx,nr-outputs: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 8 + description: + Number of outputs. + +required: + - compatible + - reg + - "#clock-cells" + - clocks + - clock-names + - xlnx,speed-grade + - xlnx,nr-outputs + +additionalProperties: false + +examples: + - | + clock-controller@b0000000 { + compatible = "xlnx,clocking-wizard"; + reg = <0xb0000000 0x10000>; + #clock-cells = <1>; + xlnx,speed-grade = <1>; + xlnx,nr-outputs = <6>; + clock-names = "clk_in1", "s_axi_aclk"; + clocks = <&clkc 15>, <&clkc 15>; + }; +... diff --git a/dts/Bindings/counter/ti,am62-ecap-capture.yaml b/dts/Bindings/counter/ti,am62-ecap-capture.yaml new file mode 100644 index 0000000000..4e0b2d2b30 --- /dev/null +++ b/dts/Bindings/counter/ti,am62-ecap-capture.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/counter/ti,am62-ecap-capture.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments Enhanced Capture (eCAP) Module + +maintainers: + - Julien Panis <jpanis@baylibre.com> + +description: | + The eCAP module resources can be used to capture timestamps + on input signal events (falling/rising edges). + +properties: + compatible: + const: ti,am62-ecap-capture + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: fck + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/soc/ti,sci_pm_domain.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + capture@23100000 { /* eCAP in capture mode on am62x */ + compatible = "ti,am62-ecap-capture"; + reg = <0x00 0x23100000 0x00 0x100>; + interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; + power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 51 0>; + clock-names = "fck"; + }; + }; diff --git a/dts/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml b/dts/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml index dedc99e34e..0401c11da8 100644 --- a/dts/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml +++ b/dts/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/crypto/allwinner,sun4i-a10-crypto.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Security System Device Tree Bindings +title: Allwinner A10 Security System maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/crypto/aspeed,ast2500-hace.yaml b/dts/Bindings/crypto/aspeed,ast2500-hace.yaml new file mode 100644 index 0000000000..a772d232de --- /dev/null +++ b/dts/Bindings/crypto/aspeed,ast2500-hace.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/aspeed,ast2500-hace.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED HACE hash and crypto Hardware Accelerator Engines + +maintainers: + - Neal Liu <neal_liu@aspeedtech.com> + +description: | + The Hash and Crypto Engine (HACE) is designed to accelerate the throughput + of hash data digest, encryption, and decryption. Basically, HACE can be + divided into two independently engines - Hash Engine and Crypto Engine. + +properties: + compatible: + enum: + - aspeed,ast2500-hace + - aspeed,ast2600-hace + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/ast2600-clock.h> + hace: crypto@1e6d0000 { + compatible = "aspeed,ast2600-hace"; + reg = <0x1e6d0000 0x200>; + interrupts = <4>; + clocks = <&syscon ASPEED_CLK_GATE_YCLK>; + resets = <&syscon ASPEED_RESET_HACE>; + }; diff --git a/dts/Bindings/crypto/intel,keembay-ocs-aes.yaml b/dts/Bindings/crypto/intel,keembay-ocs-aes.yaml index ee2c099981..fedd8be56a 100644 --- a/dts/Bindings/crypto/intel,keembay-ocs-aes.yaml +++ b/dts/Bindings/crypto/intel,keembay-ocs-aes.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-aes.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Intel Keem Bay OCS AES Device Tree Bindings +title: Intel Keem Bay OCS AES maintainers: - Daniele Alessandrelli <daniele.alessandrelli@intel.com> diff --git a/dts/Bindings/crypto/intel,keembay-ocs-ecc.yaml b/dts/Bindings/crypto/intel,keembay-ocs-ecc.yaml index a3c16451b1..2bb95247b6 100644 --- a/dts/Bindings/crypto/intel,keembay-ocs-ecc.yaml +++ b/dts/Bindings/crypto/intel,keembay-ocs-ecc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-ecc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Intel Keem Bay OCS ECC Device Tree Bindings +title: Intel Keem Bay OCS ECC maintainers: - Daniele Alessandrelli <daniele.alessandrelli@intel.com> diff --git a/dts/Bindings/crypto/intel,keembay-ocs-hcu.yaml b/dts/Bindings/crypto/intel,keembay-ocs-hcu.yaml index acb92706d2..46e2853ab8 100644 --- a/dts/Bindings/crypto/intel,keembay-ocs-hcu.yaml +++ b/dts/Bindings/crypto/intel,keembay-ocs-hcu.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-hcu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Intel Keem Bay OCS HCU Device Tree Bindings +title: Intel Keem Bay OCS HCU maintainers: - Declan Murphy <declan.murphy@intel.com> diff --git a/dts/Bindings/crypto/samsung-slimsss.yaml b/dts/Bindings/crypto/samsung-slimsss.yaml index 676950bb7b..5b31891c97 100644 --- a/dts/Bindings/crypto/samsung-slimsss.yaml +++ b/dts/Bindings/crypto/samsung-slimsss.yaml @@ -24,7 +24,6 @@ properties: maxItems: 1 clocks: - minItems: 2 maxItems: 2 clock-names: diff --git a/dts/Bindings/crypto/ti,sa2ul.yaml b/dts/Bindings/crypto/ti,sa2ul.yaml index 02f47c2e79..0c15fefb66 100644 --- a/dts/Bindings/crypto/ti,sa2ul.yaml +++ b/dts/Bindings/crypto/ti,sa2ul.yaml @@ -35,8 +35,6 @@ properties: - const: rx1 - const: rx2 - dma-coherent: true - "#address-cells": const: 2 @@ -72,16 +70,6 @@ required: - dmas - dma-names -if: - properties: - compatible: - enum: - - ti,j721e-sa2ul - - ti,am654-sa2ul -then: - required: - - dma-coherent - additionalProperties: false examples: @@ -95,5 +83,4 @@ examples: dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, <&main_udmap 0x4001>; dma-names = "tx", "rx1", "rx2"; - dma-coherent; }; diff --git a/dts/Bindings/crypto/xlnx,zynqmp-aes.yaml b/dts/Bindings/crypto/xlnx,zynqmp-aes.yaml index 55dd6e3d27..9e8fbd02b1 100644 --- a/dts/Bindings/crypto/xlnx,zynqmp-aes.yaml +++ b/dts/Bindings/crypto/xlnx,zynqmp-aes.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-aes.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Xilinx ZynqMP AES-GCM Hardware Accelerator Device Tree Bindings +title: Xilinx ZynqMP AES-GCM Hardware Accelerator maintainers: - Kalyani Akula <kalyani.akula@xilinx.com> diff --git a/dts/Bindings/display/allwinner,sun4i-a10-display-backend.yaml b/dts/Bindings/display/allwinner,sun4i-a10-display-backend.yaml index 3d8ea3c2d8..ba06d1857b 100644 --- a/dts/Bindings/display/allwinner,sun4i-a10-display-backend.yaml +++ b/dts/Bindings/display/allwinner,sun4i-a10-display-backend.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-backend.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Display Engine Backend Device Tree Bindings +title: Allwinner A10 Display Engine Backend maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/display/allwinner,sun4i-a10-display-engine.yaml b/dts/Bindings/display/allwinner,sun4i-a10-display-engine.yaml index c9c346e622..e6088f379f 100644 --- a/dts/Bindings/display/allwinner,sun4i-a10-display-engine.yaml +++ b/dts/Bindings/display/allwinner,sun4i-a10-display-engine.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-engine.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Display Engine Pipeline Device Tree Bindings +title: Allwinner A10 Display Engine Pipeline maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/display/allwinner,sun4i-a10-display-frontend.yaml b/dts/Bindings/display/allwinner,sun4i-a10-display-frontend.yaml index 055157fbf3..98e8240a05 100644 --- a/dts/Bindings/display/allwinner,sun4i-a10-display-frontend.yaml +++ b/dts/Bindings/display/allwinner,sun4i-a10-display-frontend.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-frontend.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Display Engine Frontend Device Tree Bindings +title: Allwinner A10 Display Engine Frontend maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/display/allwinner,sun4i-a10-hdmi.yaml b/dts/Bindings/display/allwinner,sun4i-a10-hdmi.yaml index 7f11452539..55703caacb 100644 --- a/dts/Bindings/display/allwinner,sun4i-a10-hdmi.yaml +++ b/dts/Bindings/display/allwinner,sun4i-a10-hdmi.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-hdmi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 HDMI Controller Device Tree Bindings +title: Allwinner A10 HDMI Controller description: | The HDMI Encoder supports the HDMI video and audio outputs, and does diff --git a/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml b/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml index f8168986a0..724d93b919 100644 --- a/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml +++ b/dts/Bindings/display/allwinner,sun4i-a10-tcon.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-tcon.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Timings Controller (TCON) Device Tree Bindings +title: Allwinner A10 Timings Controller (TCON) maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/display/allwinner,sun4i-a10-tv-encoder.yaml b/dts/Bindings/display/allwinner,sun4i-a10-tv-encoder.yaml index afc0ed799e..c39e90a594 100644 --- a/dts/Bindings/display/allwinner,sun4i-a10-tv-encoder.yaml +++ b/dts/Bindings/display/allwinner,sun4i-a10-tv-encoder.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-tv-encoder.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 TV Encoder Device Tree Bindings +title: Allwinner A10 TV Encoder maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/display/allwinner,sun6i-a31-drc.yaml b/dts/Bindings/display/allwinner,sun6i-a31-drc.yaml index 71cce56875..895506d93f 100644 --- a/dts/Bindings/display/allwinner,sun6i-a31-drc.yaml +++ b/dts/Bindings/display/allwinner,sun6i-a31-drc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-drc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A31 Dynamic Range Controller Device Tree Bindings +title: Allwinner A31 Dynamic Range Controller maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml b/dts/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml index bf0bdf54e5..7910831fa4 100644 --- a/dts/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml +++ b/dts/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A31 MIPI-DSI Controller Device Tree Bindings +title: Allwinner A31 MIPI-DSI Controller maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml b/dts/Bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml index cb243bc58e..b75c1ec686 100644 --- a/dts/Bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml +++ b/dts/Bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-de2-mixer.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner Display Engine 2.0 Mixer Device Tree Bindings +title: Allwinner Display Engine 2.0 Mixer maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml b/dts/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml index 4951b5ef5c..60fd927b5a 100644 --- a/dts/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml +++ b/dts/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A83t DWC HDMI TX Encoder Device Tree Bindings +title: Allwinner A83t DWC HDMI TX Encoder description: | The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller diff --git a/dts/Bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml b/dts/Bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml index a97366aaf9..1b47f3d99a 100644 --- a/dts/Bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml +++ b/dts/Bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-hdmi-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A83t HDMI PHY Device Tree Bindings +title: Allwinner A83t HDMI PHY maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/display/allwinner,sun8i-r40-tcon-top.yaml b/dts/Bindings/display/allwinner,sun8i-r40-tcon-top.yaml index 845e226d7a..7d849c4095 100644 --- a/dts/Bindings/display/allwinner,sun8i-r40-tcon-top.yaml +++ b/dts/Bindings/display/allwinner,sun8i-r40-tcon-top.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun8i-r40-tcon-top.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner R40 TCON TOP Device Tree Bindings +title: Allwinner R40 TCON TOP maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/display/allwinner,sun9i-a80-deu.yaml b/dts/Bindings/display/allwinner,sun9i-a80-deu.yaml index 637372ec46..193afee2c3 100644 --- a/dts/Bindings/display/allwinner,sun9i-a80-deu.yaml +++ b/dts/Bindings/display/allwinner,sun9i-a80-deu.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/allwinner,sun9i-a80-deu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A80 Detail Enhancement Unit Device Tree Bindings +title: Allwinner A80 Detail Enhancement Unit maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/display/arm,komeda.yaml b/dts/Bindings/display/arm,komeda.yaml index 9f4aade97f..3ad3eef89c 100644 --- a/dts/Bindings/display/arm,komeda.yaml +++ b/dts/Bindings/display/arm,komeda.yaml @@ -58,6 +58,7 @@ properties: patternProperties: '^pipeline@[01]$': type: object + additionalProperties: false description: clocks diff --git a/dts/Bindings/display/brcm,bcm2711-hdmi.yaml b/dts/Bindings/display/brcm,bcm2711-hdmi.yaml index a9d34dd7bb..5b35adf34c 100644 --- a/dts/Bindings/display/brcm,bcm2711-hdmi.yaml +++ b/dts/Bindings/display/brcm,bcm2711-hdmi.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/brcm,bcm2711-hdmi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Broadcom BCM2711 HDMI Controller Device Tree Bindings +title: Broadcom BCM2711 HDMI Controller maintainers: - Eric Anholt <eric@anholt.net> diff --git a/dts/Bindings/display/bridge/adi,adv7511.yaml b/dts/Bindings/display/bridge/adi,adv7511.yaml index f08a01dfed..5bbe81862c 100644 --- a/dts/Bindings/display/bridge/adi,adv7511.yaml +++ b/dts/Bindings/display/bridge/adi,adv7511.yaml @@ -117,23 +117,21 @@ properties: ports: description: - The ADV7511(W)/13 has two video ports and one audio port. This node - models their connections as documented in - Documentation/devicetree/bindings/media/video-interfaces.txt - Documentation/devicetree/bindings/graph.txt - type: object + The ADV7511(W)/13 has two video ports and one audio port. + $ref: /schemas/graph.yaml#/properties/ports + properties: port@0: description: Video port for the RGB or YUV input. - type: object + $ref: /schemas/graph.yaml#/properties/port port@1: description: Video port for the HDMI output. - type: object + $ref: /schemas/graph.yaml#/properties/port port@2: description: Audio port for the HDMI output. - type: object + $ref: /schemas/graph.yaml#/properties/port # adi,input-colorspace and adi,input-clock are required except in # "rgb 1x" and "yuv444 1x" modes, in which case they must not be diff --git a/dts/Bindings/display/bridge/adi,adv7533.yaml b/dts/Bindings/display/bridge/adi,adv7533.yaml index f36209137c..987aa83c26 100644 --- a/dts/Bindings/display/bridge/adi,adv7533.yaml +++ b/dts/Bindings/display/bridge/adi,adv7533.yaml @@ -91,25 +91,23 @@ properties: ports: description: - The ADV7533/35 has two video ports and one audio port. This node - models their connections as documented in - Documentation/devicetree/bindings/media/video-interfaces.txt - Documentation/devicetree/bindings/graph.txt - type: object + The ADV7533/35 has two video ports and one audio port. + $ref: /schemas/graph.yaml#/properties/ports + properties: port@0: description: Video port for the DSI input. The remote endpoint phandle should be a reference to a valid mipi_dsi_host_device. - type: object + $ref: /schemas/graph.yaml#/properties/port port@1: description: Video port for the HDMI output. - type: object + $ref: /schemas/graph.yaml#/properties/port port@2: description: Audio port for the HDMI output. - type: object + $ref: /schemas/graph.yaml#/properties/port required: - compatible diff --git a/dts/Bindings/display/bridge/chipone,icn6211.yaml b/dts/Bindings/display/bridge/chipone,icn6211.yaml index 4f0b7c7131..5fb54375ae 100644 --- a/dts/Bindings/display/bridge/chipone,icn6211.yaml +++ b/dts/Bindings/display/bridge/chipone,icn6211.yaml @@ -24,6 +24,15 @@ properties: maxItems: 1 description: virtual channel number of a DSI peripheral + clock-names: + const: refclk + + clocks: + maxItems: 1 + description: | + Optional external clock connected to REF_CLK input. + The clock rate must be in 10..154 MHz range. + enable-gpios: description: Bridge EN pin, chip is reset when EN is low. diff --git a/dts/Bindings/display/bridge/fsl,ldb.yaml b/dts/Bindings/display/bridge/fsl,ldb.yaml index 2ebaa43eb6..b19be0804a 100644 --- a/dts/Bindings/display/bridge/fsl,ldb.yaml +++ b/dts/Bindings/display/bridge/fsl,ldb.yaml @@ -25,7 +25,6 @@ properties: const: ldb reg: - minItems: 2 maxItems: 2 reg-names: diff --git a/dts/Bindings/display/bridge/lvds-codec.yaml b/dts/Bindings/display/bridge/lvds-codec.yaml index 3a8614e0f6..84aafcbf09 100644 --- a/dts/Bindings/display/bridge/lvds-codec.yaml +++ b/dts/Bindings/display/bridge/lvds-codec.yaml @@ -51,6 +51,7 @@ properties: properties: port@0: $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false description: | For LVDS encoders, port 0 is the parallel input For LVDS decoders, port 0 is the LVDS input diff --git a/dts/Bindings/display/bridge/nxp,tda998x.yaml b/dts/Bindings/display/bridge/nxp,tda998x.yaml new file mode 100644 index 0000000000..c4bf543974 --- /dev/null +++ b/dts/Bindings/display/bridge/nxp,tda998x.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/nxp,tda998x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP TDA998x HDMI transmitter + +maintainers: + - Russell King <linux@armlinux.org.uk> + +properties: + compatible: + const: nxp,tda998x + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + video-ports: + default: 0x230145 + maximum: 0xffffff + description: + 24 bits value which defines how the video controller output is wired to + the TDA998x input. + + audio-ports: + description: + Array of 8-bit values, 2 values per DAI (Documentation/sound/soc/dai.rst). + The implementation allows one or two DAIs. + If two DAIs are defined, they must be of different type. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + minItems: 1 + items: + - description: | + The first value defines the DAI type: TDA998x_SPDIF or TDA998x_I2S + (see include/dt-bindings/display/tda998x.h). + - description: + The second value defines the tda998x AP_ENA reg content when the + DAI in question is used. + + '#sound-dai-cells': + enum: [ 0, 1 ] + + nxp,calib-gpios: + maxItems: 1 + description: + Calibration GPIO, which must correspond with the gpio used for the + TDA998x interrupt pin. + + port: + $ref: /schemas/graph.yaml#/properties/port + description: Parallel input port + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + type: object + description: Parallel input port + + port@1: + type: object + description: HDMI output port + +required: + - compatible + - reg + +oneOf: + - required: + - port + - required: + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/display/tda998x.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + tda998x: hdmi-encoder@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + interrupt-parent = <&gpio0>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + video-ports = <0x230145>; + + #sound-dai-cells = <1>; + /* DAI-format / AP_ENA reg value */ + audio-ports = <TDA998x_SPDIF 0x04>, + <TDA998x_I2S 0x03>; + + port { + tda998x_in: endpoint { + remote-endpoint = <&lcdc_0>; + }; + }; + }; + }; diff --git a/dts/Bindings/display/bridge/renesas,dw-hdmi.yaml b/dts/Bindings/display/bridge/renesas,dw-hdmi.yaml index 0c9785c8db..e3ec697f89 100644 --- a/dts/Bindings/display/bridge/renesas,dw-hdmi.yaml +++ b/dts/Bindings/display/bridge/renesas,dw-hdmi.yaml @@ -38,6 +38,9 @@ properties: clock-names: maxItems: 2 + resets: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports @@ -67,6 +70,7 @@ required: - reg - clocks - clock-names + - resets - interrupts - ports @@ -85,6 +89,7 @@ examples: clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>; clock-names = "iahb", "isfr"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 729>; ports { #address-cells = <1>; diff --git a/dts/Bindings/display/bridge/synopsys,dw-hdmi.yaml b/dts/Bindings/display/bridge/synopsys,dw-hdmi.yaml index b00246faea..4b7e54a8f0 100644 --- a/dts/Bindings/display/bridge/synopsys,dw-hdmi.yaml +++ b/dts/Bindings/display/bridge/synopsys,dw-hdmi.yaml @@ -26,7 +26,6 @@ properties: reg-io-width: description: Width (in bytes) of the registers specified by the reg property. - $ref: /schemas/types.yaml#/definitions/uint32 enum: [1, 4] default: 1 diff --git a/dts/Bindings/display/bridge/tda998x.txt b/dts/Bindings/display/bridge/tda998x.txt deleted file mode 100644 index f5a02f61dd..0000000000 --- a/dts/Bindings/display/bridge/tda998x.txt +++ /dev/null @@ -1,54 +0,0 @@ -Device-Tree bindings for the NXP TDA998x HDMI transmitter - -Required properties; - - compatible: must be "nxp,tda998x" - - - reg: I2C address - -Required node: - - port: Input port node with endpoint definition, as described - in Documentation/devicetree/bindings/graph.txt - -Optional properties: - - interrupts: interrupt number and trigger type - default: polling - - - pinctrl-0: pin control group to be used for - screen plug/unplug interrupt. - - - pinctrl-names: must contain a "default" entry. - - - video-ports: 24 bits value which defines how the video controller - output is wired to the TDA998x input - default: <0x230145> - - - audio-ports: array of 8-bit values, 2 values per one DAI[1]. - The first value defines the DAI type: TDA998x_SPDIF or TDA998x_I2S[2]. - The second value defines the tda998x AP_ENA reg content when the DAI - in question is used. The implementation allows one or two DAIs. If two - DAIs are defined, they must be of different type. - - - nxp,calib-gpios: calibration GPIO, which must correspond with the - gpio used for the TDA998x interrupt pin. - -[1] Documentation/sound/soc/dai.rst -[2] include/dt-bindings/display/tda998x.h - -Example: - -#include <dt-bindings/display/tda998x.h> - - tda998x: hdmi-encoder { - compatible = "nxp,tda998x"; - reg = <0x70>; - interrupt-parent = <&gpio0>; - interrupts = <27 2>; /* falling edge */ - pinctrl-0 = <&pmx_camera>; - pinctrl-names = "default"; - video-ports = <0x230145>; - - #sound-dai-cells = <2>; - /* DAI-format AP_ENA reg value */ - audio-ports = < TDA998x_SPDIF 0x04 - TDA998x_I2S 0x03>; - - }; diff --git a/dts/Bindings/display/ilitek,ili9486.yaml b/dts/Bindings/display/ilitek,ili9486.yaml index aecff34f50..1f8f2182e2 100644 --- a/dts/Bindings/display/ilitek,ili9486.yaml +++ b/dts/Bindings/display/ilitek,ili9486.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/ilitek,ili9486.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Ilitek ILI9486 display panels device tree bindings +title: Ilitek ILI9486 display panels maintainers: - Kamlesh Gurudasani <kamlesh.gurudasani@gmail.com> diff --git a/dts/Bindings/display/ingenic,lcd.yaml b/dts/Bindings/display/ingenic,lcd.yaml index 0049010b37..c0bb02fb49 100644 --- a/dts/Bindings/display/ingenic,lcd.yaml +++ b/dts/Bindings/display/ingenic,lcd.yaml @@ -17,6 +17,8 @@ properties: enum: - ingenic,jz4740-lcd - ingenic,jz4725b-lcd + - ingenic,jz4760-lcd + - ingenic,jz4760b-lcd - ingenic,jz4770-lcd - ingenic,jz4780-lcd diff --git a/dts/Bindings/display/mediatek/mediatek,dp.yaml b/dts/Bindings/display/mediatek/mediatek,dp.yaml new file mode 100644 index 0000000000..ff781f2174 --- /dev/null +++ b/dts/Bindings/display/mediatek/mediatek,dp.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Display Port Controller + +maintainers: + - Chun-Kuang Hu <chunkuang.hu@kernel.org> + - Jitao shi <jitao.shi@mediatek.com> + +description: | + MediaTek DP and eDP are different hardwares and there are some features + which are not supported for eDP. For example, audio is not supported for + eDP. Therefore, we need to use two different compatibles to describe them. + In addition, We just need to enable the power domain of DP, so the clock + of DP is generated by itself and we are not using other PLL to generate + clocks. + +properties: + compatible: + enum: + - mediatek,mt8195-dp-tx + - mediatek,mt8195-edp-tx + + reg: + maxItems: 1 + + nvmem-cells: + maxItems: 1 + description: efuse data for display port calibration + + nvmem-cell-names: + const: dp_calibration_data + + power-domains: + maxItems: 1 + + interrupts: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input endpoint of the controller, usually dp_intf + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Output endpoint of the controller + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + properties: + data-lanes: + description: | + number of lanes supported by the hardware. + The possible values: + 0 - For 1 lane enabled in IP. + 0 1 - For 2 lanes enabled in IP. + 0 1 2 3 - For 4 lanes enabled in IP. + minItems: 1 + maxItems: 4 + required: + - data-lanes + + required: + - port@0 + - port@1 + + max-linkrate-mhz: + enum: [ 1620, 2700, 5400, 8100 ] + description: maximum link rate supported by the hardware. + +required: + - compatible + - reg + - interrupts + - ports + - max-linkrate-mhz + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/mt8195-power.h> + dptx@1c600000 { + compatible = "mediatek,mt8195-dp-tx"; + reg = <0x1c600000 0x8000>; + power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; + interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; + max-linkrate-mhz = <8100>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dptx_in: endpoint { + remote-endpoint = <&dp_intf0_out>; + }; + }; + port@1 { + reg = <1>; + dptx_out: endpoint { + data-lanes = <0 1 2 3>; + }; + }; + }; + }; diff --git a/dts/Bindings/display/msm/dp-controller.yaml b/dts/Bindings/display/msm/dp-controller.yaml index 94bc6e1b64..f2515af825 100644 --- a/dts/Bindings/display/msm/dp-controller.yaml +++ b/dts/Bindings/display/msm/dp-controller.yaml @@ -24,6 +24,7 @@ properties: - qcom,sm8350-dp reg: + minItems: 4 items: - description: ahb register block - description: aux register block @@ -70,14 +71,28 @@ properties: operating-points-v2: maxItems: 1 + opp-table: true + power-domains: maxItems: 1 + aux-bus: + $ref: /schemas/display/dp-aux-bus.yaml# + + data-lanes: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + items: + maximum: 3 + "#sound-dai-cells": const: 0 - vdda-0p9-supply: true - vdda-1p2-supply: true + vdda-0p9-supply: + deprecated: true + vdda-1p2-supply: + deprecated: true ports: $ref: /schemas/graph.yaml#/properties/ports @@ -98,10 +113,33 @@ required: - clock-names - phys - phy-names - - "#sound-dai-cells" - power-domains - ports +allOf: + # AUX BUS does not exist on DP controllers + # Audio output also is present only on DP output + # p1 regions is present on DP, but not on eDP + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-edp + - qcom,sc8180x-edp + then: + properties: + "#sound-dai-cells": false + reg: + maxItems: 4 + else: + properties: + aux-bus: false + reg: + minItems: 5 + required: + - "#sound-dai-cells" + additionalProperties: false examples: @@ -140,9 +178,6 @@ examples: power-domains = <&rpmhpd SC7180_CX>; - vdda-0p9-supply = <&vdda_usb_ss_dp_core>; - vdda-1p2-supply = <&vdda_usb_ss_dp_1p2>; - ports { #address-cells = <1>; #size-cells = <0>; diff --git a/dts/Bindings/display/msm/dpu-msm8998.yaml b/dts/Bindings/display/msm/dpu-msm8998.yaml index 2df64afb76..253665c693 100644 --- a/dts/Bindings/display/msm/dpu-msm8998.yaml +++ b/dts/Bindings/display/msm/dpu-msm8998.yaml @@ -62,6 +62,7 @@ patternProperties: "^display-controller@[0-9a-f]+$": type: object description: Node containing the properties of DPU. + additionalProperties: false properties: compatible: @@ -105,6 +106,9 @@ patternProperties: maxItems: 1 operating-points-v2: true + opp-table: + type: object + ports: $ref: /schemas/graph.yaml#/properties/ports description: | diff --git a/dts/Bindings/display/msm/dpu-qcm2290.yaml b/dts/Bindings/display/msm/dpu-qcm2290.yaml index 734d14de96..c5824e1d23 100644 --- a/dts/Bindings/display/msm/dpu-qcm2290.yaml +++ b/dts/Bindings/display/msm/dpu-qcm2290.yaml @@ -74,6 +74,7 @@ patternProperties: "^display-controller@[0-9a-f]+$": type: object description: Node containing the properties of DPU. + additionalProperties: false properties: compatible: @@ -113,6 +114,8 @@ patternProperties: maxItems: 1 operating-points-v2: true + opp-table: + type: object ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/dts/Bindings/display/msm/dpu-sc7180.yaml b/dts/Bindings/display/msm/dpu-sc7180.yaml index d3c3e4b078..4890bc25f3 100644 --- a/dts/Bindings/display/msm/dpu-sc7180.yaml +++ b/dts/Bindings/display/msm/dpu-sc7180.yaml @@ -73,6 +73,7 @@ patternProperties: "^display-controller@[0-9a-f]+$": type: object description: Node containing the properties of DPU. + additionalProperties: false properties: compatible: @@ -114,6 +115,8 @@ patternProperties: maxItems: 1 operating-points-v2: true + opp-table: + type: object ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/dts/Bindings/display/msm/dpu-sc7280.yaml b/dts/Bindings/display/msm/dpu-sc7280.yaml index f427eec3d3..584d646021 100644 --- a/dts/Bindings/display/msm/dpu-sc7280.yaml +++ b/dts/Bindings/display/msm/dpu-sc7280.yaml @@ -72,6 +72,7 @@ patternProperties: "^display-controller@[0-9a-f]+$": type: object description: Node containing the properties of DPU. + additionalProperties: false properties: compatible: @@ -112,6 +113,8 @@ patternProperties: maxItems: 1 operating-points-v2: true + opp-table: + type: object ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/dts/Bindings/display/msm/dpu-sdm845.yaml b/dts/Bindings/display/msm/dpu-sdm845.yaml index 2bb8896bef..7d10373731 100644 --- a/dts/Bindings/display/msm/dpu-sdm845.yaml +++ b/dts/Bindings/display/msm/dpu-sdm845.yaml @@ -65,6 +65,7 @@ patternProperties: "^display-controller@[0-9a-f]+$": type: object description: Node containing the properties of DPU. + additionalProperties: false properties: compatible: @@ -102,6 +103,9 @@ patternProperties: maxItems: 1 operating-points-v2: true + opp-table: + type: object + ports: $ref: /schemas/graph.yaml#/properties/ports description: | diff --git a/dts/Bindings/display/msm/dsi-controller-main.yaml b/dts/Bindings/display/msm/dsi-controller-main.yaml index 880bfe9308..3b609c19e0 100644 --- a/dts/Bindings/display/msm/dsi-controller-main.yaml +++ b/dts/Bindings/display/msm/dsi-controller-main.yaml @@ -66,13 +66,11 @@ properties: 2 DSI links. assigned-clocks: - minItems: 2 maxItems: 2 description: | Parents of "byte" and "pixel" for the given platform. assigned-clock-parents: - minItems: 2 maxItems: 2 description: | The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. diff --git a/dts/Bindings/display/msm/dsi-phy-10nm.yaml b/dts/Bindings/display/msm/dsi-phy-10nm.yaml index 716f921e35..d9ad8b659f 100644 --- a/dts/Bindings/display/msm/dsi-phy-10nm.yaml +++ b/dts/Bindings/display/msm/dsi-phy-10nm.yaml @@ -37,7 +37,6 @@ properties: qcom,phy-rescode-offset-top: $ref: /schemas/types.yaml#/definitions/int8-array - minItems: 5 maxItems: 5 description: Integer array of offset for pull-up legs rescode for all five lanes. @@ -49,7 +48,6 @@ properties: qcom,phy-rescode-offset-bot: $ref: /schemas/types.yaml#/definitions/int8-array - minItems: 5 maxItems: 5 description: Integer array of offset for pull-down legs rescode for all five lanes. diff --git a/dts/Bindings/display/msm/gmu.yaml b/dts/Bindings/display/msm/gmu.yaml index fe55611d26..67fdeeabae 100644 --- a/dts/Bindings/display/msm/gmu.yaml +++ b/dts/Bindings/display/msm/gmu.yaml @@ -20,35 +20,24 @@ description: | properties: compatible: items: - - enum: - - qcom,adreno-gmu-630.2 + - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$' - const: qcom,adreno-gmu reg: - items: - - description: Core GMU registers - - description: GMU PDC registers - - description: GMU PDC sequence registers + minItems: 3 + maxItems: 4 reg-names: - items: - - const: gmu - - const: gmu_pdc - - const: gmu_pdc_seq + minItems: 3 + maxItems: 4 clocks: - items: - - description: GMU clock - - description: GPU CX clock - - description: GPU AXI clock - - description: GPU MEMNOC clock + minItems: 4 + maxItems: 7 clock-names: - items: - - const: gmu - - const: cxo - - const: axi - - const: memnoc + minItems: 4 + maxItems: 7 interrupts: items: @@ -76,6 +65,9 @@ properties: operating-points-v2: true + opp-table: + type: object + required: - compatible - reg @@ -91,6 +83,140 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-gmu-618.0 + - qcom,adreno-gmu-630.2 + then: + properties: + reg: + items: + - description: Core GMU registers + - description: GMU PDC registers + - description: GMU PDC sequence registers + reg-names: + items: + - const: gmu + - const: gmu_pdc + - const: gmu_pdc_seq + clocks: + items: + - description: GMU clock + - description: GPU CX clock + - description: GPU AXI clock + - description: GPU MEMNOC clock + clock-names: + items: + - const: gmu + - const: cxo + - const: axi + - const: memnoc + + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-gmu-635.0 + then: + properties: + reg: + items: + - description: Core GMU registers + - description: Resource controller registers + - description: GMU PDC registers + reg-names: + items: + - const: gmu + - const: rscc + - const: gmu_pdc + clocks: + items: + - description: GMU clock + - description: GPU CX clock + - description: GPU AXI clock + - description: GPU MEMNOC clock + - description: GPU AHB clock + - description: GPU HUB CX clock + - description: GPU SMMU vote clock + clock-names: + items: + - const: gmu + - const: cxo + - const: axi + - const: memnoc + - const: ahb + - const: hub + - const: smmu_vote + + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-gmu-640.1 + then: + properties: + reg: + items: + - description: Core GMU registers + - description: GMU PDC registers + - description: GMU PDC sequence registers + reg-names: + items: + - const: gmu + - const: gmu_pdc + - const: gmu_pdc_seq + + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-gmu-650.2 + then: + properties: + reg: + items: + - description: Core GMU registers + - description: Resource controller registers + - description: GMU PDC registers + - description: GMU PDC sequence registers + reg-names: + items: + - const: gmu + - const: rscc + - const: gmu_pdc + - const: gmu_pdc_seq + + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-gmu-640.1 + - qcom,adreno-gmu-650.2 + then: + properties: + clocks: + items: + - description: GPU AHB clock + - description: GMU clock + - description: GPU CX clock + - description: GPU AXI clock + - description: GPU MEMNOC clock + clock-names: + items: + - const: ahb + - const: gmu + - const: cxo + - const: axi + - const: memnoc + examples: - | #include <dt-bindings/clock/qcom,gpucc-sdm845.h> diff --git a/dts/Bindings/display/msm/gpu.yaml b/dts/Bindings/display/msm/gpu.yaml index 3397bc31d0..ec4b1a75f4 100644 --- a/dts/Bindings/display/msm/gpu.yaml +++ b/dts/Bindings/display/msm/gpu.yaml @@ -58,7 +58,8 @@ properties: - const: ocmem iommus: - maxItems: 1 + minItems: 1 + maxItems: 64 sram: $ref: /schemas/types.yaml#/definitions/phandle-array @@ -81,6 +82,7 @@ properties: zap-shader: type: object + additionalProperties: false description: | For a5xx and a6xx devices this node contains a memory-region that points to reserved memory to store the zap shader that can be used to diff --git a/dts/Bindings/display/msm/mdp4.yaml b/dts/Bindings/display/msm/mdp4.yaml index f63f60fea2..58c13f5277 100644 --- a/dts/Bindings/display/msm/mdp4.yaml +++ b/dts/Bindings/display/msm/mdp4.yaml @@ -36,7 +36,7 @@ properties: maxItems: 1 iommus: - maxItems: 1 + maxItems: 4 ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/dts/Bindings/display/panel/arm,versatile-tft-panel.yaml b/dts/Bindings/display/panel/arm,versatile-tft-panel.yaml index be69e0cc50..c9958f824d 100644 --- a/dts/Bindings/display/panel/arm,versatile-tft-panel.yaml +++ b/dts/Bindings/display/panel/arm,versatile-tft-panel.yaml @@ -37,9 +37,6 @@ examples: compatible = "arm,versatile-sysreg", "syscon", "simple-mfd"; reg = <0x00000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - panel { compatible = "arm,versatile-tft-panel"; diff --git a/dts/Bindings/display/panel/kingdisplay,kd035g6-54nt.yaml b/dts/Bindings/display/panel/kingdisplay,kd035g6-54nt.yaml index 2a2756d196..b4be9bd8dd 100644 --- a/dts/Bindings/display/panel/kingdisplay,kd035g6-54nt.yaml +++ b/dts/Bindings/display/panel/kingdisplay,kd035g6-54nt.yaml @@ -23,6 +23,8 @@ properties: reg: true reset-gpios: true + spi-3wire: true + required: - compatible - power-supply diff --git a/dts/Bindings/display/panel/leadtek,ltk035c5444t.yaml b/dts/Bindings/display/panel/leadtek,ltk035c5444t.yaml index 817a9bed7d..ebdca5f5a0 100644 --- a/dts/Bindings/display/panel/leadtek,ltk035c5444t.yaml +++ b/dts/Bindings/display/panel/leadtek,ltk035c5444t.yaml @@ -24,6 +24,8 @@ properties: reg: true reset-gpios: true + spi-3wire: true + required: - compatible - power-supply diff --git a/dts/Bindings/display/panel/panel-simple.yaml b/dts/Bindings/display/panel/panel-simple.yaml index bc8e9c0c1d..18241f4051 100644 --- a/dts/Bindings/display/panel/panel-simple.yaml +++ b/dts/Bindings/display/panel/panel-simple.yaml @@ -234,6 +234,8 @@ properties: - mitsubishi,aa070mc01-ca1 # Multi-Inno Technology Co.,Ltd MI0700S4T-6 7" 800x480 TFT Resistive Touch Module - multi-inno,mi0700s4t-6 + # Multi-Inno Technology Co.,Ltd MI0800FT-9 8" 800x600 TFT Resistive Touch Module + - multi-inno,mi0800ft-9 # Multi-Inno Technology Co.,Ltd MI1010AIT-1CP 10.1" 1280x800 LVDS IPS Cap Touch Mod. - multi-inno,mi1010ait-1cp # NEC LCD Technologies, Ltd. 12.1" WXGA (1280x800) LVDS TFT LCD panel @@ -280,6 +282,8 @@ properties: - samsung,atna33xc20 # Samsung 12.2" (2560x1600 pixels) TFT LCD panel - samsung,lsn122dl01-c01 + # Samsung Electronics 10.1" WXGA (1280x800) TFT LCD panel + - samsung,ltl101al01 # Samsung Electronics 10.1" WSVGA TFT LCD panel - samsung,ltn101nt05 # Samsung Electronics 14" WXGA (1366x768) TFT LCD panel diff --git a/dts/Bindings/display/panel/samsung,s6e63m0.yaml b/dts/Bindings/display/panel/samsung,s6e63m0.yaml index 940f7f8852..6f1fc7469f 100644 --- a/dts/Bindings/display/panel/samsung,s6e63m0.yaml +++ b/dts/Bindings/display/panel/samsung,s6e63m0.yaml @@ -24,6 +24,10 @@ properties: default-brightness: true max-brightness: true + spi-3wire: true + spi-cpha: true + spi-cpol: true + vdd3-supply: description: VDD regulator diff --git a/dts/Bindings/display/panel/sitronix,st7701.yaml b/dts/Bindings/display/panel/sitronix,st7701.yaml index 6dff59fe4b..34d5e20c6c 100644 --- a/dts/Bindings/display/panel/sitronix,st7701.yaml +++ b/dts/Bindings/display/panel/sitronix,st7701.yaml @@ -17,6 +17,9 @@ description: | Techstar TS8550B is 480x854, 2-lane MIPI DSI LCD panel which has inbuilt ST7701 chip. + Densitron DMT028VGHMCMI-1A is 480x640, 2-lane MIPI DSI LCD panel + which has built-in ST7701 chip. + allOf: - $ref: panel-common.yaml# @@ -24,6 +27,7 @@ properties: compatible: items: - enum: + - densitron,dmt028vghmcmi-1a - techstar,ts8550b - const: sitronix,st7701 diff --git a/dts/Bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/dts/Bindings/display/rockchip/dw_mipi_dsi_rockchip.txt index 39792f051d..9a223df853 100644 --- a/dts/Bindings/display/rockchip/dw_mipi_dsi_rockchip.txt +++ b/dts/Bindings/display/rockchip/dw_mipi_dsi_rockchip.txt @@ -8,6 +8,7 @@ Required properties: "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi" "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi" "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi" + "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi" - reg: Represent the physical address range of the controller. - interrupts: Represent the controller's interrupt to the CPU(s). - clocks, clock-names: Phandles to the controller's pll reference diff --git a/dts/Bindings/display/samsung/samsung,exynos5433-decon.yaml b/dts/Bindings/display/samsung/samsung,exynos5433-decon.yaml index 921bfe925c..6380eeebb0 100644 --- a/dts/Bindings/display/samsung/samsung,exynos5433-decon.yaml +++ b/dts/Bindings/display/samsung/samsung,exynos5433-decon.yaml @@ -24,7 +24,6 @@ properties: - samsung,exynos5433-decon-tv clocks: - minItems: 11 maxItems: 11 clock-names: @@ -59,7 +58,6 @@ properties: - const: te iommus: - minItems: 2 maxItems: 2 iommu-names: diff --git a/dts/Bindings/display/samsung/samsung,exynos5433-mic.yaml b/dts/Bindings/display/samsung/samsung,exynos5433-mic.yaml index 7d405f2feb..26e5017737 100644 --- a/dts/Bindings/display/samsung/samsung,exynos5433-mic.yaml +++ b/dts/Bindings/display/samsung/samsung,exynos5433-mic.yaml @@ -24,7 +24,6 @@ properties: const: samsung,exynos5433-mic clocks: - minItems: 2 maxItems: 2 clock-names: diff --git a/dts/Bindings/display/samsung/samsung,exynos7-decon.yaml b/dts/Bindings/display/samsung/samsung,exynos7-decon.yaml index 969bd8c563..992c23ca7a 100644 --- a/dts/Bindings/display/samsung/samsung,exynos7-decon.yaml +++ b/dts/Bindings/display/samsung/samsung,exynos7-decon.yaml @@ -22,7 +22,6 @@ properties: const: samsung,exynos7-decon clocks: - minItems: 4 maxItems: 4 clock-names: @@ -37,6 +36,7 @@ properties: i80-if-timings: type: object + additionalProperties: false description: timing configuration for lcd i80 interface support properties: cs-setup: diff --git a/dts/Bindings/display/samsung/samsung,fimd.yaml b/dts/Bindings/display/samsung/samsung,fimd.yaml index 5d5cc220f7..075231716b 100644 --- a/dts/Bindings/display/samsung/samsung,fimd.yaml +++ b/dts/Bindings/display/samsung/samsung,fimd.yaml @@ -27,7 +27,6 @@ properties: const: 1 clocks: - minItems: 2 maxItems: 2 clock-names: @@ -40,6 +39,7 @@ properties: i80-if-timings: type: object + additionalProperties: false description: | Timing configuration for lcd i80 interface support. The parameters are defined as:: diff --git a/dts/Bindings/display/simple-framebuffer.yaml b/dts/Bindings/display/simple-framebuffer.yaml index 1f905d85dd..dd64f70b50 100644 --- a/dts/Bindings/display/simple-framebuffer.yaml +++ b/dts/Bindings/display/simple-framebuffer.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/simple-framebuffer.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Simple Framebuffer Device Tree Bindings +title: Simple Framebuffer maintainers: - Hans de Goede <hdegoede@redhat.com> diff --git a/dts/Bindings/display/sitronix,st7735r.yaml b/dts/Bindings/display/sitronix,st7735r.yaml index 53f181ef36..621f271484 100644 --- a/dts/Bindings/display/sitronix,st7735r.yaml +++ b/dts/Bindings/display/sitronix,st7735r.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/sitronix,st7735r.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Sitronix ST7735R Display Panels Device Tree Bindings +title: Sitronix ST7735R Display Panels maintainers: - David Lechner <david@lechnology.com> diff --git a/dts/Bindings/display/st,stm32-dsi.yaml b/dts/Bindings/display/st,stm32-dsi.yaml index 54f67cb510..c488308d7b 100644 --- a/dts/Bindings/display/st,stm32-dsi.yaml +++ b/dts/Bindings/display/st,stm32-dsi.yaml @@ -58,9 +58,20 @@ properties: DSI input port node, connected to the ltdc rgb output port. port@1: - $ref: /schemas/graph.yaml#/properties/port - description: - DSI output port node, connected to a panel or a bridge input port" + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: | + DSI output port node, connected to a panel or a bridge input port. + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + properties: + data-lanes: + minItems: 1 + items: + - const: 1 + - const: 2 required: - "#address-cells" diff --git a/dts/Bindings/display/tegra/nvidia,tegra20-gr3d.yaml b/dts/Bindings/display/tegra/nvidia,tegra20-gr3d.yaml index dbdf0229d9..4755a73473 100644 --- a/dts/Bindings/display/tegra/nvidia,tegra20-gr3d.yaml +++ b/dts/Bindings/display/tegra/nvidia,tegra20-gr3d.yaml @@ -59,7 +59,6 @@ properties: maxItems: 2 power-domain-names: - minItems: 2 maxItems: 2 allOf: diff --git a/dts/Bindings/display/tegra/nvidia,tegra20-mpe.yaml b/dts/Bindings/display/tegra/nvidia,tegra20-mpe.yaml index 4154ae01ad..5f4f0fb4b6 100644 --- a/dts/Bindings/display/tegra/nvidia,tegra20-mpe.yaml +++ b/dts/Bindings/display/tegra/nvidia,tegra20-mpe.yaml @@ -42,11 +42,9 @@ properties: maxItems: 1 interconnects: - minItems: 6 maxItems: 6 interconnect-names: - minItems: 6 maxItems: 6 operating-points-v2: diff --git a/dts/Bindings/dma/allwinner,sun4i-a10-dma.yaml b/dts/Bindings/dma/allwinner,sun4i-a10-dma.yaml index 8380819965..26d0d8ab79 100644 --- a/dts/Bindings/dma/allwinner,sun4i-a10-dma.yaml +++ b/dts/Bindings/dma/allwinner,sun4i-a10-dma.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/dma/allwinner,sun4i-a10-dma.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 DMA Controller Device Tree Bindings +title: Allwinner A10 DMA Controller maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/dma/allwinner,sun50i-a64-dma.yaml b/dts/Bindings/dma/allwinner,sun50i-a64-dma.yaml index e712444abf..bd599bda26 100644 --- a/dts/Bindings/dma/allwinner,sun50i-a64-dma.yaml +++ b/dts/Bindings/dma/allwinner,sun50i-a64-dma.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/dma/allwinner,sun50i-a64-dma.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A64 DMA Controller Device Tree Bindings +title: Allwinner A64 DMA Controller maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/dma/allwinner,sun6i-a31-dma.yaml b/dts/Bindings/dma/allwinner,sun6i-a31-dma.yaml index a6df6f8b54..344dc7e049 100644 --- a/dts/Bindings/dma/allwinner,sun6i-a31-dma.yaml +++ b/dts/Bindings/dma/allwinner,sun6i-a31-dma.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/dma/allwinner,sun6i-a31-dma.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A31 DMA Controller Device Tree Bindings +title: Allwinner A31 DMA Controller maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/dma/apple,admac.yaml b/dts/Bindings/dma/apple,admac.yaml index bdc8c129c4..3b1e667f7e 100644 --- a/dts/Bindings/dma/apple,admac.yaml +++ b/dts/Bindings/dma/apple,admac.yaml @@ -49,6 +49,13 @@ properties: in an interrupts-extended list the disconnected positions will contain an empty phandle reference <0>. + iommus: + minItems: 1 + maxItems: 2 + + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/dts/Bindings/dma/arm,pl330.yaml b/dts/Bindings/dma/arm,pl330.yaml index 2bec69b308..4a3dd6f530 100644 --- a/dts/Bindings/dma/arm,pl330.yaml +++ b/dts/Bindings/dma/arm,pl330.yaml @@ -55,6 +55,12 @@ properties: dma-coherent: true + iommus: + minItems: 1 + maxItems: 9 + description: Up to 1 IOMMU entry per DMA channel for writes and 1 + IOMMU entry for reads. + power-domains: maxItems: 1 diff --git a/dts/Bindings/dma/mediatek,uart-dma.yaml b/dts/Bindings/dma/mediatek,uart-dma.yaml index 19ea8dcbcb..9ab4d81ead 100644 --- a/dts/Bindings/dma/mediatek,uart-dma.yaml +++ b/dts/Bindings/dma/mediatek,uart-dma.yaml @@ -22,6 +22,7 @@ properties: - items: - enum: - mediatek,mt2712-uart-dma + - mediatek,mt6795-uart-dma - mediatek,mt8365-uart-dma - mediatek,mt8516-uart-dma - const: mediatek,mt6577-uart-dma diff --git a/dts/Bindings/dma/nvidia,tegra186-gpc-dma.yaml b/dts/Bindings/dma/nvidia,tegra186-gpc-dma.yaml index 7e575296df..c8894476b6 100644 --- a/dts/Bindings/dma/nvidia,tegra186-gpc-dma.yaml +++ b/dts/Bindings/dma/nvidia,tegra186-gpc-dma.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: NVIDIA Tegra GPC DMA Controller Device Tree Bindings +title: NVIDIA Tegra GPC DMA Controller description: | The Tegra General Purpose Central (GPC) DMA controller is used for faster diff --git a/dts/Bindings/dma/qcom,adm.yaml b/dts/Bindings/dma/qcom,adm.yaml new file mode 100644 index 0000000000..6a9d7bc74a --- /dev/null +++ b/dts/Bindings/dma/qcom,adm.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/qcom,adm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm ADM DMA Controller + +maintainers: + - Christian Marangi <ansuelsmth@gmail.com> + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: | + QCOM ADM DMA controller provides DMA capabilities for + peripheral buses such as NAND and SPI. + +properties: + compatible: + const: qcom,adm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#dma-cells": + const: 1 + + clocks: + items: + - description: phandle to the core clock + - description: phandle to the iface clock + + clock-names: + items: + - const: core + - const: iface + + resets: + items: + - description: phandle to the clk reset + - description: phandle to the pbus reset + - description: phandle to the c0 reset + - description: phandle to the c1 reset + - description: phandle to the c2 reset + + reset-names: + items: + - const: clk + - const: pbus + - const: c0 + - const: c1 + - const: c2 + + qcom,ee: + $ref: /schemas/types.yaml#/definitions/uint32 + description: indicates the security domain identifier used in the secure world. + minimum: 0 + maximum: 255 + +required: + - compatible + - reg + - interrupts + - "#dma-cells" + - clocks + - clock-names + - resets + - reset-names + - qcom,ee + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-ipq806x.h> + #include <dt-bindings/reset/qcom,gcc-ipq806x.h> + + adm_dma: dma-controller@18300000 { + compatible = "qcom,adm"; + reg = <0x18300000 0x100000>; + interrupts = <0 170 0>; + #dma-cells = <1>; + + clocks = <&gcc ADM0_CLK>, + <&gcc ADM0_PBUS_CLK>; + clock-names = "core", "iface"; + + resets = <&gcc ADM0_RESET>, + <&gcc ADM0_PBUS_RESET>, + <&gcc ADM0_C0_RESET>, + <&gcc ADM0_C1_RESET>, + <&gcc ADM0_C2_RESET>; + reset-names = "clk", "pbus", "c0", "c1", "c2"; + qcom,ee = <0>; + }; + +... diff --git a/dts/Bindings/dma/qcom,bam-dma.yaml b/dts/Bindings/dma/qcom,bam-dma.yaml index 9bf3a1b164..003098caf7 100644 --- a/dts/Bindings/dma/qcom,bam-dma.yaml +++ b/dts/Bindings/dma/qcom,bam-dma.yaml @@ -8,7 +8,7 @@ title: Qualcomm Technologies Inc BAM DMA controller maintainers: - Andy Gross <agross@kernel.org> - - Bjorn Andersson <bjorn.andersson@linaro.org> + - Bjorn Andersson <andersson@kernel.org> allOf: - $ref: "dma-controller.yaml#" @@ -20,7 +20,7 @@ properties: - qcom,bam-v1.3.0 # MSM8974, APQ8074 and APQ8084 - qcom,bam-v1.4.0 - # MSM8916 + # MSM8916 and SDM845 - qcom,bam-v1.7.0 clocks: @@ -90,8 +90,8 @@ examples: dma-controller@f9944000 { compatible = "qcom,bam-v1.4.0"; - reg = <0xf9944000 0x15000>; - interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xf9944000 0x19000>; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "bam_clk"; #dma-cells = <1>; diff --git a/dts/Bindings/dma/qcom,gpi.yaml b/dts/Bindings/dma/qcom,gpi.yaml index 7d2fc4eb55..eabf8a76d3 100644 --- a/dts/Bindings/dma/qcom,gpi.yaml +++ b/dts/Bindings/dma/qcom,gpi.yaml @@ -21,6 +21,7 @@ properties: enum: - qcom,sc7280-gpi-dma - qcom,sdm845-gpi-dma + - qcom,sm6350-gpi-dma - qcom,sm8150-gpi-dma - qcom,sm8250-gpi-dma - qcom,sm8350-gpi-dma diff --git a/dts/Bindings/dma/qcom_adm.txt b/dts/Bindings/dma/qcom_adm.txt deleted file mode 100644 index 9d3b2f917b..0000000000 --- a/dts/Bindings/dma/qcom_adm.txt +++ /dev/null @@ -1,61 +0,0 @@ -QCOM ADM DMA Controller - -Required properties: -- compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960 -- reg: Address range for DMA registers -- interrupts: Should contain one interrupt shared by all channels -- #dma-cells: must be <2>. First cell denotes the channel number. Second cell - denotes CRCI (client rate control interface) flow control assignment. -- clocks: Should contain the core clock and interface clock. -- clock-names: Must contain "core" for the core clock and "iface" for the - interface clock. -- resets: Must contain an entry for each entry in reset names. -- reset-names: Must include the following entries: - - clk - - c0 - - c1 - - c2 -- qcom,ee: indicates the security domain identifier used in the secure world. - -Example: - adm_dma: dma@18300000 { - compatible = "qcom,adm"; - reg = <0x18300000 0x100000>; - interrupts = <0 170 0>; - #dma-cells = <2>; - - clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; - clock-names = "core", "iface"; - - resets = <&gcc ADM0_RESET>, - <&gcc ADM0_C0_RESET>, - <&gcc ADM0_C1_RESET>, - <&gcc ADM0_C2_RESET>; - reset-names = "clk", "c0", "c1", "c2"; - qcom,ee = <0>; - }; - -DMA clients must use the format descripted in the dma.txt file, using a three -cell specifier for each channel. - -Each dmas request consists of 3 cells: - 1. phandle pointing to the DMA controller - 2. channel number - 3. CRCI assignment, if applicable. If no CRCI flow control is required, use 0. - The CRCI is used for flow control. It identifies the peripheral device that - is the source/destination for the transferred data. - -Example: - - spi4: spi@1a280000 { - spi-max-frequency = <50000000>; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 0>; - - dmas = <&adm_dma 6 9>, - <&adm_dma 5 10>; - dma-names = "rx", "tx"; - }; diff --git a/dts/Bindings/dma/renesas,rcar-dmac.yaml b/dts/Bindings/dma/renesas,rcar-dmac.yaml index 7202cd68e7..89b591a05b 100644 --- a/dts/Bindings/dma/renesas,rcar-dmac.yaml +++ b/dts/Bindings/dma/renesas,rcar-dmac.yaml @@ -45,6 +45,7 @@ properties: - enum: - renesas,dmac-r8a779a0 # R-Car V3U - renesas,dmac-r8a779f0 # R-Car S4-8 + - renesas,dmac-r8a779g0 # R-Car V4H - const: renesas,rcar-gen4-dmac # R-Car Gen4 reg: true diff --git a/dts/Bindings/dma/ti-dma-crossbar.txt b/dts/Bindings/dma/ti-dma-crossbar.txt index b849a1ed38..47e477cce6 100644 --- a/dts/Bindings/dma/ti-dma-crossbar.txt +++ b/dts/Bindings/dma/ti-dma-crossbar.txt @@ -4,7 +4,7 @@ Required properties: - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar "ti,am335x-edma-crossbar" for AM335x and AM437x - reg: Memory map for accessing module -- #dma-cells: Should be set to to match with the DMA controller's dma-cells +- #dma-cells: Should be set to match with the DMA controller's dma-cells for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar. - dma-requests: Number of DMA requests the crossbar can receive - dma-masters: phandle pointing to the DMA controller diff --git a/dts/Bindings/dsp/fsl,dsp.yaml b/dts/Bindings/dsp/fsl,dsp.yaml index e66ef2da78..9af40da568 100644 --- a/dts/Bindings/dsp/fsl,dsp.yaml +++ b/dts/Bindings/dsp/fsl,dsp.yaml @@ -20,6 +20,7 @@ properties: - fsl,imx8qxp-dsp - fsl,imx8qm-dsp - fsl,imx8mp-dsp + - fsl,imx8ulp-dsp - fsl,imx8qxp-hifi4 - fsl,imx8qm-hifi4 - fsl,imx8mp-hifi4 diff --git a/dts/Bindings/firmware/fsl,scu.yaml b/dts/Bindings/firmware/fsl,scu.yaml index b40b0ef569..557e524786 100644 --- a/dts/Bindings/firmware/fsl,scu.yaml +++ b/dts/Bindings/firmware/fsl,scu.yaml @@ -30,6 +30,11 @@ properties: Clock controller node that provides the clocks controlled by the SCU $ref: /schemas/clock/fsl,scu-clk.yaml + gpio: + description: + Control the GPIO PINs on SCU domain over the firmware APIs + $ref: /schemas/gpio/fsl,imx8qxp-sc-gpio.yaml + ocotp: description: OCOTP controller node provided by the SCU diff --git a/dts/Bindings/firmware/qcom,scm.txt b/dts/Bindings/firmware/qcom,scm.txt deleted file mode 100644 index b3f702cbed..0000000000 --- a/dts/Bindings/firmware/qcom,scm.txt +++ /dev/null @@ -1,61 +0,0 @@ -QCOM Secure Channel Manager (SCM) - -Qualcomm processors include an interface to communicate to the secure firmware. -This interface allows for clients to request different types of actions. These -can include CPU power up/down, HDCP requests, loading of firmware, and other -assorted actions. - -Required properties: -- compatible: must contain one of the following: - * "qcom,scm-apq8064" - * "qcom,scm-apq8084" - * "qcom,scm-ipq4019" - * "qcom,scm-ipq806x" - * "qcom,scm-ipq8074" - * "qcom,scm-mdm9607" - * "qcom,scm-msm8226" - * "qcom,scm-msm8660" - * "qcom,scm-msm8916" - * "qcom,scm-msm8953" - * "qcom,scm-msm8960" - * "qcom,scm-msm8974" - * "qcom,scm-msm8976" - * "qcom,scm-msm8994" - * "qcom,scm-msm8996" - * "qcom,scm-msm8998" - * "qcom,scm-qcs404" - * "qcom,scm-sc7180" - * "qcom,scm-sc7280" - * "qcom,scm-sm6125" - * "qcom,scm-sdm845" - * "qcom,scm-sdx55" - * "qcom,scm-sdx65" - * "qcom,scm-sm6350" - * "qcom,scm-sm8150" - * "qcom,scm-sm8250" - * "qcom,scm-sm8350" - * "qcom,scm-sm8450" - and: - * "qcom,scm" -- clocks: Specifies clocks needed by the SCM interface, if any: - * core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660" and - "qcom,scm-msm8960" - * core, iface and bus clocks required for "qcom,scm-apq8084", - "qcom,scm-msm8916", "qcom,scm-msm8953", "qcom,scm-msm8974" and "qcom,scm-msm8976" -- clock-names: Must contain "core" for the core clock, "iface" for the interface - clock and "bus" for the bus clock per the requirements of the compatible. -- qcom,dload-mode: phandle to the TCSR hardware block and offset of the - download mode control register (optional) -- interconnects: Specifies the bandwidth requirements of the SCM interface (optional) - -Example for MSM8916: - - firmware { - scm { - compatible = "qcom,msm8916", "qcom,scm"; - clocks = <&gcc GCC_CRYPTO_CLK> , - <&gcc GCC_CRYPTO_AXI_CLK>, - <&gcc GCC_CRYPTO_AHB_CLK>; - clock-names = "core", "bus", "iface"; - }; - }; diff --git a/dts/Bindings/firmware/qcom,scm.yaml b/dts/Bindings/firmware/qcom,scm.yaml new file mode 100644 index 0000000000..c5b76c9f7a --- /dev/null +++ b/dts/Bindings/firmware/qcom,scm.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/qcom,scm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QCOM Secure Channel Manager (SCM) + +description: | + Qualcomm processors include an interface to communicate to the secure firmware. + This interface allows for clients to request different types of actions. + These can include CPU power up/down, HDCP requests, loading of firmware, + and other assorted actions. + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + - Robert Marko <robimarko@gmail.com> + - Guru Das Srinagesh <quic_gurus@quicinc.com> + +properties: + compatible: + items: + - enum: + - qcom,scm-apq8064 + - qcom,scm-apq8084 + - qcom,scm-ipq4019 + - qcom,scm-ipq6018 + - qcom,scm-ipq806x + - qcom,scm-ipq8074 + - qcom,scm-mdm9607 + - qcom,scm-msm8226 + - qcom,scm-msm8660 + - qcom,scm-msm8916 + - qcom,scm-msm8953 + - qcom,scm-msm8960 + - qcom,scm-msm8974 + - qcom,scm-msm8976 + - qcom,scm-msm8994 + - qcom,scm-msm8996 + - qcom,scm-msm8998 + - qcom,scm-sc7180 + - qcom,scm-sc7280 + - qcom,scm-sc8280xp + - qcom,scm-sdm845 + - qcom,scm-sdx55 + - qcom,scm-sdx65 + - qcom,scm-sm6115 + - qcom,scm-sm6125 + - qcom,scm-sm6350 + - qcom,scm-sm8150 + - qcom,scm-sm8250 + - qcom,scm-sm8350 + - qcom,scm-sm8450 + - qcom,scm-qcs404 + - const: qcom,scm + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + minItems: 1 + maxItems: 3 + + interconnects: + maxItems: 1 + + interconnect-names: + maxItems: 1 + + '#reset-cells': + const: 1 + + qcom,dload-mode: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to TCSR hardware block + - description: offset of the download mode control register + description: TCSR hardware block + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,scm-apq8064 + - qcom,scm-msm8660 + - qcom,scm-msm8960 + then: + properties: + clock-names: + items: + - const: core + + clocks: + maxItems: 1 + + required: + - clocks + - clock-names + + - if: + properties: + compatible: + contains: + enum: + - qcom,scm-apq8084 + - qcom,scm-mdm9607 + - qcom,scm-msm8916 + - qcom,scm-msm8953 + - qcom,scm-msm8974 + - qcom,scm-msm8976 + then: + properties: + clock-names: + items: + - const: core + - const: bus + - const: iface + + clocks: + minItems: 3 + maxItems: 3 + + required: + - clocks + - clock-names + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-msm8916.h> + + firmware { + scm { + compatible = "qcom,scm-msm8916", "qcom,scm"; + clocks = <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "core", "bus", "iface"; + }; + }; diff --git a/dts/Bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml b/dts/Bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml index aee45cb155..527532f039 100644 --- a/dts/Bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml +++ b/dts/Bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml @@ -22,13 +22,14 @@ properties: description: SPI chip select maxItems: 1 - spi-max-frequency: true - required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/fpga/xilinx-zynq-fpga-mgr.yaml b/dts/Bindings/fpga/xilinx-zynq-fpga-mgr.yaml index 29daca4be4..f47b6140a7 100644 --- a/dts/Bindings/fpga/xilinx-zynq-fpga-mgr.yaml +++ b/dts/Bindings/fpga/xilinx-zynq-fpga-mgr.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/fpga/xilinx-zynq-fpga-mgr.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Xilinx Zynq FPGA Manager Device Tree Bindings +title: Xilinx Zynq FPGA Manager maintainers: - Michal Simek <michal.simek@xilinx.com> diff --git a/dts/Bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml b/dts/Bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml index 6cd2bdc06b..00a8d92ff7 100644 --- a/dts/Bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml +++ b/dts/Bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Xilinx Zynq Ultrascale MPSoC FPGA Manager Device Tree Bindings +title: Xilinx Zynq Ultrascale MPSoC FPGA Manager maintainers: - Nava kishore Manne <navam@xilinx.com> diff --git a/dts/Bindings/gnss/brcm,bcm4751.yaml b/dts/Bindings/gnss/brcm,bcm4751.yaml index e62b30386a..c21549e0fb 100644 --- a/dts/Bindings/gnss/brcm,bcm4751.yaml +++ b/dts/Bindings/gnss/brcm,bcm4751.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/gnss/brcm,bcm4751.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Broadcom BCM4751 family GNSS Receiver Device Tree Bindings +title: Broadcom BCM4751 family GNSS Receiver maintainers: - Johan Hovold <johan@kernel.org> diff --git a/dts/Bindings/gnss/mediatek.yaml b/dts/Bindings/gnss/mediatek.yaml index 45cf01b277..c0eb35beb2 100644 --- a/dts/Bindings/gnss/mediatek.yaml +++ b/dts/Bindings/gnss/mediatek.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/gnss/mediatek.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek GNSS Receiver Device Tree Bindings +title: Mediatek GNSS Receiver maintainers: - Johan Hovold <johan@kernel.org> diff --git a/dts/Bindings/gnss/sirfstar.yaml b/dts/Bindings/gnss/sirfstar.yaml index 991599cdaa..0bbe684d82 100644 --- a/dts/Bindings/gnss/sirfstar.yaml +++ b/dts/Bindings/gnss/sirfstar.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/gnss/sirfstar.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: SiRFstar GNSS Receiver Device Tree Bindings +title: SiRFstar GNSS Receiver maintainers: - Johan Hovold <johan@kernel.org> diff --git a/dts/Bindings/gnss/u-blox,neo-6m.yaml b/dts/Bindings/gnss/u-blox,neo-6m.yaml index 35a760cfd3..4835a280b3 100644 --- a/dts/Bindings/gnss/u-blox,neo-6m.yaml +++ b/dts/Bindings/gnss/u-blox,neo-6m.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/gnss/u-blox,neo-6m.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: U-blox GNSS Receiver Device Tree Bindings +title: U-blox GNSS Receiver allOf: - $ref: gnss-common.yaml# diff --git a/dts/Bindings/gpio/fairchild,74hc595.yaml b/dts/Bindings/gpio/fairchild,74hc595.yaml index a99e7842ca..c0ad70e66f 100644 --- a/dts/Bindings/gpio/fairchild,74hc595.yaml +++ b/dts/Bindings/gpio/fairchild,74hc595.yaml @@ -33,8 +33,6 @@ properties: description: GPIO connected to the OE (Output Enable) pin. maxItems: 1 - spi-max-frequency: true - patternProperties: "^(hog-[0-9]+|.+-hog(-[0-9]+)?)$": type: object @@ -59,7 +57,10 @@ required: - '#gpio-cells' - registers-number -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/gpio/fsl,imx8qxp-sc-gpio.yaml b/dts/Bindings/gpio/fsl,imx8qxp-sc-gpio.yaml new file mode 100644 index 0000000000..b7b3222093 --- /dev/null +++ b/dts/Bindings/gpio/fsl,imx8qxp-sc-gpio.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/fsl,imx8qxp-sc-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GPIO driver over IMX SCU firmware API + +maintainers: + - Shenwei Wang <shenwei.wang@nxp.com> + +description: | + This module provides the standard interface to control the + resource pins in SCU domain on i.MX8 platforms. + +properties: + compatible: + enum: + - fsl,imx8qxp-sc-gpio + + "#gpio-cells": + const: 2 + + gpio-controller: true + +required: + - compatible + - "#gpio-cells" + - gpio-controller + +additionalProperties: false + +examples: + - | + gpio0: gpio { + compatible = "fsl,imx8qxp-sc-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; diff --git a/dts/Bindings/gpio/gpio-pca95xx.yaml b/dts/Bindings/gpio/gpio-pca95xx.yaml index 977b14db09..1b70e9f308 100644 --- a/dts/Bindings/gpio/gpio-pca95xx.yaml +++ b/dts/Bindings/gpio/gpio-pca95xx.yaml @@ -15,52 +15,59 @@ description: |+ properties: compatible: - enum: - - exar,xra1202 - - maxim,max7310 - - maxim,max7312 - - maxim,max7313 - - maxim,max7315 - - maxim,max7319 - - maxim,max7320 - - maxim,max7321 - - maxim,max7322 - - maxim,max7323 - - maxim,max7324 - - maxim,max7325 - - maxim,max7326 - - maxim,max7327 - - nxp,pca6408 - - nxp,pca6416 - - nxp,pca9505 - - nxp,pca9506 - - nxp,pca9534 - - nxp,pca9535 - - nxp,pca9536 - - nxp,pca9537 - - nxp,pca9538 - - nxp,pca9539 - - nxp,pca9554 - - nxp,pca9555 - - nxp,pca9556 - - nxp,pca9557 - - nxp,pca9574 - - nxp,pca9575 - - nxp,pca9698 - - nxp,pcal6416 - - nxp,pcal6524 - - nxp,pcal9535 - - nxp,pcal9554b - - nxp,pcal9555a - - onnn,cat9554 - - onnn,pca9654 - - ti,pca6107 - - ti,pca9536 - - ti,tca6408 - - ti,tca6416 - - ti,tca6424 - - ti,tca9539 - - ti,tca9554 + oneOf: + - items: + - const: diodes,pi4ioe5v6534q + - const: nxp,pcal6534 + - items: + - enum: + - exar,xra1202 + - maxim,max7310 + - maxim,max7312 + - maxim,max7313 + - maxim,max7315 + - maxim,max7319 + - maxim,max7320 + - maxim,max7321 + - maxim,max7322 + - maxim,max7323 + - maxim,max7324 + - maxim,max7325 + - maxim,max7326 + - maxim,max7327 + - nxp,pca6408 + - nxp,pca6416 + - nxp,pca9505 + - nxp,pca9506 + - nxp,pca9534 + - nxp,pca9535 + - nxp,pca9536 + - nxp,pca9537 + - nxp,pca9538 + - nxp,pca9539 + - nxp,pca9554 + - nxp,pca9555 + - nxp,pca9556 + - nxp,pca9557 + - nxp,pca9574 + - nxp,pca9575 + - nxp,pca9698 + - nxp,pcal6408 + - nxp,pcal6416 + - nxp,pcal6524 + - nxp,pcal6534 + - nxp,pcal9535 + - nxp,pcal9554b + - nxp,pcal9555a + - onnn,cat9554 + - onnn,pca9654 + - ti,pca6107 + - ti,pca9536 + - ti,tca6408 + - ti,tca6416 + - ti,tca6424 + - ti,tca9539 + - ti,tca9554 reg: maxItems: 1 diff --git a/dts/Bindings/gpio/gpio-stmpe.txt b/dts/Bindings/gpio/gpio-stmpe.txt index a0e4cf8852..b33f8f02c0 100644 --- a/dts/Bindings/gpio/gpio-stmpe.txt +++ b/dts/Bindings/gpio/gpio-stmpe.txt @@ -8,8 +8,7 @@ Optional properties: - st,norequest-mask: bitmask specifying which GPIOs should _not_ be requestable due to different usage (e.g. touch, keypad) -Node name must be stmpe_gpio and should be child node of stmpe node to which it -belongs. +Node should be child node of stmpe node to which it belongs. Example: stmpe_gpio { diff --git a/dts/Bindings/gpio/gpio-xilinx.txt b/dts/Bindings/gpio/gpio-xilinx.txt deleted file mode 100644 index e506f30e1a..0000000000 --- a/dts/Bindings/gpio/gpio-xilinx.txt +++ /dev/null @@ -1,48 +0,0 @@ -Xilinx plb/axi GPIO controller - -Dual channel GPIO controller with configurable number of pins -(from 1 to 32 per channel). Every pin can be configured as -input/output/tristate. Both channels share the same global IRQ but -local interrupts can be enabled on channel basis. - -Required properties: -- compatible : Should be "xlnx,xps-gpio-1.00.a" -- reg : Address and length of the register set for the device -- #gpio-cells : Should be two. The first cell is the pin number and the - second cell is used to specify optional parameters (currently unused). -- gpio-controller : Marks the device node as a GPIO controller. - -Optional properties: -- clocks : Input clock specifier. Refer to common clock bindings. -- interrupts : Interrupt mapping for GPIO IRQ. -- xlnx,all-inputs : if n-th bit is setup, GPIO-n is input -- xlnx,dout-default : if n-th bit is 1, GPIO-n default value is 1 -- xlnx,gpio-width : gpio width -- xlnx,tri-default : if n-th bit is 1, GPIO-n is in tristate mode -- xlnx,is-dual : if 1, controller also uses the second channel -- xlnx,all-inputs-2 : as above but for the second channel -- xlnx,dout-default-2 : as above but the second channel -- xlnx,gpio2-width : as above but for the second channel -- xlnx,tri-default-2 : as above but for the second channel - - -Example: -gpio: gpio@40000000 { - #gpio-cells = <2>; - compatible = "xlnx,xps-gpio-1.00.a"; - clocks = <&clkc25>; - gpio-controller ; - interrupt-parent = <µblaze_0_intc>; - interrupts = < 6 2 >; - reg = < 0x40000000 0x10000 >; - xlnx,all-inputs = <0x0>; - xlnx,all-inputs-2 = <0x0>; - xlnx,dout-default = <0x0>; - xlnx,dout-default-2 = <0x0>; - xlnx,gpio-width = <0x2>; - xlnx,gpio2-width = <0x2>; - xlnx,interrupt-present = <0x1>; - xlnx,is-dual = <0x1>; - xlnx,tri-default = <0xffffffff>; - xlnx,tri-default-2 = <0xffffffff>; -} ; diff --git a/dts/Bindings/gpio/gpio-zynq.yaml b/dts/Bindings/gpio/gpio-zynq.yaml index 29c27eadba..572e1718f5 100644 --- a/dts/Bindings/gpio/gpio-zynq.yaml +++ b/dts/Bindings/gpio/gpio-zynq.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/gpio/gpio-zynq.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Xilinx Zynq GPIO controller Device Tree Bindings +title: Xilinx Zynq GPIO controller maintainers: - Michal Simek <michal.simek@xilinx.com> diff --git a/dts/Bindings/gpio/microchip,mpfs-gpio.yaml b/dts/Bindings/gpio/microchip,mpfs-gpio.yaml index 110651eafa..d481e78958 100644 --- a/dts/Bindings/gpio/microchip,mpfs-gpio.yaml +++ b/dts/Bindings/gpio/microchip,mpfs-gpio.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Microchip MPFS GPIO Controller Device Tree Bindings +title: Microchip MPFS GPIO Controller maintainers: - Conor Dooley <conor.dooley@microchip.com> @@ -44,6 +44,24 @@ properties: gpio-controller: true +patternProperties: + "^.+-hog(-[0-9]+)?$": + type: object + + additionalProperties: false + + properties: + gpio-hog: true + gpios: true + input: true + output-high: true + output-low: true + line-name: true + + required: + - gpio-hog + - gpios + required: - compatible - reg diff --git a/dts/Bindings/gpio/renesas,rcar-gpio.yaml b/dts/Bindings/gpio/renesas,rcar-gpio.yaml index 75e5da6a7c..aa424e2b95 100644 --- a/dts/Bindings/gpio/renesas,rcar-gpio.yaml +++ b/dts/Bindings/gpio/renesas,rcar-gpio.yaml @@ -52,6 +52,7 @@ properties: - enum: - renesas,gpio-r8a779a0 # R-Car V3U - renesas,gpio-r8a779f0 # R-Car S4-8 + - renesas,gpio-r8a779g0 # R-Car V4H - const: renesas,rcar-gen4-gpio # R-Car Gen4 reg: diff --git a/dts/Bindings/gpio/x-powers,axp209-gpio.yaml b/dts/Bindings/gpio/x-powers,axp209-gpio.yaml index 14486aee97..7f26f6b1ee 100644 --- a/dts/Bindings/gpio/x-powers,axp209-gpio.yaml +++ b/dts/Bindings/gpio/x-powers,axp209-gpio.yaml @@ -4,7 +4,7 @@ $id: "http://devicetree.org/schemas/gpio/x-powers,axp209-gpio.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: X-Powers AXP209 GPIO Device Tree Bindings +title: X-Powers AXP209 GPIO maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/gpio/xlnx,gpio-xilinx.yaml b/dts/Bindings/gpio/xlnx,gpio-xilinx.yaml new file mode 100644 index 0000000000..f333ee2288 --- /dev/null +++ b/dts/Bindings/gpio/xlnx,gpio-xilinx.yaml @@ -0,0 +1,154 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/xlnx,gpio-xilinx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx AXI GPIO controller + +maintainers: + - Neeli Srinivas <srinivas.neeli@xilinx.com> + +description: + The AXI GPIO design provides a general purpose input/output interface + to an AXI4-Lite interface. The AXI GPIO can be configured as either + a single or a dual-channel device. The width of each channel is + independently configurable. The channels can be configured to + generate an interrupt when a transition on any of their inputs occurs. + +properties: + compatible: + enum: + - xlnx,xps-gpio-1.00.a + + reg: + maxItems: 1 + + "#gpio-cells": + const: 2 + + interrupts: + maxItems: 1 + + gpio-controller: true + + gpio-line-names: + description: strings describing the names of each gpio line + minItems: 1 + maxItems: 64 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + clocks: + maxItems: 1 + + interrupt-names: true + + xlnx,all-inputs: + $ref: /schemas/types.yaml#/definitions/uint32 + description: This option sets this GPIO channel1 bits in input mode. + + xlnx,all-inputs-2: + $ref: /schemas/types.yaml#/definitions/uint32 + description: This option sets this GPIO channel2 bits in input mode. + + xlnx,all-outputs: + $ref: /schemas/types.yaml#/definitions/uint32 + description: This option sets this GPIO channel1 bits in output mode. + + xlnx,all-outputs-2: + $ref: /schemas/types.yaml#/definitions/uint32 + description: This option sets this GPIO channel2 bits in output mode. + + xlnx,dout-default: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Sets the default value of all the enabled bits of + channel1. + default: 0 + + xlnx,dout-default-2: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Sets the default value of all the enabled bits of + channel2. + default: 0 + + xlnx,gpio-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The value defines the bit width of the GPIO channel1. + minimum: 1 + maximum: 32 + default: 32 + + xlnx,gpio2-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The value defines the bit width of the GPIO channel2. + minimum: 1 + maximum: 32 + default: 32 + + xlnx,interrupt-present: + $ref: /schemas/types.yaml#/definitions/uint32 + description: This parameter enables interrupt control logic + and interrupt registers in GPIO module. + minimum: 0 + maximum: 1 + default: 0 + + xlnx,is-dual: + $ref: /schemas/types.yaml#/definitions/uint32 + description: This parameter enables a second GPIO channel (GPIO2). + minimum: 0 + maximum: 1 + default: 0 + + xlnx,tri-default: + $ref: /schemas/types.yaml#/definitions/uint32 + description: This value configures the input or output mode + of each bit of GPIO channel1. + + xlnx,tri-default-2: + $ref: /schemas/types.yaml#/definitions/uint32 + description: This value configures the input or output mode + of each bit of GPIO channel2. + +required: + - reg + - compatible + - gpio-controller + - "#gpio-cells" + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + gpio@e000a000 { + compatible = "xlnx,xps-gpio-1.00.a"; + reg = <0xa0020000 0x10000>; + #gpio-cells = <2>; + #interrupt-cells = <0x2>; + clocks = <&zynqmp_clk 71>; + gpio-controller; + interrupt-controller; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&gic>; + interrupts = <0 89 4>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x0>; + xlnx,dout-default-2 = <0x0>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x1>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + +... diff --git a/dts/Bindings/gpu/arm,mali-midgard.yaml b/dts/Bindings/gpu/arm,mali-midgard.yaml index d209f27262..2a25384ca3 100644 --- a/dts/Bindings/gpu/arm,mali-midgard.yaml +++ b/dts/Bindings/gpu/arm,mali-midgard.yaml @@ -74,7 +74,8 @@ properties: - const: bus mali-supply: true - opp-table: true + opp-table: + type: object power-domains: maxItems: 1 diff --git a/dts/Bindings/gpu/arm,mali-utgard.yaml b/dts/Bindings/gpu/arm,mali-utgard.yaml index eceaa176bd..318122d95e 100644 --- a/dts/Bindings/gpu/arm,mali-utgard.yaml +++ b/dts/Bindings/gpu/arm,mali-utgard.yaml @@ -101,7 +101,8 @@ properties: mali-supply: true - opp-table: true + opp-table: + type: object power-domains: maxItems: 1 diff --git a/dts/Bindings/hwmon/adi,axi-fan-control.yaml b/dts/Bindings/hwmon/adi,axi-fan-control.yaml index 6747b870f2..f2f99afb3a 100644 --- a/dts/Bindings/hwmon/adi,axi-fan-control.yaml +++ b/dts/Bindings/hwmon/adi,axi-fan-control.yaml @@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/hwmon/adi,axi-fan-control.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Analog Devices AXI FAN Control Device Tree Bindings +title: Analog Devices AXI FAN Control maintainers: - Nuno Sá <nuno.sa@analog.com> diff --git a/dts/Bindings/hwmon/adi,max31760.yaml b/dts/Bindings/hwmon/adi,max31760.yaml new file mode 100644 index 0000000000..9f2d08d7b9 --- /dev/null +++ b/dts/Bindings/hwmon/adi,max31760.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/adi,max31760.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices MAX31760 Fan-Speed Controller + +maintainers: + - Ibrahim Tilki <Ibrahim.Tilki@analog.com> + +description: | + Analog Devices MAX31760 Fan-Speed Controller + https://datasheets.maximintegrated.com/en/ds/MAX31760.pdf + +properties: + compatible: + enum: + - adi,max31760 + + reg: + description: I2C address of slave device. + minimum: 0x50 + maximum: 0x57 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + fan-controller@50 { + reg = <0x50>; + compatible = "adi,max31760"; + }; + }; diff --git a/dts/Bindings/hwmon/ibm,occ-hwmon.yaml b/dts/Bindings/hwmon/ibm,occ-hwmon.yaml new file mode 100644 index 0000000000..3dbdc5af28 --- /dev/null +++ b/dts/Bindings/hwmon/ibm,occ-hwmon.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/ibm,occ-hwmon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IBM On-Chip Controller (OCC) accessed from a service processor + +maintainers: + - Eddie James <eajames@linux.ibm.com> + +description: | + The POWER processor On-Chip Controller (OCC) helps manage power and + thermals for the system. A service processor or baseboard management + controller can query the OCC for it's power and thermal data to report + through hwmon. + +properties: + compatible: + enum: + - ibm,p9-occ-hwmon + - ibm,p10-occ-hwmon + + ibm,no-poll-on-init: + description: This property describes whether or not the OCC should + be polled during driver initialization. + type: boolean + +required: + - compatible + +additionalProperties: false + +examples: + - | + hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; diff --git a/dts/Bindings/hwmon/iio-hwmon.yaml b/dts/Bindings/hwmon/iio-hwmon.yaml index f5a6cc3efd..e1ccbd30e0 100644 --- a/dts/Bindings/hwmon/iio-hwmon.yaml +++ b/dts/Bindings/hwmon/iio-hwmon.yaml @@ -4,7 +4,7 @@ $id: "http://devicetree.org/schemas/hwmon/iio-hwmon.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: ADC-attached Hardware Sensor Device Tree Bindings +title: ADC-attached Hardware Sensor maintainers: - Jonathan Cameron <jic23@kernel.org> diff --git a/dts/Bindings/hwmon/microchip,sparx5-temp.yaml b/dts/Bindings/hwmon/microchip,sparx5-temp.yaml index 76be625d56..51e8619dbf 100644 --- a/dts/Bindings/hwmon/microchip,sparx5-temp.yaml +++ b/dts/Bindings/hwmon/microchip,sparx5-temp.yaml @@ -22,7 +22,7 @@ properties: clocks: items: - - description: AHB reference clock + - description: System reference clock '#thermal-sensor-cells': const: 0 @@ -40,5 +40,5 @@ examples: compatible = "microchip,sparx5-temp"; reg = <0x10508110 0xc>; #thermal-sensor-cells = <0>; - clocks = <&ahb_clk>; + clocks = <&sys_clk>; }; diff --git a/dts/Bindings/hwmon/moortec,mr75203.yaml b/dts/Bindings/hwmon/moortec,mr75203.yaml index 8ea97e7743..d0d5497492 100644 --- a/dts/Bindings/hwmon/moortec,mr75203.yaml +++ b/dts/Bindings/hwmon/moortec,mr75203.yaml @@ -9,6 +9,32 @@ title: Moortec Semiconductor MR75203 PVT Controller bindings maintainers: - Rahul Tanwar <rtanwar@maxlinear.com> +description: | + A Moortec PVT (Process, Voltage, Temperature) monitoring logic design can + include many different units. + Such a design will usually consists of several Moortec's embedded analog IPs, + and a single Moortec controller (mr75203) to configure and control the IPs. + + Some of the Moortec's analog hard IPs that can be used in a design: + *) Temperature Sensor (TS) - used to monitor core temperature (e.g. mr74137). + *) Voltage Monitor (VM) - used to monitor voltage levels (e.g. mr74138). + *) Process Detector (PD) - used to assess silicon speed (e.g. mr74139). + *) Delay Chain - ring oscillator connected to the PD, used to measure IO + based transistors (e.g. mr76008 ring oscillator at 1.1V, mr76007 ring + oscillator at 1.8V). + *) Pre Scaler - provides divide-by-X scaling of input voltage, which can then + be presented for VM for measurement within its range (e.g. mr76006 - + divide by 2 pre-scaler). + + TS, VM & PD also include a digital interface, which consists of configuration + inputs and measurement outputs. + + Some of the units have number of series, each series can have slightly + different characteristics. + + The mr75203 binding describes configuration for the controller unit, but also + for some of the analog IPs. + properties: compatible: const: moortec,mr75203 @@ -44,12 +70,76 @@ properties: "#thermal-sensor-cells": const: 1 + moortec,vm-active-channels: + description: + Defines the number of channels per VM that are actually used and are + connected to some input source. + Maximum number of items - number of VMs. + Maximum value of each item - number of channels. + Minimum value of each item - 0 (which means entire VM sensor is not used). + $ref: /schemas/types.yaml#/definitions/uint8-array + + moortec,vm-pre-scaler-x2: + description: + Defines the channels that use a mr76006 pre-scaler to divide the input + source by 2. + The pre-scaler is used for input sources that exceed the VM input range. + The driver uses this information to present to the user with the actual + value of the voltage source. + For channels that are not listed, no pre-scaler is assumed. + Maximum number of items - total number of channels in all VMs. + Each channel should not appear more than once. + $ref: /schemas/types.yaml#/definitions/uint8-array + + moortec,ts-series: + description: + Definition of the temperature equation and coefficients that shall be + used to convert the digital output to value in milli-Celsius. + minimum: 5 + maximum: 6 + default: 5 + $ref: /schemas/types.yaml#/definitions/uint32 + + moortec,ts-coeff-g: + description: + G coefficient for temperature equation. + Default for series 5 = 60000 + Default for series 6 = 57400 + multipleOf: 1000 + minimum: 1000 + $ref: /schemas/types.yaml#/definitions/uint32 + + moortec,ts-coeff-h: + description: + H coefficient for temperature equation. + Default for series 5 = 200000 + Default for series 6 = 249400 + multipleOf: 1000 + minimum: 1000 + $ref: /schemas/types.yaml#/definitions/uint32 + + moortec,ts-coeff-cal5: + description: + cal5 coefficient for temperature equation. + Default for series 5 = 4094 + Default for series 6 = 4096 + minimum: 1 + $ref: /schemas/types.yaml#/definitions/uint32 + + moortec,ts-coeff-j: + description: + J coefficient for temperature equation. + Default for series 5 = -100 + Default for series 6 = 0 + multipleOf: 1000 + maximum: 0 + $ref: /schemas/types.yaml#/definitions/int32 + required: - compatible - reg - reg-names - clocks - - resets - "#thermal-sensor-cells" additionalProperties: false @@ -66,5 +156,9 @@ examples: intel,vm-map = [03 01 04 ff ff]; clocks = <&osc0>; resets = <&rcu0 0x40 7>; + moortec,vm-active-channels = /bits/ 8 <0x10 0x05>; + moortec,vm-pre-scaler-x2 = /bits/ 8 <5 6 20>; + moortec,ts-coeff-g = <61400>; + moortec,ts-coeff-h = <253700>; #thermal-sensor-cells = <1>; }; diff --git a/dts/Bindings/hwmon/sensirion,shtc1.yaml b/dts/Bindings/hwmon/sensirion,shtc1.yaml index 7d49478d96..159238efa9 100644 --- a/dts/Bindings/hwmon/sensirion,shtc1.yaml +++ b/dts/Bindings/hwmon/sensirion,shtc1.yaml @@ -10,7 +10,7 @@ maintainers: - Christopher Ruehl chris.ruehl@gtsys.com.hk description: | - The SHTC1, SHTW1 and SHTC3 are digital humidity and temperature sensor + The SHTC1, SHTW1 and SHTC3 are digital humidity and temperature sensors designed especially for battery-driven high-volume consumer electronics applications. For further information refere to Documentation/hwmon/shtc1.rst @@ -31,13 +31,13 @@ properties: sensirion,blocking-io: $ref: /schemas/types.yaml#/definitions/flag description: - If set, the driver hold the i2c bus until measurement is finished. + If set, the driver holds the i2c bus until the measurement is finished. sensirion,low-precision: $ref: /schemas/types.yaml#/definitions/flag description: - If set, the sensor aquire data with low precision (not recommended). - The driver aquire data with high precision by default. + If set, the sensor acquires data with low precision (not recommended). + The driver acquires data with high precision by default. required: - compatible diff --git a/dts/Bindings/i2c/allwinner,sun6i-a31-p2wi.yaml b/dts/Bindings/i2c/allwinner,sun6i-a31-p2wi.yaml index 1b03810d4b..5a799246a3 100644 --- a/dts/Bindings/i2c/allwinner,sun6i-a31-p2wi.yaml +++ b/dts/Bindings/i2c/allwinner,sun6i-a31-p2wi.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/i2c/allwinner,sun6i-a31-p2wi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A31 P2WI (Push/Pull 2 Wires Interface) Device Tree Bindings +title: Allwinner A31 P2WI (Push/Pull 2 Wires Interface) maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/i2c/aspeed,i2c.yaml b/dts/Bindings/i2c/aspeed,i2c.yaml index f597f73ccd..869b4d6333 100644 --- a/dts/Bindings/i2c/aspeed,i2c.yaml +++ b/dts/Bindings/i2c/aspeed,i2c.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/i2c/aspeed,i2c.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ASPEED I2C on the AST24XX, AST25XX, and AST26XX SoCs Device Tree Bindings +title: ASPEED I2C on the AST24XX, AST25XX, and AST26XX SoCs maintainers: - Rayn Chen <rayn_chen@aspeedtech.com> diff --git a/dts/Bindings/i2c/cdns,i2c-r1p10.yaml b/dts/Bindings/i2c/cdns,i2c-r1p10.yaml index 1ca1cd19bd..2e95cda726 100644 --- a/dts/Bindings/i2c/cdns,i2c-r1p10.yaml +++ b/dts/Bindings/i2c/cdns,i2c-r1p10.yaml @@ -4,7 +4,7 @@ $id: "http://devicetree.org/schemas/i2c/cdns,i2c-r1p10.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: Cadence I2C controller Device Tree Bindings +title: Cadence I2C controller maintainers: - Michal Simek <michal.simek@xilinx.com> diff --git a/dts/Bindings/i2c/i2c-imx-lpi2c.yaml b/dts/Bindings/i2c/i2c-imx-lpi2c.yaml index 529bea56d3..4656f5112b 100644 --- a/dts/Bindings/i2c/i2c-imx-lpi2c.yaml +++ b/dts/Bindings/i2c/i2c-imx-lpi2c.yaml @@ -23,6 +23,7 @@ properties: - fsl,imx8dxl-lpi2c - fsl,imx8qm-lpi2c - fsl,imx8ulp-lpi2c + - fsl,imx93-lpi2c - const: fsl,imx7ulp-lpi2c reg: @@ -37,10 +38,22 @@ properties: clock-frequency: true clock-names: - maxItems: 1 + items: + - const: per + - const: ipg clocks: - maxItems: 1 + maxItems: 2 + + dmas: + items: + - description: DMA controller phandle and request line for TX + - description: DMA controller phandle and request line for RX + + dma-names: + items: + - const: tx + - const: rx power-domains: maxItems: 1 @@ -63,5 +76,6 @@ examples: reg = <0x40A50000 0x10000>; interrupt-parent = <&intc>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7ULP_CLK_LPI2C7>; + clocks = <&clks IMX7ULP_CLK_LPI2C7>, + <&clks IMX7ULP_CLK_NIC1_BUS_DIV>; }; diff --git a/dts/Bindings/i2c/i2c-imx.yaml b/dts/Bindings/i2c/i2c-imx.yaml index 01720e338b..85ee1282d6 100644 --- a/dts/Bindings/i2c/i2c-imx.yaml +++ b/dts/Bindings/i2c/i2c-imx.yaml @@ -19,6 +19,17 @@ properties: - const: fsl,imx21-i2c - const: fsl,vf610-i2c - items: + - enum: + - fsl,ls1012a-i2c + - fsl,ls1021a-i2c + - fsl,ls1028a-i2c + - fsl,ls1043a-i2c + - fsl,ls1046a-i2c + - fsl,ls1088a-i2c + - fsl,ls208xa-i2c + - fsl,lx2160a-i2c + - const: fsl,vf610-i2c + - items: - const: fsl,imx35-i2c - const: fsl,imx1-i2c - items: diff --git a/dts/Bindings/i2c/i2c-mt7621.txt b/dts/Bindings/i2c/i2c-mt7621.txt deleted file mode 100644 index bc36f0eb94..0000000000 --- a/dts/Bindings/i2c/i2c-mt7621.txt +++ /dev/null @@ -1,25 +0,0 @@ -MediaTek MT7621/MT7628 I2C master controller - -Required properties: - -- compatible: Should be one of the following: - - "mediatek,mt7621-i2c": for MT7621/MT7628/MT7688 platforms -- #address-cells: should be 1. -- #size-cells: should be 0. -- reg: Address and length of the register set for the device -- resets: phandle to the reset controller asserting this device in - reset - See ../reset/reset.txt for details. - -Optional properties : - -Example: - -i2c: i2c@900 { - compatible = "mediatek,mt7621-i2c"; - reg = <0x900 0x100>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&rstctrl 16>; - reset-names = "i2c"; -}; diff --git a/dts/Bindings/i2c/i2c-rk3x.yaml b/dts/Bindings/i2c/i2c-rk3x.yaml index ee9f8b91d2..82b9d66822 100644 --- a/dts/Bindings/i2c/i2c-rk3x.yaml +++ b/dts/Bindings/i2c/i2c-rk3x.yaml @@ -29,6 +29,7 @@ properties: - items: - enum: - rockchip,rk3036-i2c + - rockchip,rk3128-i2c - rockchip,rk3368-i2c - const: rockchip,rk3288-i2c - items: diff --git a/dts/Bindings/i2c/marvell,mv64xxx-i2c.yaml b/dts/Bindings/i2c/marvell,mv64xxx-i2c.yaml index 0ec033e488..93c164aa00 100644 --- a/dts/Bindings/i2c/marvell,mv64xxx-i2c.yaml +++ b/dts/Bindings/i2c/marvell,mv64xxx-i2c.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/i2c/marvell,mv64xxx-i2c.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Marvell MV64XXX I2C Controller Device Tree Bindings +title: Marvell MV64XXX I2C Controller maintainers: - Gregory CLEMENT <gregory.clement@bootlin.com> @@ -66,6 +66,19 @@ properties: resets: maxItems: 1 + dmas: + items: + - description: RX DMA Channel + - description: TX DMA Channel + + dma-names: + items: + - const: rx + - const: tx + +dependencies: + dmas: [ dma-names ] + required: - compatible - reg diff --git a/dts/Bindings/i2c/mediatek,mt7621-i2c.yaml b/dts/Bindings/i2c/mediatek,mt7621-i2c.yaml new file mode 100644 index 0000000000..118ec00fc1 --- /dev/null +++ b/dts/Bindings/i2c/mediatek,mt7621-i2c.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/mediatek,mt7621-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +maintainers: + - Stefan Roese <sr@denx.de> + +title: Mediatek MT7621/MT7628 I2C master controller + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + const: mediatek,mt7621-i2c + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: i2c + + resets: + maxItems: 1 + + reset-names: + const: i2c + +required: + - compatible + - reg + - resets + - "#address-cells" + - "#size-cells" + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/mt7621-clk.h> + #include <dt-bindings/reset/mt7621-reset.h> + + i2c: i2c@900 { + compatible = "mediatek,mt7621-i2c"; + reg = <0x900 0x100>; + clocks = <&sysc MT7621_CLK_I2C>; + clock-names = "i2c"; + resets = <&sysc MT7621_RST_I2C>; + reset-names = "i2c"; + + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins>; + }; diff --git a/dts/Bindings/i2c/mellanox,i2c-mlxbf.yaml b/dts/Bindings/i2c/mellanox,i2c-mlxbf.yaml deleted file mode 100644 index 93198d5d43..0000000000 --- a/dts/Bindings/i2c/mellanox,i2c-mlxbf.yaml +++ /dev/null @@ -1,77 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/i2c/mellanox,i2c-mlxbf.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Mellanox I2C SMBus on BlueField SoCs - -maintainers: - - Khalil Blaiech <kblaiech@nvidia.com> - -allOf: - - $ref: /schemas/i2c/i2c-controller.yaml# - -properties: - compatible: - enum: - - mellanox,i2c-mlxbf1 - - mellanox,i2c-mlxbf2 - - reg: - minItems: 3 - items: - - description: Smbus block registers - - description: Cause master registers - - description: Cause slave registers - - description: Cause coalesce registers - - interrupts: - maxItems: 1 - - clock-frequency: - enum: [ 100000, 400000, 1000000 ] - description: - bus frequency used to configure timing registers; - The frequency is expressed in Hz. Default is 100000. - -required: - - compatible - - reg - - interrupts - -unevaluatedProperties: false - -if: - properties: - compatible: - contains: - enum: - - mellanox,i2c-mlxbf1 - -then: - properties: - reg: - maxItems: 3 - -examples: - - | - i2c@2804000 { - compatible = "mellanox,i2c-mlxbf1"; - reg = <0x02804000 0x800>, - <0x02801200 0x020>, - <0x02801260 0x020>; - interrupts = <57>; - clock-frequency = <100000>; - }; - - - | - i2c@2808800 { - compatible = "mellanox,i2c-mlxbf2"; - reg = <0x02808800 0x600>, - <0x02808e00 0x020>, - <0x02808e20 0x020>, - <0x02808e40 0x010>; - interrupts = <57>; - clock-frequency = <400000>; - }; diff --git a/dts/Bindings/i2c/microchip,corei2c.yaml b/dts/Bindings/i2c/microchip,corei2c.yaml index 7bad4b946a..afa3db7262 100644 --- a/dts/Bindings/i2c/microchip,corei2c.yaml +++ b/dts/Bindings/i2c/microchip,corei2c.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/i2c/microchip,corei2c.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Microchip MPFS I2C Controller Device Tree Bindings +title: Microchip MPFS I2C Controller maintainers: - Daire McNamara <daire.mcnamara@microchip.com> diff --git a/dts/Bindings/i2c/nuvoton,npcm7xx-i2c.yaml b/dts/Bindings/i2c/nuvoton,npcm7xx-i2c.yaml index 09d2591e1f..00eb6ff6f5 100644 --- a/dts/Bindings/i2c/nuvoton,npcm7xx-i2c.yaml +++ b/dts/Bindings/i2c/nuvoton,npcm7xx-i2c.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/i2c/nuvoton,npcm7xx-i2c.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: nuvoton NPCM7XX I2C Controller Device Tree Bindings +title: nuvoton NPCM7XX I2C Controller description: | I2C bus controllers of the NPCM series support both master and diff --git a/dts/Bindings/i2c/qcom,i2c-cci.yaml b/dts/Bindings/i2c/qcom,i2c-cci.yaml index 90c9e40122..cf9f8fda59 100644 --- a/dts/Bindings/i2c/qcom,i2c-cci.yaml +++ b/dts/Bindings/i2c/qcom,i2c-cci.yaml @@ -13,6 +13,7 @@ maintainers: properties: compatible: enum: + - qcom,msm8226-cci - qcom,msm8916-cci - qcom,msm8974-cci - qcom,msm8996-cci @@ -27,11 +28,11 @@ properties: const: 0 clocks: - minItems: 4 + minItems: 3 maxItems: 6 clock-names: - minItems: 4 + minItems: 3 maxItems: 6 interrupts: @@ -78,6 +79,7 @@ allOf: compatible: contains: enum: + - qcom,msm8226-cci - qcom,msm8916-cci then: properties: @@ -88,6 +90,23 @@ allOf: compatible: contains: enum: + - qcom,msm8226-cci + - qcom,msm8974-cci + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: camss_top_ahb + - const: cci_ahb + - const: cci + + - if: + properties: + compatible: + contains: + enum: - qcom,msm8916-cci - qcom,msm8996-cci then: @@ -126,6 +145,7 @@ allOf: contains: enum: - qcom,sm8250-cci + - qcom,sm8450-cci then: properties: clocks: diff --git a/dts/Bindings/i2c/renesas,rcar-i2c.yaml b/dts/Bindings/i2c/renesas,rcar-i2c.yaml index f9929578c7..c4ace5585e 100644 --- a/dts/Bindings/i2c/renesas,rcar-i2c.yaml +++ b/dts/Bindings/i2c/renesas,rcar-i2c.yaml @@ -52,6 +52,7 @@ properties: - enum: - renesas,i2c-r8a779a0 # R-Car V3U - renesas,i2c-r8a779f0 # R-Car S4-8 + - renesas,i2c-r8a779g0 # R-Car V4H - const: renesas,rcar-gen4-i2c # R-Car Gen4 reg: diff --git a/dts/Bindings/i2c/xlnx,xps-iic-2.00.a.yaml b/dts/Bindings/i2c/xlnx,xps-iic-2.00.a.yaml index 715dcfa5a9..8d241a703d 100644 --- a/dts/Bindings/i2c/xlnx,xps-iic-2.00.a.yaml +++ b/dts/Bindings/i2c/xlnx,xps-iic-2.00.a.yaml @@ -4,7 +4,7 @@ $id: "http://devicetree.org/schemas/i2c/xlnx,xps-iic-2.00.a.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: Xilinx IIC controller Device Tree Bindings +title: Xilinx IIC controller maintainers: - info@mocean-labs.com diff --git a/dts/Bindings/i3c/mipi-i3c-hci.yaml b/dts/Bindings/i3c/mipi-i3c-hci.yaml index 04da001fc6..c002afdbfc 100644 --- a/dts/Bindings/i3c/mipi-i3c-hci.yaml +++ b/dts/Bindings/i3c/mipi-i3c-hci.yaml @@ -4,7 +4,7 @@ $id: "http://devicetree.org/schemas/i3c/mipi-i3c-hci.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: MIPI I3C HCI Device Tree Bindings +title: MIPI I3C HCI maintainers: - Nicolas Pitre <npitre@baylibre.com> diff --git a/dts/Bindings/iio/accel/adi,adis16201.yaml b/dts/Bindings/iio/accel/adi,adis16201.yaml index 6f8f8a6258..7332442e56 100644 --- a/dts/Bindings/iio/accel/adi,adis16201.yaml +++ b/dts/Bindings/iio/accel/adi,adis16201.yaml @@ -27,15 +27,16 @@ properties: interrupts: maxItems: 1 - spi-max-frequency: true - vdd-supply: true required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/accel/adi,adis16240.yaml b/dts/Bindings/iio/accel/adi,adis16240.yaml index 8d829ef878..f6f97164c2 100644 --- a/dts/Bindings/iio/accel/adi,adis16240.yaml +++ b/dts/Bindings/iio/accel/adi,adis16240.yaml @@ -25,14 +25,15 @@ properties: interrupts: maxItems: 1 - spi-max-frequency: true - required: - compatible - reg - interrupts -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/accel/adi,adxl313.yaml b/dts/Bindings/iio/accel/adi,adxl313.yaml index d6afc1b8c2..185b68ffb5 100644 --- a/dts/Bindings/iio/accel/adi,adxl313.yaml +++ b/dts/Bindings/iio/accel/adi,adxl313.yaml @@ -4,28 +4,30 @@ $id: http://devicetree.org/schemas/iio/accel/adi,adxl313.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Analog Devices ADXL313 3-Axis Digital Accelerometer +title: Analog Devices ADXL312, ADXL313, and ADXL314 3-Axis Digital Accelerometers maintainers: - Lucas Stankus <lucas.p.stankus@gmail.com> description: | - Analog Devices ADXL313 3-Axis Digital Accelerometer that supports - both I2C & SPI interfaces. + Analog Devices ADXL312, ADXL313, and ADXL314 3-Axis Digital Accelerometer that + support both I2C & SPI interfaces. + https://www.analog.com/en/products/adxl312.html https://www.analog.com/en/products/adxl313.html + https://www.analog.com/en/products/adxl314.html properties: compatible: enum: + - adi,adxl312 - adi,adxl313 + - adi,adxl314 reg: maxItems: 1 spi-3wire: true - spi-max-frequency: true - vs-supply: description: Regulator that supplies power to the accelerometer @@ -48,7 +50,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/accel/adi,adxl345.yaml b/dts/Bindings/iio/accel/adi,adxl345.yaml index 9bb039e2f5..346abfb13a 100644 --- a/dts/Bindings/iio/accel/adi,adxl345.yaml +++ b/dts/Bindings/iio/accel/adi,adxl345.yaml @@ -32,8 +32,6 @@ properties: spi-cpol: true - spi-max-frequency: true - interrupts: maxItems: 1 @@ -42,7 +40,10 @@ required: - reg - interrupts -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/accel/adi,adxl355.yaml b/dts/Bindings/iio/accel/adi,adxl355.yaml index ba54d6998f..14b487088a 100644 --- a/dts/Bindings/iio/accel/adi,adxl355.yaml +++ b/dts/Bindings/iio/accel/adi,adxl355.yaml @@ -45,13 +45,14 @@ properties: vddio-supply: description: Regulator that provides power to the bus - spi-max-frequency: true - required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/accel/adi,adxl367.yaml b/dts/Bindings/iio/accel/adi,adxl367.yaml index d259e796c1..f10d98d34c 100644 --- a/dts/Bindings/iio/accel/adi,adxl367.yaml +++ b/dts/Bindings/iio/accel/adi,adxl367.yaml @@ -35,8 +35,6 @@ properties: interrupts: maxItems: 1 - spi-max-frequency: true - vdd-supply: true vddio-supply: true @@ -45,7 +43,10 @@ required: - reg - interrupts -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/accel/adi,adxl372.yaml b/dts/Bindings/iio/accel/adi,adxl372.yaml index 38b59b6454..73a5c8f814 100644 --- a/dts/Bindings/iio/accel/adi,adxl372.yaml +++ b/dts/Bindings/iio/accel/adi,adxl372.yaml @@ -25,14 +25,15 @@ properties: interrupts: maxItems: 1 - spi-max-frequency: true - required: - compatible - reg - interrupts -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/accel/bosch,bma220.yaml b/dts/Bindings/iio/accel/bosch,bma220.yaml index 942b23ad07..5dd06f5905 100644 --- a/dts/Bindings/iio/accel/bosch,bma220.yaml +++ b/dts/Bindings/iio/accel/bosch,bma220.yaml @@ -20,8 +20,6 @@ properties: interrupts: maxItems: 1 - spi-max-frequency: true - vdda-supply: true vddd-supply: true vddio-supply: true @@ -30,7 +28,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/accel/bosch,bma255.yaml b/dts/Bindings/iio/accel/bosch,bma255.yaml index 478e75ae08..457a709b58 100644 --- a/dts/Bindings/iio/accel/bosch,bma255.yaml +++ b/dts/Bindings/iio/accel/bosch,bma255.yaml @@ -72,7 +72,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/accel/bosch,bmi088.yaml b/dts/Bindings/iio/accel/bosch,bmi088.yaml index 272eb48eef..3cb82576d7 100644 --- a/dts/Bindings/iio/accel/bosch,bmi088.yaml +++ b/dts/Bindings/iio/accel/bosch,bmi088.yaml @@ -24,8 +24,6 @@ properties: reg: maxItems: 1 - spi-max-frequency: true - vdd-supply: true vddio-supply: true @@ -50,7 +48,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/accel/fsl,mma7455.yaml b/dts/Bindings/iio/accel/fsl,mma7455.yaml index 9c7c66feef..c8659c5eba 100644 --- a/dts/Bindings/iio/accel/fsl,mma7455.yaml +++ b/dts/Bindings/iio/accel/fsl,mma7455.yaml @@ -39,13 +39,14 @@ properties: - "INT1" - "INT2" - spi-max-frequency: true - required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/accel/kionix,kxsd9.yaml b/dts/Bindings/iio/accel/kionix,kxsd9.yaml index 390b87242f..f64d99b354 100644 --- a/dts/Bindings/iio/accel/kionix,kxsd9.yaml +++ b/dts/Bindings/iio/accel/kionix,kxsd9.yaml @@ -29,13 +29,14 @@ properties: mount-matrix: description: an optional 3x3 mounting rotation matrix. - spi-max-frequency: true - required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/accel/memsensing,msa311.yaml b/dts/Bindings/iio/accel/memsensing,msa311.yaml new file mode 100644 index 0000000000..23528dcaa0 --- /dev/null +++ b/dts/Bindings/iio/accel/memsensing,msa311.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/iio/accel/memsensing,msa311.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MEMSensing digital 3-Axis accelerometer + +maintainers: + - Dmitry Rokosov <ddrokosov@sberdevices.ru> + +description: | + MSA311 is a tri-axial, low-g accelerometer with I2C digital output for + sensitivity consumer applications. It has dynamical user selectable full + scales range of +-2g/+-4g/+-8g/+-16g and allows acceleration measurements + with output data rates from 1Hz to 1000Hz. + Datasheet can be found at following URL + https://cdn-shop.adafruit.com/product-files/5309/MSA311-V1.1-ENG.pdf + +properties: + compatible: + const: memsensing,msa311 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vdd-supply: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + accelerometer@62 { + compatible = "memsensing,msa311"; + reg = <0x62>; + interrupt-parent = <&gpio_intc>; + interrupts = <29 IRQ_TYPE_EDGE_RISING>; + vdd-supply = <&vcc_5v>; + }; + }; diff --git a/dts/Bindings/iio/accel/murata,sca3300.yaml b/dts/Bindings/iio/accel/murata,sca3300.yaml index f6e2a16a71..00c990caa1 100644 --- a/dts/Bindings/iio/accel/murata,sca3300.yaml +++ b/dts/Bindings/iio/accel/murata,sca3300.yaml @@ -29,7 +29,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/accel/nxp,fxls8962af.yaml b/dts/Bindings/iio/accel/nxp,fxls8962af.yaml index ad529ab2c6..65ce8ea14b 100644 --- a/dts/Bindings/iio/accel/nxp,fxls8962af.yaml +++ b/dts/Bindings/iio/accel/nxp,fxls8962af.yaml @@ -27,8 +27,6 @@ properties: vdd-supply: description: phandle to the regulator that provides power to the accelerometer - spi-max-frequency: true - interrupts: maxItems: 1 @@ -44,7 +42,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/adi,ad7124.yaml b/dts/Bindings/iio/adc/adi,ad7124.yaml index fb3d0dae9b..75a7184a47 100644 --- a/dts/Bindings/iio/adc/adi,ad7124.yaml +++ b/dts/Bindings/iio/adc/adi,ad7124.yaml @@ -52,8 +52,6 @@ properties: avdd-supply: description: avdd supply can be used as reference for conversion. - spi-max-frequency: true - required: - compatible - reg @@ -106,7 +104,10 @@ patternProperties: additionalProperties: false -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/adi,ad7192.yaml b/dts/Bindings/iio/adc/adi,ad7192.yaml index 22b7ed3723..cc347dade4 100644 --- a/dts/Bindings/iio/adc/adi,ad7192.yaml +++ b/dts/Bindings/iio/adc/adi,ad7192.yaml @@ -30,8 +30,6 @@ properties: spi-cpha: true - spi-max-frequency: true - clocks: maxItems: 1 description: phandle to the master clock (mclk) @@ -94,7 +92,10 @@ required: - spi-cpol - spi-cpha -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/adi,ad7280a.yaml b/dts/Bindings/iio/adc/adi,ad7280a.yaml index a694d5794d..dfb8f305e2 100644 --- a/dts/Bindings/iio/adc/adi,ad7280a.yaml +++ b/dts/Bindings/iio/adc/adi,ad7280a.yaml @@ -28,8 +28,6 @@ properties: description: IRQ line for the ADC maxItems: 1 - spi-max-frequency: true - adi,voltage-alert-last-chan: $ref: /schemas/types.yaml#/definitions/uint32 description: @@ -55,7 +53,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/adi,ad7292.yaml b/dts/Bindings/iio/adc/adi,ad7292.yaml index a3e39a40c9..1bfbeed6f2 100644 --- a/dts/Bindings/iio/adc/adi,ad7292.yaml +++ b/dts/Bindings/iio/adc/adi,ad7292.yaml @@ -30,8 +30,6 @@ properties: spi-cpha: true - spi-max-frequency: true - '#address-cells': const: 1 @@ -65,7 +63,10 @@ patternProperties: additionalProperties: true -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/adi,ad7298.yaml b/dts/Bindings/iio/adc/adi,ad7298.yaml index ca414bb396..cd8ac5162d 100644 --- a/dts/Bindings/iio/adc/adi,ad7298.yaml +++ b/dts/Bindings/iio/adc/adi,ad7298.yaml @@ -24,13 +24,15 @@ properties: vref-supply: true vdd-supply: true - spi-max-frequency: true required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/adi,ad7476.yaml b/dts/Bindings/iio/adc/adi,ad7476.yaml index 666414a9c0..44c671eeda 100644 --- a/dts/Bindings/iio/adc/adi,ad7476.yaml +++ b/dts/Bindings/iio/adc/adi,ad7476.yaml @@ -66,8 +66,6 @@ properties: to the other supplies. Needed to be able to establish channel scaling unless there is also an internal reference available (e.g. ad7091r) - spi-max-frequency: true - adi,conversion-start-gpios: description: A GPIO used to trigger the start of a conversion maxItems: 1 @@ -76,9 +74,9 @@ required: - compatible - reg -additionalProperties: false - allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + # Devices where reference is vcc - if: properties: @@ -158,6 +156,8 @@ allOf: properties: adi,conversion-start-gpios: false +unevaluatedProperties: false + examples: - | spi { diff --git a/dts/Bindings/iio/adc/adi,ad7606.yaml b/dts/Bindings/iio/adc/adi,ad7606.yaml index 516fc24d33..ac5a47c8f0 100644 --- a/dts/Bindings/iio/adc/adi,ad7606.yaml +++ b/dts/Bindings/iio/adc/adi,ad7606.yaml @@ -32,8 +32,6 @@ properties: spi-cpol: true - spi-max-frequency: true - avcc-supply: true interrupts: @@ -105,7 +103,10 @@ required: - interrupts - adi,conversion-start-gpios -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/adi,ad7768-1.yaml b/dts/Bindings/iio/adc/adi,ad7768-1.yaml index a85a28145e..3ce59d4d06 100644 --- a/dts/Bindings/iio/adc/adi,ad7768-1.yaml +++ b/dts/Bindings/iio/adc/adi,ad7768-1.yaml @@ -50,8 +50,6 @@ properties: reset-gpios: maxItems: 1 - spi-max-frequency: true - spi-cpol: true spi-cpha: true @@ -88,7 +86,10 @@ patternProperties: - reg additionalProperties: false -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/adi,ad7923.yaml b/dts/Bindings/iio/adc/adi,ad7923.yaml index e82194974e..07f9d1c09c 100644 --- a/dts/Bindings/iio/adc/adi,ad7923.yaml +++ b/dts/Bindings/iio/adc/adi,ad7923.yaml @@ -8,7 +8,6 @@ title: Analog Devices AD7923 and similars with 4 and 8 Channel ADCs. maintainers: - Michael Hennerich <michael.hennerich@analog.com> - - Patrick Vasseur <patrick.vasseur@c-s.fr> description: | Analog Devices AD7904, AD7914, AD7923, AD7924 4 Channel ADCs, and AD7908, @@ -37,19 +36,24 @@ properties: description: | The regulator supply for ADC reference voltage. + adi,range-double: + description: Sets the analog input range from 0 to 2xVREF. + type: boolean + '#address-cells': const: 1 '#size-cells': const: 0 - spi-max-frequency: true - required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/adi,ad7949.yaml b/dts/Bindings/iio/adc/adi,ad7949.yaml index 0b10ed5f74..9ee4d977c5 100644 --- a/dts/Bindings/iio/adc/adi,ad7949.yaml +++ b/dts/Bindings/iio/adc/adi,ad7949.yaml @@ -49,8 +49,6 @@ properties: default: 4096000 - spi-max-frequency: true - '#io-channel-cells': const: 1 @@ -64,7 +62,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/holt,hi8435.yaml b/dts/Bindings/iio/adc/holt,hi8435.yaml index 52490cbb0a..56bcbe5dcd 100644 --- a/dts/Bindings/iio/adc/holt,hi8435.yaml +++ b/dts/Bindings/iio/adc/holt,hi8435.yaml @@ -24,8 +24,6 @@ properties: GPIO used for controlling the reset pin maxItems: 1 - spi-max-frequency: true - "#io-channel-cells": const: 1 @@ -33,7 +31,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/lltc,ltc2496.yaml b/dts/Bindings/iio/adc/lltc,ltc2496.yaml index 0bd2fc0356..5207c919ab 100644 --- a/dts/Bindings/iio/adc/lltc,ltc2496.yaml +++ b/dts/Bindings/iio/adc/lltc,ltc2496.yaml @@ -22,15 +22,15 @@ properties: reg: maxItems: 1 - spi-max-frequency: - description: maximal spi bus frequency supported - required: - compatible - vref-supply - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/lltc,ltc2497.yaml b/dts/Bindings/iio/adc/lltc,ltc2497.yaml index c1772b568c..875f394576 100644 --- a/dts/Bindings/iio/adc/lltc,ltc2497.yaml +++ b/dts/Bindings/iio/adc/lltc,ltc2497.yaml @@ -13,10 +13,14 @@ description: | 16bit ADC supporting up to 16 single ended or 8 differential inputs. I2C interface. + https://www.analog.com/media/en/technical-documentation/data-sheets/2497fb.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/2499fe.pdf + properties: compatible: - const: - lltc,ltc2497 + enum: + - lltc,ltc2497 + - lltc,ltc2499 reg: true vref-supply: true diff --git a/dts/Bindings/iio/adc/maxim,max1027.yaml b/dts/Bindings/iio/adc/maxim,max1027.yaml index 46b7747076..d0a7ed26d9 100644 --- a/dts/Bindings/iio/adc/maxim,max1027.yaml +++ b/dts/Bindings/iio/adc/maxim,max1027.yaml @@ -45,7 +45,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/maxim,max11100.yaml b/dts/Bindings/iio/adc/maxim,max11100.yaml index 0cf87556ef..4f74cb3338 100644 --- a/dts/Bindings/iio/adc/maxim,max11100.yaml +++ b/dts/Bindings/iio/adc/maxim,max11100.yaml @@ -26,13 +26,16 @@ properties: minimum: 100000 maximum: 4800000 -additionalProperties: false - required: - compatible - reg - vref-supply +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + examples: - | spi { diff --git a/dts/Bindings/iio/adc/maxim,max1118.yaml b/dts/Bindings/iio/adc/maxim,max1118.yaml index e948b3e37b..bb336e33eb 100644 --- a/dts/Bindings/iio/adc/maxim,max1118.yaml +++ b/dts/Bindings/iio/adc/maxim,max1118.yaml @@ -28,23 +28,25 @@ properties: vref-supply: description: External reference, needed to establish input scaling -if: - properties: - compatible: - contains: - const: maxim,max1118 -then: - required: - - vref-supply -else: - properties: - vref-supply: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + - if: + properties: + compatible: + contains: + const: maxim,max1118 + then: + required: + - vref-supply + else: + properties: + vref-supply: false required: - compatible - reg -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/maxim,max11205.yaml b/dts/Bindings/iio/adc/maxim,max11205.yaml new file mode 100644 index 0000000000..5f9e043cf5 --- /dev/null +++ b/dts/Bindings/iio/adc/maxim,max11205.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/maxim,max11205.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX11205 ADC + +maintainers: + - Ramona Bolboaca <ramona.bolboaca@analog.com> + +description: | + The MAX11205 is an ultra-low-power (< 300FA max active current), + high-resolution, serial-output ADC. + + https://datasheets.maximintegrated.com/en/ds/MAX11205.pdf + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - maxim,max11205a + - maxim,max11205b + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + spi-max-frequency: + maximum: 5000000 + + spi-cpha: true + + vref-supply: + description: + The regulator supply for the ADC reference voltage. This is a differential + reference. It is equal to the V_REFP - V_REFN. The maximum value is 3.6V. + +required: + - compatible + - reg + - interrupts + - spi-max-frequency + - spi-cpha + - vref-supply + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + adc@0 { + compatible = "maxim,max11205a"; + reg = <0>; + spi-max-frequency = <5000000>; + spi-cpha; + interrupt-parent = <&gpio>; + interrupts = <19 IRQ_TYPE_EDGE_FALLING>; + vref-supply = <&max11205_vref>; + }; + }; +... diff --git a/dts/Bindings/iio/adc/maxim,max1241.yaml b/dts/Bindings/iio/adc/maxim,max1241.yaml index 4c7e0d94bf..58b12fe807 100644 --- a/dts/Bindings/iio/adc/maxim,max1241.yaml +++ b/dts/Bindings/iio/adc/maxim,max1241.yaml @@ -39,15 +39,16 @@ properties: thus enabling power-down mode. maxItems: 1 - spi-max-frequency: true - required: - compatible - reg - vdd-supply - vref-supply -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/microchip,mcp3201.yaml b/dts/Bindings/iio/adc/microchip,mcp3201.yaml index fcc1ba53b2..18108f0f37 100644 --- a/dts/Bindings/iio/adc/microchip,mcp3201.yaml +++ b/dts/Bindings/iio/adc/microchip,mcp3201.yaml @@ -32,7 +32,6 @@ properties: reg: maxItems: 1 - spi-max-frequency: true spi-cpha: true spi-cpol: true @@ -51,7 +50,10 @@ required: - reg - vref-supply -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/microchip,mcp3911.yaml b/dts/Bindings/iio/adc/microchip,mcp3911.yaml index 95ab285f4e..2c93fb41f1 100644 --- a/dts/Bindings/iio/adc/microchip,mcp3911.yaml +++ b/dts/Bindings/iio/adc/microchip,mcp3911.yaml @@ -36,6 +36,13 @@ properties: description: IRQ line of the ADC maxItems: 1 + microchip,data-ready-hiz: + description: + Data Ready Pin Inactive State Control + true = The DR pin state is high-impedance + false = The DR pin state is logic high + type: boolean + microchip,device-addr: description: Device address when multiple MCP3911 chips are present on the same SPI bus. $ref: /schemas/types.yaml#/definitions/uint32 @@ -51,7 +58,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/qcom,spmi-vadc.yaml b/dts/Bindings/iio/adc/qcom,spmi-vadc.yaml index 74a4a9d957..8bac0c4120 100644 --- a/dts/Bindings/iio/adc/qcom,spmi-vadc.yaml +++ b/dts/Bindings/iio/adc/qcom,spmi-vadc.yaml @@ -58,6 +58,7 @@ required: patternProperties: "^.*@[0-9a-f]+$": type: object + additionalProperties: false description: | Represents the external channels which are connected to the ADC. For compatible property "qcom,spmi-vadc" following channels, also known as diff --git a/dts/Bindings/iio/adc/richtek,rtq6056.yaml b/dts/Bindings/iio/adc/richtek,rtq6056.yaml new file mode 100644 index 0000000000..88e008629e --- /dev/null +++ b/dts/Bindings/iio/adc/richtek,rtq6056.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/richtek,rtq6056.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RTQ6056 Bi-Directional Current and Power Monitor with 16-bit ADC + +maintainers: + - ChiYuan Huang <cy_huang@richtek.com> + +description: | + The RTQ6056 is a high accuracy current-sense monitor with I2C and SMBus + interface, and the device provides full information for system by reading + out the loading current and power. + + The device monitors both of the drops across sense resistor and the BUS + voltage, converts into the current in amperes, and power in watts through + internal analog-to-digital converter ADC. The programmable calibration, + adjustable conversion time, and averaging function are also built in for + more design flexibility. + + Datasheet is available at + https://www.richtek.com/assets/product_file/RTQ6056/DSQ6056-00.pdf + +properties: + compatible: + const: richtek,rtq6056 + + reg: + maxItems: 1 + + "#io-channel-cells": + const: 1 + + shunt-resistor-micro-ohms: + description: Shunt IN+/IN- sensing node resistor + +required: + - compatible + - reg + - "#io-channel-cells" + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + adc@40 { + compatible = "richtek,rtq6056"; + reg = <0x40>; + #io-channel-cells = <1>; + }; + }; diff --git a/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml index 92f9472a77..1970503389 100644 --- a/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml +++ b/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml @@ -72,6 +72,7 @@ additionalProperties: false patternProperties: "^filter@[0-9]+$": type: object + unevaluatedProperties: false description: child node properties: @@ -225,6 +226,7 @@ patternProperties: patternProperties: "^dfsdm-dai+$": type: object + additionalProperties: false description: child node properties: diff --git a/dts/Bindings/iio/adc/st,stmpe-adc.yaml b/dts/Bindings/iio/adc/st,stmpe-adc.yaml index 9049c69915..333744a215 100644 --- a/dts/Bindings/iio/adc/st,stmpe-adc.yaml +++ b/dts/Bindings/iio/adc/st,stmpe-adc.yaml @@ -13,8 +13,7 @@ description: This ADC forms part of an ST microelectronics STMPE multifunction device . The ADC is shared with the STMPE touchscreen. As a result some ADC related settings are specified in the parent node. - The node name myst be stmpe_adc and should be a child node of the stmpe node - to which it belongs. + The node should be a child node of the stmpe node to which it belongs. properties: compatible: diff --git a/dts/Bindings/iio/adc/ti,adc0832.yaml b/dts/Bindings/iio/adc/ti,adc0832.yaml index f5a923cc84..686721176a 100644 --- a/dts/Bindings/iio/adc/ti,adc0832.yaml +++ b/dts/Bindings/iio/adc/ti,adc0832.yaml @@ -24,8 +24,6 @@ properties: reg: maxItems: 1 - spi-max-frequency: true - vref-supply: description: External reference, needed to establish input scaling @@ -37,7 +35,10 @@ required: - reg - vref-supply -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/ti,adc084s021.yaml b/dts/Bindings/iio/adc/ti,adc084s021.yaml index 1a113b30a4..726d2cbfa3 100644 --- a/dts/Bindings/iio/adc/ti,adc084s021.yaml +++ b/dts/Bindings/iio/adc/ti,adc084s021.yaml @@ -19,8 +19,6 @@ properties: reg: maxItems: 1 - spi-max-frequency: true - vref-supply: description: External reference, needed to establish input scaling @@ -37,7 +35,10 @@ required: - spi-cpol - spi-cpha -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/ti,adc108s102.yaml b/dts/Bindings/iio/adc/ti,adc108s102.yaml index ae5ce60987..9b072b057f 100644 --- a/dts/Bindings/iio/adc/ti,adc108s102.yaml +++ b/dts/Bindings/iio/adc/ti,adc108s102.yaml @@ -19,7 +19,6 @@ properties: reg: true vref-supply: true - spi-max-frequency: true "#io-channel-cells": const: 1 @@ -28,7 +27,10 @@ required: - reg - vref-supply -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/ti,adc12138.yaml b/dts/Bindings/iio/adc/ti,adc12138.yaml index ec3b2edf1f..076088a328 100644 --- a/dts/Bindings/iio/adc/ti,adc12138.yaml +++ b/dts/Bindings/iio/adc/ti,adc12138.yaml @@ -31,8 +31,6 @@ properties: maxItems: 1 description: Conversion clock input. - spi-max-frequency: true - vref-p-supply: description: The regulator supply for positive analog voltage reference @@ -62,7 +60,10 @@ required: - clocks - vref-p-supply -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/ti,adc128s052.yaml b/dts/Bindings/iio/adc/ti,adc128s052.yaml index d54a0183f0..775eee972b 100644 --- a/dts/Bindings/iio/adc/ti,adc128s052.yaml +++ b/dts/Bindings/iio/adc/ti,adc128s052.yaml @@ -27,8 +27,6 @@ properties: reg: maxItems: 1 - spi-max-frequency: true - vref-supply: true "#io-channel-cells": @@ -39,7 +37,10 @@ required: - reg - vref-supply -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/ti,adc161s626.yaml b/dts/Bindings/iio/adc/ti,adc161s626.yaml index 3f4f334d6f..afe7825229 100644 --- a/dts/Bindings/iio/adc/ti,adc161s626.yaml +++ b/dts/Bindings/iio/adc/ti,adc161s626.yaml @@ -21,8 +21,6 @@ properties: reg: maxItems: 1 - spi-max-frequency: true - vdda-supply: true "#io-channel-cells": @@ -32,7 +30,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/ti,ads1015.yaml b/dts/Bindings/iio/adc/ti,ads1015.yaml index a3b79438a1..2c3c2cf214 100644 --- a/dts/Bindings/iio/adc/ti,ads1015.yaml +++ b/dts/Bindings/iio/adc/ti,ads1015.yaml @@ -43,6 +43,7 @@ additionalProperties: false patternProperties: "^channel@[0-7]+$": type: object + additionalProperties: false description: Child nodes needed for each channel that the platform uses. diff --git a/dts/Bindings/iio/adc/ti,ads124s08.yaml b/dts/Bindings/iio/adc/ti,ads124s08.yaml index 2e6abc9d74..56a3f1766a 100644 --- a/dts/Bindings/iio/adc/ti,ads124s08.yaml +++ b/dts/Bindings/iio/adc/ti,ads124s08.yaml @@ -18,8 +18,6 @@ properties: reg: maxItems: 1 - spi-max-frequency: true - spi-cpha: true reset-gpios: @@ -32,7 +30,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/ti,ads131e08.yaml b/dts/Bindings/iio/adc/ti,ads131e08.yaml index e0670e3fbb..55c2c73626 100644 --- a/dts/Bindings/iio/adc/ti,ads131e08.yaml +++ b/dts/Bindings/iio/adc/ti,ads131e08.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Texas Instruments ADS131E0x 4-, 6- and 8-Channel ADCs maintainers: - - Tomislav Denis <tomislav.denis@avl.com> + - Jonathan Cameron <jic23@kernel.org> description: | The ADS131E0x are a family of multichannel, simultaneous sampling, @@ -28,8 +28,6 @@ properties: reg: maxItems: 1 - spi-max-frequency: true - spi-cpha: true clocks: @@ -120,7 +118,10 @@ patternProperties: additionalProperties: false -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/ti,ads8344.yaml b/dts/Bindings/iio/adc/ti,ads8344.yaml index b8c398187d..f75b2c7029 100644 --- a/dts/Bindings/iio/adc/ti,ads8344.yaml +++ b/dts/Bindings/iio/adc/ti,ads8344.yaml @@ -19,8 +19,6 @@ properties: reg: maxItems: 1 - spi-max-frequency: true - vref-supply: description: Supply the 2.5V or 5V reference voltage @@ -32,7 +30,10 @@ required: - reg - vref-supply -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/ti,ads8688.yaml b/dts/Bindings/iio/adc/ti,ads8688.yaml index a0af4b2487..f26fdbc15f 100644 --- a/dts/Bindings/iio/adc/ti,ads8688.yaml +++ b/dts/Bindings/iio/adc/ti,ads8688.yaml @@ -25,13 +25,14 @@ properties: description: Optional external reference. If not supplied, assume REFSEL input tied low to enable the internal reference. - spi-max-frequency: true - required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/ti,am3359-adc.yaml b/dts/Bindings/iio/adc/ti,am3359-adc.yaml index d6f21d5ccc..b32be24a9f 100644 --- a/dts/Bindings/iio/adc/ti,am3359-adc.yaml +++ b/dts/Bindings/iio/adc/ti,am3359-adc.yaml @@ -11,9 +11,14 @@ maintainers: properties: compatible: - enum: - - ti,am3359-adc - - ti,am4372-adc + oneOf: + - enum: + - ti,am3359-adc + - ti,am4372-adc + - items: + - enum: + - ti,am654-adc + - const: ti,am3359-adc '#io-channel-cells': const: 1 diff --git a/dts/Bindings/iio/adc/ti,tlc4541.yaml b/dts/Bindings/iio/adc/ti,tlc4541.yaml index 6c2539b3d7..314d1d99bf 100644 --- a/dts/Bindings/iio/adc/ti,tlc4541.yaml +++ b/dts/Bindings/iio/adc/ti,tlc4541.yaml @@ -21,8 +21,6 @@ properties: reg: maxItems: 1 - spi-max-frequency: true - vref-supply: true "#io-channel-cells": @@ -33,7 +31,10 @@ required: - reg - vref-supply -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/ti,tsc2046.yaml b/dts/Bindings/iio/adc/ti,tsc2046.yaml index 601d69971d..bdf3bba2d7 100644 --- a/dts/Bindings/iio/adc/ti,tsc2046.yaml +++ b/dts/Bindings/iio/adc/ti,tsc2046.yaml @@ -23,7 +23,8 @@ properties: interrupts: maxItems: 1 - spi-max-frequency: true + vref-supply: + description: Optional supply of the reference voltage "#io-channel-cells": const: 1 @@ -59,7 +60,10 @@ patternProperties: additionalProperties: false -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/adc/xlnx,zynqmp-ams.yaml b/dts/Bindings/iio/adc/xlnx,zynqmp-ams.yaml index 3698b4b090..be93c109d6 100644 --- a/dts/Bindings/iio/adc/xlnx,zynqmp-ams.yaml +++ b/dts/Bindings/iio/adc/xlnx,zynqmp-ams.yaml @@ -134,6 +134,7 @@ properties: ams-pl@400: type: object + additionalProperties: false description: PL-SYSMON is capable of monitoring off chip voltage and temperature. PL-SYSMON block has DRP, JTAG and I2C interface to enable monitoring diff --git a/dts/Bindings/iio/addac/adi,ad74413r.yaml b/dts/Bindings/iio/addac/adi,ad74413r.yaml index baa65a521b..03bb90a7f4 100644 --- a/dts/Bindings/iio/addac/adi,ad74413r.yaml +++ b/dts/Bindings/iio/addac/adi,ad74413r.yaml @@ -63,6 +63,7 @@ additionalProperties: false patternProperties: "^channel@[0-3]$": type: object + additionalProperties: false description: Represents the external channels which are connected to the device. properties: diff --git a/dts/Bindings/iio/amplifiers/adi,ada4250.yaml b/dts/Bindings/iio/amplifiers/adi,ada4250.yaml index 5277479be3..c15da155d3 100644 --- a/dts/Bindings/iio/amplifiers/adi,ada4250.yaml +++ b/dts/Bindings/iio/amplifiers/adi,ada4250.yaml @@ -27,14 +27,15 @@ properties: Enable internal buffer to drive the reference pin. type: boolean - spi-max-frequency: true - required: - compatible - reg - avdd-supply -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/dac/adi,ad3552r.yaml b/dts/Bindings/iio/dac/adi,ad3552r.yaml index 9c48c76993..fee0f023a8 100644 --- a/dts/Bindings/iio/dac/adi,ad3552r.yaml +++ b/dts/Bindings/iio/dac/adi,ad3552r.yaml @@ -78,6 +78,7 @@ patternProperties: custom-output-range-config: type: object + additionalProperties: false description: Configuration of custom range when adi,output-range-microvolt is not present. The formulas for calculation the output voltages are diff --git a/dts/Bindings/iio/dac/adi,ad5064.yaml b/dts/Bindings/iio/dac/adi,ad5064.yaml index 05ed4e0ec3..c04165fa92 100644 --- a/dts/Bindings/iio/dac/adi,ad5064.yaml +++ b/dts/Bindings/iio/dac/adi,ad5064.yaml @@ -95,15 +95,12 @@ properties: vrefD-supply: true vref-supply: true - spi-max-frequency: true - -additionalProperties: false - required: - compatible - reg allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# - # Shared external vref, no internal reference if: properties: @@ -232,6 +229,8 @@ allOf: - vrefA-supply - vrefB-supply +unevaluatedProperties: false + examples: - | spi { diff --git a/dts/Bindings/iio/dac/adi,ad5360.yaml b/dts/Bindings/iio/dac/adi,ad5360.yaml index 65f86f2694..86e2884cdf 100644 --- a/dts/Bindings/iio/dac/adi,ad5360.yaml +++ b/dts/Bindings/iio/dac/adi,ad5360.yaml @@ -28,10 +28,6 @@ properties: vref1-supply: true vref2-supply: true - spi-max-frequency: true - -additionalProperties: false - required: - compatible - reg @@ -39,6 +35,7 @@ required: - vref1-supply allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# - if: properties: compatible: @@ -63,6 +60,8 @@ allOf: required: - vref2-supply +unevaluatedProperties: false + examples: - | spi { diff --git a/dts/Bindings/iio/dac/adi,ad5380.yaml b/dts/Bindings/iio/dac/adi,ad5380.yaml index d599b418a0..ff50c72c62 100644 --- a/dts/Bindings/iio/dac/adi,ad5380.yaml +++ b/dts/Bindings/iio/dac/adi,ad5380.yaml @@ -39,14 +39,15 @@ properties: description: If not supplied devices will use internal regulators. - spi-max-frequency: true - -additionalProperties: false - required: - compatible - reg +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + examples: - | spi { diff --git a/dts/Bindings/iio/dac/adi,ad5421.yaml b/dts/Bindings/iio/dac/adi,ad5421.yaml index 188f656617..52d089ebde 100644 --- a/dts/Bindings/iio/dac/adi,ad5421.yaml +++ b/dts/Bindings/iio/dac/adi,ad5421.yaml @@ -26,13 +26,14 @@ properties: maxItems: 1 description: Fault signal. - spi-max-frequency: true - required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/dac/adi,ad5449.yaml b/dts/Bindings/iio/dac/adi,ad5449.yaml index 044332c977..d2af2d4919 100644 --- a/dts/Bindings/iio/dac/adi,ad5449.yaml +++ b/dts/Bindings/iio/dac/adi,ad5449.yaml @@ -27,19 +27,16 @@ properties: reg: maxItems: 1 - spi-max-frequency: true - VREF-supply: true VREFA-supply: true VREFB-supply: true -additionalProperties: false - required: - compatible - reg allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# - if: properties: compatible: @@ -72,6 +69,8 @@ allOf: - VREFA-supply - VREFB-supply +unevaluatedProperties: false + examples: - | spi { diff --git a/dts/Bindings/iio/dac/adi,ad5624r.yaml b/dts/Bindings/iio/dac/adi,ad5624r.yaml index 330383b85e..4d5111a5f9 100644 --- a/dts/Bindings/iio/dac/adi,ad5624r.yaml +++ b/dts/Bindings/iio/dac/adi,ad5624r.yaml @@ -22,17 +22,18 @@ properties: reg: maxItems: 1 - spi-max-frequency: true - vref-supply: description: If not present, internal reference will be used. -additionalProperties: false - required: - compatible - reg +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + examples: - | spi { diff --git a/dts/Bindings/iio/dac/adi,ad5686.yaml b/dts/Bindings/iio/dac/adi,ad5686.yaml index 5c26441eae..13f214234b 100644 --- a/dts/Bindings/iio/dac/adi,ad5686.yaml +++ b/dts/Bindings/iio/dac/adi,ad5686.yaml @@ -53,14 +53,15 @@ properties: vcc-supply: description: If not supplied the internal reference is used. - spi-max-frequency: true - -additionalProperties: false - required: - compatible - reg +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + examples: - | spi { diff --git a/dts/Bindings/iio/dac/adi,ad5755.yaml b/dts/Bindings/iio/dac/adi,ad5755.yaml index f866b88e14..9a3c2926bf 100644 --- a/dts/Bindings/iio/dac/adi,ad5755.yaml +++ b/dts/Bindings/iio/dac/adi,ad5755.yaml @@ -25,8 +25,6 @@ properties: description: Either this or spi-cpol but not both. spi-cpol: true - spi-max-frequency: true - adi,ext-dc-dc-compenstation-resistor: $ref: /schemas/types.yaml#/definitions/flag description: @@ -67,8 +65,6 @@ required: - compatible - reg -additionalProperties: false - patternProperties: "^channel@[0-7]$": type: object @@ -123,6 +119,11 @@ oneOf: - required: - spi-cpol +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + examples: - | spi { diff --git a/dts/Bindings/iio/dac/adi,ad5758.yaml b/dts/Bindings/iio/dac/adi,ad5758.yaml index fd4edca34a..e49e755617 100644 --- a/dts/Bindings/iio/dac/adi,ad5758.yaml +++ b/dts/Bindings/iio/dac/adi,ad5758.yaml @@ -16,7 +16,6 @@ properties: reg: maxItems: 1 - spi-max-frequency: true spi-cpha: true adi,dc-dc-mode: @@ -99,6 +98,7 @@ required: - adi,dc-dc-mode allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# - if: properties: adi,dc-dc-mode: @@ -115,7 +115,7 @@ allOf: required: - adi,range-microvolt -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/dac/adi,ad5761.yaml b/dts/Bindings/iio/dac/adi,ad5761.yaml index 7f95a9ed55..df550b5af2 100644 --- a/dts/Bindings/iio/dac/adi,ad5761.yaml +++ b/dts/Bindings/iio/dac/adi,ad5761.yaml @@ -22,18 +22,15 @@ properties: reg: maxItems: 1 - spi-max-frequency: true - vref-supply: description: If not supplied, internal reference will be used. -additionalProperties: false - required: - compatible - reg allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# - if: properties: compatible: @@ -45,6 +42,8 @@ allOf: required: - vref-supply +unevaluatedProperties: false + examples: - | spi { diff --git a/dts/Bindings/iio/dac/adi,ad5764.yaml b/dts/Bindings/iio/dac/adi,ad5764.yaml index 8e893d52bf..0b409a727a 100644 --- a/dts/Bindings/iio/dac/adi,ad5764.yaml +++ b/dts/Bindings/iio/dac/adi,ad5764.yaml @@ -22,18 +22,15 @@ properties: reg: maxItems: 1 - spi-max-frequency: true - vrefAB-supply: true vrefCD-supply: true -additionalProperties: false - required: - compatible - reg allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# - if: properties: compatible: @@ -46,6 +43,8 @@ allOf: - vrefAB-supply - vrefCD-supply +unevaluatedProperties: false + examples: - | spi { diff --git a/dts/Bindings/iio/dac/adi,ad5770r.yaml b/dts/Bindings/iio/dac/adi,ad5770r.yaml index 24ac40180a..8e7da0de91 100644 --- a/dts/Bindings/iio/dac/adi,ad5770r.yaml +++ b/dts/Bindings/iio/dac/adi,ad5770r.yaml @@ -49,8 +49,6 @@ properties: asserted during driver probe. maxItems: 1 - spi-max-frequency: true - '#address-cells': const: 1 @@ -62,6 +60,7 @@ properties: connected to the DAC. Channel 0 can act both as a current source and sink. type: object + additionalProperties: false properties: reg: @@ -85,6 +84,7 @@ properties: description: Represents an external channel which are connected to the DAC. type: object + additionalProperties: false properties: reg: @@ -101,6 +101,7 @@ properties: description: Represents an external channel which are connected to the DAC. type: object + additionalProperties: false properties: reg: @@ -116,6 +117,7 @@ properties: patternProperties: "^channel@([3-5])$": type: object + additionalProperties: false description: Represents the external channels which are connected to the DAC. properties: reg: @@ -138,7 +140,10 @@ required: - channel@4 - channel@5 -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/dac/adi,ad5791.yaml b/dts/Bindings/iio/dac/adi,ad5791.yaml index 650d1ebdce..3a84739736 100644 --- a/dts/Bindings/iio/dac/adi,ad5791.yaml +++ b/dts/Bindings/iio/dac/adi,ad5791.yaml @@ -23,19 +23,20 @@ properties: reg: maxItems: 1 - spi-max-frequency: true - vdd-supply: true vss-supply: true -additionalProperties: false - required: - compatible - reg - vdd-supply - vss-supply +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + examples: - | spi { diff --git a/dts/Bindings/iio/dac/adi,ad8801.yaml b/dts/Bindings/iio/dac/adi,ad8801.yaml index 6a3990a8d0..1849a2ff05 100644 --- a/dts/Bindings/iio/dac/adi,ad8801.yaml +++ b/dts/Bindings/iio/dac/adi,ad8801.yaml @@ -19,19 +19,16 @@ properties: reg: maxItems: 1 - spi-max-frequency: true - vrefh-supply: true vrefl-supply: true -additionalProperties: false - required: - compatible - reg - vrefh-supply allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# - if: properties: compatible: @@ -44,6 +41,8 @@ allOf: properties: vrefl-supply: false +unevaluatedProperties: false + examples: - | spi { diff --git a/dts/Bindings/iio/dac/adi,ltc2688.yaml b/dts/Bindings/iio/dac/adi,ltc2688.yaml index 48f9e7d294..15cc6bf59b 100644 --- a/dts/Bindings/iio/dac/adi,ltc2688.yaml +++ b/dts/Bindings/iio/dac/adi,ltc2688.yaml @@ -48,6 +48,7 @@ properties: patternProperties: "^channel@([0-9]|1[0-5])$": type: object + additionalProperties: false properties: reg: diff --git a/dts/Bindings/iio/dac/microchip,mcp4922.yaml b/dts/Bindings/iio/dac/microchip,mcp4922.yaml index 4c430abcdb..19374401e5 100644 --- a/dts/Bindings/iio/dac/microchip,mcp4922.yaml +++ b/dts/Bindings/iio/dac/microchip,mcp4922.yaml @@ -21,17 +21,18 @@ properties: reg: maxItems: 1 - spi-max-frequency: true - vref-supply: true -additionalProperties: false - required: - compatible - reg - vref-supply +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + examples: - | spi { diff --git a/dts/Bindings/iio/dac/ti,dac082s085.yaml b/dts/Bindings/iio/dac/ti,dac082s085.yaml index b0157050f1..201b04af2b 100644 --- a/dts/Bindings/iio/dac/ti,dac082s085.yaml +++ b/dts/Bindings/iio/dac/ti,dac082s085.yaml @@ -33,21 +33,22 @@ properties: vref-supply: description: Needed to provide output scaling. - spi-max-frequency: true - required: - compatible - reg - vref-supply -additionalProperties: false - oneOf: - required: - spi-cpha - required: - spi-cpol +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + examples: - | vref_2v5_reg: regulator-vref { diff --git a/dts/Bindings/iio/dac/ti,dac7311.yaml b/dts/Bindings/iio/dac/ti,dac7311.yaml index 10be98d1f1..a6814587db 100644 --- a/dts/Bindings/iio/dac/ti,dac7311.yaml +++ b/dts/Bindings/iio/dac/ti,dac7311.yaml @@ -24,14 +24,15 @@ properties: Reference voltage must be supplied to establish the scaling of the output voltage. - spi-max-frequency: true - required: - compatible - reg - vref-supply -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/dac/ti,dac7612.yaml b/dts/Bindings/iio/dac/ti,dac7612.yaml index d172b142f6..20dd137066 100644 --- a/dts/Bindings/iio/dac/ti,dac7612.yaml +++ b/dts/Bindings/iio/dac/ti,dac7612.yaml @@ -29,13 +29,14 @@ properties: DACs are loaded when the pin connected to this GPIO is pulled low. maxItems: 1 - spi-max-frequency: true - required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/frequency/adf4371.yaml b/dts/Bindings/iio/frequency/adf4371.yaml index 6b3a611e1c..0144f74a47 100644 --- a/dts/Bindings/iio/frequency/adf4371.yaml +++ b/dts/Bindings/iio/frequency/adf4371.yaml @@ -40,15 +40,16 @@ properties: output stage will shut down until the ADF4371/ADF4372 achieves lock as measured by the digital lock detect circuitry. - spi-max-frequency: true - required: - compatible - reg - clocks - clock-names -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/health/ti,afe4403.yaml b/dts/Bindings/iio/health/ti,afe4403.yaml index d861526c5c..6c5ad426a0 100644 --- a/dts/Bindings/iio/health/ti,afe4403.yaml +++ b/dts/Bindings/iio/health/ti,afe4403.yaml @@ -25,14 +25,15 @@ properties: reset-gpios: true - spi-max-frequency: true - -additionalProperties: false - required: - compatible - reg +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + examples: - | #include <dt-bindings/gpio/gpio.h> diff --git a/dts/Bindings/iio/imu/adi,adis16460.yaml b/dts/Bindings/iio/imu/adi,adis16460.yaml index 340be256f2..d166dbca18 100644 --- a/dts/Bindings/iio/imu/adi,adis16460.yaml +++ b/dts/Bindings/iio/imu/adi,adis16460.yaml @@ -25,8 +25,6 @@ properties: spi-cpol: true - spi-max-frequency: true - interrupts: maxItems: 1 @@ -35,7 +33,10 @@ required: - reg - interrupts -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/imu/adi,adis16480.yaml b/dts/Bindings/iio/imu/adi,adis16480.yaml index dd29dc6c4c..56e0dc20f5 100644 --- a/dts/Bindings/iio/imu/adi,adis16480.yaml +++ b/dts/Bindings/iio/imu/adi,adis16480.yaml @@ -47,8 +47,6 @@ properties: - DIO3 - DIO4 - spi-max-frequency: true - spi-cpha: true spi-cpol: true @@ -96,8 +94,6 @@ properties: - DIO3 - DIO4 -additionalProperties: false - required: - compatible - reg @@ -106,6 +102,11 @@ required: - spi-cpol - spi-max-frequency +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + examples: - | #include <dt-bindings/interrupt-controller/irq.h> diff --git a/dts/Bindings/iio/imu/bosch,bmi160.yaml b/dts/Bindings/iio/imu/bosch,bmi160.yaml index 6e73cd889b..a076038254 100644 --- a/dts/Bindings/iio/imu/bosch,bmi160.yaml +++ b/dts/Bindings/iio/imu/bosch,bmi160.yaml @@ -46,13 +46,14 @@ properties: mount-matrix: description: an optional 3x3 mounting rotation matrix - spi-max-frequency: true - required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/imu/bosch,bno055.yaml b/dts/Bindings/iio/imu/bosch,bno055.yaml new file mode 100644 index 0000000000..e0d06db161 --- /dev/null +++ b/dts/Bindings/iio/imu/bosch,bno055.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/imu/bosch,bno055.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bosch BNO055 + +maintainers: + - Andrea Merello <andrea.merello@iit.it> + +description: | + Inertial Measurement Unit with Accelerometer, Gyroscope, Magnetometer and + internal MCU for sensor fusion + https://www.bosch-sensortec.com/products/smart-sensors/bno055/ + +properties: + compatible: + enum: + - bosch,bno055 + + reg: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + serial { + imu { + compatible = "bosch,bno055"; + reset-gpios = <&gpio0 54 GPIO_ACTIVE_LOW>; + clocks = <&imu_clk>; + }; + }; + + - | + #include <dt-bindings/gpio/gpio.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + imu@28 { + compatible = "bosch,bno055"; + reg = <0x28>; + reset-gpios = <&gpio0 54 GPIO_ACTIVE_LOW>; + clocks = <&imu_clk>; + }; + }; diff --git a/dts/Bindings/iio/imu/invensense,icm42600.yaml b/dts/Bindings/iio/imu/invensense,icm42600.yaml index 4c1c083d0e..488349755c 100644 --- a/dts/Bindings/iio/imu/invensense,icm42600.yaml +++ b/dts/Bindings/iio/imu/invensense,icm42600.yaml @@ -47,7 +47,6 @@ properties: vddio-supply: description: Regulator that provides power to the bus - spi-max-frequency: true spi-cpha: true spi-cpol: true @@ -56,7 +55,10 @@ required: - reg - interrupts -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/imu/invensense,mpu6050.yaml b/dts/Bindings/iio/imu/invensense,mpu6050.yaml index 3ebc6526d8..ec64d7877f 100644 --- a/dts/Bindings/iio/imu/invensense,mpu6050.yaml +++ b/dts/Bindings/iio/imu/invensense,mpu6050.yaml @@ -40,8 +40,6 @@ properties: interrupts: maxItems: 1 - spi-max-frequency: true - vdd-supply: true vddio-supply: true @@ -54,6 +52,7 @@ properties: These devices also support an auxiliary i2c bus via an i2c-gate. allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# - if: not: properties: @@ -67,7 +66,7 @@ allOf: properties: i2c-gate: false -additionalProperties: false +unevaluatedProperties: false required: - compatible diff --git a/dts/Bindings/iio/imu/nxp,fxos8700.yaml b/dts/Bindings/iio/imu/nxp,fxos8700.yaml index 0203b83b85..24416b59b7 100644 --- a/dts/Bindings/iio/imu/nxp,fxos8700.yaml +++ b/dts/Bindings/iio/imu/nxp,fxos8700.yaml @@ -36,13 +36,14 @@ properties: drive-open-drain: type: boolean - spi-max-frequency: true - required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/imu/st,lsm6dsx.yaml b/dts/Bindings/iio/imu/st,lsm6dsx.yaml index 5d4839f008..fe1e02e5d7 100644 --- a/dts/Bindings/iio/imu/st,lsm6dsx.yaml +++ b/dts/Bindings/iio/imu/st,lsm6dsx.yaml @@ -35,6 +35,9 @@ properties: - items: - const: st,asm330lhhx - const: st,lsm6dsr + - items: + - const: st,lsm6dstx + - const: st,lsm6dst reg: maxItems: 1 @@ -45,8 +48,6 @@ properties: description: Supports up to 2 interrupt lines via the INT1 and INT2 pins. - spi-max-frequency: true - vdd-supply: description: if defined provides VDD power to the sensor. @@ -81,12 +82,15 @@ properties: wakeup-source: $ref: /schemas/types.yaml#/definitions/flag -additionalProperties: false - required: - compatible - reg +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + examples: - | #include <dt-bindings/interrupt-controller/irq.h> diff --git a/dts/Bindings/iio/light/liteon,ltrf216a.yaml b/dts/Bindings/iio/light/liteon,ltrf216a.yaml new file mode 100644 index 0000000000..7de1b0e721 --- /dev/null +++ b/dts/Bindings/iio/light/liteon,ltrf216a.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/light/liteon,ltrf216a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LTRF216A Ambient Light Sensor + +maintainers: + - Shreeya Patel <shreeya.patel@collabora.com> + +description: + Ambient light sensing with an i2c interface. + +properties: + compatible: + const: liteon,ltrf216a + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vdd-supply: + description: Regulator that provides power to the sensor. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + light-sensor@53 { + compatible = "liteon,ltrf216a"; + reg = <0x53>; + vdd-supply = <&vdd_regulator>; + interrupt-parent = <&gpio0>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + }; + }; diff --git a/dts/Bindings/iio/potentiometer/microchip,mcp41010.yaml b/dts/Bindings/iio/potentiometer/microchip,mcp41010.yaml index 567697d996..87e88f2a99 100644 --- a/dts/Bindings/iio/potentiometer/microchip,mcp41010.yaml +++ b/dts/Bindings/iio/potentiometer/microchip,mcp41010.yaml @@ -25,14 +25,15 @@ properties: reg: maxItems: 1 - spi-max-frequency: true - -additionalProperties: false - required: - compatible - reg +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + examples: - | spi { diff --git a/dts/Bindings/iio/potentiometer/microchip,mcp4131.yaml b/dts/Bindings/iio/potentiometer/microchip,mcp4131.yaml index 32e92bced8..896fe0b5ed 100644 --- a/dts/Bindings/iio/potentiometer/microchip,mcp4131.yaml +++ b/dts/Bindings/iio/potentiometer/microchip,mcp4131.yaml @@ -80,14 +80,15 @@ properties: reg: maxItems: 1 - spi-max-frequency: true - -additionalProperties: false - required: - compatible - reg +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + examples: - | spi { diff --git a/dts/Bindings/iio/pressure/asc,dlhl60d.yaml b/dts/Bindings/iio/pressure/asc,dlhl60d.yaml index be2be4b556..1f9fe15b4b 100644 --- a/dts/Bindings/iio/pressure/asc,dlhl60d.yaml +++ b/dts/Bindings/iio/pressure/asc,dlhl60d.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: All Sensors DLH series low voltage digital pressure sensors maintainers: - - Tomislav Denis <tomislav.denis@avl.com> + - Jonathan Cameron <jic23@kernel.org> description: | Bindings for the All Sensors DLH series pressure sensors. diff --git a/dts/Bindings/iio/pressure/bmp085.yaml b/dts/Bindings/iio/pressure/bmp085.yaml index 49257f9251..72cd2c2d3f 100644 --- a/dts/Bindings/iio/pressure/bmp085.yaml +++ b/dts/Bindings/iio/pressure/bmp085.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/iio/pressure/bmp085.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: BMP085/BMP180/BMP280/BME280 pressure iio sensors +title: BMP085/BMP180/BMP280/BME280/BMP380 pressure iio sensors maintainers: - Andreas Klinger <ak@it-klinger.de> @@ -16,6 +16,7 @@ description: | https://www.bosch-sensortec.com/bst/products/all_products/bmp180 https://www.bosch-sensortec.com/bst/products/all_products/bmp280 https://www.bosch-sensortec.com/bst/products/all_products/bme280 + https://www.bosch-sensortec.com/bst/products/all_products/bmp380 properties: compatible: @@ -24,6 +25,7 @@ properties: - bosch,bmp180 - bosch,bmp280 - bosch,bme280 + - bosch,bmp380 reg: maxItems: 1 diff --git a/dts/Bindings/iio/samsung,sensorhub-rinato.yaml b/dts/Bindings/iio/samsung,sensorhub-rinato.yaml index a88b3b14d6..dd2ae2bd1a 100644 --- a/dts/Bindings/iio/samsung,sensorhub-rinato.yaml +++ b/dts/Bindings/iio/samsung,sensorhub-rinato.yaml @@ -40,10 +40,6 @@ properties: description: Reset the sensorhub. - spi-max-frequency: true - -additionalProperties: false - required: - compatible - reg @@ -52,6 +48,11 @@ required: - mcu-ap-gpios - mcu-reset-gpios +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + examples: - | spi { diff --git a/dts/Bindings/iio/st,st-sensors.yaml b/dts/Bindings/iio/st,st-sensors.yaml index fcb2902683..250439b131 100644 --- a/dts/Bindings/iio/st,st-sensors.yaml +++ b/dts/Bindings/iio/st,st-sensors.yaml @@ -73,6 +73,7 @@ properties: - description: STMicroelectronics Pressure Sensors enum: - st,lps001wp-press + - st,lps22df - st,lps22hb-press - st,lps22hh - st,lps25h-press @@ -141,6 +142,7 @@ allOf: - st,lis2mdl - st,lis3l02dq - st,lis3lv02dl-accel + - st,lps22df - st,lps22hb-press - st,lps22hh - st,lps25h-press diff --git a/dts/Bindings/iio/temperature/maxim,max31855k.yaml b/dts/Bindings/iio/temperature/maxim,max31855k.yaml index 9969bac66a..0805ed7e21 100644 --- a/dts/Bindings/iio/temperature/maxim,max31855k.yaml +++ b/dts/Bindings/iio/temperature/maxim,max31855k.yaml @@ -32,7 +32,6 @@ properties: reg: maxItems: 1 - spi-max-frequency: true spi-cpha: true required: @@ -40,6 +39,7 @@ required: - reg allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# - if: properties: compatible: @@ -53,7 +53,7 @@ allOf: properties: spi-cpha: false -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/temperature/maxim,max31856.yaml b/dts/Bindings/iio/temperature/maxim,max31856.yaml index 873b347666..228a941654 100644 --- a/dts/Bindings/iio/temperature/maxim,max31856.yaml +++ b/dts/Bindings/iio/temperature/maxim,max31856.yaml @@ -19,7 +19,6 @@ properties: reg: maxItems: 1 - spi-max-frequency: true spi-cpha: true thermocouple-type: @@ -34,7 +33,10 @@ required: - reg - spi-cpha -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/temperature/maxim,max31865.yaml b/dts/Bindings/iio/temperature/maxim,max31865.yaml index aafb33b165..a2823ed686 100644 --- a/dts/Bindings/iio/temperature/maxim,max31865.yaml +++ b/dts/Bindings/iio/temperature/maxim,max31865.yaml @@ -25,7 +25,6 @@ properties: enables 3-wire RTD connection. Else 2-wire or 4-wire RTD connection. type: boolean - spi-max-frequency: true spi-cpha: true required: @@ -33,7 +32,10 @@ required: - reg - spi-cpha -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/iio/temperature/melexis,mlx90632.yaml b/dts/Bindings/iio/temperature/melexis,mlx90632.yaml index b547ddcd54..4a55e7f25a 100644 --- a/dts/Bindings/iio/temperature/melexis,mlx90632.yaml +++ b/dts/Bindings/iio/temperature/melexis,mlx90632.yaml @@ -35,6 +35,9 @@ properties: maxItems: 1 description: Default is 0x3a, but can be reprogrammed. + vdd-supply: + description: provide VDD power to the sensor. + required: - compatible - reg @@ -50,6 +53,7 @@ examples: temp-sensor@3a { compatible = "melexis,mlx90632"; reg = <0x3a>; + vdd-supply = <&ldo4_reg>; }; }; ... diff --git a/dts/Bindings/input/adc-joystick.yaml b/dts/Bindings/input/adc-joystick.yaml index 64d961458a..da0f8dfca8 100644 --- a/dts/Bindings/input/adc-joystick.yaml +++ b/dts/Bindings/input/adc-joystick.yaml @@ -14,6 +14,9 @@ description: > Bindings for joystick devices connected to ADC controllers supporting the Industrial I/O subsystem. +allOf: + - $ref: input.yaml# + properties: compatible: const: adc-joystick @@ -28,6 +31,8 @@ properties: https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/iio-consumer.yaml for details. + poll-interval: true + '#address-cells': const: 1 diff --git a/dts/Bindings/input/adi,adp5588.yaml b/dts/Bindings/input/adi,adp5588.yaml new file mode 100644 index 0000000000..26ea66834a --- /dev/null +++ b/dts/Bindings/input/adi,adp5588.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/adi,adp5588.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADP5588 Keypad Controller + +maintainers: + - Nuno Sá <nuno.sa@analog.com> + +description: | + Analog Devices Mobile I/O Expander and QWERTY Keypad Controller + https://www.analog.com/media/en/technical-documentation/data-sheets/ADP5588.pdf + +allOf: + - $ref: matrix-keymap.yaml# + - $ref: input.yaml# + +properties: + compatible: + enum: + - adi,adp5587 + - adi,adp5588 + + reg: + maxItems: 1 + + vcc-supply: + description: Supply Voltage Input + + reset-gpios: + description: + If specified, it will be asserted during driver probe. As the line is + active low, it should be marked GPIO_ACTIVE_LOW. + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-controller: + description: + This property applies if either keypad,num-rows lower than 8 or + keypad,num-columns lower than 10. + + '#gpio-cells': + const: 2 + + interrupt-controller: + description: + This property applies if either keypad,num-rows lower than 8 or + keypad,num-columns lower than 10. + + '#interrupt-cells': + const: 2 + + adi,unlock-keys: + description: + Specifies a maximum of 2 keys that can be used to unlock the keypad. + If this property is set, the keyboard will be locked and only unlocked + after these keys are pressed. If only one key is set, a double click is + needed to unlock the keypad. The value of this property cannot be bigger + or equal than keypad,num-rows * keypad,num-columns. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + +required: + - compatible + - reg + - interrupts + - keypad,num-rows + - keypad,num-columns + - linux,keymap + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/input/input.h> + #include <dt-bindings/gpio/gpio.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + keys@34 { + compatible = "adi,adp5588"; + reg = <0x34>; + + vcc-supply = <&vcc>; + interrupts = <21 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio>; + reset-gpios = <&gpio 20 GPIO_ACTIVE_LOW>; + + keypad,num-rows = <1>; + keypad,num-columns = <9>; + linux,keymap = < + MATRIX_KEY(0x00, 0x00, KEY_1) + MATRIX_KEY(0x00, 0x01, KEY_2) + MATRIX_KEY(0x00, 0x02, KEY_3) + MATRIX_KEY(0x00, 0x03, KEY_4) + MATRIX_KEY(0x00, 0x04, KEY_5) + MATRIX_KEY(0x00, 0x05, KEY_6) + MATRIX_KEY(0x00, 0x06, KEY_7) + MATRIX_KEY(0x00, 0x07, KEY_8) + MATRIX_KEY(0x00, 0x08, KEY_9) + >; + }; + }; +... diff --git a/dts/Bindings/input/allwinner,sun4i-a10-lradc-keys.yaml b/dts/Bindings/input/allwinner,sun4i-a10-lradc-keys.yaml index 9700dc468b..5d631f7137 100644 --- a/dts/Bindings/input/allwinner,sun4i-a10-lradc-keys.yaml +++ b/dts/Bindings/input/allwinner,sun4i-a10-lradc-keys.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/input/allwinner,sun4i-a10-lradc-keys.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 LRADC Device Tree Bindings +title: Allwinner A10 LRADC maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/input/hid-over-i2c.txt b/dts/Bindings/input/hid-over-i2c.txt deleted file mode 100644 index 34c43d3bdd..0000000000 --- a/dts/Bindings/input/hid-over-i2c.txt +++ /dev/null @@ -1,46 +0,0 @@ -* HID over I2C Device-Tree bindings - -HID over I2C provides support for various Human Interface Devices over the -I2C bus. These devices can be for example touchpads, keyboards, touch screens -or sensors. - -The specification has been written by Microsoft and is currently available here: -http://msdn.microsoft.com/en-us/library/windows/hardware/hh852380.aspx - -If this binding is used, the kernel module i2c-hid will handle the communication -with the device and the generic hid core layer will handle the protocol. - -Required properties: -- compatible: must be "hid-over-i2c" -- reg: i2c slave address -- hid-descr-addr: HID descriptor address -- interrupts: interrupt line - -Additional optional properties: - -Some devices may support additional optional properties to help with, e.g., -power sequencing. The following properties can be supported by one or more -device-specific compatible properties, which should be used in addition to the -"hid-over-i2c" string. - -- compatible: - * "wacom,w9013" (Wacom W9013 digitizer). Supports: - - vdd-supply (3.3V) - - vddl-supply (1.8V) - - post-power-on-delay-ms - -- vdd-supply: phandle of the regulator that provides the supply voltage. -- post-power-on-delay-ms: time required by the device after enabling its regulators - or powering it on, before it is ready for communication. -- touchscreen-inverted-x: See touchscreen.txt -- touchscreen-inverted-y: See touchscreen.txt - -Example: - - i2c-hid-dev@2c { - compatible = "hid-over-i2c"; - reg = <0x2c>; - hid-descr-addr = <0x0020>; - interrupt-parent = <&gpx3>; - interrupts = <3 2>; - }; diff --git a/dts/Bindings/input/hid-over-i2c.yaml b/dts/Bindings/input/hid-over-i2c.yaml new file mode 100644 index 0000000000..7156b08f76 --- /dev/null +++ b/dts/Bindings/input/hid-over-i2c.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/hid-over-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HID over I2C Devices + +maintainers: + - Benjamin Tissoires <benjamin.tissoires@redhat.com> + - Jiri Kosina <jkosina@suse.cz> + +description: |+ + HID over I2C provides support for various Human Interface Devices over the + I2C bus. These devices can be for example touchpads, keyboards, touch screens + or sensors. + + The specification has been written by Microsoft and is currently available here: + https://msdn.microsoft.com/en-us/library/windows/hardware/hh852380.aspx + + If this binding is used, the kernel module i2c-hid will handle the communication + with the device and the generic hid core layer will handle the protocol. + +allOf: + - $ref: /schemas/input/touchscreen/touchscreen.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - wacom,w9013 + - const: hid-over-i2c + - description: Just "hid-over-i2c" alone is allowed, but not recommended. + const: hid-over-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + hid-descr-addr: + description: HID descriptor address + $ref: /schemas/types.yaml#/definitions/uint32 + + post-power-on-delay-ms: + description: Time required by the device after enabling its regulators + or powering it on, before it is ready for communication. + + touchscreen-inverted-x: true + + touchscreen-inverted-y: true + + vdd-supply: + description: 3.3V supply + + vddl-supply: + description: 1.8V supply + + wakeup-source: true + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + hid@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + hid-descr-addr = <0x0020>; + interrupts = <3 2>; + }; + }; +... diff --git a/dts/Bindings/input/ibm,op-panel.yaml b/dts/Bindings/input/ibm,op-panel.yaml new file mode 100644 index 0000000000..29a1879e35 --- /dev/null +++ b/dts/Bindings/input/ibm,op-panel.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/ibm,op-panel.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IBM Operation Panel + +maintainers: + - Eddie James <eajames@linux.ibm.com> + +allOf: + - $ref: input.yaml# + +description: | + The IBM Operation Panel provides a simple interface to control the connected + server. It has a display and three buttons: two directional arrows and one + 'Enter' button. + +properties: + compatible: + const: ibm,op-panel + + reg: + maxItems: 1 + + linux,keycodes: + minItems: 1 + maxItems: 3 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/i2c/i2c.h> + #include <dt-bindings/input/input.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + ibm-op-panel@62 { + compatible = "ibm,op-panel"; + reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>; + linux,keycodes = <KEY_UP>, <KEY_DOWN>, <KEY_ENTER>; + }; + }; diff --git a/dts/Bindings/input/imx-keypad.yaml b/dts/Bindings/input/imx-keypad.yaml index f21db81206..7514df62b5 100644 --- a/dts/Bindings/input/imx-keypad.yaml +++ b/dts/Bindings/input/imx-keypad.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/input/imx-keypad.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Freescale i.MX Keypad Port(KPP) device tree bindings +title: Freescale i.MX Keypad Port(KPP) maintainers: - Liu Ying <gnuiyl@gmail.com> diff --git a/dts/Bindings/input/mediatek,mt6779-keypad.yaml b/dts/Bindings/input/mediatek,mt6779-keypad.yaml index 03ebd2665d..d768c30f48 100644 --- a/dts/Bindings/input/mediatek,mt6779-keypad.yaml +++ b/dts/Bindings/input/mediatek,mt6779-keypad.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/input/mediatek,mt6779-keypad.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek's Keypad Controller device tree bindings +title: Mediatek's Keypad Controller maintainers: - Mattijs Korpershoek <mkorpershoek@baylibre.com> @@ -49,6 +49,12 @@ properties: maximum: 256 default: 16 + mediatek,keys-per-group: + description: each (row, column) group has multiple keys + $ref: /schemas/types.yaml#/definitions/uint32 + default: 1 + maximum: 2 + required: - compatible - reg @@ -56,7 +62,7 @@ required: - clocks - clock-names -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/input/mediatek,pmic-keys.yaml b/dts/Bindings/input/mediatek,pmic-keys.yaml new file mode 100644 index 0000000000..2f72ec4184 --- /dev/null +++ b/dts/Bindings/input/mediatek,pmic-keys.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/mediatek,pmic-keys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek PMIC Keys + +maintainers: + - Chen Zhong <chen.zhong@mediatek.com> + +allOf: + - $ref: input.yaml# + +description: | + There are two key functions provided by MT6397, MT6323 and other MediaTek + PMICs: pwrkey and homekey. + The key functions are defined as the subnode of the function node provided + by the PMIC that is defined as a Multi-Function Device (MFD). + + For MediaTek MT6323/MT6397 PMIC bindings see + Documentation/devicetree/bindings/mfd/mt6397.txt + +properties: + compatible: + enum: + - mediatek,mt6323-keys + - mediatek,mt6331-keys + - mediatek,mt6358-keys + - mediatek,mt6397-keys + + power-off-time-sec: true + + mediatek,long-press-mode: + description: | + Key long-press force shutdown setting + 0 - disabled + 1 - pwrkey + 2 - pwrkey+homekey + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + maximum: 2 + +patternProperties: + "^((power|home)|(key-[a-z0-9-]+|[a-z0-9-]+-key))$": + $ref: input.yaml# + + properties: + interrupts: + minItems: 1 + items: + - description: Key press interrupt + - description: Key release interrupt + + interrupt-names: true + + linux-keycodes: + maxItems: 1 + + wakeup-source: true + + required: + - linux,keycodes + + if: + properties: + interrupt-names: + contains: + const: powerkey + then: + properties: + interrupt-names: + minItems: 1 + items: + - const: powerkey + - const: powerkey_r + else: + properties: + interrupt-names: + minItems: 1 + items: + - const: homekey + - const: homekey_r + + unevaluatedProperties: false + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/input/input.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pmic { + compatible = "mediatek,mt6397"; + + keys { + compatible = "mediatek,mt6397-keys"; + mediatek,long-press-mode = <1>; + power-off-time-sec = <0>; + + key-power { + linux,keycodes = <KEY_POWER>; + wakeup-source; + }; + + key-home { + linux,keycodes = <KEY_VOLUMEDOWN>; + }; + }; + }; diff --git a/dts/Bindings/input/mtk-pmic-keys.txt b/dts/Bindings/input/mtk-pmic-keys.txt deleted file mode 100644 index 9d00f2a8e1..0000000000 --- a/dts/Bindings/input/mtk-pmic-keys.txt +++ /dev/null @@ -1,46 +0,0 @@ -MediaTek MT6397/MT6323 PMIC Keys Device Driver - -There are two key functions provided by MT6397/MT6323 PMIC, pwrkey -and homekey. The key functions are defined as the subnode of the function -node provided by MT6397/MT6323 PMIC that is being defined as one kind -of Muti-Function Device (MFD) - -For MT6397/MT6323 MFD bindings see: -Documentation/devicetree/bindings/mfd/mt6397.txt - -Required properties: -- compatible: Should be one of: - - "mediatek,mt6397-keys" - - "mediatek,mt6323-keys" - - "mediatek,mt6358-keys" -- linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml - -Optional Properties: -- wakeup-source: See Documentation/devicetree/bindings/power/wakeup-source.txt -- mediatek,long-press-mode: Long press key shutdown setting, 1 for - pwrkey only, 2 for pwrkey/homekey together, others for disabled. -- power-off-time-sec: See Documentation/devicetree/bindings/input/input.yaml - -Example: - - pmic: mt6397 { - compatible = "mediatek,mt6397"; - - ... - - mt6397keys: mt6397keys { - compatible = "mediatek,mt6397-keys"; - mediatek,long-press-mode = <1>; - power-off-time-sec = <0>; - - power { - linux,keycodes = <116>; - wakeup-source; - }; - - home { - linux,keycodes = <114>; - }; - }; - - }; diff --git a/dts/Bindings/input/pine64,pinephone-keyboard.yaml b/dts/Bindings/input/pine64,pinephone-keyboard.yaml new file mode 100644 index 0000000000..e4a0ac0fff --- /dev/null +++ b/dts/Bindings/input/pine64,pinephone-keyboard.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/pine64,pinephone-keyboard.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Pine64 PinePhone keyboard device tree bindings + +maintainers: + - Samuel Holland <samuel@sholland.org> + +description: + A keyboard accessory is available for the Pine64 PinePhone and PinePhone Pro. + It connects via I2C, providing a raw scan matrix, a flashing interface, and a + subordinate I2C bus for communication with a battery charger IC. + +properties: + compatible: + const: pine64,pinephone-keyboard + + reg: + const: 0x15 + + interrupts: + maxItems: 1 + + vbat-supply: + description: Supply for the keyboard MCU + + wakeup-source: true + + i2c: + $ref: /schemas/i2c/i2c-controller.yaml# + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/input/input.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + keyboard@15 { + compatible = "pine64,pinephone-keyboard"; + reg = <0x15>; + interrupt-parent = <&r_pio>; + interrupts = <0 12 IRQ_TYPE_EDGE_FALLING>; /* PL12 */ + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + charger@75 { + reg = <0x75>; + }; + }; + }; + }; diff --git a/dts/Bindings/input/qcom,pm8xxx-vib.txt b/dts/Bindings/input/qcom,pm8xxx-vib.txt deleted file mode 100644 index 64bb990075..0000000000 --- a/dts/Bindings/input/qcom,pm8xxx-vib.txt +++ /dev/null @@ -1,23 +0,0 @@ -Qualcomm PM8xxx PMIC Vibrator - -PROPERTIES - -- compatible: - Usage: required - Value type: <string> - Definition: must be one of: - "qcom,pm8058-vib" - "qcom,pm8916-vib" - "qcom,pm8921-vib" - -- reg: - Usage: required - Value type: <prop-encoded-array> - Definition: address of vibration control register - -EXAMPLE - - vibrator@4a { - compatible = "qcom,pm8058-vib"; - reg = <0x4a>; - }; diff --git a/dts/Bindings/input/qcom,pm8xxx-vib.yaml b/dts/Bindings/input/qcom,pm8xxx-vib.yaml new file mode 100644 index 0000000000..c8832cd0d7 --- /dev/null +++ b/dts/Bindings/input/qcom,pm8xxx-vib.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/qcom,pm8xxx-vib.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PM8xxx PMIC Vibrator + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +properties: + compatible: + enum: + - qcom,pm8058-vib + - qcom,pm8916-vib + - qcom,pm8921-vib + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pmic { + #address-cells = <1>; + #size-cells = <0>; + + vibrator@4a { + compatible = "qcom,pm8058-vib"; + reg = <0x4a>; + }; + }; diff --git a/dts/Bindings/input/regulator-haptic.yaml b/dts/Bindings/input/regulator-haptic.yaml index b1ae72f9cd..627891e1ef 100644 --- a/dts/Bindings/input/regulator-haptic.yaml +++ b/dts/Bindings/input/regulator-haptic.yaml @@ -4,7 +4,7 @@ $id: "http://devicetree.org/schemas/input/regulator-haptic.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: Regulator Haptic Device Tree Bindings +title: Regulator Haptic maintainers: - Jaewon Kim <jaewon02.kim@samsung.com> diff --git a/dts/Bindings/input/sprd,sc27xx-vibrator.yaml b/dts/Bindings/input/sprd,sc27xx-vibrator.yaml index 5d67fc8ebc..a401a0bfcb 100644 --- a/dts/Bindings/input/sprd,sc27xx-vibrator.yaml +++ b/dts/Bindings/input/sprd,sc27xx-vibrator.yaml @@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/input/sprd,sc27xx-vibrator.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Spreadtrum SC27xx PMIC Vibrator Device Tree Bindings +title: Spreadtrum SC27xx PMIC Vibrator maintainers: - Orson Zhai <orsonzhai@gmail.com> diff --git a/dts/Bindings/input/touchscreen/auo_pixcir_ts.txt b/dts/Bindings/input/touchscreen/auo_pixcir_ts.txt index f40f21c642..b8db975e9f 100644 --- a/dts/Bindings/input/touchscreen/auo_pixcir_ts.txt +++ b/dts/Bindings/input/touchscreen/auo_pixcir_ts.txt @@ -17,10 +17,10 @@ Example: auo_pixcir_ts@5c { compatible = "auo,auo_pixcir_ts"; reg = <0x5c>; - interrupts = <2 0>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - gpios = <&gpf 2 0 2>, /* INT */ - <&gpf 5 1 0>; /* RST */ + gpios = <&gpf 2 0 GPIO_LEVEL_HIGH>, /* INT */ + <&gpf 5 1 GPIO_LEVEL_LOW>; /* RST */ x-size = <800>; y-size = <600>; diff --git a/dts/Bindings/input/touchscreen/colibri-vf50-ts.txt b/dts/Bindings/input/touchscreen/colibri-vf50-ts.txt index 2e1490a8fe..ca304357c3 100644 --- a/dts/Bindings/input/touchscreen/colibri-vf50-ts.txt +++ b/dts/Bindings/input/touchscreen/colibri-vf50-ts.txt @@ -3,15 +3,16 @@ Required Properties: - compatible must be toradex,vf50-touchscreen - io-channels: adc channels being used by the Colibri VF50 module + IIO ADC for Y-, X-, Y+, X+ connections - xp-gpios: FET gate driver for input of X+ - xm-gpios: FET gate driver for input of X- - yp-gpios: FET gate driver for input of Y+ - ym-gpios: FET gate driver for input of Y- -- interrupts: pen irq interrupt for touch detection -- pinctrl-names: "idle", "default", "gpios" -- pinctrl-0: pinctrl node for pen/touch detection state pinmux +- interrupts: pen irq interrupt for touch detection, signal from X plate +- pinctrl-names: "idle", "default" +- pinctrl-0: pinctrl node for pen/touch detection, pinctrl must provide + pull-up resistor on X+, X-. - pinctrl-1: pinctrl node for X/Y and pressure measurement (ADC) state pinmux -- pinctrl-2: pinctrl node for gpios functioning as FET gate drivers - vf50-ts-min-pressure: pressure level at which to stop measuring X/Y values Example: @@ -26,9 +27,8 @@ Example: ym-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; interrupt-parent = <&gpio0>; interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "idle","default","gpios"; - pinctrl-0 = <&pinctrl_touchctrl_idle>; - pinctrl-1 = <&pinctrl_touchctrl_default>; - pinctrl-2 = <&pinctrl_touchctrl_gpios>; + pinctrl-names = "idle","default"; + pinctrl-0 = <&pinctrl_touchctrl_idle>, <&pinctrl_touchctrl_gpios>; + pinctrl-1 = <&pinctrl_touchctrl_default>, <&pinctrl_touchctrl_gpios>; vf50-ts-min-pressure = <200>; }; diff --git a/dts/Bindings/input/touchscreen/elan,elants_i2c.yaml b/dts/Bindings/input/touchscreen/elan,elants_i2c.yaml index a9b53c2e6f..f9053e5e9b 100644 --- a/dts/Bindings/input/touchscreen/elan,elants_i2c.yaml +++ b/dts/Bindings/input/touchscreen/elan,elants_i2c.yaml @@ -14,9 +14,13 @@ allOf: properties: compatible: - enum: - - elan,ektf3624 - - elan,ekth3500 + oneOf: + - enum: + - elan,ektf3624 + - elan,ekth3500 + - items: + - const: elan,ekth3915 + - const: elan,ekth3500 reg: maxItems: 1 diff --git a/dts/Bindings/input/touchscreen/stmpe.txt b/dts/Bindings/input/touchscreen/stmpe.txt index c549924603..238b51555c 100644 --- a/dts/Bindings/input/touchscreen/stmpe.txt +++ b/dts/Bindings/input/touchscreen/stmpe.txt @@ -54,8 +54,7 @@ Optional properties common with MFD (deprecated): 1 -> 3.25 MHz 2 || 3 -> 6.5 MHz -Node name must be stmpe_touchscreen and should be child node of stmpe node to -which it belongs. +Node should be child node of stmpe node to which it belongs. Note that common ADC settings of stmpe_touchscreen (child) will take precedence over the settings done in MFD. diff --git a/dts/Bindings/interconnect/fsl,imx8m-noc.yaml b/dts/Bindings/interconnect/fsl,imx8m-noc.yaml index fa4f7685ab..f7a5e31c50 100644 --- a/dts/Bindings/interconnect/fsl,imx8m-noc.yaml +++ b/dts/Bindings/interconnect/fsl,imx8m-noc.yaml @@ -47,7 +47,8 @@ properties: maxItems: 1 operating-points-v2: true - opp-table: true + opp-table: + type: object fsl,ddrc: $ref: "/schemas/types.yaml#/definitions/phandle" diff --git a/dts/Bindings/interconnect/mediatek,cci.yaml b/dts/Bindings/interconnect/mediatek,cci.yaml index 449c7c9882..58611ba2a0 100644 --- a/dts/Bindings/interconnect/mediatek,cci.yaml +++ b/dts/Bindings/interconnect/mediatek,cci.yaml @@ -36,7 +36,8 @@ properties: - const: intermediate operating-points-v2: true - opp-table: true + opp-table: + type: object proc-supply: description: diff --git a/dts/Bindings/interconnect/qcom,msm8998-bwmon.yaml b/dts/Bindings/interconnect/qcom,msm8998-bwmon.yaml index c2e697f6e6..2684562df4 100644 --- a/dts/Bindings/interconnect/qcom,msm8998-bwmon.yaml +++ b/dts/Bindings/interconnect/qcom,msm8998-bwmon.yaml @@ -24,9 +24,12 @@ properties: oneOf: - items: - enum: + - qcom,sc7280-bwmon - qcom,sdm845-bwmon - const: qcom,msm8998-bwmon - const: qcom,msm8998-bwmon # BWMON v4 + - const: qcom,sc7280-llcc-bwmon # BWMON v5 + - const: qcom,sdm845-llcc-bwmon # BWMON v5 interconnects: maxItems: 1 @@ -35,7 +38,8 @@ properties: maxItems: 1 operating-points-v2: true - opp-table: true + opp-table: + type: object reg: # BWMON v4 (currently described) and BWMON v5 use one register address diff --git a/dts/Bindings/interrupt-controller/allwinner,sun4i-a10-ic.yaml b/dts/Bindings/interrupt-controller/allwinner,sun4i-a10-ic.yaml index 953d875b5e..a713633be7 100644 --- a/dts/Bindings/interrupt-controller/allwinner,sun4i-a10-ic.yaml +++ b/dts/Bindings/interrupt-controller/allwinner,sun4i-a10-ic.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun4i-a10-ic.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Interrupt Controller Device Tree Bindings +title: Allwinner A10 Interrupt Controller maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml b/dts/Bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml index 4db24b8a9f..4fa6fd400e 100644 --- a/dts/Bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml +++ b/dts/Bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A31 NMI/Wakeup Interrupt Controller Device Tree Bindings +title: Allwinner A31 NMI/Wakeup Interrupt Controller maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml b/dts/Bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml index 7fc9ad5ef3..83603180d8 100644 --- a/dts/Bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml +++ b/dts/Bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A20 Non-Maskable Interrupt Controller Device Tree Bindings +title: Allwinner A20 Non-Maskable Interrupt Controller maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/interrupt-controller/arm,gic-v3.yaml b/dts/Bindings/interrupt-controller/arm,gic-v3.yaml index 3912a89162..9f7d3e11aa 100644 --- a/dts/Bindings/interrupt-controller/arm,gic-v3.yaml +++ b/dts/Bindings/interrupt-controller/arm,gic-v3.yaml @@ -170,7 +170,6 @@ dependencies: required: - compatible - - interrupts - reg patternProperties: diff --git a/dts/Bindings/interrupt-controller/arm,gic.yaml b/dts/Bindings/interrupt-controller/arm,gic.yaml index 62219a5c21..2202569074 100644 --- a/dts/Bindings/interrupt-controller/arm,gic.yaml +++ b/dts/Bindings/interrupt-controller/arm,gic.yaml @@ -64,9 +64,9 @@ properties: interrupt-controller: true "#address-cells": - enum: [ 0, 1 ] + enum: [ 0, 1, 2 ] "#size-cells": - const: 1 + enum: [ 1, 2 ] "#interrupt-cells": const: 3 diff --git a/dts/Bindings/interrupt-controller/fsl,mu-msi.yaml b/dts/Bindings/interrupt-controller/fsl,mu-msi.yaml new file mode 100644 index 0000000000..799ae5c3e3 --- /dev/null +++ b/dts/Bindings/interrupt-controller/fsl,mu-msi.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: | + The Messaging Unit module enables two processors within the SoC to + communicate and coordinate by passing messages (e.g. data, status + and control) through the MU interface. The MU also provides the ability + for one processor (A side) to signal the other processor (B side) using + interrupts. + + Because the MU manages the messaging between processors, the MU uses + different clocks (from each side of the different peripheral buses). + Therefore, the MU must synchronize the accesses from one side to the + other. The MU accomplishes synchronization using two sets of matching + registers (Processor A-side, Processor B-side). + + MU can work as msi interrupt controller to do doorbell + +allOf: + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + enum: + - fsl,imx6sx-mu-msi + - fsl,imx7ulp-mu-msi + - fsl,imx8ulp-mu-msi + - fsl,imx8ulp-mu-msi-s4 + + reg: + items: + - description: a side register base address + - description: b side register base address + + reg-names: + items: + - const: processor-a-side + - const: processor-b-side + + interrupts: + description: a side interrupt number. + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + items: + - description: a side power domain + - description: b side power domain + + power-domain-names: + items: + - const: processor-a-side + - const: processor-b-side + + interrupt-controller: true + + msi-controller: true + + "#msi-cells": + const: 0 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - msi-controller + - "#msi-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/firmware/imx/rsrc.h> + + msi-controller@5d270000 { + compatible = "fsl,imx6sx-mu-msi"; + msi-controller; + #msi-cells = <0>; + interrupt-controller; + reg = <0x5d270000 0x10000>, /* A side */ + <0x5d300000 0x10000>; /* B side */ + reg-names = "processor-a-side", "processor-b-side"; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd IMX_SC_R_MU_12A>, + <&pd IMX_SC_R_MU_12B>; + power-domain-names = "processor-a-side", "processor-b-side"; + }; diff --git a/dts/Bindings/interrupt-controller/idt,32434-pic.yaml b/dts/Bindings/interrupt-controller/idt,32434-pic.yaml index 160ff4b07c..afb3dd80b6 100644 --- a/dts/Bindings/interrupt-controller/idt,32434-pic.yaml +++ b/dts/Bindings/interrupt-controller/idt,32434-pic.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/interrupt-controller/idt,32434-pic.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: IDT 79RC32434 Interrupt Controller Device Tree Bindings +title: IDT 79RC32434 Interrupt Controller maintainers: - Thomas Bogendoerfer <tsbogend@alpha.franken.de> diff --git a/dts/Bindings/interrupt-controller/mti,cpu-interrupt-controller.yaml b/dts/Bindings/interrupt-controller/mti,cpu-interrupt-controller.yaml new file mode 100644 index 0000000000..46a1f5f54b --- /dev/null +++ b/dts/Bindings/interrupt-controller/mti,cpu-interrupt-controller.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/mti,cpu-interrupt-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MIPS CPU Interrupt Controller + +description: > + On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU + IRQs from a devicetree file and create a irq_domain for IRQ controller. + + With the irq_domain in place we can describe how the 8 IRQs are wired to the + platforms internal interrupt controller cascade. + +maintainers: + - Thomas Bogendoerfer <tsbogend@alpha.franken.de> + +properties: + compatible: + const: mti,cpu-interrupt-controller + + '#interrupt-cells': + const: 1 + + '#address-cells': + const: 0 + + interrupt-controller: true + +additionalProperties: false + +required: + - compatible + - '#interrupt-cells' + - '#address-cells' + - interrupt-controller + +examples: + - | + interrupt-controller { + compatible = "mti,cpu-interrupt-controller"; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; diff --git a/dts/Bindings/interrupt-controller/qcom,pdc.txt b/dts/Bindings/interrupt-controller/qcom,pdc.txt deleted file mode 100644 index 159a423e55..0000000000 --- a/dts/Bindings/interrupt-controller/qcom,pdc.txt +++ /dev/null @@ -1,78 +0,0 @@ -PDC interrupt controller - -Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a -Power Domain Controller (PDC) that is on always-on domain. In addition to -providing power control for the power domains, the hardware also has an -interrupt controller that can be used to help detect edge low interrupts as -well detect interrupts when the GIC is non-operational. - -GIC is parent interrupt controller at the highest level. Platform interrupt -controller PDC is next in hierarchy, followed by others. Drivers requiring -wakeup capabilities of their device interrupts routed through the PDC, must -specify PDC as their interrupt controller and request the PDC port associated -with the GIC interrupt. See example below. - -Properties: - -- compatible: - Usage: required - Value type: <string> - Definition: Should contain "qcom,<soc>-pdc" and "qcom,pdc" - - "qcom,sc7180-pdc": For SC7180 - - "qcom,sc7280-pdc": For SC7280 - - "qcom,sdm845-pdc": For SDM845 - - "qcom,sm6350-pdc": For SM6350 - - "qcom,sm8150-pdc": For SM8150 - - "qcom,sm8250-pdc": For SM8250 - - "qcom,sm8350-pdc": For SM8350 - -- reg: - Usage: required - Value type: <prop-encoded-array> - Definition: Specifies the base physical address for PDC hardware. - -- interrupt-cells: - Usage: required - Value type: <u32> - Definition: Specifies the number of cells needed to encode an interrupt - source. - Must be 2. - The first element of the tuple is the PDC pin for the - interrupt. - The second element is the trigger type. - -- interrupt-controller: - Usage: required - Value type: <bool> - Definition: Identifies the node as an interrupt controller. - -- qcom,pdc-ranges: - Usage: required - Value type: <u32 array> - Definition: Specifies the PDC pin offset and the number of PDC ports. - The tuples indicates the valid mapping of valid PDC ports - and their hwirq mapping. - The first element of the tuple is the starting PDC port. - The second element is the GIC hwirq number for the PDC port. - The third element is the number of interrupts in sequence. - -Example: - - pdc: interrupt-controller@b220000 { - compatible = "qcom,sdm845-pdc"; - reg = <0xb220000 0x30000>; - qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - -DT binding of a device that wants to use the GIC SPI 514 as a wakeup -interrupt, must do - - - wake-device { - interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>; - }; - -In this case interrupt 514 would be mapped to port 2 on the PDC as defined by -the qcom,pdc-ranges property. diff --git a/dts/Bindings/interrupt-controller/qcom,pdc.yaml b/dts/Bindings/interrupt-controller/qcom,pdc.yaml new file mode 100644 index 0000000000..b6f56cf5fb --- /dev/null +++ b/dts/Bindings/interrupt-controller/qcom,pdc.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PDC interrupt controller + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: | + Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a + Power Domain Controller (PDC) that is on always-on domain. In addition to + providing power control for the power domains, the hardware also has an + interrupt controller that can be used to help detect edge low interrupts as + well detect interrupts when the GIC is non-operational. + + GIC is parent interrupt controller at the highest level. Platform interrupt + controller PDC is next in hierarchy, followed by others. Drivers requiring + wakeup capabilities of their device interrupts routed through the PDC, must + specify PDC as their interrupt controller and request the PDC port associated + with the GIC interrupt. See example below. + +properties: + compatible: + items: + - enum: + - qcom,sc7180-pdc + - qcom,sc7280-pdc + - qcom,sdm845-pdc + - qcom,sm6350-pdc + - qcom,sm8150-pdc + - qcom,sm8250-pdc + - qcom,sm8350-pdc + - const: qcom,pdc + + reg: + minItems: 1 + items: + - description: PDC base register region + - description: Edge or Level config register for SPI interrupts + + '#interrupt-cells': + const: 2 + + interrupt-controller: true + + qcom,pdc-ranges: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + maxItems: 32 # no hard limit + items: + items: + - description: starting PDC port + - description: GIC hwirq number for the PDC port + - description: number of interrupts in sequence + description: | + Specifies the PDC pin offset and the number of PDC ports. + The tuples indicates the valid mapping of valid PDC ports + and their hwirq mapping. + +required: + - compatible + - reg + - '#interrupt-cells' + - interrupt-controller + - qcom,pdc-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sdm845-pdc", "qcom,pdc"; + reg = <0xb220000 0x30000>; + qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + wake-device { + interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/dts/Bindings/interrupt-controller/realtek,rtl-intc.yaml b/dts/Bindings/interrupt-controller/realtek,rtl-intc.yaml index 9e76fff203..13a893b18f 100644 --- a/dts/Bindings/interrupt-controller/realtek,rtl-intc.yaml +++ b/dts/Bindings/interrupt-controller/realtek,rtl-intc.yaml @@ -6,6 +6,14 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Realtek RTL SoC interrupt controller devicetree bindings +description: + Interrupt controller and router for Realtek MIPS SoCs, allowing each SoC + interrupt to be routed to one parent CPU (hardware) interrupt, or left + disconnected. + All connected input lines from SoC peripherals can be masked individually, + and an interrupt status register is present to indicate which interrupts are + pending. + maintainers: - Birger Koblitz <mail@birger-koblitz.de> - Bert Vermeulen <bert@biot.com> @@ -13,23 +21,33 @@ maintainers: properties: compatible: - const: realtek,rtl-intc + oneOf: + - items: + - enum: + - realtek,rtl8380-intc + - const: realtek,rtl-intc + - const: realtek,rtl-intc + deprecated: true "#interrupt-cells": + description: + SoC interrupt line index. const: 1 reg: maxItems: 1 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 15 + description: + List of parent interrupts, in the order that they are connected to this + interrupt router's outputs, starting at the first output. interrupt-controller: true - "#address-cells": - const: 0 - interrupt-map: + deprecated: true description: Describes mapping from SoC interrupts to CPU interrupts required: @@ -37,21 +55,33 @@ required: - reg - "#interrupt-cells" - interrupt-controller - - "#address-cells" - - interrupt-map + +allOf: + - if: + properties: + compatible: + const: realtek,rtl-intc + then: + properties: + "#address-cells": + const: 0 + required: + - "#address-cells" + - interrupt-map + else: + required: + - interrupts additionalProperties: false examples: - | - intc: interrupt-controller@3000 { - compatible = "realtek,rtl-intc"; + interrupt-controller@3000 { + compatible = "realtek,rtl8380-intc", "realtek,rtl-intc"; #interrupt-cells = <1>; interrupt-controller; - reg = <0x3000 0x20>; - #address-cells = <0>; - interrupt-map = - <31 &cpuintc 2>, - <30 &cpuintc 1>, - <29 &cpuintc 5>; + reg = <0x3000 0x18>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>, <3>, <4>, <5>, <6>; }; diff --git a/dts/Bindings/interrupt-controller/renesas,irqc.yaml b/dts/Bindings/interrupt-controller/renesas,irqc.yaml index 620f01775e..62fd47c882 100644 --- a/dts/Bindings/interrupt-controller/renesas,irqc.yaml +++ b/dts/Bindings/interrupt-controller/renesas,irqc.yaml @@ -37,6 +37,7 @@ properties: - renesas,intc-ex-r8a77990 # R-Car E3 - renesas,intc-ex-r8a77995 # R-Car D3 - renesas,intc-ex-r8a779a0 # R-Car V3U + - renesas,intc-ex-r8a779g0 # R-Car V4H - const: renesas,irqc '#interrupt-cells': diff --git a/dts/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/dts/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 92e0f8c3ef..99e01f4d0a 100644 --- a/dts/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/dts/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -66,6 +66,11 @@ properties: - enum: - allwinner,sun20i-d1-plic - const: thead,c900-plic + - items: + - const: sifive,plic-1.0.0 + - const: riscv,plic0 + deprecated: true + description: For the QEMU virt machine only reg: maxItems: 1 diff --git a/dts/Bindings/interrupt-controller/st,stm32-exti.yaml b/dts/Bindings/interrupt-controller/st,stm32-exti.yaml index e44daa09b1..00c10a8258 100644 --- a/dts/Bindings/interrupt-controller/st,stm32-exti.yaml +++ b/dts/Bindings/interrupt-controller/st,stm32-exti.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/interrupt-controller/st,stm32-exti.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: STM32 External Interrupt Controller Device Tree Bindings +title: STM32 External Interrupt Controller maintainers: - Alexandre Torgue <alexandre.torgue@foss.st.com> diff --git a/dts/Bindings/interrupt-controller/ti,sci-inta.yaml b/dts/Bindings/interrupt-controller/ti,sci-inta.yaml index 88c46e6173..1151518859 100644 --- a/dts/Bindings/interrupt-controller/ti,sci-inta.yaml +++ b/dts/Bindings/interrupt-controller/ti,sci-inta.yaml @@ -59,6 +59,9 @@ properties: interrupt-controller: true + '#interrupt-cells': + const: 0 + msi-controller: true ti,interrupt-ranges: diff --git a/dts/Bindings/interrupt-controller/ti,sci-intr.yaml b/dts/Bindings/interrupt-controller/ti,sci-intr.yaml index e12aee42b1..c99cc7323c 100644 --- a/dts/Bindings/interrupt-controller/ti,sci-intr.yaml +++ b/dts/Bindings/interrupt-controller/ti,sci-intr.yaml @@ -58,6 +58,9 @@ properties: 1 = If intr supports edge triggered interrupts. 4 = If intr supports level triggered interrupts. + reg: + maxItems: 1 + interrupt-controller: true '#interrupt-cells': diff --git a/dts/Bindings/iommu/allwinner,sun50i-h6-iommu.yaml b/dts/Bindings/iommu/allwinner,sun50i-h6-iommu.yaml index 5e125cf2a8..e20016f120 100644 --- a/dts/Bindings/iommu/allwinner,sun50i-h6-iommu.yaml +++ b/dts/Bindings/iommu/allwinner,sun50i-h6-iommu.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/iommu/allwinner,sun50i-h6-iommu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner H6 IOMMU Device Tree Bindings +title: Allwinner H6 IOMMU maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/iommu/arm,smmu-v3.yaml b/dts/Bindings/iommu/arm,smmu-v3.yaml index c57a53d87e..75fcf4cb52 100644 --- a/dts/Bindings/iommu/arm,smmu-v3.yaml +++ b/dts/Bindings/iommu/arm,smmu-v3.yaml @@ -39,16 +39,11 @@ properties: any others. - minItems: 1 items: - - enum: - - eventq # Event Queue not empty - - gerror # Global Error activated - - const: gerror - - enum: - - cmdq-sync # CMD_SYNC complete - - priq # PRI Queue not empty - - enum: - - cmdq-sync - - priq + enum: + - eventq # Event Queue not empty + - gerror # Global Error activated + - cmdq-sync # CMD_SYNC complete + - priq # PRI Queue not empty '#iommu-cells': const: 1 diff --git a/dts/Bindings/iommu/mediatek,iommu.yaml b/dts/Bindings/iommu/mediatek,iommu.yaml index fee0241b50..839e3be0bf 100644 --- a/dts/Bindings/iommu/mediatek,iommu.yaml +++ b/dts/Bindings/iommu/mediatek,iommu.yaml @@ -73,6 +73,7 @@ properties: - mediatek,mt2701-m4u # generation one - mediatek,mt2712-m4u # generation two - mediatek,mt6779-m4u # generation two + - mediatek,mt6795-m4u # generation two - mediatek,mt8167-m4u # generation two - mediatek,mt8173-m4u # generation two - mediatek,mt8183-m4u # generation two @@ -124,6 +125,7 @@ properties: dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623, dt-binding/memory/mt2712-larb-port.h for mt2712, dt-binding/memory/mt6779-larb-port.h for mt6779, + dt-binding/memory/mt6795-larb-port.h for mt6795, dt-binding/memory/mt8167-larb-port.h for mt8167, dt-binding/memory/mt8173-larb-port.h for mt8173, dt-binding/memory/mt8183-larb-port.h for mt8183, @@ -148,6 +150,7 @@ allOf: enum: - mediatek,mt2701-m4u - mediatek,mt2712-m4u + - mediatek,mt6795-m4u - mediatek,mt8173-m4u - mediatek,mt8186-iommu-mm - mediatek,mt8192-m4u @@ -177,6 +180,7 @@ allOf: contains: enum: - mediatek,mt2712-m4u + - mediatek,mt6795-m4u - mediatek,mt8173-m4u then: diff --git a/dts/Bindings/ipmi/npcm7xx-kcs-bmc.txt b/dts/Bindings/ipmi/npcm7xx-kcs-bmc.txt index 352f5e9c75..4fda76e633 100644 --- a/dts/Bindings/ipmi/npcm7xx-kcs-bmc.txt +++ b/dts/Bindings/ipmi/npcm7xx-kcs-bmc.txt @@ -1,12 +1,13 @@ -* Nuvoton NPCM7xx KCS (Keyboard Controller Style) IPMI interface +* Nuvoton NPCM KCS (Keyboard Controller Style) IPMI interface -The Nuvoton SOCs (NPCM7xx) are commonly used as BMCs +The Nuvoton SOCs (NPCM) are commonly used as BMCs (Baseboard Management Controllers) and the KCS interface can be used to perform in-band IPMI communication with their host. Required properties: - compatible : should be one of "nuvoton,npcm750-kcs-bmc" + "nuvoton,npcm845-kcs-bmc", "nuvoton,npcm750-kcs-bmc" - interrupts : interrupt generated by the controller - kcs_chan : The KCS channel number in the controller diff --git a/dts/Bindings/leds/backlight/mediatek,mt6370-backlight.yaml b/dts/Bindings/leds/backlight/mediatek,mt6370-backlight.yaml new file mode 100644 index 0000000000..5533b6562d --- /dev/null +++ b/dts/Bindings/leds/backlight/mediatek,mt6370-backlight.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/backlight/mediatek,mt6370-backlight.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6370 Backlight + +maintainers: + - ChiaEn Wu <chiaen_wu@richtek.com> + +description: | + This module is part of the MT6370 MFD device. + The MT6370 Backlight WLED driver supports up to a 29V output voltage for + 4 channels of 8 series WLEDs. Each channel supports up to 30mA of current + capability with 2048 current steps (11 bits, only for MT6370/MT6371) or + 16384 current steps (14 bits, only for MT6372) in exponential or linear + mapping curves. + +allOf: + - $ref: common.yaml# + +properties: + compatible: + enum: + - mediatek,mt6370-backlight + - mediatek,mt6372-backlight + + default-brightness: + minimum: 0 + + max-brightness: + minimum: 0 + + enable-gpios: + description: External backlight 'enable' pin + maxItems: 1 + + mediatek,bled-pwm-enable: + description: | + Enable external PWM input for backlight dimming + type: boolean + + mediatek,bled-pwm-hys-enable: + description: | + Enable the backlight input-hysteresis for PWM mode + type: boolean + + mediatek,bled-pwm-hys-input-th-steps: + $ref: /schemas/types.yaml#/definitions/uint8 + enum: [1, 4, 16, 64] + description: | + The selection of the upper and lower bounds threshold of backlight + PWM resolution. If we choose selection 64, the variation of PWM + resolution needs more than 64 steps. + + mediatek,bled-ovp-shutdown: + description: | + Enable the backlight shutdown when OVP level triggered + type: boolean + + mediatek,bled-ovp-microvolt: + enum: [17000000, 21000000, 25000000, 29000000] + description: | + Backlight OVP level selection. + + mediatek,bled-ocp-shutdown: + description: | + Enable the backlight shutdown when OCP level triggerred. + type: boolean + + mediatek,bled-ocp-microamp: + enum: [900000, 1200000, 1500000, 1800000] + description: | + Backlight OC level selection. + + mediatek,bled-exponential-mode-enable: + description: | + Enable the exponential mode of backlight brightness. If this property + is not enabled, the default is to use linear mode. + type: boolean + + mediatek,bled-channel-use: + $ref: /schemas/types.yaml#/definitions/uint8 + description: | + Backlight LED channel to be used. + Each bit mapping to: + - 0: CH4 + - 1: CH3 + - 2: CH2 + - 3: CH1 + minimum: 1 + maximum: 15 + +if: + properties: + compatible: + contains: + const: mediatek,mt6372-backlight + +then: + properties: + default-brightness: + maximum: 16384 + + max-brightness: + maximum: 16384 + +else: + properties: + default-brightness: + maximum: 2048 + + max-brightness: + maximum: 2048 + +required: + - compatible + - mediatek,bled-channel-use + +additionalProperties: false diff --git a/dts/Bindings/leds/backlight/qcom-wled.yaml b/dts/Bindings/leds/backlight/qcom-wled.yaml index 5d66c3e4de..4c15693f7a 100644 --- a/dts/Bindings/leds/backlight/qcom-wled.yaml +++ b/dts/Bindings/leds/backlight/qcom-wled.yaml @@ -26,7 +26,8 @@ properties: - qcom,pm8150l-wled reg: - maxItems: 1 + minItems: 1 + maxItems: 2 default-brightness: description: | @@ -171,6 +172,9 @@ allOf: then: properties: + reg: + maxItems: 1 + qcom,current-boost-limit: enum: [ 105, 385, 525, 805, 980, 1260, 1400, 1680 ] default: 805 @@ -189,6 +193,9 @@ allOf: else: properties: + reg: + minItems: 2 + qcom,current-boost-limit: enum: [ 105, 280, 450, 620, 970, 1150, 1300, 1500 ] default: 970 diff --git a/dts/Bindings/leds/common.yaml b/dts/Bindings/leds/common.yaml index 328952d7ac..3c14a98430 100644 --- a/dts/Bindings/leds/common.yaml +++ b/dts/Bindings/leds/common.yaml @@ -79,24 +79,27 @@ properties: the LED. $ref: /schemas/types.yaml#/definitions/string - enum: - # LED will act as a back-light, controlled by the framebuffer system - - backlight - # LED will turn on (but for leds-gpio see "default-state" property in - # Documentation/devicetree/bindings/leds/leds-gpio.yaml) - - default-on - # LED "double" flashes at a load average based rate - - heartbeat - # LED indicates disk activity - - disk-activity - # LED indicates IDE disk activity (deprecated), in new implementations - # use "disk-activity" - - ide-disk - # LED flashes at a fixed, configurable rate - - timer - # LED alters the brightness for the specified duration with one software - # timer (requires "led-pattern" property) - - pattern + oneOf: + - enum: + # LED will act as a back-light, controlled by the framebuffer system + - backlight + # LED will turn on (but for leds-gpio see "default-state" property in + # Documentation/devicetree/bindings/leds/leds-gpio.yaml) + - default-on + # LED "double" flashes at a load average based rate + - heartbeat + # LED indicates disk activity + - disk-activity + # LED indicates IDE disk activity (deprecated), in new implementations + # use "disk-activity" + - ide-disk + # LED flashes at a fixed, configurable rate + - timer + # LED alters the brightness for the specified duration with one software + # timer (requires "led-pattern" property) + - pattern + # LED is triggered by SD/MMC activity + - pattern: "^mmc[0-9]+$" led-pattern: description: | diff --git a/dts/Bindings/leds/mediatek,mt6370-flashlight.yaml b/dts/Bindings/leds/mediatek,mt6370-flashlight.yaml new file mode 100644 index 0000000000..e9d02ed6a5 --- /dev/null +++ b/dts/Bindings/leds/mediatek,mt6370-flashlight.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/mediatek,mt6370-flashlight.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Flash LED driver for MT6370 PMIC from MediaTek Integrated. + +maintainers: + - Alice Chen <alice_chen@richtek.com> + +description: | + This module is part of the MT6370 MFD device. + Add MT6370 flash LED driver include 2-channel flash LED support Torch/Strobe Mode. + +properties: + compatible: + const: mediatek,mt6370-flashlight + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^led@[0-1]$": + type: object + $ref: common.yaml# + unevaluatedProperties: false + + properties: + reg: + enum: [0, 1] + +required: + - compatible + - "#address-cells" + - "#size-cells" + +additionalProperties: false diff --git a/dts/Bindings/leds/mediatek,mt6370-indicator.yaml b/dts/Bindings/leds/mediatek,mt6370-indicator.yaml new file mode 100644 index 0000000000..16b3abc2af --- /dev/null +++ b/dts/Bindings/leds/mediatek,mt6370-indicator.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/mediatek,mt6370-indicator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LED driver for MT6370 PMIC from MediaTek Integrated. + +maintainers: + - Alice Chen <alice_chen@richtek.com> + +description: | + This module is part of the MT6370 MFD device. + Add MT6370 LED driver include 4-channel RGB LED support Register/PWM/Breath Mode + +properties: + compatible: + const: mediatek,mt6370-indicator + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^multi-led@[0-3]$": + type: object + $ref: leds-class-multicolor.yaml# + unevaluatedProperties: false + + properties: + reg: + enum: [0, 1, 2, 3] + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^led@[0-2]$": + type: object + $ref: common.yaml# + unevaluatedProperties: false + + properties: + reg: + enum: [0, 1, 2] + + required: + - reg + - color + + required: + - reg + - color + - "#address-cells" + - "#size-cells" + + "^led@[0-3]$": + type: object + $ref: common.yaml# + unevaluatedProperties: false + + properties: + reg: + enum: [0, 1, 2, 3] + + required: + - reg + - color + +required: + - compatible + - "#address-cells" + - "#size-cells" + +additionalProperties: false diff --git a/dts/Bindings/mailbox/mediatek,gce-mailbox.yaml b/dts/Bindings/mailbox/mediatek,gce-mailbox.yaml new file mode 100644 index 0000000000..c579ac074c --- /dev/null +++ b/dts/Bindings/mailbox/mediatek,gce-mailbox.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/mediatek,gce-mailbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Global Command Engine Mailbox + +maintainers: + - Houlong Wei <houlong.wei@mediatek.com> + +description: + The Global Command Engine (GCE) is used to help read/write registers with + critical time limitation, such as updating display configuration during the + vblank. The GCE can be used to implement the Command Queue (CMDQ) driver. + +properties: + compatible: + enum: + - mediatek,mt6779-gce + - mediatek,mt8173-gce + - mediatek,mt8183-gce + - mediatek,mt8186-gce + - mediatek,mt8192-gce + - mediatek,mt8195-gce + + "#mbox-cells": + const: 2 + description: + The first cell describes the Thread ID of the GCE, + the second cell describes the priority of the GCE thread + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Global Command Engine clock + + clock-names: + items: + - const: gce + +required: + - compatible + - "#mbox-cells" + - reg + - interrupts + - clocks + +allOf: + - if: + not: + properties: + compatible: + contains: + const: mediatek,mt8195-gce + then: + required: + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8173-clk.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + gce: mailbox@10212000 { + compatible = "mediatek,mt8173-gce"; + reg = <0 0x10212000 0 0x1000>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; + #mbox-cells = <2>; + clocks = <&infracfg CLK_INFRA_GCE>; + clock-names = "gce"; + }; + }; diff --git a/dts/Bindings/mailbox/microchip,mpfs-mailbox.yaml b/dts/Bindings/mailbox/microchip,mpfs-mailbox.yaml index 082d397d3e..935937c671 100644 --- a/dts/Bindings/mailbox/microchip,mpfs-mailbox.yaml +++ b/dts/Bindings/mailbox/microchip,mpfs-mailbox.yaml @@ -14,9 +14,15 @@ properties: const: microchip,mpfs-mailbox reg: - items: - - description: mailbox data registers - - description: mailbox interrupt registers + oneOf: + - items: + - description: mailbox control & data registers + - description: mailbox interrupt registers + deprecated: true + - items: + - description: mailbox control registers + - description: mailbox interrupt registers + - description: mailbox data registers interrupts: maxItems: 1 @@ -39,7 +45,8 @@ examples: #size-cells = <2>; mbox: mailbox@37020000 { compatible = "microchip,mpfs-mailbox"; - reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>; + reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>, + <0x0 0x37020800 0x0 0x100>; interrupt-parent = <&L1>; interrupts = <96>; #mbox-cells = <1>; diff --git a/dts/Bindings/mailbox/mtk-gce.txt b/dts/Bindings/mailbox/mtk-gce.txt deleted file mode 100644 index c2aeba63bd..0000000000 --- a/dts/Bindings/mailbox/mtk-gce.txt +++ /dev/null @@ -1,82 +0,0 @@ -MediaTek GCE -=============== - -The Global Command Engine (GCE) is used to help read/write registers with -critical time limitation, such as updating display configuration during the -vblank. The GCE can be used to implement the Command Queue (CMDQ) driver. - -CMDQ driver uses mailbox framework for communication. Please refer to -mailbox.txt for generic information about mailbox device-tree bindings. - -Required properties: -- compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce", - "mediatek,mt8186-gce", "mediatek,mt8192-gce", "mediatek,mt8195-gce" or - "mediatek,mt6779-gce". -- reg: Address range of the GCE unit -- interrupts: The interrupt signal from the GCE block -- clock: Clocks according to the common clock binding -- clock-names: Must be "gce" to stand for GCE clock -- #mbox-cells: Should be 2. - <&phandle channel priority> - phandle: Label name of a gce node. - channel: Channel of mailbox. Be equal to the thread id of GCE. - priority: Priority of GCE thread. - -Required properties for a client device: -- mboxes: Client use mailbox to communicate with GCE, it should have this - property and list of phandle, mailbox specifiers. -Optional properties for a client device: -- mediatek,gce-client-reg: Specify the sub-system id which is corresponding - to the register address, it should have this property and list of phandle, - sub-system specifiers. - <&phandle subsys_number start_offset size> - phandle: Label name of a gce node. - subsys_number: specify the sub-system id which is corresponding - to the register address. - start_offset: the start offset of register address that GCE can access. - size: the total size of register address that GCE can access. - -Optional properties for a client mutex node: -- mediatek,gce-events: GCE events used by clients. The event numbers are - defined in 'dt-bindings/gce/<chip>-gce.h'. - -Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h', -'dt-bindings/gce/mt8183-gce.h', 'dt-bindings/gce/mt8186-gce.h' -'dt-bindings/gce/mt8192-gce.h', 'dt-bindings/gce/mt8195-gce.h' or -'dt-bindings/gce/mt6779-gce.h'. -Such as sub-system ids, thread priority, event ids. - -Example: - - gce: gce@10212000 { - compatible = "mediatek,mt8173-gce"; - reg = <0 0x10212000 0 0x1000>; - interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; - clocks = <&infracfg CLK_INFRA_GCE>; - clock-names = "gce"; - #mbox-cells = <2>; - }; - -Example for a client device: - - mmsys: clock-controller@14000000 { - compatible = "mediatek,mt8173-mmsys"; - mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST>, - <&gce 1 CMDQ_THR_PRIO_LOWEST>; - mutex-event-eof = <CMDQ_EVENT_MUTEX0_STREAM_EOF - CMDQ_EVENT_MUTEX1_STREAM_EOF>; - mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>, - <&gce SUBSYS_1401XXXX 0x2000 0x100>; - ... - }; - -Example for a client mutex node: - mutex: mutex@14020000 { - compatible = "mediatek,mt8173-disp-mutex"; - reg = <0 0x14020000 0 0x1000>; - interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_MUTEX_32K>; - mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>, - <CMDQ_EVENT_MUTEX1_STREAM_EOF>; - }; diff --git a/dts/Bindings/mailbox/qcom,apcs-kpss-global.yaml b/dts/Bindings/mailbox/qcom,apcs-kpss-global.yaml index f504652fc0..f24fd84b4b 100644 --- a/dts/Bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/dts/Bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -45,23 +45,17 @@ properties: clocks: description: phandles to the parent clocks of the clock driver minItems: 2 - items: - - description: primary pll parent of the clock driver - - description: auxiliary parent - - description: reference clock + maxItems: 3 '#mbox-cells': const: 1 '#clock-cells': - const: 0 + enum: [0, 1] clock-names: minItems: 2 - items: - - const: pll - - const: aux - - const: ref + maxItems: 3 required: - compatible @@ -75,8 +69,6 @@ allOf: properties: compatible: enum: - - qcom,ipq6018-apcs-apps-global - - qcom,ipq8074-apcs-apps-global - qcom,msm8916-apcs-kpss-global - qcom,msm8994-apcs-kpss-global - qcom,msm8996-apcs-hmss-global @@ -90,7 +82,13 @@ allOf: then: properties: clocks: - maxItems: 2 + items: + - description: primary pll parent of the clock driver + - description: auxiliary parent + clock-names: + items: + - const: pll + - const: aux - if: properties: compatible: @@ -99,7 +97,46 @@ allOf: then: properties: clocks: - maxItems: 3 + items: + - description: primary pll parent of the clock driver + - description: auxiliary parent + - description: reference clock + clock-names: + items: + - const: pll + - const: aux + - const: ref + - if: + properties: + compatible: + enum: + - qcom,ipq6018-apcs-apps-global + - qcom,ipq8074-apcs-apps-global + then: + properties: + clocks: + items: + - description: primary pll parent of the clock driver + - description: XO clock + clock-names: + items: + - const: pll + - const: xo + - if: + properties: + compatible: + enum: + - qcom,ipq6018-apcs-apps-global + - qcom,ipq8074-apcs-apps-global + then: + properties: + '#clock-cells': + const: 1 + else: + properties: + '#clock-cells': + const: 0 + examples: # Example apcs with msm8996 diff --git a/dts/Bindings/media/allegro,al5e.yaml b/dts/Bindings/media/allegro,al5e.yaml index 135bea94b5..2899d26d69 100644 --- a/dts/Bindings/media/allegro,al5e.yaml +++ b/dts/Bindings/media/allegro,al5e.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/media/allegro,al5e.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allegro DVT Video IP Codecs Device Tree Bindings +title: Allegro DVT Video IP Codecs maintainers: - Michael Tretter <m.tretter@pengutronix.de> diff --git a/dts/Bindings/media/allwinner,sun4i-a10-csi.yaml b/dts/Bindings/media/allwinner,sun4i-a10-csi.yaml index 6ced940642..617264ce47 100644 --- a/dts/Bindings/media/allwinner,sun4i-a10-csi.yaml +++ b/dts/Bindings/media/allwinner,sun4i-a10-csi.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-csi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 CMOS Sensor Interface (CSI) Device Tree Bindings +title: Allwinner A10 CMOS Sensor Interface (CSI) maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/media/allwinner,sun4i-a10-ir.yaml b/dts/Bindings/media/allwinner,sun4i-a10-ir.yaml index 6d8395d6bc..704033e21e 100644 --- a/dts/Bindings/media/allwinner,sun4i-a10-ir.yaml +++ b/dts/Bindings/media/allwinner,sun4i-a10-ir.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-ir.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Infrared Controller Device Tree Bindings +title: Allwinner A10 Infrared Controller maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/media/allwinner,sun4i-a10-video-engine.yaml b/dts/Bindings/media/allwinner,sun4i-a10-video-engine.yaml index ee7fc3515d..541325f900 100644 --- a/dts/Bindings/media/allwinner,sun4i-a10-video-engine.yaml +++ b/dts/Bindings/media/allwinner,sun4i-a10-video-engine.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-video-engine.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Video Engine Device Tree Bindings +title: Allwinner A10 Video Engine maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/media/allwinner,sun6i-a31-csi.yaml b/dts/Bindings/media/allwinner,sun6i-a31-csi.yaml index 8551c4a711..f1ccca35a7 100644 --- a/dts/Bindings/media/allwinner,sun6i-a31-csi.yaml +++ b/dts/Bindings/media/allwinner,sun6i-a31-csi.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-csi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A31 CMOS Sensor Interface (CSI) Device Tree Bindings +title: Allwinner A31 CMOS Sensor Interface (CSI) maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml b/dts/Bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml index 09725ca955..54e15ab8a7 100644 --- a/dts/Bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml +++ b/dts/Bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-mipi-csi2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A31 MIPI CSI-2 Device Tree Bindings +title: Allwinner A31 MIPI CSI-2 maintainers: - Paul Kocialkowski <paul.kocialkowski@bootlin.com> diff --git a/dts/Bindings/media/allwinner,sun8i-a83t-de2-rotate.yaml b/dts/Bindings/media/allwinner,sun8i-a83t-de2-rotate.yaml index a258832d52..c2f292dd01 100644 --- a/dts/Bindings/media/allwinner,sun8i-a83t-de2-rotate.yaml +++ b/dts/Bindings/media/allwinner,sun8i-a83t-de2-rotate.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/media/allwinner,sun8i-a83t-de2-rotate.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A83T DE2 Rotate Device Tree Bindings +title: Allwinner A83T DE2 Rotate maintainers: - Jernej Skrabec <jernej.skrabec@siol.net> diff --git a/dts/Bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml b/dts/Bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml index 5b27482b56..3cac68a87a 100644 --- a/dts/Bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml +++ b/dts/Bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/media/allwinner,sun8i-a83t-mipi-csi2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A83T MIPI CSI-2 Device Tree Bindings +title: Allwinner A83T MIPI CSI-2 maintainers: - Paul Kocialkowski <paul.kocialkowski@bootlin.com> diff --git a/dts/Bindings/media/allwinner,sun8i-h3-deinterlace.yaml b/dts/Bindings/media/allwinner,sun8i-h3-deinterlace.yaml index b80980b190..3ccd52164f 100644 --- a/dts/Bindings/media/allwinner,sun8i-h3-deinterlace.yaml +++ b/dts/Bindings/media/allwinner,sun8i-h3-deinterlace.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/media/allwinner,sun8i-h3-deinterlace.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner H3 Deinterlace Device Tree Bindings +title: Allwinner H3 Deinterlace maintainers: - Jernej Skrabec <jernej.skrabec@siol.net> diff --git a/dts/Bindings/media/exynos5-gsc.txt b/dts/Bindings/media/exynos5-gsc.txt deleted file mode 100644 index 1872688fa4..0000000000 --- a/dts/Bindings/media/exynos5-gsc.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Samsung Exynos5 G-Scaler device - -G-Scaler is used for scaling and color space conversion on Exynos5 SoCs. - -Required properties: -- compatible: should be one of - "samsung,exynos5250-gsc" - "samsung,exynos5420-gsc" - "samsung,exynos5433-gsc" - "samsung,exynos5-gsc" (deprecated) -- reg: should contain G-Scaler physical address location and length. -- interrupts: should contain G-Scaler interrupt number - -Optional properties: -- samsung,sysreg: handle to syscon used to control the system registers to - set writeback input and destination - -Example: - -gsc_0: gsc@13e00000 { - compatible = "samsung,exynos5250-gsc"; - reg = <0x13e00000 0x1000>; - interrupts = <0 85 0>; -}; - -Aliases: -Each G-Scaler node should have a numbered alias in the aliases node, -in the form of gscN, N = 0...3. G-Scaler driver uses these aliases -to retrieve the device IDs using "of_alias_get_id()" call. - -Example: - -aliases { - gsc0 =&gsc_0; - gsc1 =&gsc_1; - gsc2 =&gsc_2; - gsc3 =&gsc_3; -}; diff --git a/dts/Bindings/media/i2c/dongwoon,dw9714.txt b/dts/Bindings/media/i2c/dongwoon,dw9714.txt deleted file mode 100644 index b88dcdd41d..0000000000 --- a/dts/Bindings/media/i2c/dongwoon,dw9714.txt +++ /dev/null @@ -1,9 +0,0 @@ -Dongwoon Anatech DW9714 camera voice coil lens driver - -DW9174 is a 10-bit DAC with current sink capability. It is intended -for driving voice coil lenses in camera modules. - -Mandatory properties: - -- compatible: "dongwoon,dw9714" -- reg: I²C slave address diff --git a/dts/Bindings/media/i2c/dongwoon,dw9714.yaml b/dts/Bindings/media/i2c/dongwoon,dw9714.yaml new file mode 100644 index 0000000000..66229a3dc0 --- /dev/null +++ b/dts/Bindings/media/i2c/dongwoon,dw9714.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/dongwoon,dw9714.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Dongwoon Anatech DW9714 camera voice coil lens driver + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + +description: + DW9174 is a 10-bit DAC with current sink capability. It is intended for + driving voice coil lenses in camera modules. + +properties: + compatible: + const: dongwoon,dw9714 + + reg: + maxItems: 1 + + powerdown-gpios: + description: + XSD pin for shutdown (active low) + + vcc-supply: + description: VDD power supply + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + camera-lens@c { + compatible = "dongwoon,dw9714"; + reg = <0x0c>; + vcc-supply = <®_csi_1v8>; + }; + }; diff --git a/dts/Bindings/media/mediatek,mdp3-rdma.yaml b/dts/Bindings/media/mediatek,mdp3-rdma.yaml new file mode 100644 index 0000000000..9cfc0c7d23 --- /dev/null +++ b/dts/Bindings/media/mediatek,mdp3-rdma.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Read Direct Memory Access + +maintainers: + - Matthias Brugger <matthias.bgg@gmail.com> + - Moudy Ho <moudy.ho@mediatek.com> + +description: | + MediaTek Read Direct Memory Access(RDMA) component used to do read DMA. + It contains one line buffer to store the sufficient pixel data, and + must be siblings to the central MMSYS_CONFIG node. + For a description of the MMSYS_CONFIG binding, see + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml + for details. + +properties: + compatible: + items: + - const: mediatek,mt8183-mdp3-rdma + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + description: The register of client driver can be configured by gce with + 4 arguments defined in this property. Each GCE subsys id is mapping to + a client defined in the header include/dt-bindings/gce/<chip>-gce.h. + + mediatek,gce-events: + description: + The event id which is mapping to the specific hardware event signal + to gce. The event id is defined in the gce header + include/dt-bindings/gce/<chip>-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/uint32-array + + power-domains: + maxItems: 1 + + clocks: + items: + - description: RDMA clock + - description: RSZ clock + + iommus: + maxItems: 1 + + mboxes: + items: + - description: used for 1st data pipe from RDMA + - description: used for 2nd data pipe from RDMA + +required: + - compatible + - reg + - mediatek,gce-client-reg + - mediatek,gce-events + - power-domains + - clocks + - iommus + - mboxes + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8183-clk.h> + #include <dt-bindings/gce/mt8183-gce.h> + #include <dt-bindings/power/mt8183-power.h> + #include <dt-bindings/memory/mt8183-larb-port.h> + + mdp3_rdma0: mdp3-rdma0@14001000 { + compatible = "mediatek,mt8183-mdp3-rdma"; + reg = <0x14001000 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>, + <CMDQ_EVENT_MDP_RDMA0_EOF>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_RDMA0>, + <&mmsys CLK_MM_MDP_RSZ1>; + iommus = <&iommu>; + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>, + <&gce 21 CMDQ_THR_PRIO_LOWEST>; + }; diff --git a/dts/Bindings/media/mediatek,mdp3-rsz.yaml b/dts/Bindings/media/mediatek,mdp3-rsz.yaml new file mode 100644 index 0000000000..78f9de6192 --- /dev/null +++ b/dts/Bindings/media/mediatek,mdp3-rsz.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Resizer + +maintainers: + - Matthias Brugger <matthias.bgg@gmail.com> + - Moudy Ho <moudy.ho@mediatek.com> + +description: | + One of Media Data Path 3 (MDP3) components used to do frame resizing. + +properties: + compatible: + items: + - enum: + - mediatek,mt8183-mdp3-rsz + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + description: The register of client driver can be configured by gce with + 4 arguments defined in this property. Each GCE subsys id is mapping to + a client defined in the header include/dt-bindings/gce/<chip>-gce.h. + + mediatek,gce-events: + description: + The event id which is mapping to the specific hardware event signal + to gce. The event id is defined in the gce header + include/dt-bindings/gce/<chip>-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/uint32-array + + clocks: + minItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - mediatek,gce-events + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8183-clk.h> + #include <dt-bindings/gce/mt8183-gce.h> + + mdp3_rsz0: mdp3-rsz0@14003000 { + compatible = "mediatek,mt8183-mdp3-rsz"; + reg = <0x14003000 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>, + <CMDQ_EVENT_MDP_RSZ0_EOF>; + clocks = <&mmsys CLK_MM_MDP_RSZ0>; + }; + + mdp3_rsz1: mdp3-rsz1@14004000 { + compatible = "mediatek,mt8183-mdp3-rsz"; + reg = <0x14004000 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>, + <CMDQ_EVENT_MDP_RSZ1_EOF>; + clocks = <&mmsys CLK_MM_MDP_RSZ1>; + }; diff --git a/dts/Bindings/media/mediatek,mdp3-wrot.yaml b/dts/Bindings/media/mediatek,mdp3-wrot.yaml new file mode 100644 index 0000000000..0baa77198f --- /dev/null +++ b/dts/Bindings/media/mediatek,mdp3-wrot.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Write DMA with Rotation + +maintainers: + - Matthias Brugger <matthias.bgg@gmail.com> + - Moudy Ho <moudy.ho@mediatek.com> + +description: | + One of Media Data Path 3 (MDP3) components used to write DMA with frame rotation. + +properties: + compatible: + items: + - enum: + - mediatek,mt8183-mdp3-wrot + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + description: The register of client driver can be configured by gce with + 4 arguments defined in this property. Each GCE subsys id is mapping to + a client defined in the header include/dt-bindings/gce/<chip>-gce.h. + + mediatek,gce-events: + description: + The event id which is mapping to the specific hardware event signal + to gce. The event id is defined in the gce header + include/dt-bindings/gce/<chip>-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/uint32-array + + power-domains: + maxItems: 1 + + clocks: + minItems: 1 + + iommus: + maxItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - mediatek,gce-events + - power-domains + - clocks + - iommus + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8183-clk.h> + #include <dt-bindings/gce/mt8183-gce.h> + #include <dt-bindings/power/mt8183-power.h> + #include <dt-bindings/memory/mt8183-larb-port.h> + + mdp3_wrot0: mdp3-wrot0@14005000 { + compatible = "mediatek,mt8183-mdp3-wrot"; + reg = <0x14005000 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>, + <CMDQ_EVENT_MDP_WROT0_EOF>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_WROT0>; + iommus = <&iommu>; + }; diff --git a/dts/Bindings/media/mediatek,vcodec-encoder.yaml b/dts/Bindings/media/mediatek,vcodec-encoder.yaml index d36fcca04c..32aee09aea 100644 --- a/dts/Bindings/media/mediatek,vcodec-encoder.yaml +++ b/dts/Bindings/media/mediatek,vcodec-encoder.yaml @@ -20,6 +20,7 @@ properties: - mediatek,mt8173-vcodec-enc-vp8 - mediatek,mt8173-vcodec-enc - mediatek,mt8183-vcodec-enc + - mediatek,mt8188-vcodec-enc - mediatek,mt8192-vcodec-enc - mediatek,mt8195-vcodec-enc diff --git a/dts/Bindings/media/mediatek,vcodec-subdev-decoder.yaml b/dts/Bindings/media/mediatek,vcodec-subdev-decoder.yaml index d4e2051bee..c4f20acdc1 100644 --- a/dts/Bindings/media/mediatek,vcodec-subdev-decoder.yaml +++ b/dts/Bindings/media/mediatek,vcodec-subdev-decoder.yaml @@ -57,6 +57,7 @@ properties: enum: - mediatek,mt8192-vcodec-dec - mediatek,mt8186-vcodec-dec + - mediatek,mt8188-vcodec-dec - mediatek,mt8195-vcodec-dec reg: diff --git a/dts/Bindings/media/mediatek-jpeg-decoder.yaml b/dts/Bindings/media/mediatek-jpeg-decoder.yaml index 052e752157..5e8d001492 100644 --- a/dts/Bindings/media/mediatek-jpeg-decoder.yaml +++ b/dts/Bindings/media/mediatek-jpeg-decoder.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/media/mediatek-jpeg-decoder.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: MediaTek JPEG Decoder Device Tree Bindings +title: MediaTek JPEG Decoder maintainers: - Xia Jiang <xia.jiang@mediatek.com> diff --git a/dts/Bindings/media/mediatek-jpeg-encoder.yaml b/dts/Bindings/media/mediatek-jpeg-encoder.yaml index 4fd390c042..fc727300b4 100644 --- a/dts/Bindings/media/mediatek-jpeg-encoder.yaml +++ b/dts/Bindings/media/mediatek-jpeg-encoder.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/media/mediatek-jpeg-encoder.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: MediaTek JPEG Encoder Device Tree Bindings +title: MediaTek JPEG Encoder maintainers: - Xia Jiang <xia.jiang@mediatek.com> diff --git a/dts/Bindings/media/microchip,csi2dc.yaml b/dts/Bindings/media/microchip,csi2dc.yaml index e8544fb2d0..b3a345fc64 100644 --- a/dts/Bindings/media/microchip,csi2dc.yaml +++ b/dts/Bindings/media/microchip,csi2dc.yaml @@ -75,6 +75,7 @@ properties: properties: port@0: $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false description: Input port node, single endpoint describing the input port. @@ -103,6 +104,7 @@ properties: port@1: $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false description: Output port node, single endpoint describing the output port. diff --git a/dts/Bindings/media/nxp,dw100.yaml b/dts/Bindings/media/nxp,dw100.yaml new file mode 100644 index 0000000000..21910ff0e1 --- /dev/null +++ b/dts/Bindings/media/nxp,dw100.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/nxp,dw100.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MP DW100 Dewarper core + +maintainers: + - Xavier Roumegue <xavier.roumegue@oss.nxp.com> + +description: |- + The Dewarp Engine provides high-performance dewarp processing for the + correction of the distortion that is introduced in images produced by fisheye + and wide angle lenses. It is implemented with a line/tile-cache based + architecture. With configurable address mapping look up tables and per tile + processing, it successfully generates a corrected output image. + The engine can be used to perform scaling, cropping and pixel format + conversion. + +properties: + compatible: + enum: + - nxp,imx8mp-dw100 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: The AXI clock + - description: The AHB clock + + clock-names: + items: + - const: axi + - const: ahb + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8mp-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/imx8mp-power.h> + + dewarp: dwe@32e30000 { + compatible = "nxp,imx8mp-dw100"; + reg = <0x32e30000 0x10000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "axi", "ahb"; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>; + }; diff --git a/dts/Bindings/media/nxp,imx8-jpeg.yaml b/dts/Bindings/media/nxp,imx8-jpeg.yaml index 3cc6f42aeb..3d9d1db370 100644 --- a/dts/Bindings/media/nxp,imx8-jpeg.yaml +++ b/dts/Bindings/media/nxp,imx8-jpeg.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/media/nxp,imx8-jpeg.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: i.MX8QXP/QM JPEG decoder/encoder Device Tree Bindings +title: i.MX8QXP/QM JPEG decoder/encoder maintainers: - Mirela Rabulea <mirela.rabulea@nxp.com> diff --git a/dts/Bindings/media/qcom,msm8916-venus.yaml b/dts/Bindings/media/qcom,msm8916-venus.yaml index 59ab16ad12..2abb7d21c0 100644 --- a/dts/Bindings/media/qcom,msm8916-venus.yaml +++ b/dts/Bindings/media/qcom,msm8916-venus.yaml @@ -68,6 +68,7 @@ properties: video-firmware: type: object + additionalProperties: false description: | Firmware subnode is needed when the platform does not diff --git a/dts/Bindings/media/qcom,msm8996-venus.yaml b/dts/Bindings/media/qcom,msm8996-venus.yaml index 199f45217b..29d0cb6c6e 100644 --- a/dts/Bindings/media/qcom,msm8996-venus.yaml +++ b/dts/Bindings/media/qcom,msm8996-venus.yaml @@ -95,6 +95,7 @@ properties: video-firmware: type: object + additionalProperties: false description: | Firmware subnode is needed when the platform does not diff --git a/dts/Bindings/media/qcom,sc7180-venus.yaml b/dts/Bindings/media/qcom,sc7180-venus.yaml index 90b4af2c97..42ee3f06c6 100644 --- a/dts/Bindings/media/qcom,sc7180-venus.yaml +++ b/dts/Bindings/media/qcom,sc7180-venus.yaml @@ -86,6 +86,7 @@ properties: video-firmware: type: object + additionalProperties: false description: | Firmware subnode is needed when the platform does not diff --git a/dts/Bindings/media/qcom,sc7280-venus.yaml b/dts/Bindings/media/qcom,sc7280-venus.yaml index e2874683b4..cf361dd9de 100644 --- a/dts/Bindings/media/qcom,sc7280-venus.yaml +++ b/dts/Bindings/media/qcom,sc7280-venus.yaml @@ -86,6 +86,7 @@ properties: video-firmware: type: object + additionalProperties: false description: | Firmware subnode is needed when the platform does not diff --git a/dts/Bindings/media/qcom,sdm660-venus.yaml b/dts/Bindings/media/qcom,sdm660-venus.yaml index 33da7d3cfd..45e3f58f52 100644 --- a/dts/Bindings/media/qcom,sdm660-venus.yaml +++ b/dts/Bindings/media/qcom,sdm660-venus.yaml @@ -104,6 +104,7 @@ properties: video-firmware: type: object + additionalProperties: false description: | Firmware subnode is needed when the platform does not diff --git a/dts/Bindings/media/qcom,sdm845-venus-v2.yaml b/dts/Bindings/media/qcom,sdm845-venus-v2.yaml index 177bf81544..8edc8a2f43 100644 --- a/dts/Bindings/media/qcom,sdm845-venus-v2.yaml +++ b/dts/Bindings/media/qcom,sdm845-venus-v2.yaml @@ -81,6 +81,7 @@ properties: video-firmware: type: object + additionalProperties: false description: | Firmware subnode is needed when the platform does not diff --git a/dts/Bindings/media/qcom,sdm845-venus.yaml b/dts/Bindings/media/qcom,sdm845-venus.yaml index 680f37726f..57d503373e 100644 --- a/dts/Bindings/media/qcom,sdm845-venus.yaml +++ b/dts/Bindings/media/qcom,sdm845-venus.yaml @@ -96,6 +96,7 @@ properties: video-firmware: type: object + additionalProperties: false description: | Firmware subnode is needed when the platform does not diff --git a/dts/Bindings/media/qcom,sm8250-venus.yaml b/dts/Bindings/media/qcom,sm8250-venus.yaml index ebf8f3d866..4b7a12523d 100644 --- a/dts/Bindings/media/qcom,sm8250-venus.yaml +++ b/dts/Bindings/media/qcom,sm8250-venus.yaml @@ -92,6 +92,7 @@ properties: video-firmware: type: object + additionalProperties: false description: | Firmware subnode is needed when the platform does not diff --git a/dts/Bindings/media/rc.yaml b/dts/Bindings/media/rc.yaml index b11d14ab89..e732b7f3a6 100644 --- a/dts/Bindings/media/rc.yaml +++ b/dts/Bindings/media/rc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/media/rc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Generic Infrared Remote Controller Device Tree Bindings +title: Generic Infrared Remote Controller maintainers: - Mauro Carvalho Chehab <mchehab@kernel.org> diff --git a/dts/Bindings/media/renesas,vsp1.yaml b/dts/Bindings/media/renesas,vsp1.yaml index 990e9c1dbc..7a8f324738 100644 --- a/dts/Bindings/media/renesas,vsp1.yaml +++ b/dts/Bindings/media/renesas,vsp1.yaml @@ -17,6 +17,7 @@ description: properties: compatible: enum: + - renesas,r9a07g044-vsp2 # RZ/G2L - renesas,vsp1 # R-Car Gen2 and RZ/G1 - renesas,vsp2 # R-Car Gen3 and RZ/G2 @@ -26,8 +27,8 @@ properties: interrupts: maxItems: 1 - clocks: - maxItems: 1 + clocks: true + clock-names: true power-domains: maxItems: 1 @@ -50,17 +51,43 @@ required: additionalProperties: false -if: - properties: - compatible: - items: - - const: renesas,vsp1 -then: - properties: - renesas,fcp: false -else: - required: - - renesas,fcp +allOf: + - if: + properties: + compatible: + contains: + const: renesas,vsp1 + then: + properties: + renesas,fcp: false + else: + required: + - renesas,fcp + + - if: + properties: + compatible: + contains: + const: renesas,r9a07g044-vsp2 + then: + properties: + clocks: + items: + - description: Main clock + - description: Register access clock + - description: Video clock + clock-names: + items: + - const: aclk + - const: pclk + - const: vclk + required: + - clock-names + else: + properties: + clocks: + maxItems: 1 + clock-names: false examples: # R8A7790 (R-Car H2) VSP1-S diff --git a/dts/Bindings/media/rockchip,vdec.yaml b/dts/Bindings/media/rockchip,vdec.yaml index 3bcfb8e123..08b02ec167 100644 --- a/dts/Bindings/media/rockchip,vdec.yaml +++ b/dts/Bindings/media/rockchip,vdec.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/media/rockchip,vdec.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Rockchip Video Decoder (VDec) Device Tree Bindings +title: Rockchip Video Decoder (VDec) maintainers: - Heiko Stuebner <heiko@sntech.de> diff --git a/dts/Bindings/media/samsung,exynos5250-gsc.yaml b/dts/Bindings/media/samsung,exynos5250-gsc.yaml new file mode 100644 index 0000000000..878397830a --- /dev/null +++ b/dts/Bindings/media/samsung,exynos5250-gsc.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/samsung,exynos5250-gsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC G-Scaler + +maintainers: + - Inki Dae <inki.dae@samsung.com> + - Krzysztof Kozlowski <krzk@kernel.org> + - Seung-Woo Kim <sw0312.kim@samsung.com + +description: + G-Scaler is used for scaling and color space conversion on Samsung Exynos + SoCs. + + Each G-Scaler node should have a numbered alias in the aliases node, in the + form of gscN, N = 0...3. + +properties: + compatible: + oneOf: + - items: + - enum: + - samsung,exynos5250-gsc + - samsung,exynos5420-gsc + - const: samsung,exynos5-gsc + - enum: + - samsung,exynos5433-gsc + - const: samsung,exynos5-gsc + deprecated: True + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + interrupts: + maxItems: 1 + + iommus: + maxItems: 1 + + power-domains: + maxItems: 1 + + reg: + maxItems: 1 + + samsung,sysreg: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Syscon used to control the system registers to set writeback input and destination. + +required: + - compatible + - clocks + - clock-names + - interrupts + - reg + +allOf: + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos5-gsc + - samsung,exynos5250-gsc + - samsung,exynos5420-gsc + then: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: gscl + else: + properties: + clocks: + minItems: 5 + clock-names: + items: + - const: pclk + - const: aclk + - const: aclk_xiu + - const: aclk_gsclbend + - const: gsd + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/exynos5250.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + video-scaler@13e00000 { + compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; + reg = <0x13e00000 0x1000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_gsc>; + clocks = <&clock CLK_GSCL0>; + clock-names = "gscl"; + iommus = <&sysmmu_gsc0>; + }; diff --git a/dts/Bindings/media/ti,cal.yaml b/dts/Bindings/media/ti,cal.yaml index 7e078424ca..f8e4d260d1 100644 --- a/dts/Bindings/media/ti,cal.yaml +++ b/dts/Bindings/media/ti,cal.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/media/ti,cal.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Texas Instruments DRA72x CAMERA ADAPTATION LAYER (CAL) Device Tree Bindings +title: Texas Instruments DRA72x CAMERA ADAPTATION LAYER (CAL) maintainers: - Benoit Parrot <bparrot@ti.com> diff --git a/dts/Bindings/media/ti,vpe.yaml b/dts/Bindings/media/ti,vpe.yaml index ef473f2873..7fa8a367ed 100644 --- a/dts/Bindings/media/ti,vpe.yaml +++ b/dts/Bindings/media/ti,vpe.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/media/ti,vpe.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Texas Instruments DRA7x Video Processing Engine (VPE) Device Tree Bindings +title: Texas Instruments DRA7x Video Processing Engine (VPE) maintainers: - Benoit Parrot <bparrot@ti.com> diff --git a/dts/Bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml b/dts/Bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml new file mode 100644 index 0000000000..4b072c879b --- /dev/null +++ b/dts/Bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/brcm,brcmstb-memc-ddr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Memory controller (MEMC) for Broadcom STB + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + +properties: + compatible: + items: + - enum: + - brcm,brcmstb-memc-ddr-rev-b.1.x + - brcm,brcmstb-memc-ddr-rev-b.2.0 + - brcm,brcmstb-memc-ddr-rev-b.2.1 + - brcm,brcmstb-memc-ddr-rev-b.2.2 + - brcm,brcmstb-memc-ddr-rev-b.2.3 + - brcm,brcmstb-memc-ddr-rev-b.2.5 + - brcm,brcmstb-memc-ddr-rev-b.2.6 + - brcm,brcmstb-memc-ddr-rev-b.2.7 + - brcm,brcmstb-memc-ddr-rev-b.2.8 + - brcm,brcmstb-memc-ddr-rev-b.3.0 + - brcm,brcmstb-memc-ddr-rev-b.3.1 + - brcm,brcmstb-memc-ddr-rev-c.1.0 + - brcm,brcmstb-memc-ddr-rev-c.1.1 + - brcm,brcmstb-memc-ddr-rev-c.1.2 + - brcm,brcmstb-memc-ddr-rev-c.1.3 + - brcm,brcmstb-memc-ddr-rev-c.1.4 + - const: brcm,brcmstb-memc-ddr + + reg: + maxItems: 1 + + clock-frequency: + description: DDR PHY frequency in Hz + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + memory-controller@9902000 { + compatible = "brcm,brcmstb-memc-ddr-rev-c.1.1", "brcm,brcmstb-memc-ddr"; + reg = <0x9902000 0x600>; + clock-frequency = <2133000000>; + }; diff --git a/dts/Bindings/memory-controllers/fsl/imx8m-ddrc.yaml b/dts/Bindings/memory-controllers/fsl/imx8m-ddrc.yaml index 2b39fce5f6..519b123116 100644 --- a/dts/Bindings/memory-controllers/fsl/imx8m-ddrc.yaml +++ b/dts/Bindings/memory-controllers/fsl/imx8m-ddrc.yaml @@ -47,7 +47,8 @@ properties: - const: apb operating-points-v2: true - opp-table: true + opp-table: + type: object required: - reg diff --git a/dts/Bindings/memory-controllers/mediatek,mt7621-memc.yaml b/dts/Bindings/memory-controllers/mediatek,mt7621-memc.yaml index 85e02854f0..6ccdaf99c7 100644 --- a/dts/Bindings/memory-controllers/mediatek,mt7621-memc.yaml +++ b/dts/Bindings/memory-controllers/mediatek,mt7621-memc.yaml @@ -11,7 +11,9 @@ maintainers: properties: compatible: - const: mediatek,mt7621-memc + items: + - const: mediatek,mt7621-memc + - const: syscon reg: maxItems: 1 @@ -25,6 +27,6 @@ additionalProperties: false examples: - | memory-controller@5000 { - compatible = "mediatek,mt7621-memc"; + compatible = "mediatek,mt7621-memc", "syscon"; reg = <0x5000 0x1000>; }; diff --git a/dts/Bindings/memory-controllers/mediatek,smi-common.yaml b/dts/Bindings/memory-controllers/mediatek,smi-common.yaml index 71bc5cefb4..a8fda30ccc 100644 --- a/dts/Bindings/memory-controllers/mediatek,smi-common.yaml +++ b/dts/Bindings/memory-controllers/mediatek,smi-common.yaml @@ -16,7 +16,7 @@ description: | MediaTek SMI have two generations of HW architecture, here is the list which generation the SoCs use: generation 1: mt2701 and mt7623. - generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8192 and mt8195. + generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8188, mt8192 and mt8195. There's slight differences between the two SMI, for generation 2, the register which control the iommu port is at each larb's register base. But @@ -37,6 +37,8 @@ properties: - mediatek,mt8173-smi-common - mediatek,mt8183-smi-common - mediatek,mt8186-smi-common + - mediatek,mt8188-smi-common-vdo + - mediatek,mt8188-smi-common-vpp - mediatek,mt8192-smi-common - mediatek,mt8195-smi-common-vdo - mediatek,mt8195-smi-common-vpp @@ -144,7 +146,16 @@ allOf: - const: gals0 - const: gals1 - else: # for gen2 HW that don't have gals + - if: # for gen2 HW that don't have gals + properties: + compatible: + enum: + - mediatek,mt2712-smi-common + - mediatek,mt6795-smi-common + - mediatek,mt8167-smi-common + - mediatek,mt8173-smi-common + + then: properties: clocks: minItems: 2 diff --git a/dts/Bindings/memory-controllers/mediatek,smi-larb.yaml b/dts/Bindings/memory-controllers/mediatek,smi-larb.yaml index 59dcd16366..5f4ac36098 100644 --- a/dts/Bindings/memory-controllers/mediatek,smi-larb.yaml +++ b/dts/Bindings/memory-controllers/mediatek,smi-larb.yaml @@ -25,6 +25,7 @@ properties: - mediatek,mt8173-smi-larb - mediatek,mt8183-smi-larb - mediatek,mt8186-smi-larb + - mediatek,mt8188-smi-larb - mediatek,mt8192-smi-larb - mediatek,mt8195-smi-larb @@ -78,6 +79,7 @@ allOf: enum: - mediatek,mt8183-smi-larb - mediatek,mt8186-smi-larb + - mediatek,mt8188-smi-larb - mediatek,mt8195-smi-larb then: @@ -111,6 +113,7 @@ allOf: - mediatek,mt2712-smi-larb - mediatek,mt6779-smi-larb - mediatek,mt8186-smi-larb + - mediatek,mt8188-smi-larb - mediatek,mt8192-smi-larb - mediatek,mt8195-smi-larb diff --git a/dts/Bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml b/dts/Bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml new file mode 100644 index 0000000000..e68c430602 --- /dev/null +++ b/dts/Bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare Universal Multi-Protocol Memory Controller + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + - Manish Narani <manish.narani@xilinx.com> + - Michal Simek <michal.simek@xilinx.com> + +description: | + Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of + working with the memory devices supporting up to (LP)DDR4 protocol. It can + be equipped with SEC/DEC ECC feature if DRAM data bus width is either + 16-bits or 32-bits or 64-bits wide. + + For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a + controller. It has an optional SEC/DEC ECC support in 64- and 32-bits + bus width configurations. + +properties: + compatible: + oneOf: + - deprecated: true + description: Synopsys DW uMCTL2 DDR controller v3.80a + const: snps,ddrc-3.80a + - description: Synopsys DW uMCTL2 DDR controller + const: snps,dw-umctl2-ddrc + - description: Xilinx ZynqMP DDR controller v2.40a + const: xlnx,zynqmp-ddrc-2.40a + + interrupts: + description: + DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":" + ECC Corrected Error, ECC Uncorrected Error, ECC Address Protection, + Scrubber-Done signal, DFI Parity/CRC Error. Some platforms may have the + signals merged before they reach the IRQ controller or have some of them + absent in case if the corresponding feature is unavailable/disabled. + minItems: 1 + maxItems: 5 + + interrupt-names: + minItems: 1 + maxItems: 5 + oneOf: + - description: Common ECC CE/UE/Scrubber/DFI Errors IRQ + items: + - const: ecc + - description: Individual ECC CE/UE/Scrubber/DFI Errors IRQs + items: + enum: [ ecc_ce, ecc_ue, ecc_ap, ecc_sbr, dfi_e ] + + reg: + maxItems: 1 + + clocks: + description: + A standard set of the clock sources contains CSRs bus clock, AXI-ports + reference clock, DDRC core clock, Scrubber standalone clock + (synchronous to the DDRC clock). + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + items: + enum: [ pclk, aclk, core, sbr ] + + resets: + description: + Each clock domain can have separate reset signal. + minItems: 1 + maxItems: 4 + + reset-names: + minItems: 1 + maxItems: 4 + items: + enum: [ prst, arst, core, sbr ] + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + memory-controller@fd070000 { + compatible = "xlnx,zynqmp-ddrc-2.40a"; + reg = <0xfd070000 0x30000>; + + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ecc"; + }; + - | + #include <dt-bindings/interrupt-controller/irq.h> + + memory-controller@3d400000 { + compatible = "snps,dw-umctl2-ddrc"; + reg = <0x3d400000 0x400000>; + + interrupts = <147 IRQ_TYPE_LEVEL_HIGH>, <148 IRQ_TYPE_LEVEL_HIGH>, + <149 IRQ_TYPE_LEVEL_HIGH>, <150 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ecc_ce", "ecc_ue", "ecc_sbr", "dfi_e"; + + clocks = <&pclk>, <&aclk>, <&core_clk>, <&sbr_clk>; + clock-names = "pclk", "aclk", "core", "sbr"; + }; +... diff --git a/dts/Bindings/memory-controllers/synopsys,ddrc-ecc.yaml b/dts/Bindings/memory-controllers/synopsys,ddrc-ecc.yaml deleted file mode 100644 index f46e95704f..0000000000 --- a/dts/Bindings/memory-controllers/synopsys,ddrc-ecc.yaml +++ /dev/null @@ -1,76 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/memory-controllers/synopsys,ddrc-ecc.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Synopsys IntelliDDR Multi Protocol memory controller - -maintainers: - - Krzysztof Kozlowski <krzk@kernel.org> - - Manish Narani <manish.narani@xilinx.com> - - Michal Simek <michal.simek@xilinx.com> - -description: | - The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and - 32-bit bus width configurations. - - The Zynq DDR ECC controller has an optional ECC support in half-bus width - (16-bit) configuration. - - These both ECC controllers correct single bit ECC errors and detect double bit - ECC errors. - -properties: - compatible: - enum: - - snps,ddrc-3.80a - - xlnx,zynq-ddrc-a05 - - xlnx,zynqmp-ddrc-2.40a - - interrupts: - maxItems: 1 - - reg: - maxItems: 1 - -required: - - compatible - - reg - -allOf: - - if: - properties: - compatible: - contains: - enum: - - snps,ddrc-3.80a - - xlnx,zynqmp-ddrc-2.40a - then: - required: - - interrupts - else: - properties: - interrupts: false - -additionalProperties: false - -examples: - - | - memory-controller@f8006000 { - compatible = "xlnx,zynq-ddrc-a05"; - reg = <0xf8006000 0x1000>; - }; - - - | - axi { - #address-cells = <2>; - #size-cells = <2>; - - memory-controller@fd070000 { - compatible = "xlnx,zynqmp-ddrc-2.40a"; - reg = <0x0 0xfd070000 0x0 0x30000>; - interrupt-parent = <&gic>; - interrupts = <0 112 4>; - }; - }; diff --git a/dts/Bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml b/dts/Bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml new file mode 100644 index 0000000000..8f72e2f858 --- /dev/null +++ b/dts/Bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Zynq A05 DDR Memory Controller + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + - Manish Narani <manish.narani@xilinx.com> + - Michal Simek <michal.simek@xilinx.com> + +description: + The Zynq DDR ECC controller has an optional ECC support in half-bus width + (16-bit) configuration. It is cappable of correcting single bit ECC errors + and detecting double bit ECC errors. + +properties: + compatible: + const: xlnx,zynq-ddrc-a05 + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + memory-controller@f8006000 { + compatible = "xlnx,zynq-ddrc-a05"; + reg = <0xf8006000 0x1000>; + }; +... diff --git a/dts/Bindings/mfd/allwinner,sun4i-a10-ts.yaml b/dts/Bindings/mfd/allwinner,sun4i-a10-ts.yaml index f591332fc4..93f5065a62 100644 --- a/dts/Bindings/mfd/allwinner,sun4i-a10-ts.yaml +++ b/dts/Bindings/mfd/allwinner,sun4i-a10-ts.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mfd/allwinner,sun4i-a10-ts.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Resistive Touchscreen Controller Device Tree Bindings +title: Allwinner A10 Resistive Touchscreen Controller maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/mfd/allwinner,sun6i-a31-prcm.yaml b/dts/Bindings/mfd/allwinner,sun6i-a31-prcm.yaml index d131759cca..cf94176fe1 100644 --- a/dts/Bindings/mfd/allwinner,sun6i-a31-prcm.yaml +++ b/dts/Bindings/mfd/allwinner,sun6i-a31-prcm.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mfd/allwinner,sun6i-a31-prcm.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A31 PRCM Device Tree Bindings +title: Allwinner A31 PRCM maintainers: - Chen-Yu Tsai <wens@csie.org> @@ -22,6 +22,7 @@ properties: patternProperties: "^.*_(clk|rst)$": type: object + unevaluatedProperties: false properties: compatible: @@ -38,6 +39,45 @@ patternProperties: properties: compatible: contains: + const: fixed-factor-clock + + then: + $ref: /schemas/clock/fixed-factor-clock.yaml# + + - if: + properties: + compatible: + contains: + const: allwinner,sun4i-a10-mod0-clk + + then: + properties: + "#clock-cells": + const: 0 + + # Already checked in the main schema + compatible: true + + clocks: + maxItems: 2 + + clock-output-names: + maxItems: 1 + + phandle: true + + required: + - "#clock-cells" + - compatible + - clocks + - clock-output-names + + additionalProperties: false + + - if: + properties: + compatible: + contains: const: allwinner,sun6i-a31-apb0-clk then: diff --git a/dts/Bindings/mfd/allwinner,sun8i-a23-prcm.yaml b/dts/Bindings/mfd/allwinner,sun8i-a23-prcm.yaml index aa5e683b23..16c80a7eec 100644 --- a/dts/Bindings/mfd/allwinner,sun8i-a23-prcm.yaml +++ b/dts/Bindings/mfd/allwinner,sun8i-a23-prcm.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mfd/allwinner,sun8i-a23-prcm.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A23 PRCM Device Tree Bindings +title: Allwinner A23 PRCM maintainers: - Chen-Yu Tsai <wens@csie.org> @@ -22,6 +22,7 @@ properties: patternProperties: "^.*(clk|rst|codec).*$": type: object + unevaluatedProperties: false properties: compatible: @@ -40,6 +41,15 @@ patternProperties: properties: compatible: contains: + const: fixed-factor-clock + + then: + $ref: /schemas/clock/fixed-factor-clock.yaml# + + - if: + properties: + compatible: + contains: const: allwinner,sun8i-a23-apb0-clk then: diff --git a/dts/Bindings/mfd/aspeed,ast2x00-scu.yaml b/dts/Bindings/mfd/aspeed,ast2x00-scu.yaml new file mode 100644 index 0000000000..1689b986f4 --- /dev/null +++ b/dts/Bindings/mfd/aspeed,ast2x00-scu.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/aspeed,ast2x00-scu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed System Control Unit + +description: + The Aspeed System Control Unit manages the global behaviour of the SoC, + configuring elements such as clocks, pinmux, and reset. + +maintainers: + - Joel Stanley <joel@jms.id.au> + - Andrew Jeffery <andrew@aj.id.au> + +properties: + compatible: + items: + - enum: + - aspeed,ast2400-scu + - aspeed,ast2500-scu + - aspeed,ast2600-scu + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + ranges: true + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +patternProperties: + '^p2a-control@[0-9a-f]+$': + description: See Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt + type: object + + '^pinctrl(@[0-9a-f]+)?$': + oneOf: + - $ref: /schemas/pinctrl/aspeed,ast2400-pinctrl.yaml + - $ref: /schemas/pinctrl/aspeed,ast2500-pinctrl.yaml + - $ref: /schemas/pinctrl/aspeed,ast2600-pinctrl.yaml + + '^interrupt-controller@[0-9a-f]+$': + description: See Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt + type: object + + '^silicon-id@[0-9a-f]+$': + description: Unique hardware silicon identifiers within the SoC + type: object + additionalProperties: false + + properties: + compatible: + items: + - enum: + - aspeed,ast2400-silicon-id + - aspeed,ast2500-silicon-id + - aspeed,ast2600-silicon-id + - const: aspeed,silicon-id + + reg: + description: + The reg should be the unique silicon id register, and not backwards + compatible one in eg. the 2600. + minItems: 1 + items: + - description: silicon id information registers + - description: unique chip id registers + +required: + - compatible + - reg + - ranges + - '#address-cells' + - '#size-cells' + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + syscon@1e6e2000 { + compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; + reg = <0x1e6e2000 0x1a8>; + #clock-cells = <1>; + #reset-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e6e2000 0x1000>; + + silicon-id@7c { + compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id"; + reg = <0x7c 0x4>, <0x150 0x8>; + }; + }; +... diff --git a/dts/Bindings/mfd/aspeed-scu.txt b/dts/Bindings/mfd/aspeed-scu.txt deleted file mode 100644 index 857ee33f73..0000000000 --- a/dts/Bindings/mfd/aspeed-scu.txt +++ /dev/null @@ -1,48 +0,0 @@ -The Aspeed System Control Unit manages the global behaviour of the SoC, -configuring elements such as clocks, pinmux, and reset. - -Required properties: -- compatible: One of: - "aspeed,ast2400-scu", "syscon", "simple-mfd" - "aspeed,ast2500-scu", "syscon", "simple-mfd" - -- reg: contains the offset and length of the SCU memory region -- #clock-cells: should be set to <1> - the system controller is also a - clock provider -- #reset-cells: should be set to <1> - the system controller is also a - reset line provider - -Example: - -syscon: syscon@1e6e2000 { - compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; - reg = <0x1e6e2000 0x1a8>; - #clock-cells = <1>; - #reset-cells = <1>; -}; - -Silicon ID ------------------ - -Families have unique hardware silicon identifiers within the SoC. - -Required properties: - - - compatible: "aspeed,silicon-id" or: - "aspeed,ast2400-silicon-id" or - "aspeed,ast2500-silicon-id" or - "aspeed,ast2600-silicon-id" - - - reg: offset and length of the silicon id information - optionally, a second offset and length describes the unique chip id - - The reg should be the unique silicon id register, and - not backwards compatible one in eg. the 2600. - -Example: - - -silicon-id@7c { - compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id"; - reg = <0x7c 0x4 0x150 0x8>; -}; diff --git a/dts/Bindings/mfd/atmel-usart.txt b/dts/Bindings/mfd/atmel-usart.txt deleted file mode 100644 index a09133066a..0000000000 --- a/dts/Bindings/mfd/atmel-usart.txt +++ /dev/null @@ -1,98 +0,0 @@ -* Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART) - -Required properties for USART: -- compatible: Should be one of the following: - - "atmel,at91rm9200-usart" - - "atmel,at91sam9260-usart" - - "microchip,sam9x60-usart" - - "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart" - - "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart" - - "microchip,sam9x60-dbgu", "microchip,sam9x60-usart" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt -- clock-names: tuple listing input clock names. - Required elements: "usart" -- clocks: phandles to input clocks. - -Required properties for USART in SPI mode: -- #size-cells : Must be <0> -- #address-cells : Must be <1> -- cs-gpios: chipselects (internal cs not supported) -- atmel,usart-mode : Must be <AT91_USART_MODE_SPI> (found in dt-bindings/mfd/at91-usart.h) - -Optional properties in serial and SPI mode: -- dma bindings for dma transfer: - - dmas: DMA specifier, consisting of a phandle to DMA controller node, - memory peripheral interface and USART DMA channel ID, FIFO configuration. - The order of DMA channels is fixed. The first DMA channel must be TX - associated channel and the second one must be RX associated channel. - Refer to dma.txt and atmel-dma.txt for details. - - dma-names: "tx" for TX channel. - "rx" for RX channel. - The order of dma-names is also fixed. The first name must be "tx" - and the second one must be "rx" as in the examples below. - -Optional properties in serial mode: -- atmel,use-dma-rx: use of PDC or DMA for receiving data -- atmel,use-dma-tx: use of PDC or DMA for transmitting data -- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD line respectively. - It will use specified PIO instead of the peripheral function pin for the USART feature. - If unsure, don't specify this property. -- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO - capable USARTs. -- rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt - -<chip> compatible description: -- at91rm9200: legacy USART support -- at91sam9260: generic USART implementation for SAM9 SoCs - -Example: -- use PDC: - usart0: serial@fff8c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff8c000 0x4000>; - interrupts = <7>; - clocks = <&usart0_clk>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - rts-gpios = <&pioD 15 GPIO_ACTIVE_LOW>; - cts-gpios = <&pioD 16 GPIO_ACTIVE_LOW>; - dtr-gpios = <&pioD 17 GPIO_ACTIVE_LOW>; - dsr-gpios = <&pioD 18 GPIO_ACTIVE_LOW>; - dcd-gpios = <&pioD 20 GPIO_ACTIVE_LOW>; - rng-gpios = <&pioD 19 GPIO_ACTIVE_LOW>; - }; - -- use DMA: - usart0: serial@f001c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf001c000 0x100>; - interrupts = <12 4 5>; - clocks = <&usart0_clk>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - dmas = <&dma0 2 0x3>, - <&dma0 2 0x204>; - dma-names = "tx", "rx"; - atmel,fifo-size = <32>; - }; - -- SPI mode: - #include <dt-bindings/mfd/at91-usart.h> - - spi0: spi@f001c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-usart", "atmel,at91sam9260-usart"; - atmel,usart-mode = <AT91_USART_MODE_SPI>; - reg = <0xf001c000 0x100>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&usart0_clk>; - clock-names = "usart"; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, - <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - cs-gpios = <&pioB 3 0>; - }; diff --git a/dts/Bindings/mfd/brcm,bcm6318-gpio-sysctl.yaml b/dts/Bindings/mfd/brcm,bcm6318-gpio-sysctl.yaml index afc569bc15..148f1da476 100644 --- a/dts/Bindings/mfd/brcm,bcm6318-gpio-sysctl.yaml +++ b/dts/Bindings/mfd/brcm,bcm6318-gpio-sysctl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mfd/brcm,bcm6318-gpio-sysctl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Broadcom BCM6318 GPIO System Controller Device Tree Bindings +title: Broadcom BCM6318 GPIO System Controller maintainers: - Álvaro Fernández Rojas <noltari@gmail.com> diff --git a/dts/Bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml b/dts/Bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml index c7771c86d7..7e582243ea 100644 --- a/dts/Bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml +++ b/dts/Bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mfd/brcm,bcm63268-gpio-sysctl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Broadcom BCM63268 GPIO System Controller Device Tree Bindings +title: Broadcom BCM63268 GPIO System Controller maintainers: - Álvaro Fernández Rojas <noltari@gmail.com> diff --git a/dts/Bindings/mfd/brcm,bcm6328-gpio-sysctl.yaml b/dts/Bindings/mfd/brcm,bcm6328-gpio-sysctl.yaml index 33963c11ae..2230848e11 100644 --- a/dts/Bindings/mfd/brcm,bcm6328-gpio-sysctl.yaml +++ b/dts/Bindings/mfd/brcm,bcm6328-gpio-sysctl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mfd/brcm,bcm6328-gpio-sysctl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Broadcom BCM6328 GPIO System Controller Device Tree Bindings +title: Broadcom BCM6328 GPIO System Controller maintainers: - Álvaro Fernández Rojas <noltari@gmail.com> diff --git a/dts/Bindings/mfd/brcm,bcm6358-gpio-sysctl.yaml b/dts/Bindings/mfd/brcm,bcm6358-gpio-sysctl.yaml index 3e44bea78b..c06693b6f7 100644 --- a/dts/Bindings/mfd/brcm,bcm6358-gpio-sysctl.yaml +++ b/dts/Bindings/mfd/brcm,bcm6358-gpio-sysctl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mfd/brcm,bcm6358-gpio-sysctl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Broadcom BCM6358 GPIO System Controller Device Tree Bindings +title: Broadcom BCM6358 GPIO System Controller maintainers: - Álvaro Fernández Rojas <noltari@gmail.com> diff --git a/dts/Bindings/mfd/brcm,bcm6362-gpio-sysctl.yaml b/dts/Bindings/mfd/brcm,bcm6362-gpio-sysctl.yaml index 48d14a5fe0..c560bede0e 100644 --- a/dts/Bindings/mfd/brcm,bcm6362-gpio-sysctl.yaml +++ b/dts/Bindings/mfd/brcm,bcm6362-gpio-sysctl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mfd/brcm,bcm6362-gpio-sysctl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Broadcom BCM6362 GPIO System Controller Device Tree Bindings +title: Broadcom BCM6362 GPIO System Controller maintainers: - Álvaro Fernández Rojas <noltari@gmail.com> diff --git a/dts/Bindings/mfd/brcm,bcm6368-gpio-sysctl.yaml b/dts/Bindings/mfd/brcm,bcm6368-gpio-sysctl.yaml index 307270b0cf..c534f5f240 100644 --- a/dts/Bindings/mfd/brcm,bcm6368-gpio-sysctl.yaml +++ b/dts/Bindings/mfd/brcm,bcm6368-gpio-sysctl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mfd/brcm,bcm6368-gpio-sysctl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Broadcom BCM6368 GPIO System Controller Device Tree Bindings +title: Broadcom BCM6368 GPIO System Controller maintainers: - Álvaro Fernández Rojas <noltari@gmail.com> diff --git a/dts/Bindings/mfd/canaan,k210-sysctl.yaml b/dts/Bindings/mfd/canaan,k210-sysctl.yaml index c24ad45cab..e2046f07a4 100644 --- a/dts/Bindings/mfd/canaan,k210-sysctl.yaml +++ b/dts/Bindings/mfd/canaan,k210-sysctl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mfd/canaan,k210-sysctl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Canaan Kendryte K210 System Controller Device Tree Bindings +title: Canaan Kendryte K210 System Controller maintainers: - Damien Le Moal <damien.lemoal@wdc.com> diff --git a/dts/Bindings/mfd/cirrus,lochnagar.yaml b/dts/Bindings/mfd/cirrus,lochnagar.yaml index ad285cb480..ebbedabb2b 100644 --- a/dts/Bindings/mfd/cirrus,lochnagar.yaml +++ b/dts/Bindings/mfd/cirrus,lochnagar.yaml @@ -144,6 +144,7 @@ properties: CODECs digital core if not being provided by an internal regulator. type: object $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false properties: compatible: enum: @@ -161,6 +162,7 @@ properties: CODECs MICVDD. type: object $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false properties: compatible: enum: @@ -177,6 +179,7 @@ properties: Initialisation data for the MIC1VDD supplies. type: object $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false properties: compatible: enum: @@ -202,6 +205,7 @@ properties: Initialisation data for the MIC2VDD supplies. type: object $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false properties: compatible: enum: @@ -228,6 +232,7 @@ properties: the CODECs analog and 1.8V digital supplies. type: object $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false properties: compatible: enum: @@ -261,7 +266,7 @@ additionalProperties: false examples: - | - #include <dt-bindings/clk/lochnagar.h> + #include <dt-bindings/clock/lochnagar.h> #include <dt-bindings/pinctrl/lochnagar.h> i2c@e0004000 { #address-cells = <1>; diff --git a/dts/Bindings/mfd/dlg,da9063.yaml b/dts/Bindings/mfd/dlg,da9063.yaml index d71933460e..e8e74e9107 100644 --- a/dts/Bindings/mfd/dlg,da9063.yaml +++ b/dts/Bindings/mfd/dlg,da9063.yaml @@ -71,8 +71,9 @@ properties: regulators: type: object + additionalProperties: false patternProperties: - "^(ldo[1-11]|bcore[1-2]|bpro|bmem|bio|bperi)$": + "^(ldo([1-9]|1[01])|bcore([1-2]|s-merged)|b(pro|mem|io|peri)|bmem-bio-merged)$": $ref: /schemas/regulator/regulator.yaml unevaluatedProperties: false @@ -112,7 +113,7 @@ examples: }; regulators { - regulator-bcore1 { + bcore1 { regulator-name = "BCORE1"; regulator-min-microvolt = <300000>; regulator-max-microvolt = <1570000>; @@ -120,7 +121,7 @@ examples: regulator-max-microamp = <2000000>; regulator-boot-on; }; - regulator-ldo11 { + ldo11 { regulator-name = "LDO_11"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <3600000>; diff --git a/dts/Bindings/mfd/gateworks-gsc.yaml b/dts/Bindings/mfd/gateworks-gsc.yaml index 5e0fe3ebe1..acb9c54942 100644 --- a/dts/Bindings/mfd/gateworks-gsc.yaml +++ b/dts/Bindings/mfd/gateworks-gsc.yaml @@ -46,6 +46,7 @@ properties: adc: type: object + additionalProperties: false description: Optional hardware monitoring module properties: @@ -59,8 +60,9 @@ properties: const: 0 patternProperties: - "^channel@[0-9]+$": + "^channel@[0-9a-f]+$": type: object + additionalProperties: false description: | Properties for a single ADC which can report cooked values (i.e. temperature sensor based on thermister), raw values @@ -113,6 +115,7 @@ properties: patternProperties: "^fan-controller@[0-9a-f]+$": type: object + additionalProperties: false description: Optional fan controller properties: diff --git a/dts/Bindings/mfd/khadas,mcu.yaml b/dts/Bindings/mfd/khadas,mcu.yaml index 5750cc06e9..084960fd5a 100644 --- a/dts/Bindings/mfd/khadas,mcu.yaml +++ b/dts/Bindings/mfd/khadas,mcu.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mfd/khadas,mcu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Khadas on-board Microcontroller Device Tree Bindings +title: Khadas on-board Microcontroller maintainers: - Neil Armstrong <neil.armstrong@linaro.org> diff --git a/dts/Bindings/mfd/maxim,max14577.yaml b/dts/Bindings/mfd/maxim,max14577.yaml index 52edd1bf54..995e96ee74 100644 --- a/dts/Bindings/mfd/maxim,max14577.yaml +++ b/dts/Bindings/mfd/maxim,max14577.yaml @@ -39,6 +39,7 @@ properties: extcon: type: object + additionalProperties: false properties: compatible: enum: diff --git a/dts/Bindings/mfd/maxim,max77843.yaml b/dts/Bindings/mfd/maxim,max77843.yaml index f30f96bbff..2e2a2a86b5 100644 --- a/dts/Bindings/mfd/maxim,max77843.yaml +++ b/dts/Bindings/mfd/maxim,max77843.yaml @@ -32,6 +32,7 @@ properties: motor-driver: type: object + additionalProperties: false properties: compatible: const: maxim,max77843-haptic diff --git a/dts/Bindings/mfd/mediatek,mt6370.yaml b/dts/Bindings/mfd/mediatek,mt6370.yaml new file mode 100644 index 0000000000..5644882db2 --- /dev/null +++ b/dts/Bindings/mfd/mediatek,mt6370.yaml @@ -0,0 +1,280 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/mediatek,mt6370.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6370 SubPMIC + +maintainers: + - ChiYuan Huang <cy_huang@richtek.com> + +description: | + MT6370 is a highly-integrated smart power management IC, which includes a + single cell Li-Ion/Li-Polymer switching battery charger, a USB Type-C & + Power Delivery (PD) controller, dual flash LED current sources, a RGB LED + driver, a backlight WLED driver, a display bias driver and a general LDO for + portable devices. + +properties: + compatible: + const: mediatek,mt6370 + + reg: + maxItems: 1 + + wakeup-source: true + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + + adc: + type: object + description: | + Provides 9 channels for system monitoring, including VBUSDIV5 (lower + accuracy, higher measure range), VBUSDIV2 (higher accuracy, lower + measure range), VBAT, VSYS, CHG_VDDP, TS_BAT, IBUS, IBAT, and TEMP_JC. + + properties: + compatible: + const: mediatek,mt6370-adc + + "#io-channel-cells": + const: 1 + + required: + - compatible + - "#io-channel-cells" + + backlight: + type: object + $ref: /schemas/leds/backlight/mediatek,mt6370-backlight.yaml# + + charger: + type: object + $ref: /schemas/power/supply/mediatek,mt6370-charger.yaml# + + tcpc: + type: object + $ref: /schemas/usb/mediatek,mt6370-tcpc.yaml# + + indicator: + type: object + $ref: /schemas/leds/mediatek,mt6370-indicator.yaml# + + flashlight: + type: object + $ref: /schemas/leds/mediatek,mt6370-flashlight.yaml# + + regulators: + type: object + description: | + List all supported regulators, which support the control for DisplayBias + voltages and one general purpose LDO which commonly used to drive the + vibrator. + + patternProperties: + "^(dsvbst|vibldo)$": + $ref: /schemas/regulator/regulator.yaml# + type: object + unevaluatedProperties: false + + "^(dsvpos|dsvneg)$": + $ref: /schemas/regulator/regulator.yaml# + type: object + unevaluatedProperties: false + + properties: + enable-gpios: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - "#interrupt-cells" + - regulators + - adc + - backlight + - indicator + - tcpc + - charger + - flashlight + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/leds/common.h> + #include <dt-bindings/iio/adc/mediatek,mt6370_adc.h> + #include <dt-bindings/usb/pd.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@34 { + compatible = "mediatek,mt6370"; + reg = <0x34>; + wakeup-source; + interrupts-extended = <&gpio26 3 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + + mt6370_adc: adc { + compatible = "mediatek,mt6370-adc"; + #io-channel-cells = <1>; + }; + + backlight { + compatible = "mediatek,mt6370-backlight"; + mediatek,bled-channel-use = /bits/ 8 <15>; + }; + + charger { + compatible = "mediatek,mt6370-charger"; + interrupts = <68>, <48>, <6>; + interrupt-names = "uvp_d_evt", "attach_i", "mivr"; + io-channels = <&mt6370_adc MT6370_CHAN_IBUS>; + + mt6370_otg_vbus: usb-otg-vbus-regulator { + regulator-name = "mt6370-usb-otg-vbus"; + regulator-min-microvolt = <4350000>; + regulator-max-microvolt = <5800000>; + regulator-min-microamp = <500000>; + regulator-max-microamp = <3000000>; + }; + }; + + indicator { + compatible = "mediatek,mt6370-indicator"; + #address-cells = <1>; + #size-cells = <0>; + + multi-led@0 { + reg = <0>; + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_RGB>; + led-max-microamp = <24000>; + #address-cells = <1>; + #size-cells = <0>; + led@0 { + reg = <0>; + color = <LED_COLOR_ID_RED>; + }; + led@1 { + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + }; + led@2 { + reg = <2>; + color = <LED_COLOR_ID_BLUE>; + }; + }; + led@3 { + reg = <3>; + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_WHITE>; + led-max-microamp = <6000>; + }; + }; + + flashlight { + compatible = "mediatek,mt6370-flashlight"; + #address-cells = <1>; + #size-cells = <0>; + led@0 { + reg = <0>; + led-sources = <0>; + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_WHITE>; + function-enumerator = <1>; + led-max-microamp = <200000>; + flash-max-microamp = <500000>; + flash-max-timeout-us = <1248000>; + }; + led@1 { + reg = <1>; + led-sources = <1>; + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_WHITE>; + function-enumerator = <2>; + led-max-microamp = <200000>; + flash-max-microamp = <500000>; + flash-max-timeout-us = <1248000>; + }; + }; + + tcpc { + compatible = "mediatek,mt6370-tcpc"; + interrupts-extended = <&gpio26 4 IRQ_TYPE_LEVEL_LOW>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + vbus-supply = <&mt6370_otg_vbus>; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 1000, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)>; + sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)>; + op-sink-microwatt = <10000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&usb_hs>; + }; + }; + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&usb_ss>; + }; + }; + port@2 { + reg = <2>; + endpoint { + remote-endpoint = <&dp_aux>; + }; + }; + }; + }; + }; + + regulators { + dsvbst { + regulator-name = "mt6370-dsv-vbst"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6200000>; + }; + dsvpos { + regulator-name = "mt6370-dsv-vpos"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + regulator-boot-on; + }; + dsvneg { + regulator-name = "mt6370-dsv-vneg"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + regulator-boot-on; + }; + vibldo { + regulator-name = "mt6370-vib-ldo"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <4000000>; + }; + }; + }; + }; diff --git a/dts/Bindings/mfd/mediatek,mt8195-scpsys.yaml b/dts/Bindings/mfd/mediatek,mt8195-scpsys.yaml new file mode 100644 index 0000000000..c8c4812fff --- /dev/null +++ b/dts/Bindings/mfd/mediatek,mt8195-scpsys.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/mediatek,mt8195-scpsys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek System Control Processor System + +maintainers: + - MandyJH Liu <mandyjh.liu@mediatek.com> + +description: + MediaTek System Control Processor System (SCPSYS) has several + power management tasks. The tasks include MTCMOS power + domain control, thermal measurement, DVFS, etc. + +properties: + compatible: + items: + - enum: + - mediatek,mt8167-scpsys + - mediatek,mt8173-scpsys + - mediatek,mt8183-scpsys + - mediatek,mt8186-scpsys + - mediatek,mt8192-scpsys + - mediatek,mt8195-scpsys + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + power-controller: + $ref: /schemas/power/mediatek,power-controller.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8195-clk.h> + #include <dt-bindings/power/mt8195-power.h> + + syscon@10006000 { + compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; + reg = <0x10006000 0x100>; + + spm: power-controller { + compatible = "mediatek,mt8195-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* sample of power domain nodes */ + power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { + reg = <MT8195_POWER_DOMAIN_PCIE_PHY>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { + reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; + #power-domain-cells = <0>; + }; + }; + }; diff --git a/dts/Bindings/mfd/mscc,ocelot.yaml b/dts/Bindings/mfd/mscc,ocelot.yaml new file mode 100644 index 0000000000..8bf45a5673 --- /dev/null +++ b/dts/Bindings/mfd/mscc,ocelot.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/mscc,ocelot.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ocelot Externally-Controlled Ethernet Switch + +maintainers: + - Colin Foster <colin.foster@in-advantage.com> + +description: | + The Ocelot ethernet switch family contains chips that have an internal CPU + (VSC7513, VSC7514) and chips that don't (VSC7511, VSC7512). All switches have + the option to be controlled externally, which is the purpose of this driver. + + The switch family is a multi-port networking switch that supports many + interfaces. Additionally, the device can perform pin control, MDIO buses, and + external GPIO expanders. + +properties: + compatible: + enum: + - mscc,vsc7512 + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + spi-max-frequency: + maxItems: 1 + +patternProperties: + "^pinctrl@[0-9a-f]+$": + type: object + $ref: /schemas/pinctrl/mscc,ocelot-pinctrl.yaml + + "^gpio@[0-9a-f]+$": + type: object + $ref: /schemas/pinctrl/microchip,sparx5-sgpio.yaml + properties: + compatible: + enum: + - mscc,ocelot-sgpio + + "^mdio@[0-9a-f]+$": + type: object + $ref: /schemas/net/mscc,miim.yaml + properties: + compatible: + enum: + - mscc,ocelot-miim + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + - spi-max-frequency + +additionalProperties: false + +examples: + - | + ocelot_clock: ocelot-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + + soc@0 { + compatible = "mscc,vsc7512"; + spi-max-frequency = <2500000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mdio@7107009c { + compatible = "mscc,ocelot-miim"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7107009c 0x24>; + + sw_phy0: ethernet-phy@0 { + reg = <0x0>; + }; + }; + + mdio@710700c0 { + compatible = "mscc,ocelot-miim"; + pinctrl-names = "default"; + pinctrl-0 = <&miim1_pins>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x710700c0 0x24>; + + sw_phy4: ethernet-phy@4 { + reg = <0x4>; + }; + }; + + gpio: pinctrl@71070034 { + compatible = "mscc,ocelot-pinctrl"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 22>; + reg = <0x71070034 0x6c>; + + sgpio_pins: sgpio-pins { + pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; + function = "sg0"; + }; + + miim1_pins: miim1-pins { + pins = "GPIO_14", "GPIO_15"; + function = "miim"; + }; + }; + + gpio@710700f8 { + compatible = "mscc,ocelot-sgpio"; + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <12500000>; + clocks = <&ocelot_clock>; + microchip,sgpio-port-ranges = <0 15>; + pinctrl-names = "default"; + pinctrl-0 = <&sgpio_pins>; + reg = <0x710700f8 0x100>; + + sgpio_in0: gpio@0 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <0>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <64>; + }; + + sgpio_out1: gpio@1 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <1>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <64>; + }; + }; + }; + }; + +... + diff --git a/dts/Bindings/mfd/qcom,spmi-pmic.yaml b/dts/Bindings/mfd/qcom,spmi-pmic.yaml index 65cbc6dee5..6a3e3ede1e 100644 --- a/dts/Bindings/mfd/qcom,spmi-pmic.yaml +++ b/dts/Bindings/mfd/qcom,spmi-pmic.yaml @@ -33,19 +33,22 @@ properties: compatible: items: - enum: - - qcom,pm660 - - qcom,pm660l - qcom,pm6150 - qcom,pm6150l - qcom,pm6350 + - qcom,pm660 + - qcom,pm660l + - qcom,pm7250b - qcom,pm7325 - qcom,pm8004 - qcom,pm8005 - qcom,pm8009 - qcom,pm8019 + - qcom,pm8028 - qcom,pm8110 - qcom,pm8150 - qcom,pm8150b + - qcom,pm8150c - qcom,pm8150l - qcom,pm8226 - qcom,pm8350 @@ -56,6 +59,7 @@ properties: - qcom,pm8916 - qcom,pm8941 - qcom,pm8950 + - qcom,pm8953 - qcom,pm8994 - qcom,pm8998 - qcom,pma8084 @@ -64,8 +68,10 @@ properties: - qcom,pmi8962 - qcom,pmi8994 - qcom,pmi8998 + - qcom,pmk8002 - qcom,pmk8350 - qcom,pmm8155au + - qcom,pmp8074 - qcom,pmr735a - qcom,pmr735b - qcom,pms405 @@ -90,7 +96,7 @@ properties: regulators: type: object - $ref: /schemas/regulator/regulator.yaml# + $ref: /schemas/regulator/qcom,spmi-regulator.yaml# patternProperties: "^adc@[0-9a-f]+$": @@ -99,7 +105,7 @@ patternProperties: "^adc-tm@[0-9a-f]+$": type: object - $ref: /schemas/thermal/qcom-spmi-adc-tm5.yaml# + # ref depends on compatible, see allOf below "^audio-codec@[0-9a-f]+$": type: object @@ -146,6 +152,22 @@ required: - compatible - reg +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8998 + then: + patternProperties: + "^adc-tm@[0-9a-f]+$": + $ref: /schemas/thermal/qcom-spmi-adc-tm-hc.yaml# + else: + patternProperties: + "^adc-tm@[0-9a-f]+$": + $ref: /schemas/thermal/qcom-spmi-adc-tm5.yaml# + additionalProperties: false examples: @@ -188,3 +210,87 @@ examples: }; }; }; + + - | + #include <dt-bindings/input/input.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/iio/qcom,spmi-vadc.h> + #include <dt-bindings/spmi/spmi.h> + + pmic@0 { + compatible = "qcom,pm6150", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pon@800 { + compatible = "qcom,pm8998-pon"; + reg = <0x800>; + mode-bootloader = <0x2>; + mode-recovery = <0x1>; + + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = <KEY_POWER>; + }; + }; + + temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm6150_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm6150_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + adc-chan@6 { + reg = <ADC5_DIE_TEMP>; + label = "die_temp"; + }; + + adc-chan@4f { + reg = <ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + }; + + adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + charger-thermistor@0 { + reg = <0>; + io-channels = <&pm6150_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + }; + + pm6150_gpio: gpios@c000 { + compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pm6150_gpio 0 0 10>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; diff --git a/dts/Bindings/mfd/qcom,tcsr.yaml b/dts/Bindings/mfd/qcom,tcsr.yaml index 2f816fd0c9..b12809b5cc 100644 --- a/dts/Bindings/mfd/qcom,tcsr.yaml +++ b/dts/Bindings/mfd/qcom,tcsr.yaml @@ -15,23 +15,27 @@ description: properties: compatible: - oneOf: - - items: - - enum: - - qcom,tcsr-apq8064 - - qcom,tcsr-apq8084 - - qcom,tcsr-ipq8064 - - qcom,tcsr-mdm9615 - - qcom,tcsr-msm8660 - - qcom,tcsr-msm8916 - - qcom,tcsr-msm8953 - - qcom,tcsr-msm8960 - - qcom,tcsr-msm8974 - - const: syscon - - items: - - const: qcom,tcsr-ipq6018 - - const: syscon - - const: simple-mfd + items: + - enum: + - qcom,msm8998-tcsr + - qcom,qcs404-tcsr + - qcom,sc7180-tcsr + - qcom,sc7280-tcsr + - qcom,sdm630-tcsr + - qcom,sdm845-tcsr + - qcom,sm8150-tcsr + - qcom,tcsr-apq8064 + - qcom,tcsr-apq8084 + - qcom,tcsr-ipq6018 + - qcom,tcsr-ipq8064 + - qcom,tcsr-mdm9615 + - qcom,tcsr-msm8660 + - qcom,tcsr-msm8916 + - qcom,tcsr-msm8953 + - qcom,tcsr-msm8960 + - qcom,tcsr-msm8974 + - qcom,tcsr-msm8996 + - const: syscon reg: maxItems: 1 diff --git a/dts/Bindings/mfd/richtek,rt5120.yaml b/dts/Bindings/mfd/richtek,rt5120.yaml new file mode 100644 index 0000000000..f73b8b25d7 --- /dev/null +++ b/dts/Bindings/mfd/richtek,rt5120.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/richtek,rt5120.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Richtek RT5120 PMIC + +maintainers: + - ChiYuan Huang <cy_huang@richtek.com> + +description: | + The RT5120 provides four high-efficiency buck converters and one LDO voltage + regulator. The device is targeted at providingthe processor voltage, memory, + I/O, and peripheral rails in home entertainment devices. The I2C interface is + used for dynamic voltage scaling of the processor voltage, power rails on/off + sequence control, operation mode selection. + +properties: + compatible: + enum: + - richtek,rt5120 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + + wakeup-source: true + + richtek,enable-undervolt-hiccup: + type: boolean + description: | + If used, under voltage protection trigger hiccup behavior, else latchup as + default + + richtek,enable-overvolt-hiccup: + type: boolean + description: + Like as 'enable-uv-hiccup', it configures over voltage protection to + hiccup, else latchup as default + + vin1-supply: + description: phandle for buck1 input power source + + vin2-supply: + description: phandle for buck2 input power source + + vin3-supply: + description: phandle for buck3 input power source + + vin4-supply: + description: phandle for buck4 input power source + + vinldo-supply: + description: phandle for ldo input power source + + regulators: + type: object + + patternProperties: + "^buck[1-4]$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + properties: + regulator-allowed-modes: + description: | + Used to specify the allowed buck converter operating mode + mode mapping: + 0: auto mode + 1: force pwm mode + items: + enum: [0, 1] + + "^(ldo|exten)$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + additionalProperties: false + + powerkey: + type: object + description: + PON key that connected to RT5120 PMIC. + + properties: + compatible: + enum: + - richtek,rt5120-pwrkey + + required: + - compatible + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - '#interrupt-cells' + - interrupt-controller + - regulators + - powerkey + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@62 { + compatible = "richtek,rt5120"; + reg = <0x62>; + interrupts-extended = <&gpio_intc 32 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + wakeup-source; + + regulators { + buck1 { + regulator-name = "rt5120-buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1393750>; + regulator-allowed-modes = <0 1>; + regulator-boot-on; + }; + buck2 { + regulator-name = "rt5120-buck2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-allowed-modes = <0 1>; + regulator-always-on; + }; + buck3 { + regulator-name = "rt5120-buck3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allowed-modes = <0 1>; + regulator-always-on; + }; + buck4 { + regulator-name = "rt5120-buck4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allowed-modes = <0 1>; + regulator-always-on; + }; + ldo { + regulator-name = "rt5120-ldo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + exten { + regulator-name = "rt5120-exten"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + }; + powerkey { + compatible = "richtek,rt5120-pwrkey"; + }; + }; + }; diff --git a/dts/Bindings/mfd/rockchip,rk817.yaml b/dts/Bindings/mfd/rockchip,rk817.yaml index bfc1720adc..935e170992 100644 --- a/dts/Bindings/mfd/rockchip,rk817.yaml +++ b/dts/Bindings/mfd/rockchip,rk817.yaml @@ -87,6 +87,7 @@ properties: patternProperties: "^(LDO_REG[1-9]|DCDC_REG[1-4]|BOOST|OTG_SWITCH)$": type: object + unevaluatedProperties: false $ref: ../regulator/regulator.yaml# unevaluatedProperties: false @@ -111,12 +112,56 @@ properties: additional properties are required for the codec, this node can be omitted. type: object + additionalProperties: false properties: rockchip,mic-in-differential: type: boolean description: Describes if the microphone uses differential mode. + charger: + description: | + The child node for the charger to hold additional properties. If a + battery is not in use, this node can be omitted. + type: object + properties: + monitored-battery: + description: | + A phandle to a monitored battery node that contains a valid + value for: + charge-full-design-microamp-hours, + charge-term-current-microamp, + constant-charge-current-max-microamp, + constant-charge-voltage-max-microvolt, + voltage-max-design-microvolt, + voltage-min-design-microvolt, + and a valid ocv-capacity table. + + rockchip,resistor-sense-micro-ohms: + description: | + Value in microohms of the battery sense resistor. This value is + used by the driver to set the correct divisor value to translate + ADC readings into the proper units of measure. + enum: [10000, 20000] + + rockchip,sleep-enter-current-microamp: + description: | + Value in microamps of the sleep enter current for the charger. + Value is used by the driver to calibrate the relax threshold. + + rockchip,sleep-filter-current-microamp: + description: + Value in microamps of the sleep filter current for the charger. + Value is used by the driver to derive the sleep sample current. + + required: + - monitored-battery + - rockchip,resistor-sense-micro-ohms + - rockchip,sleep-enter-current-microamp + - rockchip,sleep-filter-current-microamp + + additionalProperties: false + allOf: - if: properties: @@ -323,6 +368,13 @@ examples: }; }; + rk817_charger: charger { + monitored-battery = <&battery>; + rockchip,resistor-sense-micro-ohms = <10000>; + rockchip,sleep-enter-current-microamp = <300000>; + rockchip,sleep-filter-current-microamp = <100000>; + }; + rk817_codec: codec { rockchip,mic-in-differential; }; diff --git a/dts/Bindings/mfd/silergy,sy7636a.yaml b/dts/Bindings/mfd/silergy,sy7636a.yaml index 6de74c7016..ee0be32ac0 100644 --- a/dts/Bindings/mfd/silergy,sy7636a.yaml +++ b/dts/Bindings/mfd/silergy,sy7636a.yaml @@ -42,6 +42,7 @@ properties: vcom: type: object $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false description: The regulator for the compenstation voltage. Enabling/disabling this enables/disables the entire device. diff --git a/dts/Bindings/mfd/sprd,ums512-glbreg.yaml b/dts/Bindings/mfd/sprd,ums512-glbreg.yaml new file mode 100644 index 0000000000..996bd4a17c --- /dev/null +++ b/dts/Bindings/mfd/sprd,ums512-glbreg.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2022 Unisoc Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/sprd,ums512-glbreg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Unisoc System Global Register + +maintainers: + - Orson Zhai <orsonzhai@gmail.com> + - Baolin Wang <baolin.wang7@gmail.com> + - Chunyan Zhang <zhang.lyra@gmail.com> + +description: + Unisoc system global registers provide register map + for clocks and some multimedia modules of the SoC. + +properties: + compatible: + items: + - const: sprd,ums512-glbregs + - const: syscon + - const: simple-mfd + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: + maxItems: 1 + + reg: + maxItems: 1 + +patternProperties: + "^clock-controller@[0-9a-f]+$": + type: object + $ref: /schemas/clock/sprd,ums512-clk.yaml# + description: + Clock controller for the SoC clocks. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + ap_apb_regs: syscon@71000000 { + compatible = "sprd,ums512-glbregs", "syscon", "simple-mfd"; + reg = <0x71000000 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x71000000 0x3000>; + + clock-controller@0 { + compatible = "sprd,ums512-apahb-gate"; + reg = <0x0 0x2000>; + #clock-cells = <1>; + }; + }; + + - | + ap_intc5_regs: syscon@32360000 { + compatible = "sprd,ums512-glbregs", "syscon", "simple-mfd"; + reg = <0x32360000 0x1000>; + }; diff --git a/dts/Bindings/mfd/st,stm32-lptimer.yaml b/dts/Bindings/mfd/st,stm32-lptimer.yaml index a58f08aa43..d950dd5d48 100644 --- a/dts/Bindings/mfd/st,stm32-lptimer.yaml +++ b/dts/Bindings/mfd/st,stm32-lptimer.yaml @@ -46,6 +46,7 @@ properties: pwm: type: object + additionalProperties: false properties: compatible: @@ -60,6 +61,7 @@ properties: counter: type: object + additionalProperties: false properties: compatible: @@ -70,6 +72,7 @@ properties: timer: type: object + additionalProperties: false properties: compatible: @@ -81,6 +84,7 @@ properties: patternProperties: "^trigger@[0-9]+$": type: object + additionalProperties: false properties: compatible: diff --git a/dts/Bindings/mfd/st,stm32-timers.yaml b/dts/Bindings/mfd/st,stm32-timers.yaml index 5db00af8e1..e2c3c3b44a 100644 --- a/dts/Bindings/mfd/st,stm32-timers.yaml +++ b/dts/Bindings/mfd/st,stm32-timers.yaml @@ -69,6 +69,7 @@ properties: pwm: type: object + additionalProperties: false properties: compatible: @@ -104,6 +105,7 @@ properties: counter: type: object + additionalProperties: false properties: compatible: @@ -115,6 +117,7 @@ properties: patternProperties: "^timer@[0-9]+$": type: object + additionalProperties: false properties: compatible: diff --git a/dts/Bindings/mfd/st,stmfx.yaml b/dts/Bindings/mfd/st,stmfx.yaml index b2a4e4aa7f..b4d5430258 100644 --- a/dts/Bindings/mfd/st,stmfx.yaml +++ b/dts/Bindings/mfd/st,stmfx.yaml @@ -57,6 +57,7 @@ properties: patternProperties: "^[a-zA-Z]*-pins$": type: object + additionalProperties: false allOf: - $ref: ../pinctrl/pinmux-node.yaml diff --git a/dts/Bindings/mfd/stericsson,ab8500.yaml b/dts/Bindings/mfd/stericsson,ab8500.yaml index 623a4b5cd2..6c8d42f27f 100644 --- a/dts/Bindings/mfd/stericsson,ab8500.yaml +++ b/dts/Bindings/mfd/stericsson,ab8500.yaml @@ -51,6 +51,7 @@ properties: provides the reference clock for the entire U8500 system and the DB8500 counterpart. type: object + additionalProperties: false properties: compatible: @@ -63,6 +64,7 @@ properties: description: Node describing the AB8500 GPIO controller. A few GPIO pins available for misc usage. type: object + additionalProperties: false properties: compatible: @@ -78,6 +80,7 @@ properties: rtc: description: Node describing the AB8500 battery-backed RTC. type: object + additionalProperties: false properties: compatible: @@ -337,34 +340,40 @@ properties: description: The voltage for the auxilary LDO regulator 1 type: object $ref: ../regulator/regulator.yaml# + unevaluatedProperties: false ab8500_ldo_aux2: description: The voltage for the auxilary LDO regulator 2 type: object $ref: ../regulator/regulator.yaml# + unevaluatedProperties: false ab8500_ldo_aux3: description: The voltage for the auxilary LDO regulator 3 type: object $ref: ../regulator/regulator.yaml# + unevaluatedProperties: false ab8500_ldo_aux4: description: The voltage for the auxilary LDO regulator 4 only present on AB8505 type: object $ref: ../regulator/regulator.yaml# + unevaluatedProperties: false ab8500_ldo_aux5: description: The voltage for the auxilary LDO regulator 5 only present on AB8505 type: object $ref: ../regulator/regulator.yaml# + unevaluatedProperties: false ab8500_ldo_aux6: description: The voltage for the auxilary LDO regulator 6 only present on AB8505 type: object $ref: ../regulator/regulator.yaml# + unevaluatedProperties: false # There is never any AUX7 regulator which is confusing @@ -373,18 +382,21 @@ properties: only present on AB8505 type: object $ref: ../regulator/regulator.yaml# + unevaluatedProperties: false ab8500_ldo_intcore: description: The LDO regulator for the internal core voltage of the AB8500 type: object $ref: ../regulator/regulator.yaml# + unevaluatedProperties: false ab8500_ldo_adc: description: Analog power regulator for the analog to digital converter ADC, only present on AB8505 type: object $ref: ../regulator/regulator.yaml# + unevaluatedProperties: false ab8500_ldo_tvout: description: The voltage for the TV output regulator, incidentally @@ -393,33 +405,39 @@ properties: Only present on AB8500. type: object $ref: ../regulator/regulator.yaml# + unevaluatedProperties: false ab8500_ldo_audio: description: The LDO regulator for the audio codec output type: object $ref: ../regulator/regulator.yaml# + unevaluatedProperties: false ab8500_ldo_anamic1: description: The LDO regulator for the analog microphone 1 type: object $ref: ../regulator/regulator.yaml# + unevaluatedProperties: false ab8500_ldo_anamic2: description: The LDO regulator for the analog microphone 2 type: object $ref: ../regulator/regulator.yaml# + unevaluatedProperties: false ab8500_ldo_dmic: description: The LDO regulator for the digital microphone only present on AB8500 type: object $ref: ../regulator/regulator.yaml# + unevaluatedProperties: false ab8500_ldo_ana: description: Analog power regulator for CSI and DSI interfaces, Camera Serial Interface CSI and Display Serial Interface DSI. type: object $ref: ../regulator/regulator.yaml# + unevaluatedProperties: false required: - compatible @@ -442,16 +460,19 @@ properties: description: The voltage for the VSMPS1 external regulator type: object $ref: ../regulator/regulator.yaml# + unevaluatedProperties: false ab8500_ext2: description: The voltage for the VSMPS2 external regulator type: object $ref: ../regulator/regulator.yaml# + unevaluatedProperties: false ab8500_ext3: description: The voltage for the VSMPS3 external regulator type: object $ref: ../regulator/regulator.yaml# + unevaluatedProperties: false required: - compatible @@ -462,6 +483,7 @@ patternProperties: "^pwm@[1-9]+?$": type: object $ref: ../pwm/pwm.yaml# + unevaluatedProperties: false description: Represents each of the PWM blocks in the AB8500 properties: diff --git a/dts/Bindings/mfd/syscon.yaml b/dts/Bindings/mfd/syscon.yaml index c10f0b5772..4e4baf5379 100644 --- a/dts/Bindings/mfd/syscon.yaml +++ b/dts/Bindings/mfd/syscon.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mfd/syscon.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: System Controller Registers R/W Device Tree Bindings +title: System Controller Registers R/W description: | System controller node represents a register region containing a set @@ -40,6 +40,8 @@ properties: - allwinner,sun50i-a64-system-controller - brcm,cru-clkset - freecom,fsg-cs2-system-controller + - fsl,imx93-aonmix-ns-syscfg + - fsl,imx93-wakeupmix-syscfg - hisilicon,dsa-subctrl - hisilicon,hi6220-sramctrl - hisilicon,pcie-sas-subctrl @@ -59,6 +61,8 @@ properties: - rockchip,rk3368-qos - rockchip,rk3399-qos - rockchip,rk3568-qos + - rockchip,rk3588-qos + - rockchip,rv1126-qos - samsung,exynos3-sysreg - samsung,exynos4-sysreg - samsung,exynos5-sysreg @@ -71,7 +75,7 @@ properties: - contains: const: syscon minItems: 2 - maxItems: 4 # Should be enough + maxItems: 5 # Should be enough reg: maxItems: 1 @@ -80,7 +84,6 @@ properties: description: | The size (in bytes) of the IO accesses that should be performed on the device. - $ref: /schemas/types.yaml#/definitions/uint32 enum: [1, 2, 4, 8] hwlocks: @@ -92,6 +95,18 @@ required: - compatible - reg +allOf: + - if: + properties: + compatible: + contains: + const: simple-mfd + then: + properties: + compatible: + minItems: 3 + maxItems: 5 + additionalProperties: true examples: diff --git a/dts/Bindings/mfd/ti,j721e-system-controller.yaml b/dts/Bindings/mfd/ti,j721e-system-controller.yaml index 73cffc45e0..873ee0c097 100644 --- a/dts/Bindings/mfd/ti,j721e-system-controller.yaml +++ b/dts/Bindings/mfd/ti,j721e-system-controller.yaml @@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/mfd/ti,j721e-system-controller.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: TI J721e System Controller Registers R/W Device Tree Bindings +title: TI J721e System Controller Registers R/W description: | This represents the Control Module registers (CTRL_MMR0) on the SoC. @@ -54,6 +54,12 @@ patternProperties: description: Clock provider for TI EHRPWM nodes. + "phy@[0-9a-f]+$": + type: object + $ref: /schemas/phy/ti,phy-gmii-sel.yaml# + description: + The phy node corresponding to the ethernet MAC. + required: - compatible - reg diff --git a/dts/Bindings/mfd/ti,tps65086.yaml b/dts/Bindings/mfd/ti,tps65086.yaml index 6aeedda3be..3fdd9cb5b3 100644 --- a/dts/Bindings/mfd/ti,tps65086.yaml +++ b/dts/Bindings/mfd/ti,tps65086.yaml @@ -38,6 +38,7 @@ properties: regulators: type: object + additionalProperties: false description: | List of child nodes that specify the regulator initialization data. Child nodes must be named after their hardware counterparts: diff --git a/dts/Bindings/mfd/x-powers,ac100.yaml b/dts/Bindings/mfd/x-powers,ac100.yaml index de330c9869..309606d2d8 100644 --- a/dts/Bindings/mfd/x-powers,ac100.yaml +++ b/dts/Bindings/mfd/x-powers,ac100.yaml @@ -4,7 +4,7 @@ $id: "http://devicetree.org/schemas/mfd/x-powers,ac100.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: X-Powers AC100 Device Tree Bindings +title: X-Powers AC100 maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/mfd/x-powers,axp152.yaml b/dts/Bindings/mfd/x-powers,axp152.yaml index 3a53bae611..b7a8747d5f 100644 --- a/dts/Bindings/mfd/x-powers,axp152.yaml +++ b/dts/Bindings/mfd/x-powers,axp152.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mfd/x-powers,axp152.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: X-Powers AXP PMIC Device Tree Bindings +title: X-Powers AXP PMIC maintainers: - Chen-Yu Tsai <wens@csie.org> @@ -93,6 +93,9 @@ properties: - x-powers,axp809 - x-powers,axp813 - items: + - const: x-powers,axp228 + - const: x-powers,axp221 + - items: - const: x-powers,axp805 - const: x-powers,axp806 - items: @@ -260,6 +263,7 @@ properties: "^(([a-f])?ldo[0-9]|dcdc[0-7a-e]|ldo(_|-)io(0|1)|(dc1)?sw|rtc(_|-)ldo|drivevbus|dc5ldo)$": $ref: /schemas/regulator/regulator.yaml# type: object + unevaluatedProperties: false properties: regulator-ramp-delay: diff --git a/dts/Bindings/mips/cpu_irq.txt b/dts/Bindings/mips/cpu_irq.txt deleted file mode 100644 index f080f06da6..0000000000 --- a/dts/Bindings/mips/cpu_irq.txt +++ /dev/null @@ -1,47 +0,0 @@ -MIPS CPU interrupt controller - -On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU -IRQs from a devicetree file and create a irq_domain for IRQ controller. - -With the irq_domain in place we can describe how the 8 IRQs are wired to the -platforms internal interrupt controller cascade. - -Below is an example of a platform describing the cascade inside the devicetree -and the code used to load it inside arch_init_irq(). - -Required properties: -- compatible : Should be "mti,cpu-interrupt-controller" - -Example devicetree: - cpu-irq: cpu-irq { - #address-cells = <0>; - - interrupt-controller; - #interrupt-cells = <1>; - - compatible = "mti,cpu-interrupt-controller"; - }; - - intc: intc@200 { - compatible = "ralink,rt2880-intc"; - reg = <0x200 0x100>; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&cpu-irq>; - interrupts = <2>; - }; - - -Example platform irq.c: -static struct of_device_id __initdata of_irq_ids[] = { - { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init }, - { .compatible = "ralink,rt2880-intc", .data = intc_of_init }, - {}, -}; - -void __init arch_init_irq(void) -{ - of_irq_init(of_irq_ids); -} diff --git a/dts/Bindings/mips/ralink.yaml b/dts/Bindings/mips/ralink.yaml index 0588cee25a..704b5b5951 100644 --- a/dts/Bindings/mips/ralink.yaml +++ b/dts/Bindings/mips/ralink.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mips/ralink.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Ralink SoC based Platforms Device Tree Bindings +title: Ralink SoC based Platforms maintainers: - Sergio Paracuellos <sergio.paracuellos@gmail.com> diff --git a/dts/Bindings/mips/realtek-rtl.yaml b/dts/Bindings/mips/realtek-rtl.yaml index aadff8ce0f..f8ac309d29 100644 --- a/dts/Bindings/mips/realtek-rtl.yaml +++ b/dts/Bindings/mips/realtek-rtl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mips/realtek-rtl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Realtek RTL83xx/93xx SoC series device tree bindings +title: Realtek RTL83xx/93xx SoC series maintainers: - Bert Vermeulen <bert@biot.com> diff --git a/dts/Bindings/misc/qcom,fastrpc.txt b/dts/Bindings/misc/qcom,fastrpc.txt deleted file mode 100644 index 5ec124b138..0000000000 --- a/dts/Bindings/misc/qcom,fastrpc.txt +++ /dev/null @@ -1,88 +0,0 @@ -Qualcomm Technologies, Inc. FastRPC Driver - -The FastRPC implements an IPC (Inter-Processor Communication) -mechanism that allows for clients to transparently make remote method -invocations across DSP and APPS boundaries. This enables developers -to offload tasks to the DSP and free up the application processor for -other tasks. - -- compatible: - Usage: required - Value type: <stringlist> - Definition: must be "qcom,fastrpc" - -- label - Usage: required - Value type: <string> - Definition: should specify the dsp domain name this fastrpc - corresponds to. must be one of this: "adsp", "mdsp", "sdsp", "cdsp" - -- qcom,non-secure-domain: - Usage: required - Value type: <boolean> - Definition: Property to specify that dsp domain is non-secure. - -- qcom,vmids: - Usage: optional - Value type: <u32 array> - Definition: Virtual machine IDs for remote processor. - -- #address-cells - Usage: required - Value type: <u32> - Definition: Must be 1 - -- #size-cells - Usage: required - Value type: <u32> - Definition: Must be 0 - -= COMPUTE BANKS -Each subnode of the Fastrpc represents compute context banks available -on the dsp. -- All Compute context banks MUST contain the following properties: - -- compatible: - Usage: required - Value type: <stringlist> - Definition: must be "qcom,fastrpc-compute-cb" - -- reg - Usage: required - Value type: <u32> - Definition: Context Bank ID. - -- qcom,nsessions: - Usage: Optional - Value type: <u32> - Defination: A value indicating how many sessions can share this - context bank. Defaults to 1 when this property - is not specified. - -Example: - -adsp-pil { - compatible = "qcom,msm8996-adsp-pil"; - ... - smd-edge { - label = "lpass"; - fastrpc { - compatible = "qcom,fastrpc"; - qcom,smd-channels = "fastrpcsmd-apps-dsp"; - label = "adsp"; - #address-cells = <1>; - #size-cells = <0>; - - cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - }; - - cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - }; - ... - }; - }; -}; diff --git a/dts/Bindings/misc/qcom,fastrpc.yaml b/dts/Bindings/misc/qcom,fastrpc.yaml new file mode 100644 index 0000000000..d7576f8ac9 --- /dev/null +++ b/dts/Bindings/misc/qcom,fastrpc.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/qcom,fastrpc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm FastRPC Driver + +maintainers: + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: | + The FastRPC implements an IPC (Inter-Processor Communication) + mechanism that allows for clients to transparently make remote method + invocations across DSP and APPS boundaries. This enables developers + to offload tasks to the DSP and free up the application processor for + other tasks. + +properties: + compatible: + const: qcom,fastrpc + + label: + enum: + - adsp + - mdsp + - sdsp + - cdsp + + memory-region: + maxItems: 1 + description: + Phandle to a node describing memory to be used for remote heap CMA. + + qcom,glink-channels: + description: + A list of channels tied to this function, used for matching + the function to a set of virtual channels. + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + - const: fastrpcglink-apps-dsp + + qcom,non-secure-domain: + description: + Used to mark the current domain as non-secure. + type: boolean + + qcom,smd-channels: + description: + Channel name used for the RPM communication + $ref: "/schemas/types.yaml#/definitions/string-array" + items: + - const: fastrpcsmd-apps-dsp + + qcom,vmids: + description: + Virtual machine IDs for remote processor. + $ref: "/schemas/types.yaml#/definitions/uint32-array" + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "(compute-)?cb@[0-9]*$": + type: object + + description: > + Each subnode of the Fastrpc represents compute context banks available on the dsp. + + properties: + compatible: + const: qcom,fastrpc-compute-cb + + reg: + maxItems: 1 + + iommus: + minItems: 1 + maxItems: 2 + + qcom,nsessions: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 1 + description: > + A value indicating how many sessions can share this context bank. + + required: + - compatible + - reg + + additionalProperties: false + +required: + - compatible + - label + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/mailbox/qcom-ipcc.h> + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + label = "lpass"; + qcom,remote-pid = <2>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "sdsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x0541 0x0>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x0542 0x0>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0543 0x0>; + }; + }; + }; diff --git a/dts/Bindings/mmc/allwinner,sun4i-a10-mmc.yaml b/dts/Bindings/mmc/allwinner,sun4i-a10-mmc.yaml index 7803597b63..02ecc93417 100644 --- a/dts/Bindings/mmc/allwinner,sun4i-a10-mmc.yaml +++ b/dts/Bindings/mmc/allwinner,sun4i-a10-mmc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mmc/allwinner,sun4i-a10-mmc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 MMC Controller Device Tree Bindings +title: Allwinner A10 MMC Controller allOf: - $ref: "mmc-controller.yaml" diff --git a/dts/Bindings/mmc/amlogic,meson-mx-sdhc.yaml b/dts/Bindings/mmc/amlogic,meson-mx-sdhc.yaml index 60955acb8e..1c391bec43 100644 --- a/dts/Bindings/mmc/amlogic,meson-mx-sdhc.yaml +++ b/dts/Bindings/mmc/amlogic,meson-mx-sdhc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mmc/amlogic,meson-mx-sdhc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Amlogic Meson SDHC controller Device Tree Bindings +title: Amlogic Meson SDHC controller allOf: - $ref: "mmc-controller.yaml" diff --git a/dts/Bindings/mmc/cdns,sdhci.yaml b/dts/Bindings/mmc/cdns,sdhci.yaml index 4207fed62d..8b1a0fdcb5 100644 --- a/dts/Bindings/mmc/cdns,sdhci.yaml +++ b/dts/Bindings/mmc/cdns,sdhci.yaml @@ -8,7 +8,6 @@ title: Cadence SD/SDIO/eMMC Host Controller (SD4HC) maintainers: - Masahiro Yamada <yamada.masahiro@socionext.com> - - Piotr Sroka <piotrs@cadence.com> allOf: - $ref: mmc-controller.yaml diff --git a/dts/Bindings/mmc/mmc-card.yaml b/dts/Bindings/mmc/mmc-card.yaml index b17d454442..fd34712644 100644 --- a/dts/Bindings/mmc/mmc-card.yaml +++ b/dts/Bindings/mmc/mmc-card.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mmc/mmc-card.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: MMC Card / eMMC Generic Device Tree Bindings +title: MMC Card / eMMC Generic maintainers: - Ulf Hansson <ulf.hansson@linaro.org> diff --git a/dts/Bindings/mmc/mmc-controller.yaml b/dts/Bindings/mmc/mmc-controller.yaml index ff5ce89e51..802e3ca8be 100644 --- a/dts/Bindings/mmc/mmc-controller.yaml +++ b/dts/Bindings/mmc/mmc-controller.yaml @@ -88,11 +88,18 @@ properties: default: 1 max-frequency: - description: - Maximum operating frequency of the bus. + description: | + Maximum operating frequency of the bus: + - for eMMC, the maximum supported frequency is 200MHz, + - for SD/SDIO cards the SDR104 mode has a max supported + frequency of 208MHz, + - some mmc host controllers do support a max frequency upto + 384MHz. + So, lets keep the maximum supported value here. + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 400000 - maximum: 200000000 + maximum: 384000000 disable-wp: $ref: /schemas/types.yaml#/definitions/flag diff --git a/dts/Bindings/mmc/mmc-spi-slot.yaml b/dts/Bindings/mmc/mmc-spi-slot.yaml index c45b910993..c0662ce994 100644 --- a/dts/Bindings/mmc/mmc-spi-slot.yaml +++ b/dts/Bindings/mmc/mmc-spi-slot.yaml @@ -23,8 +23,6 @@ properties: reg: maxItems: 1 - spi-max-frequency: true - interrupts: maxItems: 1 diff --git a/dts/Bindings/mmc/mtk-sd.yaml b/dts/Bindings/mmc/mtk-sd.yaml index 083d1ec2f6..d8e1e2e9ad 100644 --- a/dts/Bindings/mmc/mtk-sd.yaml +++ b/dts/Bindings/mmc/mtk-sd.yaml @@ -20,6 +20,7 @@ properties: - mediatek,mt2701-mmc - mediatek,mt2712-mmc - mediatek,mt6779-mmc + - mediatek,mt6795-mmc - mediatek,mt7620-mmc - mediatek,mt7622-mmc - mediatek,mt8135-mmc diff --git a/dts/Bindings/mmc/renesas,sdhi.yaml b/dts/Bindings/mmc/renesas,sdhi.yaml index 14945ebc31..0424b06cb6 100644 --- a/dts/Bindings/mmc/renesas,sdhi.yaml +++ b/dts/Bindings/mmc/renesas,sdhi.yaml @@ -89,6 +89,9 @@ properties: - tx - rx + iommus: + maxItems: 1 + power-domains: maxItems: 1 diff --git a/dts/Bindings/mmc/rockchip-dw-mshc.yaml b/dts/Bindings/mmc/rockchip-dw-mshc.yaml index 8d888b4358..95f59a5e35 100644 --- a/dts/Bindings/mmc/rockchip-dw-mshc.yaml +++ b/dts/Bindings/mmc/rockchip-dw-mshc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Rockchip designware mobile storage host controller device tree bindings +title: Rockchip designware mobile storage host controller description: Rockchip uses the Synopsys designware mobile storage host controller @@ -32,6 +32,7 @@ properties: - rockchip,px30-dw-mshc - rockchip,rk1808-dw-mshc - rockchip,rk3036-dw-mshc + - rockchip,rk3128-dw-mshc - rockchip,rk3228-dw-mshc - rockchip,rk3308-dw-mshc - rockchip,rk3328-dw-mshc diff --git a/dts/Bindings/mmc/sdhci-am654.yaml b/dts/Bindings/mmc/sdhci-am654.yaml index 0ab07759b4..ea9121fb18 100644 --- a/dts/Bindings/mmc/sdhci-am654.yaml +++ b/dts/Bindings/mmc/sdhci-am654.yaml @@ -51,6 +51,9 @@ properties: sdhci-caps-mask: true + dma-coherent: + type: boolean + # PHY output tap delays: # Used to delay the data valid window and align it to the sampling clock. # Binding needs to be provided for each supported speed mode otherwise the diff --git a/dts/Bindings/mmc/sdhci-msm.yaml b/dts/Bindings/mmc/sdhci-msm.yaml index fc0e81c206..a96f143479 100644 --- a/dts/Bindings/mmc/sdhci-msm.yaml +++ b/dts/Bindings/mmc/sdhci-msm.yaml @@ -38,9 +38,11 @@ properties: - qcom,sc7180-sdhci - qcom,sc7280-sdhci - qcom,sdm630-sdhci + - qcom,sdm670-sdhci - qcom,sdm845-sdhci - qcom,sdx55-sdhci - qcom,sdx65-sdhci + - qcom,sm6115-sdhci - qcom,sm6125-sdhci - qcom,sm6350-sdhci - qcom,sm8150-sdhci @@ -96,6 +98,10 @@ properties: description: Should specify pin control groups used for this controller. + pinctrl-1: + description: + Should specify sleep pin control groups used for this controller. + resets: maxItems: 1 diff --git a/dts/Bindings/mtd/allwinner,sun4i-a10-nand.yaml b/dts/Bindings/mtd/allwinner,sun4i-a10-nand.yaml index c033ac3f14..4741864da4 100644 --- a/dts/Bindings/mtd/allwinner,sun4i-a10-nand.yaml +++ b/dts/Bindings/mtd/allwinner,sun4i-a10-nand.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mtd/allwinner,sun4i-a10-nand.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 NAND Controller Device Tree Bindings +title: Allwinner A10 NAND Controller allOf: - $ref: "nand-controller.yaml" diff --git a/dts/Bindings/mtd/amlogic,meson-nand.txt b/dts/Bindings/mtd/amlogic,meson-nand.txt deleted file mode 100644 index 5794ab1147..0000000000 --- a/dts/Bindings/mtd/amlogic,meson-nand.txt +++ /dev/null @@ -1,60 +0,0 @@ -Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs - -This file documents the properties in addition to those available in -the MTD NAND bindings. - -Required properties: -- compatible : contains one of: - - "amlogic,meson-gxl-nfc" - - "amlogic,meson-axg-nfc" -- clocks : - A list of phandle + clock-specifier pairs for the clocks listed - in clock-names. - -- clock-names: Should contain the following: - "core" - NFC module gate clock - "device" - device clock from eMMC sub clock controller - "rx" - rx clock phase - "tx" - tx clock phase - -- amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC - controller port C - -Optional children nodes: -Children nodes represent the available nand chips. - -Other properties: -see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings. - -Example demonstrate on AXG SoC: - - sd_emmc_c_clkc: mmc@7000 { - compatible = "amlogic,meson-axg-mmc-clkc", "syscon"; - reg = <0x0 0x7000 0x0 0x800>; - }; - - nand-controller@7800 { - compatible = "amlogic,meson-axg-nfc"; - reg = <0x0 0x7800 0x0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>; - - clocks = <&clkc CLKID_SD_EMMC_C>, - <&sd_emmc_c_clkc CLKID_MMC_DIV>, - <&sd_emmc_c_clkc CLKID_MMC_PHASE_RX>, - <&sd_emmc_c_clkc CLKID_MMC_PHASE_TX>; - clock-names = "core", "device", "rx", "tx"; - amlogic,mmc-syscon = <&sd_emmc_c_clkc>; - - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins>; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - nand-on-flash-bbt; - }; - }; diff --git a/dts/Bindings/mtd/amlogic,meson-nand.yaml b/dts/Bindings/mtd/amlogic,meson-nand.yaml new file mode 100644 index 0000000000..28fb9a7dd7 --- /dev/null +++ b/dts/Bindings/mtd/amlogic,meson-nand.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/amlogic,meson-nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs + +allOf: + - $ref: nand-controller.yaml + +maintainers: + - liang.yang@amlogic.com + +properties: + compatible: + enum: + - amlogic,meson-gxl-nfc + - amlogic,meson-axg-nfc + + reg: + maxItems: 2 + + reg-names: + items: + - const: nfc + - const: emmc + + interrupts: + maxItems: 1 + + clocks: + minItems: 2 + + clock-names: + items: + - const: core + - const: device + +patternProperties: + "^nand@[0-7]$": + type: object + properties: + reg: + minimum: 0 + maximum: 1 + + nand-ecc-mode: + const: hw + + nand-ecc-step-size: + const: 1024 + + nand-ecc-strength: + enum: [8, 16, 24, 30, 40, 50, 60] + description: | + The ECC configurations that can be supported are as follows. + meson-gxl-nfc 8, 16, 24, 30, 40, 50, 60 + meson-axg-nfc 8 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/axg-clkc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + nand-controller@ffe07800 { + compatible = "amlogic,meson-axg-nfc"; + reg = <0xffe07800 0x100>, <0xffe07000 0x800>; + reg-names = "nfc", "emmc"; + interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc CLKID_SD_EMMC_C>, <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "device"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + }; + }; + +... diff --git a/dts/Bindings/mtd/arasan,nand-controller.yaml b/dts/Bindings/mtd/arasan,nand-controller.yaml index b328769332..f013fb976d 100644 --- a/dts/Bindings/mtd/arasan,nand-controller.yaml +++ b/dts/Bindings/mtd/arasan,nand-controller.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mtd/arasan,nand-controller.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Arasan NAND Flash Controller with ONFI 3.1 support device tree bindings +title: Arasan NAND Flash Controller with ONFI 3.1 support allOf: - $ref: "nand-controller.yaml" diff --git a/dts/Bindings/mtd/arm,pl353-nand-r2p1.yaml b/dts/Bindings/mtd/arm,pl353-nand-r2p1.yaml index 5f126bb9b2..023f3ef0fa 100644 --- a/dts/Bindings/mtd/arm,pl353-nand-r2p1.yaml +++ b/dts/Bindings/mtd/arm,pl353-nand-r2p1.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mtd/arm,pl353-nand-r2p1.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: PL353 NAND Controller device tree bindings +title: PL353 NAND Controller allOf: - $ref: "nand-controller.yaml" diff --git a/dts/Bindings/mtd/intel,lgm-nand.yaml b/dts/Bindings/mtd/intel,lgm-ebunand.yaml index 30e0c66ab0..741c66ee06 100644 --- a/dts/Bindings/mtd/intel,lgm-nand.yaml +++ b/dts/Bindings/mtd/intel,lgm-ebunand.yaml @@ -1,10 +1,10 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/mtd/intel,lgm-nand.yaml# +$id: http://devicetree.org/schemas/mtd/intel,lgm-ebunand.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Intel LGM SoC NAND Controller Device Tree Bindings +title: Intel LGM SoC NAND Controller allOf: - $ref: "nand-controller.yaml" @@ -14,7 +14,7 @@ maintainers: properties: compatible: - const: intel,lgm-nand + const: intel,lgm-ebunand reg: maxItems: 6 @@ -51,7 +51,7 @@ patternProperties: properties: reg: minimum: 0 - maximum: 7 + maximum: 1 nand-ecc-mode: true @@ -75,7 +75,7 @@ additionalProperties: false examples: - | nand-controller@e0f00000 { - compatible = "intel,lgm-nand"; + compatible = "intel,lgm-ebunand"; reg = <0xe0f00000 0x100>, <0xe1000000 0x300>, <0xe1400000 0x8000>, diff --git a/dts/Bindings/mtd/mtd.yaml b/dts/Bindings/mtd/mtd.yaml index 376b679cfc..3498e48567 100644 --- a/dts/Bindings/mtd/mtd.yaml +++ b/dts/Bindings/mtd/mtd.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mtd/mtd.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: MTD (Memory Technology Device) Device Tree Bindings +title: MTD (Memory Technology Device) maintainers: - Miquel Raynal <miquel.raynal@bootlin.com> diff --git a/dts/Bindings/mtd/mxicy,nand-ecc-engine.yaml b/dts/Bindings/mtd/mxicy,nand-ecc-engine.yaml index 804479999c..f92e7234de 100644 --- a/dts/Bindings/mtd/mxicy,nand-ecc-engine.yaml +++ b/dts/Bindings/mtd/mxicy,nand-ecc-engine.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mtd/mxicy,nand-ecc-engine.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Macronix NAND ECC engine device tree bindings +title: Macronix NAND ECC engine maintainers: - Miquel Raynal <miquel.raynal@bootlin.com> diff --git a/dts/Bindings/mtd/partitions/u-boot.yaml b/dts/Bindings/mtd/partitions/u-boot.yaml new file mode 100644 index 0000000000..8a88e7d165 --- /dev/null +++ b/dts/Bindings/mtd/partitions/u-boot.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/partitions/u-boot.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: U-Boot bootloader partition + +description: | + U-Boot is a bootlodaer commonly used in embedded devices. It's almost always + located on some kind of flash device. + + Device configuration is stored as a set of environment variables that are + located in a (usually standalone) block of data. + +maintainers: + - Rafał Miłecki <rafal@milecki.pl> + +allOf: + - $ref: partition.yaml# + +properties: + compatible: + oneOf: + - const: brcm,u-boot + description: | + Broadcom stores environment variables inside a U-Boot partition. They + can be identified by a custom header with magic value. + +unevaluatedProperties: false + +examples: + - | + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + compatible = "brcm,u-boot"; + reg = <0x0 0x100000>; + label = "u-boot"; + }; + + partition@100000 { + reg = <0x100000 0x1ff00000>; + label = "firmware"; + }; + }; diff --git a/dts/Bindings/mtd/renesas-nandc.yaml b/dts/Bindings/mtd/renesas-nandc.yaml index 7b18bc5cc8..f0dc78bb05 100644 --- a/dts/Bindings/mtd/renesas-nandc.yaml +++ b/dts/Bindings/mtd/renesas-nandc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mtd/renesas-nandc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas R-Car Gen3 & RZ/N1x NAND flash controller device tree bindings +title: Renesas R-Car Gen3 & RZ/N1x NAND flash controller maintainers: - Miquel Raynal <miquel.raynal@bootlin.com> diff --git a/dts/Bindings/mtd/spi-nand.yaml b/dts/Bindings/mtd/spi-nand.yaml index dd3cd1d530..4d095e6132 100644 --- a/dts/Bindings/mtd/spi-nand.yaml +++ b/dts/Bindings/mtd/spi-nand.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mtd/spi-nand.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: SPI-NAND flash device tree bindings +title: SPI-NAND flash maintainers: - Miquel Raynal <miquel.raynal@bootlin.com> diff --git a/dts/Bindings/net/adi,adin1110.yaml b/dts/Bindings/net/adi,adin1110.yaml new file mode 100644 index 0000000000..b6bd8ee38a --- /dev/null +++ b/dts/Bindings/net/adi,adin1110.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/adi,adin1110.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ADI ADIN1110 MAC-PHY + +maintainers: + - Alexandru Tachici <alexandru.tachici@analog.com> + +description: | + The ADIN1110 is a low power single port 10BASE-T1L MAC- + PHY designed for industrial Ethernet applications. It integrates + an Ethernet PHY core with a MAC and all the associated analog + circuitry, input and output clock buffering. + + The ADIN2111 is a low power, low complexity, two-Ethernet ports + switch with integrated 10BASE-T1L PHYs and one serial peripheral + interface (SPI) port. The device is designed for industrial Ethernet + applications using low power constrained nodes and is compliant + with the IEEE 802.3cg-2019 Ethernet standard for long reach + 10 Mbps single pair Ethernet (SPE). + + The device has a 4-wire SPI interface for communication + between the MAC and host processor. + +allOf: + - $ref: ethernet-controller.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - adi,adin1110 + - adi,adin2111 + + reg: + maxItems: 1 + + adi,spi-crc: + description: | + Enable CRC8 checks on SPI read/writes. + type: boolean + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + spi { + + #address-cells = <1>; + #size-cells = <0>; + + ethernet@0 { + compatible = "adi,adin2111"; + reg = <0>; + spi-max-frequency = <24500000>; + + adi,spi-crc; + + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + + local-mac-address = [ 00 11 22 33 44 55 ]; + }; + }; diff --git a/dts/Bindings/net/allwinner,sun4i-a10-emac.yaml b/dts/Bindings/net/allwinner,sun4i-a10-emac.yaml index 098b2bf7d9..987b91b9af 100644 --- a/dts/Bindings/net/allwinner,sun4i-a10-emac.yaml +++ b/dts/Bindings/net/allwinner,sun4i-a10-emac.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/net/allwinner,sun4i-a10-emac.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 EMAC Ethernet Controller Device Tree Bindings +title: Allwinner A10 EMAC Ethernet Controller allOf: - $ref: "ethernet-controller.yaml#" diff --git a/dts/Bindings/net/allwinner,sun4i-a10-mdio.yaml b/dts/Bindings/net/allwinner,sun4i-a10-mdio.yaml index 767193ec1d..ede977cdfb 100644 --- a/dts/Bindings/net/allwinner,sun4i-a10-mdio.yaml +++ b/dts/Bindings/net/allwinner,sun4i-a10-mdio.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/net/allwinner,sun4i-a10-mdio.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 MDIO Controller Device Tree Bindings +title: Allwinner A10 MDIO Controller maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/net/allwinner,sun7i-a20-gmac.yaml b/dts/Bindings/net/allwinner,sun7i-a20-gmac.yaml index 703d0d8868..3bd912ed7c 100644 --- a/dts/Bindings/net/allwinner,sun7i-a20-gmac.yaml +++ b/dts/Bindings/net/allwinner,sun7i-a20-gmac.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/net/allwinner,sun7i-a20-gmac.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A20 GMAC Device Tree Bindings +title: Allwinner A20 GMAC allOf: - $ref: "snps,dwmac.yaml#" diff --git a/dts/Bindings/net/allwinner,sun8i-a83t-emac.yaml b/dts/Bindings/net/allwinner,sun8i-a83t-emac.yaml index 55fc620c72..1432fda3b6 100644 --- a/dts/Bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/dts/Bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A83t EMAC Device Tree Bindings +title: Allwinner A83t EMAC maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/net/altera_tse.txt b/dts/Bindings/net/altera_tse.txt deleted file mode 100644 index 1d9148ff51..0000000000 --- a/dts/Bindings/net/altera_tse.txt +++ /dev/null @@ -1,113 +0,0 @@ -* Altera Triple-Speed Ethernet MAC driver (TSE) - -Required properties: -- compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should - be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE. - ALTR is supported for legacy device trees, but is deprecated. - altr should be used for all new designs. -- reg: Address and length of the register set for the device. It contains - the information of registers in the same order as described by reg-names -- reg-names: Should contain the reg names - "control_port": MAC configuration space region - "tx_csr": xDMA Tx dispatcher control and status space region - "tx_desc": MSGDMA Tx dispatcher descriptor space region - "rx_csr" : xDMA Rx dispatcher control and status space region - "rx_desc": MSGDMA Rx dispatcher descriptor space region - "rx_resp": MSGDMA Rx dispatcher response space region - "s1": SGDMA descriptor memory -- interrupts: Should contain the TSE interrupts and its mode. -- interrupt-names: Should contain the interrupt names - "rx_irq": xDMA Rx dispatcher interrupt - "tx_irq": xDMA Tx dispatcher interrupt -- rx-fifo-depth: MAC receive FIFO buffer depth in bytes -- tx-fifo-depth: MAC transmit FIFO buffer depth in bytes -- phy-mode: See ethernet.txt in the same directory. -- phy-handle: See ethernet.txt in the same directory. -- phy-addr: See ethernet.txt in the same directory. A configuration should - include phy-handle or phy-addr. -- altr,has-supplementary-unicast: - If present, TSE supports additional unicast addresses. - Otherwise additional unicast addresses are not supported. -- altr,has-hash-multicast-filter: - If present, TSE supports a hash based multicast filter. - Otherwise, hash-based multicast filtering is not supported. - -- mdio device tree subnode: When the TSE has a phy connected to its local - mdio, there must be device tree subnode with the following - required properties: - - - compatible: Must be "altr,tse-mdio". - - #address-cells: Must be <1>. - - #size-cells: Must be <0>. - - For each phy on the mdio bus, there must be a node with the following - fields: - - - reg: phy id used to communicate to phy. - - device_type: Must be "ethernet-phy". - -The MAC address will be determined using the optional properties defined in -ethernet.txt. - -Example: - - tse_sub_0_eth_tse_0: ethernet@1,00000000 { - compatible = "altr,tse-msgdma-1.0"; - reg = <0x00000001 0x00000000 0x00000400>, - <0x00000001 0x00000460 0x00000020>, - <0x00000001 0x00000480 0x00000020>, - <0x00000001 0x000004A0 0x00000008>, - <0x00000001 0x00000400 0x00000020>, - <0x00000001 0x00000420 0x00000020>; - reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc"; - interrupt-parent = <&hps_0_arm_gic_0>; - interrupts = <0 41 4>, <0 40 4>; - interrupt-names = "rx_irq", "tx_irq"; - rx-fifo-depth = <2048>; - tx-fifo-depth = <2048>; - address-bits = <48>; - max-frame-size = <1500>; - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-mode = "gmii"; - altr,has-supplementary-unicast; - altr,has-hash-multicast-filter; - phy-handle = <&phy0>; - mdio { - compatible = "altr,tse-mdio"; - #address-cells = <1>; - #size-cells = <0>; - phy0: ethernet-phy@0 { - reg = <0x0>; - device_type = "ethernet-phy"; - }; - - phy1: ethernet-phy@1 { - reg = <0x1>; - device_type = "ethernet-phy"; - }; - - }; - }; - - tse_sub_1_eth_tse_0: ethernet@1,00001000 { - compatible = "altr,tse-msgdma-1.0"; - reg = <0x00000001 0x00001000 0x00000400>, - <0x00000001 0x00001460 0x00000020>, - <0x00000001 0x00001480 0x00000020>, - <0x00000001 0x000014A0 0x00000008>, - <0x00000001 0x00001400 0x00000020>, - <0x00000001 0x00001420 0x00000020>; - reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc"; - interrupt-parent = <&hps_0_arm_gic_0>; - interrupts = <0 43 4>, <0 42 4>; - interrupt-names = "rx_irq", "tx_irq"; - rx-fifo-depth = <2048>; - tx-fifo-depth = <2048>; - address-bits = <48>; - max-frame-size = <1500>; - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-mode = "gmii"; - altr,has-supplementary-unicast; - altr,has-hash-multicast-filter; - phy-handle = <&phy1>; - }; diff --git a/dts/Bindings/net/altr,tse.yaml b/dts/Bindings/net/altr,tse.yaml new file mode 100644 index 0000000000..8d1d944943 --- /dev/null +++ b/dts/Bindings/net/altr,tse.yaml @@ -0,0 +1,168 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/altr,tse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera Triple Speed Ethernet MAC driver (TSE) + +maintainers: + - Maxime Chevallier <maxime.chevallier@bootlin.com> + +properties: + compatible: + oneOf: + - const: altr,tse-1.0 + - const: ALTR,tse-1.0 + deprecated: true + - const: altr,tse-msgdma-1.0 + + interrupts: + minItems: 2 + + interrupt-names: + items: + - const: rx_irq + - const: tx_irq + + rx-fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Depth in bytes of the RX FIFO + + tx-fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Depth in bytes of the TX FIFO + + altr,has-supplementary-unicast: + type: boolean + description: + If present, TSE supports additional unicast addresses. + + altr,has-hash-multicast-filter: + type: boolean + description: + If present, TSE supports hash based multicast filter. + + mdio: + $ref: mdio.yaml# + unevaluatedProperties: false + description: + Creates and registers an MDIO bus. + + properties: + compatible: + const: altr,tse-mdio + + required: + - compatible + +required: + - compatible + - reg + - interrupts + - rx-fifo-depth + - tx-fifo-depth + +allOf: + - $ref: "ethernet-controller.yaml#" + - if: + properties: + compatible: + contains: + enum: + - const: altr,tse-1.0 + - const: ALTR,tse-1.0 + then: + properties: + reg: + minItems: 4 + reg-names: + items: + - const: control_port + - const: rx_csr + - const: tx_csr + - const: s1 + + - if: + properties: + compatible: + contains: + enum: + - altr,tse-msgdma-1.0 + then: + properties: + reg: + minItems: 6 + maxItems: 7 + reg-names: + minItems: 6 + items: + - const: control_port + - const: rx_csr + - const: rx_desc + - const: rx_resp + - const: tx_csr + - const: tx_desc + - const: pcs + +unevaluatedProperties: false + +examples: + - | + tse_sub_0: ethernet@c0100000 { + compatible = "altr,tse-msgdma-1.0"; + reg = <0xc0100000 0x00000400>, + <0xc0101000 0x00000020>, + <0xc0102000 0x00000020>, + <0xc0103000 0x00000008>, + <0xc0104000 0x00000020>, + <0xc0105000 0x00000020>, + <0xc0106000 0x00000100>; + reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc", "pcs"; + interrupt-parent = <&intc>; + interrupts = <0 44 4>,<0 45 4>; + interrupt-names = "rx_irq","tx_irq"; + rx-fifo-depth = <2048>; + tx-fifo-depth = <2048>; + max-frame-size = <1500>; + local-mac-address = [ 00 00 00 00 00 00 ]; + altr,has-supplementary-unicast; + altr,has-hash-multicast-filter; + sfp = <&sfp0>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + - | + tse_sub_1_eth_tse_0: ethernet@1,00001000 { + compatible = "altr,tse-msgdma-1.0"; + reg = <0x00001000 0x00000400>, + <0x00001460 0x00000020>, + <0x00001480 0x00000020>, + <0x000014A0 0x00000008>, + <0x00001400 0x00000020>, + <0x00001420 0x00000020>; + reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc"; + interrupt-parent = <&hps_0_arm_gic_0>; + interrupts = <0 43 4>, <0 42 4>; + interrupt-names = "rx_irq", "tx_irq"; + rx-fifo-depth = <2048>; + tx-fifo-depth = <2048>; + max-frame-size = <1500>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-mode = "gmii"; + altr,has-supplementary-unicast; + altr,has-hash-multicast-filter; + phy-handle = <&phy1>; + mdio { + compatible = "altr,tse-mdio"; + #address-cells = <1>; + #size-cells = <0>; + phy1: ethernet-phy@1 { + reg = <0x1>; + }; + }; + }; + +... diff --git a/dts/Bindings/net/brcm,amac.yaml b/dts/Bindings/net/brcm,amac.yaml index 8f031932c8..ee2eac8f57 100644 --- a/dts/Bindings/net/brcm,amac.yaml +++ b/dts/Bindings/net/brcm,amac.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/net/brcm,amac.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Broadcom AMAC Ethernet Controller Device Tree Bindings +title: Broadcom AMAC Ethernet Controller maintainers: - Florian Fainelli <f.fainelli@gmail.com> diff --git a/dts/Bindings/net/can/nxp,sja1000.yaml b/dts/Bindings/net/can/nxp,sja1000.yaml index b1327c5b86..144a378513 100644 --- a/dts/Bindings/net/can/nxp,sja1000.yaml +++ b/dts/Bindings/net/can/nxp,sja1000.yaml @@ -30,8 +30,10 @@ properties: clocks: maxItems: 1 + power-domains: + maxItems: 1 + reg-io-width: - $ref: /schemas/types.yaml#/definitions/uint32 description: I/O register width (in bytes) implemented by this device default: 1 enum: [ 1, 2, 4 ] @@ -105,6 +107,7 @@ allOf: then: required: - clocks + - power-domains unevaluatedProperties: false @@ -129,4 +132,5 @@ examples: reg-io-width = <4>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; clocks = <&sysctrl R9A06G032_HCLK_CAN0>; + power-domains = <&sysctrl>; }; diff --git a/dts/Bindings/net/cortina,gemini-ethernet.yaml b/dts/Bindings/net/cortina,gemini-ethernet.yaml index cc01b9b575..253b5d1407 100644 --- a/dts/Bindings/net/cortina,gemini-ethernet.yaml +++ b/dts/Bindings/net/cortina,gemini-ethernet.yaml @@ -37,6 +37,7 @@ properties: patternProperties: "^ethernet-port@[0-9]+$": type: object + unevaluatedProperties: false description: contains the resources for ethernet port allOf: - $ref: ethernet-controller.yaml# diff --git a/dts/Bindings/net/dsa/ar9331.txt b/dts/Bindings/net/dsa/ar9331.txt index 320607cbbb..f824fdae0d 100644 --- a/dts/Bindings/net/dsa/ar9331.txt +++ b/dts/Bindings/net/dsa/ar9331.txt @@ -76,7 +76,6 @@ eth1: ethernet@1a000000 { switch_port0: port@0 { reg = <0x0>; - label = "cpu"; ethernet = <ð1>; phy-mode = "gmii"; diff --git a/dts/Bindings/net/dsa/arrow,xrs700x.yaml b/dts/Bindings/net/dsa/arrow,xrs700x.yaml index 3f01b65f3b..259a0c6547 100644 --- a/dts/Bindings/net/dsa/arrow,xrs700x.yaml +++ b/dts/Bindings/net/dsa/arrow,xrs700x.yaml @@ -61,8 +61,9 @@ examples: }; ethernet-port@3 { reg = <3>; - label = "cpu"; ethernet = <&fec1>; + phy-mode = "rgmii-id"; + fixed-link { speed = <1000>; full-duplex; diff --git a/dts/Bindings/net/dsa/brcm,b53.yaml b/dts/Bindings/net/dsa/brcm,b53.yaml index 23114d691d..1219b830b1 100644 --- a/dts/Bindings/net/dsa/brcm,b53.yaml +++ b/dts/Bindings/net/dsa/brcm,b53.yaml @@ -169,7 +169,6 @@ examples: port@8 { reg = <8>; - label = "cpu"; phy-mode = "rgmii-txid"; ethernet = <ð0>; fixed-link { @@ -252,8 +251,9 @@ examples: port@8 { ethernet = <&amac2>; - label = "cpu"; reg = <8>; + phy-mode = "internal"; + fixed-link { speed = <1000>; full-duplex; diff --git a/dts/Bindings/net/dsa/dsa-port.yaml b/dts/Bindings/net/dsa/dsa-port.yaml index 09317e16cb..10ad7e7109 100644 --- a/dts/Bindings/net/dsa/dsa-port.yaml +++ b/dts/Bindings/net/dsa/dsa-port.yaml @@ -76,6 +76,23 @@ properties: required: - reg +# CPU and DSA ports must have phylink-compatible link descriptions +if: + oneOf: + - required: [ ethernet ] + - required: [ link ] +then: + allOf: + - required: + - phy-mode + - oneOf: + - required: + - fixed-link + - required: + - phy-handle + - required: + - managed + additionalProperties: true ... diff --git a/dts/Bindings/net/dsa/hirschmann,hellcreek.yaml b/dts/Bindings/net/dsa/hirschmann,hellcreek.yaml index 2286837731..73b774eadd 100644 --- a/dts/Bindings/net/dsa/hirschmann,hellcreek.yaml +++ b/dts/Bindings/net/dsa/hirschmann,hellcreek.yaml @@ -91,8 +91,13 @@ examples: port@0 { reg = <0>; - label = "cpu"; ethernet = <&gmac0>; + phy-mode = "mii"; + + fixed-link { + speed = <100>; + full-duplex; + }; }; port@2 { diff --git a/dts/Bindings/net/dsa/lan9303.txt b/dts/Bindings/net/dsa/lan9303.txt index 464d6bf876..46a732087f 100644 --- a/dts/Bindings/net/dsa/lan9303.txt +++ b/dts/Bindings/net/dsa/lan9303.txt @@ -46,7 +46,6 @@ I2C managed mode: port@0 { /* RMII fixed link to master */ reg = <0>; - label = "cpu"; ethernet = <&master>; }; @@ -83,7 +82,6 @@ MDIO managed mode: port@0 { reg = <0>; - label = "cpu"; ethernet = <&master>; }; diff --git a/dts/Bindings/net/dsa/lantiq-gswip.txt b/dts/Bindings/net/dsa/lantiq-gswip.txt index e3829d3e48..8bb1eff21c 100644 --- a/dts/Bindings/net/dsa/lantiq-gswip.txt +++ b/dts/Bindings/net/dsa/lantiq-gswip.txt @@ -96,7 +96,6 @@ switch@e108000 { port@6 { reg = <0x6>; - label = "cpu"; ethernet = <ð0>; }; }; diff --git a/dts/Bindings/net/dsa/mediatek,mt7530.yaml b/dts/Bindings/net/dsa/mediatek,mt7530.yaml index 17ab6c69ec..f2e9ff3f58 100644 --- a/dts/Bindings/net/dsa/mediatek,mt7530.yaml +++ b/dts/Bindings/net/dsa/mediatek,mt7530.yaml @@ -4,67 +4,92 @@ $id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT7530 Ethernet switch +title: Mediatek MT7530 and MT7531 Ethernet Switches maintainers: - - Sean Wang <sean.wang@mediatek.com> + - Arınç ÜNAL <arinc.unal@arinc9.com> - Landen Chao <Landen.Chao@mediatek.com> - DENG Qingfang <dqfext@gmail.com> + - Sean Wang <sean.wang@mediatek.com> description: | - Port 5 of mt7530 and mt7621 switch is muxed between: - 1. GMAC5: GMAC5 can interface with another external MAC or PHY. - 2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC - of the SOC. Used in many setups where port 0/4 becomes the WAN port. - Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to - GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not - connected to external component! - - Port 5 modes/configurations: - 1. Port 5 is disabled and isolated: An external phy can interface to the 2nd - GMAC of the SOC. - In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd - GMAC and an optional external phy. Mind the GPIO/pinctl settings of the SOC! - 2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC. - It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode - and RGMII delay. - 3. Port 5 is muxed to GMAC5 and can interface to an external phy. - Port 5 becomes an extra switch port. - Only works on platform where external phy TX<->RX lines are swapped. - Like in the Ubiquiti ER-X-SFP. - 4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port. - Currently a 2nd CPU port is not supported by DSA code. - - Depending on how the external PHY is wired: - 1. normal: The PHY can only connect to 2nd GMAC but not to the switch - 2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as - a ethernet port. But can't interface to the 2nd GMAC. - - Based on the DT the port 5 mode is configured. - - Driver tries to lookup the phy-handle of the 2nd GMAC of the master device. - When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2. - phy-mode must be set, see also example 2 below! - * mt7621: phy-mode = "rgmii-txid"; - * mt7623: phy-mode = "rgmii"; - - CPU-Ports need a phy-mode property: - Allowed values on mt7530 and mt7621: - - "rgmii" - - "trgmii" - On mt7531: - - "1000base-x" - - "2500base-x" - - "rgmii" - - "sgmii" + There are two versions of MT7530, standalone and in a multi-chip module. + + MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN, + MT7620NN, MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs. + + MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has got 10/100 PHYs + and the switch registers are directly mapped into SoC's memory map rather than + using MDIO. The DSA driver currently doesn't support this. + + There is only the standalone version of MT7531. + + Port 5 on MT7530 has got various ways of configuration. + + For standalone MT7530: + + - Port 5 can be used as a CPU port. + + - PHY 0 or 4 of the switch can be muxed to connect to the gmac of the SoC + which port 5 is wired to. Usually used for connecting the wan port + directly to the CPU to achieve 2 Gbps routing in total. + + The driver looks up the reg on the ethernet-phy node which the phy-handle + property refers to on the gmac node to mux the specified phy. + + The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the + compatible string and the reg must be 1. So, for now, only gmac1 of an + MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this. + Check out example 5 for a similar configuration. + + - Port 5 can be wired to an external phy. Port 5 becomes a DSA slave. + Check out example 7 for a similar configuration. + + For multi-chip module MT7530: + + - Port 5 can be used as a CPU port. + + - PHY 0 or 4 of the switch can be muxed to connect to gmac1 of the SoC. + Usually used for connecting the wan port directly to the CPU to achieve 2 + Gbps routing in total. + + The driver looks up the reg on the ethernet-phy node which the phy-handle + property refers to on the gmac node to mux the specified phy. + + For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. + Check out example 5. + + - In case of an external phy wired to gmac1 of the SoC, port 5 must not be + enabled. + + In case of muxing PHY 0 or 4, the external phy must not be enabled. + + For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. + Check out example 6. + - Port 5 can be muxed to an external phy. Port 5 becomes a DSA slave. + The external phy must be wired TX to TX to gmac1 of the SoC for this to + work. Ubiquiti EdgeRouter X SFP is wired this way. + + Muxing PHY 0 or 4 won't work when the external phy is connected TX to TX. + + For the MT7621 SoCs, rgmii2 group must be claimed with gpio function. + Check out example 7. properties: compatible: - enum: - - mediatek,mt7530 - - mediatek,mt7531 - - mediatek,mt7621 + oneOf: + - description: + Standalone MT7530 and multi-chip module MT7530 in MT7623AI SoC + const: mediatek,mt7530 + + - description: + Standalone MT7531 + const: mediatek,mt7531 + + - description: + Multi-chip module MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs + const: mediatek,mt7621 reg: maxItems: 1 @@ -79,7 +104,14 @@ properties: gpio-controller: type: boolean description: - if defined, MT7530's LED controller will run on GPIO mode. + If defined, LED controller of the MT7530 switch will run on GPIO mode. + + There are 15 controllable pins. + port 0 LED 0..2 as GPIO 0..2 + port 1 LED 0..2 as GPIO 3..5 + port 2 LED 0..2 as GPIO 6..8 + port 3 LED 0..2 as GPIO 9..11 + port 4 LED 0..2 as GPIO 12..14 "#interrupt-cells": const: 1 @@ -92,17 +124,21 @@ properties: io-supply: description: Phandle to the regulator node necessary for the I/O power. - See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt - for details for the regulator setup on these boards. + See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt for + details for the regulator setup on these boards. mediatek,mcm: type: boolean description: - if defined, indicates that either MT7530 is the part on multi-chip - module belong to MT7623A has or the remotely standalone chip as the - function MT7623N reference board provided for. + Used for MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs which the MT7530 + switch is a part of the multi-chip module. reset-gpios: + description: + GPIO to reset the switch. Use this if mediatek,mcm is not used. + This property is optional because some boards share the reset line with + other components which makes it impossible to probe the switch if the + reset line is used. maxItems: 1 reset-names: @@ -110,8 +146,8 @@ properties: resets: description: - Phandle pointing to the system reset controller with line index for - the ethsys. + Phandle pointing to the system reset controller with line index for the + ethsys. maxItems: 1 patternProperties: @@ -128,31 +164,88 @@ patternProperties: properties: reg: description: - Port address described must be 5 or 6 for CPU port and from 0 - to 5 for user ports. + Port address described must be 5 or 6 for CPU port and from 0 to 5 + for user ports. allOf: - $ref: dsa-port.yaml# - if: - properties: - label: - items: - - const: cpu + required: [ ethernet ] then: - required: - - reg - - phy-mode + properties: + reg: + enum: + - 5 + - 6 required: - compatible - reg +$defs: + mt7530-dsa-port: + patternProperties: + "^(ethernet-)?ports$": + patternProperties: + "^(ethernet-)?port@[0-9]+$": + if: + required: [ ethernet ] + then: + if: + properties: + reg: + const: 5 + then: + properties: + phy-mode: + enum: + - gmii + - mii + - rgmii + else: + properties: + phy-mode: + enum: + - rgmii + - trgmii + + mt7531-dsa-port: + patternProperties: + "^(ethernet-)?ports$": + patternProperties: + "^(ethernet-)?port@[0-9]+$": + if: + required: [ ethernet ] + then: + if: + properties: + reg: + const: 5 + then: + properties: + phy-mode: + enum: + - 1000base-x + - 2500base-x + - rgmii + - sgmii + else: + properties: + phy-mode: + enum: + - 1000base-x + - 2500base-x + - sgmii + allOf: - - $ref: "dsa.yaml#" + - $ref: dsa.yaml# - if: required: - mediatek,mcm then: + properties: + reset-gpios: false + required: - resets - reset-names @@ -163,52 +256,139 @@ allOf: - if: properties: compatible: - items: - - const: mediatek,mt7530 + const: mediatek,mt7530 then: + $ref: "#/$defs/mt7530-dsa-port" required: - core-supply - io-supply + - if: + properties: + compatible: + const: mediatek,mt7531 + then: + $ref: "#/$defs/mt7531-dsa-port" + properties: + gpio-controller: false + mediatek,mcm: false + + - if: + properties: + compatible: + const: mediatek,mt7621 + then: + $ref: "#/$defs/mt7530-dsa-port" + required: + - mediatek,mcm + unevaluatedProperties: false examples: + # Example 1: Standalone MT7530 - | #include <dt-bindings/gpio/gpio.h> + mdio { #address-cells = <1>; #size-cells = <0>; - switch@0 { + + switch@1f { compatible = "mediatek,mt7530"; - reg = <0>; + reg = <0x1f>; + + reset-gpios = <&pio 33 0>; core-supply = <&mt6323_vpa_reg>; io-supply = <&mt6323_vemc3v3_reg>; - reset-gpios = <&pio 33 GPIO_ACTIVE_HIGH>; ethernet-ports { #address-cells = <1>; #size-cells = <0>; + port@0 { reg = <0>; - label = "lan0"; + label = "lan1"; }; port@1 { reg = <1>; - label = "lan1"; + label = "lan2"; }; port@2 { reg = <2>; - label = "lan2"; + label = "lan3"; }; port@3 { reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; + + # Example 2: MT7530 in MT7623AI SoC + - | + #include <dt-bindings/reset/mt2701-resets.h> + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch@1f { + compatible = "mediatek,mt7530"; + reg = <0x1f>; + + mediatek,mcm; + resets = <ðsys MT2701_ETHSYS_MCM_RST>; + reset-names = "mcm"; + + core-supply = <&mt6323_vpa_reg>; + io-supply = <&mt6323_vemc3v3_reg>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; label = "lan3"; }; + port@3 { + reg = <3>; + label = "lan4"; + }; + port@4 { reg = <4>; label = "wan"; @@ -216,96 +396,226 @@ examples: port@6 { reg = <6>; - label = "cpu"; ethernet = <&gmac0>; phy-mode = "trgmii"; + fixed-link { speed = <1000>; full-duplex; + pause; }; }; }; }; }; + # Example 3: Standalone MT7531 - | - //Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4. + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> - ethernet { + mdio { #address-cells = <1>; #size-cells = <0>; - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; + + switch@0 { + compatible = "mediatek,mt7531"; reg = <0>; - phy-mode = "rgmii"; - fixed-link { - speed = <1000>; - full-duplex; - pause; + reset-gpios = <&pio 54 0>; + + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; + + # Example 4: MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs + - | + #include <dt-bindings/interrupt-controller/mips-gic.h> + #include <dt-bindings/reset/mt7621-reset.h> + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch@1f { + compatible = "mediatek,mt7621"; + reg = <0x1f>; + + mediatek,mcm; + resets = <&sysc MT7621_RST_MCM>; + reset-names = "mcm"; + + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; }; }; + }; - gmac1: mac@1 { + # Example 5: MT7621: mux MT7530's phy4 to SoC's gmac1 + - | + #include <dt-bindings/interrupt-controller/mips-gic.h> + #include <dt-bindings/reset/mt7621-reset.h> + + ethernet { + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&rgmii2_pins>; + + mac@1 { compatible = "mediatek,eth-mac"; reg = <1>; - phy-mode = "rgmii-txid"; - phy-handle = <&phy4>; + + phy-mode = "rgmii"; + phy-handle = <&example5_ethphy4>; }; - mdio: mdio-bus { + mdio { #address-cells = <1>; #size-cells = <0>; - /* Internal phy */ - phy4: ethernet-phy@4 { + /* MT7530's phy4 */ + example5_ethphy4: ethernet-phy@4 { reg = <4>; }; - mt7530: switch@1f { + switch@1f { compatible = "mediatek,mt7621"; reg = <0x1f>; - mediatek,mcm; - resets = <&rstctrl 2>; + mediatek,mcm; + resets = <&sysc MT7621_RST_MCM>; reset-names = "mcm"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; + ethernet-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; - label = "lan0"; + label = "lan1"; }; port@1 { reg = <1>; - label = "lan1"; + label = "lan2"; }; port@2 { reg = <2>; - label = "lan2"; + label = "lan3"; }; port@3 { reg = <3>; - label = "lan3"; + label = "lan4"; }; - /* Commented out. Port 4 is handled by 2nd GMAC. + /* Commented out, phy4 is muxed to gmac1. port@4 { reg = <4>; - label = "lan4"; + label = "wan"; }; */ port@6 { reg = <6>; - label = "cpu"; ethernet = <&gmac0>; - phy-mode = "rgmii"; + phy-mode = "trgmii"; fixed-link { speed = <1000>; @@ -318,82 +628,169 @@ examples: }; }; + # Example 6: MT7621: mux external phy to SoC's gmac1 - | - //Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY. + #include <dt-bindings/interrupt-controller/mips-gic.h> + #include <dt-bindings/reset/mt7621-reset.h> ethernet { #address-cells = <1>; #size-cells = <0>; - gmac_0: mac@0 { + + pinctrl-names = "default"; + pinctrl-0 = <&rgmii2_pins>; + + mac@1 { compatible = "mediatek,eth-mac"; - reg = <0>; + reg = <1>; + phy-mode = "rgmii"; + phy-handle = <&example6_ethphy7>; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; - fixed-link { - speed = <1000>; - full-duplex; - pause; + /* External PHY */ + example6_ethphy7: ethernet-phy@7 { + reg = <7>; + phy-mode = "rgmii"; + }; + + switch@1f { + compatible = "mediatek,mt7621"; + reg = <0x1f>; + + mediatek,mcm; + resets = <&sysc MT7621_RST_MCM>; + reset-names = "mcm"; + + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; }; }; + }; + + # Example 7: MT7621: mux external phy to MT7530's port 5 + - | + #include <dt-bindings/interrupt-controller/mips-gic.h> + #include <dt-bindings/reset/mt7621-reset.h> + + ethernet { + #address-cells = <1>; + #size-cells = <0>; - mdio0: mdio-bus { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii2_pins>; + + mdio { #address-cells = <1>; #size-cells = <0>; - /* External phy */ - ephy5: ethernet-phy@7 { + /* External PHY */ + example7_ethphy7: ethernet-phy@7 { reg = <7>; + phy-mode = "rgmii"; }; switch@1f { compatible = "mediatek,mt7621"; reg = <0x1f>; - mediatek,mcm; - resets = <&rstctrl 2>; + mediatek,mcm; + resets = <&sysc MT7621_RST_MCM>; reset-names = "mcm"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; + ethernet-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; - label = "lan0"; + label = "lan1"; }; port@1 { reg = <1>; - label = "lan1"; + label = "lan2"; }; port@2 { reg = <2>; - label = "lan2"; + label = "lan3"; }; port@3 { reg = <3>; - label = "lan3"; + label = "lan4"; }; port@4 { reg = <4>; - label = "lan4"; + label = "wan"; }; port@5 { reg = <5>; - label = "lan5"; - phy-mode = "rgmii"; - phy-handle = <&ephy5>; + label = "extphy"; + phy-mode = "rgmii-txid"; + phy-handle = <&example7_ethphy7>; }; - cpu_port0: port@6 { + port@6 { reg = <6>; - label = "cpu"; - ethernet = <&gmac_0>; - phy-mode = "rgmii"; + ethernet = <&gmac0>; + phy-mode = "trgmii"; fixed-link { speed = <1000>; diff --git a/dts/Bindings/net/dsa/microchip,ksz.yaml b/dts/Bindings/net/dsa/microchip,ksz.yaml index 6bbd8145b6..4da75b1f95 100644 --- a/dts/Bindings/net/dsa/microchip,ksz.yaml +++ b/dts/Bindings/net/dsa/microchip,ksz.yaml @@ -107,8 +107,9 @@ examples: }; port@5 { reg = <5>; - label = "cpu"; ethernet = <ð0>; + phy-mode = "rgmii"; + fixed-link { speed = <1000>; full-duplex; @@ -144,8 +145,9 @@ examples: }; port@6 { reg = <6>; - label = "cpu"; ethernet = <ð0>; + phy-mode = "rgmii"; + fixed-link { speed = <1000>; full-duplex; diff --git a/dts/Bindings/net/dsa/mscc,ocelot.yaml b/dts/Bindings/net/dsa/mscc,ocelot.yaml new file mode 100644 index 0000000000..8d93ed9c17 --- /dev/null +++ b/dts/Bindings/net/dsa/mscc,ocelot.yaml @@ -0,0 +1,260 @@ +# SPDX-License-Identifier: (GPL-2.0 OR MIT) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dsa/mscc,ocelot.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Ocelot Switch Family Device Tree Bindings + +maintainers: + - Vladimir Oltean <vladimir.oltean@nxp.com> + - Claudiu Manoil <claudiu.manoil@nxp.com> + - Alexandre Belloni <alexandre.belloni@bootlin.com> + - UNGLinuxDriver@microchip.com + +description: | + There are multiple switches which are either part of the Ocelot-1 family, or + derivatives of this architecture. These switches can be found embedded in + various SoCs and accessed using MMIO, or as discrete chips and accessed over + SPI or PCIe. The present DSA binding shall be used when the host controlling + them performs packet I/O primarily through an Ethernet port of the switch + (which is attached to an Ethernet port of the host), rather than through + Frame DMA or register-based I/O. + + VSC9953 (Seville): + + This is found in the NXP T1040, where it is a memory-mapped platform + device. + + The following PHY interface types are supported: + + - phy-mode = "internal": on ports 8 and 9 + - phy-mode = "sgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7 + - phy-mode = "qsgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7 + - phy-mode = "1000base-x": on ports 0, 1, 2, 3, 4, 5, 6, 7 + + VSC9959 (Felix): + + This is found in the NXP LS1028A. It is a PCI device, part of the larger + enetc root complex. As a result, the ethernet-switch node is a sub-node of + the PCIe root complex node and its "reg" property conforms to the parent + node bindings, describing it as PF 5 of device 0, bus 0. + + If any external switch port is enabled, the enetc PF2 (enetc_port2) should + be enabled as well. This is because the internal MDIO bus (exposed through + EA BAR 0) used to access the MAC PCS registers truly belongs to the enetc + port 2 and not to Felix. + + The following PHY interface types are supported: + + - phy-mode = "internal": on ports 4 and 5 + - phy-mode = "sgmii": on ports 0, 1, 2, 3 + - phy-mode = "qsgmii": on ports 0, 1, 2, 3 + - phy-mode = "usxgmii": on ports 0, 1, 2, 3 + - phy-mode = "1000base-x": on ports 0, 1, 2, 3 + - phy-mode = "2500base-x": on ports 0, 1, 2, 3 + +properties: + compatible: + enum: + - mscc,vsc9953-switch + - pci1957,eef0 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + description: + Used to signal availability of PTP TX timestamps, and state changes of + the MAC merge layer of ports that support Frame Preemption. + + little-endian: true + big-endian: true + +required: + - compatible + - reg + +allOf: + - $ref: dsa.yaml# + - if: + properties: + compatible: + const: pci1957,eef0 + then: + required: + - interrupts + +unevaluatedProperties: false + +examples: + # Felix VSC9959 (NXP LS1028A) + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pcie { /* Integrated Endpoint Root Complex */ + #address-cells = <3>; + #size-cells = <2>; + + ethernet-switch@0,5 { + compatible = "pci1957,eef0"; + reg = <0x000500 0 0 0 0>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + phy-mode = "qsgmii"; + phy-handle = <&phy0>; + managed = "in-band-status"; + }; + + port@1 { + reg = <1>; + phy-mode = "qsgmii"; + phy-handle = <&phy1>; + managed = "in-band-status"; + }; + + port@2 { + reg = <2>; + phy-mode = "qsgmii"; + phy-handle = <&phy2>; + managed = "in-band-status"; + }; + + port@3 { + reg = <3>; + phy-mode = "qsgmii"; + phy-handle = <&phy3>; + managed = "in-band-status"; + }; + + port@4 { + reg = <4>; + ethernet = <&enetc_port2>; + phy-mode = "internal"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + port@5 { + reg = <5>; + ethernet = <&enetc_port3>; + phy-mode = "internal"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; + # Seville VSC9953 (NXP T1040) + - | + soc { + #address-cells = <1>; + #size-cells = <1>; + + ethernet-switch@800000 { + compatible = "mscc,vsc9953-switch"; + reg = <0x800000 0x290000>; + little-endian; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + phy-mode = "qsgmii"; + phy-handle = <&phy0>; + managed = "in-band-status"; + }; + + port@1 { + reg = <1>; + phy-mode = "qsgmii"; + phy-handle = <&phy1>; + managed = "in-band-status"; + }; + + port@2 { + reg = <2>; + phy-mode = "qsgmii"; + phy-handle = <&phy2>; + managed = "in-band-status"; + }; + + port@3 { + reg = <3>; + phy-mode = "qsgmii"; + phy-handle = <&phy3>; + managed = "in-band-status"; + }; + + port@4 { + reg = <4>; + phy-mode = "qsgmii"; + phy-handle = <&phy4>; + managed = "in-band-status"; + }; + + port@5 { + reg = <5>; + phy-mode = "qsgmii"; + phy-handle = <&phy5>; + managed = "in-band-status"; + }; + + port@6 { + reg = <6>; + phy-mode = "qsgmii"; + phy-handle = <&phy6>; + managed = "in-band-status"; + }; + + port@7 { + reg = <7>; + phy-mode = "qsgmii"; + phy-handle = <&phy7>; + managed = "in-band-status"; + }; + + port@8 { + reg = <8>; + phy-mode = "internal"; + ethernet = <&enet0>; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + port@9 { + reg = <9>; + phy-mode = "internal"; + ethernet = <&enet1>; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; diff --git a/dts/Bindings/net/dsa/ocelot.txt b/dts/Bindings/net/dsa/ocelot.txt deleted file mode 100644 index 7a271d070b..0000000000 --- a/dts/Bindings/net/dsa/ocelot.txt +++ /dev/null @@ -1,213 +0,0 @@ -Microchip Ocelot switch driver family -===================================== - -Felix ------ - -Currently the switches supported by the felix driver are: - -- VSC9959 (Felix) -- VSC9953 (Seville) - -The VSC9959 switch is found in the NXP LS1028A. It is a PCI device, part of the -larger ENETC root complex. As a result, the ethernet-switch node is a sub-node -of the PCIe root complex node and its "reg" property conforms to the parent -node bindings: - -* reg: Specifies PCIe Device Number and Function Number of the endpoint device, - in this case for the Ethernet L2Switch it is PF5 (of device 0, bus 0). - -It does not require a "compatible" string. - -The interrupt line is used to signal availability of PTP TX timestamps and for -TSN frame preemption. - -For the external switch ports, depending on board configuration, "phy-mode" and -"phy-handle" are populated by board specific device tree instances. Ports 4 and -5 are fixed as internal ports in the NXP LS1028A instantiation. - -The CPU port property ("ethernet") configures the feature called "NPI port" in -the Ocelot hardware core. The CPU port in Ocelot is a set of queues, which are -connected, in the Node Processor Interface (NPI) mode, to an Ethernet port. -By default, in fsl-ls1028a.dtsi, the NPI port is assigned to the internal -2.5Gbps port@4, but can be moved to the 1Gbps port@5, depending on the specific -use case. Moving the NPI port to an external switch port is hardware possible, -but there is no platform support for the Linux system on the LS1028A chip to -operate as an entire slave DSA chip. NPI functionality (and therefore DSA -tagging) is supported on a single port at a time. - -Any port can be disabled (and in fsl-ls1028a.dtsi, they are indeed all disabled -by default, and should be enabled on a per-board basis). But if any external -switch port is enabled at all, the ENETC PF2 (enetc_port2) should be enabled as -well, regardless of whether it is configured as the DSA master or not. This is -because the Felix PHYLINK implementation accesses the MAC PCS registers, which -in hardware truly belong to the ENETC port #2 and not to Felix. - -Supported PHY interface types (appropriate SerDes protocol setting changes are -needed in the RCW binary): - -* phy_mode = "internal": on ports 4 and 5 -* phy_mode = "sgmii": on ports 0, 1, 2, 3 -* phy_mode = "qsgmii": on ports 0, 1, 2, 3 -* phy_mode = "usxgmii": on ports 0, 1, 2, 3 -* phy_mode = "2500base-x": on ports 0, 1, 2, 3 - -For the rest of the device tree binding definitions, which are standard DSA and -PCI, refer to the following documents: - -Documentation/devicetree/bindings/net/dsa/dsa.txt -Documentation/devicetree/bindings/pci/pci.txt - -Example: - -&soc { - pcie@1f0000000 { /* Integrated Endpoint Root Complex */ - ethernet-switch@0,5 { - reg = <0x000500 0 0 0 0>; - /* IEP INT_B */ - interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* External ports */ - port@0 { - reg = <0>; - label = "swp0"; - }; - - port@1 { - reg = <1>; - label = "swp1"; - }; - - port@2 { - reg = <2>; - label = "swp2"; - }; - - port@3 { - reg = <3>; - label = "swp3"; - }; - - /* Tagging CPU port */ - port@4 { - reg = <4>; - ethernet = <&enetc_port2>; - phy-mode = "internal"; - - fixed-link { - speed = <2500>; - full-duplex; - }; - }; - - /* Non-tagging CPU port */ - port@5 { - reg = <5>; - phy-mode = "internal"; - status = "disabled"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - }; -}; - -The VSC9953 switch is found inside NXP T1040. It is a platform device with the -following required properties: - -- compatible: - Must be "mscc,vsc9953-switch". - -Supported PHY interface types (appropriate SerDes protocol setting changes are -needed in the RCW binary): - -* phy_mode = "internal": on ports 8 and 9 -* phy_mode = "sgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7 -* phy_mode = "qsgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7 - -Example: - -&soc { - ethernet-switch@800000 { - #address-cells = <0x1>; - #size-cells = <0x0>; - compatible = "mscc,vsc9953-switch"; - little-endian; - reg = <0x800000 0x290000>; - - ports { - #address-cells = <0x1>; - #size-cells = <0x0>; - - port@0 { - reg = <0x0>; - label = "swp0"; - }; - - port@1 { - reg = <0x1>; - label = "swp1"; - }; - - port@2 { - reg = <0x2>; - label = "swp2"; - }; - - port@3 { - reg = <0x3>; - label = "swp3"; - }; - - port@4 { - reg = <0x4>; - label = "swp4"; - }; - - port@5 { - reg = <0x5>; - label = "swp5"; - }; - - port@6 { - reg = <0x6>; - label = "swp6"; - }; - - port@7 { - reg = <0x7>; - label = "swp7"; - }; - - port@8 { - reg = <0x8>; - phy-mode = "internal"; - ethernet = <&enet0>; - - fixed-link { - speed = <2500>; - full-duplex; - }; - }; - - port@9 { - reg = <0x9>; - phy-mode = "internal"; - status = "disabled"; - - fixed-link { - speed = <2500>; - full-duplex; - }; - }; - }; - }; -}; diff --git a/dts/Bindings/net/dsa/qca8k.yaml b/dts/Bindings/net/dsa/qca8k.yaml index f3c88371d7..978162df51 100644 --- a/dts/Bindings/net/dsa/qca8k.yaml +++ b/dts/Bindings/net/dsa/qca8k.yaml @@ -159,7 +159,6 @@ examples: port@0 { reg = <0>; - label = "cpu"; ethernet = <&gmac1>; phy-mode = "rgmii"; @@ -221,7 +220,6 @@ examples: port@0 { reg = <0>; - label = "cpu"; ethernet = <&gmac1>; phy-mode = "rgmii"; @@ -268,7 +266,6 @@ examples: port@6 { reg = <0>; - label = "cpu"; ethernet = <&gmac1>; phy-mode = "sgmii"; diff --git a/dts/Bindings/net/dsa/realtek.yaml b/dts/Bindings/net/dsa/realtek.yaml index 4f99aff029..1a7d45a8ad 100644 --- a/dts/Bindings/net/dsa/realtek.yaml +++ b/dts/Bindings/net/dsa/realtek.yaml @@ -189,7 +189,6 @@ examples: }; port@5 { reg = <5>; - label = "cpu"; ethernet = <&gmac0>; phy-mode = "rgmii"; fixed-link { @@ -277,7 +276,6 @@ examples: }; port@6 { reg = <6>; - label = "cpu"; ethernet = <&fec1>; phy-mode = "rgmii"; tx-internal-delay-ps = <2000>; diff --git a/dts/Bindings/net/dsa/renesas,rzn1-a5psw.yaml b/dts/Bindings/net/dsa/renesas,rzn1-a5psw.yaml index 4d428f5ad0..7ca9c19a15 100644 --- a/dts/Bindings/net/dsa/renesas,rzn1-a5psw.yaml +++ b/dts/Bindings/net/dsa/renesas,rzn1-a5psw.yaml @@ -130,7 +130,8 @@ examples: port@4 { reg = <4>; ethernet = <&gmac2>; - label = "cpu"; + phy-mode = "internal"; + fixed-link { speed = <1000>; full-duplex; diff --git a/dts/Bindings/net/dsa/vitesse,vsc73xx.txt b/dts/Bindings/net/dsa/vitesse,vsc73xx.txt index bbf4a13f6d..258bef4836 100644 --- a/dts/Bindings/net/dsa/vitesse,vsc73xx.txt +++ b/dts/Bindings/net/dsa/vitesse,vsc73xx.txt @@ -75,7 +75,6 @@ switch@0 { }; vsc: port@6 { reg = <6>; - label = "cpu"; ethernet = <&gmac1>; phy-mode = "rgmii"; fixed-link { @@ -117,7 +116,6 @@ switch@2,0 { }; vsc: port@6 { reg = <6>; - label = "cpu"; ethernet = <&enet0>; phy-mode = "rgmii"; fixed-link { diff --git a/dts/Bindings/net/engleder,tsnep.yaml b/dts/Bindings/net/engleder,tsnep.yaml index d0e1476e15..5bd964a46a 100644 --- a/dts/Bindings/net/engleder,tsnep.yaml +++ b/dts/Bindings/net/engleder,tsnep.yaml @@ -20,7 +20,26 @@ properties: maxItems: 1 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 8 + + interrupt-names: + minItems: 1 + items: + - const: mac + - const: txrx-1 + - const: txrx-2 + - const: txrx-3 + - const: txrx-4 + - const: txrx-5 + - const: txrx-6 + - const: txrx-7 + description: + The main interrupt for basic MAC features and the first TX/RX queue pair + is named "mac". "txrx-[1-7]" are the interrupts for additional TX/RX + queue pairs. + + dma-coherent: true local-mac-address: true @@ -58,7 +77,7 @@ examples: axi { #address-cells = <2>; #size-cells = <2>; - tnsep0: ethernet@a0000000 { + tsnep0: ethernet@a0000000 { compatible = "engleder,tsnep"; reg = <0x0 0xa0000000 0x0 0x10000>; interrupts = <0 89 1>; @@ -76,4 +95,24 @@ examples: }; }; }; + + tsnep1: ethernet@a0010000 { + compatible = "engleder,tsnep"; + reg = <0x0 0xa0010000 0x0 0x10000>; + interrupts = <0 93 1>, <0 94 1>, <0 95 1>, <0 96 1>; + interrupt-names = "mac", "txrx-1", "txrx-2", "txrx-3"; + interrupt-parent = <&gic>; + local-mac-address = [00 00 00 00 00 00]; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + suppress-preamble; + phy1: ethernet-phy@1 { + reg = <1>; + rxc-skew-ps = <1080>; + }; + }; + }; }; diff --git a/dts/Bindings/net/ethernet-controller.yaml b/dts/Bindings/net/ethernet-controller.yaml index c138a10228..4b3c590fce 100644 --- a/dts/Bindings/net/ethernet-controller.yaml +++ b/dts/Bindings/net/ethernet-controller.yaml @@ -67,6 +67,7 @@ properties: - gmii - sgmii - qsgmii + - qusgmii - tbi - rev-mii - rmii diff --git a/dts/Bindings/net/ethernet-phy.yaml b/dts/Bindings/net/ethernet-phy.yaml index ed1415a438..ad808e9ce5 100644 --- a/dts/Bindings/net/ethernet-phy.yaml +++ b/dts/Bindings/net/ethernet-phy.yaml @@ -144,6 +144,12 @@ properties: Mark the corresponding energy efficient ethernet mode as broken and request the ethernet to stop advertising it. + pses: + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + description: + Specifies a reference to a node representing a Power Sourcing Equipment. + phy-is-integrated: $ref: /schemas/types.yaml#/definitions/flag description: diff --git a/dts/Bindings/net/fsl,fec.yaml b/dts/Bindings/net/fsl,fec.yaml index 5cfb661be1..e0f376f7e2 100644 --- a/dts/Bindings/net/fsl,fec.yaml +++ b/dts/Bindings/net/fsl,fec.yaml @@ -21,6 +21,7 @@ properties: - fsl,imx28-fec - fsl,imx6q-fec - fsl,mvf600-fec + - fsl,s32v234-fec - items: - enum: - fsl,imx53-fec diff --git a/dts/Bindings/net/fsl,fman-dtsec.yaml b/dts/Bindings/net/fsl,fman-dtsec.yaml new file mode 100644 index 0000000000..3a35ac1c26 --- /dev/null +++ b/dts/Bindings/net/fsl,fman-dtsec.yaml @@ -0,0 +1,145 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/fsl,fman-dtsec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP FMan MAC + +maintainers: + - Madalin Bucur <madalin.bucur@nxp.com> + +description: | + Each FMan has several MACs, each implementing an Ethernet interface. Earlier + versions of FMan used the Datapath Three Speed Ethernet Controller (dTSEC) for + 10/100/1000 MBit/s speeds, and the 10-Gigabit Ethernet Media Access Controller + (10GEC) for 10 Gbit/s speeds. Later versions of FMan use the Multirate + Ethernet Media Access Controller (mEMAC) to handle all speeds. + +properties: + compatible: + enum: + - fsl,fman-dtsec + - fsl,fman-xgec + - fsl,fman-memac + + cell-index: + maximum: 64 + description: | + FManV2: + register[bit] MAC cell-index + ============================================================ + FM_EPI[16] XGEC 8 + FM_EPI[16+n] dTSECn n-1 + FM_NPI[11+n] dTSECn n-1 + n = 1,..,5 + + FManV3: + register[bit] MAC cell-index + ============================================================ + FM_EPI[16+n] mEMACn n-1 + FM_EPI[25] mEMAC10 9 + + FM_NPI[11+n] mEMACn n-1 + FM_NPI[10] mEMAC10 9 + FM_NPI[11] mEMAC9 8 + n = 1,..8 + + FM_EPI and FM_NPI are located in the FMan memory map. + + 2. SoC registers: + + - P2041, P3041, P4080 P5020, P5040: + register[bit] FMan MAC cell + Unit index + ============================================================ + DCFG_DEVDISR2[7] 1 XGEC 8 + DCFG_DEVDISR2[7+n] 1 dTSECn n-1 + DCFG_DEVDISR2[15] 2 XGEC 8 + DCFG_DEVDISR2[15+n] 2 dTSECn n-1 + n = 1,..5 + + - T1040, T2080, T4240, B4860: + register[bit] FMan MAC cell + Unit index + ============================================================ + DCFG_CCSR_DEVDISR2[n-1] 1 mEMACn n-1 + DCFG_CCSR_DEVDISR2[11+n] 2 mEMACn n-1 + n = 1,..6,9,10 + + EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in + the specific SoC "Device Configuration/Pin Control" Memory + Map. + + reg: + maxItems: 1 + + fsl,fman-ports: + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 2 + description: | + An array of two references: the first is the FMan RX port and the second + is the TX port used by this MAC. + + ptp-timer: + $ref: /schemas/types.yaml#/definitions/phandle + description: A reference to the IEEE1588 timer + + pcsphy-handle: + $ref: /schemas/types.yaml#/definitions/phandle + description: A reference to the PCS (typically found on the SerDes) + + tbi-handle: + $ref: /schemas/types.yaml#/definitions/phandle + description: A reference to the (TBI-based) PCS + +required: + - compatible + - cell-index + - reg + - fsl,fman-ports + - ptp-timer + +allOf: + - $ref: ethernet-controller.yaml# + - if: + properties: + compatible: + contains: + const: fsl,fman-dtsec + then: + required: + - tbi-handle + - if: + properties: + compatible: + contains: + const: fsl,fman-memac + then: + required: + - pcsphy-handle + +unevaluatedProperties: false + +examples: + - | + ethernet@e0000 { + compatible = "fsl,fman-dtsec"; + cell-index = <0>; + reg = <0xe0000 0x1000>; + fsl,fman-ports = <&fman1_rx8 &fman1_tx28>; + ptp-timer = <&ptp_timer>; + tbi-handle = <&tbi0>; + }; + - | + ethernet@e8000 { + cell-index = <4>; + compatible = "fsl,fman-memac"; + reg = <0xe8000 0x1000>; + fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>; + ptp-timer = <&ptp_timer0>; + pcsphy-handle = <&pcsphy4>; + phy-handle = <&sgmii_phy1>; + phy-connection-type = "sgmii"; + }; +... diff --git a/dts/Bindings/net/fsl-fman.txt b/dts/Bindings/net/fsl-fman.txt index 801efc7d68..b9055335db 100644 --- a/dts/Bindings/net/fsl-fman.txt +++ b/dts/Bindings/net/fsl-fman.txt @@ -232,133 +232,7 @@ port@81000 { ============================================================================= FMan dTSEC/XGEC/mEMAC Node -DESCRIPTION - -mEMAC/dTSEC/XGEC are the Ethernet network interfaces - -PROPERTIES - -- compatible - Usage: required - Value type: <stringlist> - Definition: A standard property. - Must include one of the following: - - "fsl,fman-dtsec" for dTSEC MAC - - "fsl,fman-xgec" for XGEC MAC - - "fsl,fman-memac" for mEMAC MAC - -- cell-index - Usage: required - Value type: <u32> - Definition: Specifies the MAC id. - - The cell-index value may be used by the FMan or the SoC, to - identify the MAC unit in the FMan (or SoC) memory map. - In the tables below there's a description of the cell-index - use, there are two tables, one describes the use of cell-index - by the FMan, the second describes the use by the SoC: - - 1. FMan Registers - - FManV2: - register[bit] MAC cell-index - ============================================================ - FM_EPI[16] XGEC 8 - FM_EPI[16+n] dTSECn n-1 - FM_NPI[11+n] dTSECn n-1 - n = 1,..,5 - - FManV3: - register[bit] MAC cell-index - ============================================================ - FM_EPI[16+n] mEMACn n-1 - FM_EPI[25] mEMAC10 9 - - FM_NPI[11+n] mEMACn n-1 - FM_NPI[10] mEMAC10 9 - FM_NPI[11] mEMAC9 8 - n = 1,..8 - - FM_EPI and FM_NPI are located in the FMan memory map. - - 2. SoC registers: - - - P2041, P3041, P4080 P5020, P5040: - register[bit] FMan MAC cell - Unit index - ============================================================ - DCFG_DEVDISR2[7] 1 XGEC 8 - DCFG_DEVDISR2[7+n] 1 dTSECn n-1 - DCFG_DEVDISR2[15] 2 XGEC 8 - DCFG_DEVDISR2[15+n] 2 dTSECn n-1 - n = 1,..5 - - - T1040, T2080, T4240, B4860: - register[bit] FMan MAC cell - Unit index - ============================================================ - DCFG_CCSR_DEVDISR2[n-1] 1 mEMACn n-1 - DCFG_CCSR_DEVDISR2[11+n] 2 mEMACn n-1 - n = 1,..6,9,10 - - EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in - the specific SoC "Device Configuration/Pin Control" Memory - Map. - -- reg - Usage: required - Value type: <prop-encoded-array> - Definition: A standard property. - -- fsl,fman-ports - Usage: required - Value type: <prop-encoded-array> - Definition: An array of two phandles - the first references is - the FMan RX port and the second is the TX port used by this - MAC. - -- ptp-timer - Usage required - Value type: <phandle> - Definition: A phandle for 1EEE1588 timer. - -- pcsphy-handle - Usage required for "fsl,fman-memac" MACs - Value type: <phandle> - Definition: A phandle for pcsphy. - -- tbi-handle - Usage required for "fsl,fman-dtsec" MACs - Value type: <phandle> - Definition: A phandle for tbiphy. - -EXAMPLE - -fman1_tx28: port@a8000 { - cell-index = <0x28>; - compatible = "fsl,fman-v2-port-tx"; - reg = <0xa8000 0x1000>; -}; - -fman1_rx8: port@88000 { - cell-index = <0x8>; - compatible = "fsl,fman-v2-port-rx"; - reg = <0x88000 0x1000>; -}; - -ptp-timer: ptp_timer@fe000 { - compatible = "fsl,fman-ptp-timer"; - reg = <0xfe000 0x1000>; -}; - -ethernet@e0000 { - compatible = "fsl,fman-dtsec"; - cell-index = <0>; - reg = <0xe0000 0x1000>; - fsl,fman-ports = <&fman1_rx8 &fman1_tx28>; - ptp-timer = <&ptp-timer>; - tbi-handle = <&tbi0>; -}; +Refer to Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml ============================================================================ FMan IEEE 1588 Node diff --git a/dts/Bindings/net/intel,dwmac-plat.yaml b/dts/Bindings/net/intel,dwmac-plat.yaml index 52a7fa4f49..d23fa37712 100644 --- a/dts/Bindings/net/intel,dwmac-plat.yaml +++ b/dts/Bindings/net/intel,dwmac-plat.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Intel DWMAC glue layer Device Tree Bindings +title: Intel DWMAC glue layer maintainers: - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com> diff --git a/dts/Bindings/net/mediatek,mt7620-gsw.txt b/dts/Bindings/net/mediatek,mt7620-gsw.txt deleted file mode 100644 index 358fed2fab..0000000000 --- a/dts/Bindings/net/mediatek,mt7620-gsw.txt +++ /dev/null @@ -1,24 +0,0 @@ -Mediatek Gigabit Switch -======================= - -The mediatek gigabit switch can be found on Mediatek SoCs (mt7620, mt7621). - -Required properties: -- compatible: Should be "mediatek,mt7620-gsw" or "mediatek,mt7621-gsw" -- reg: Address and length of the register set for the device -- interrupts: Should contain the gigabit switches interrupt -- resets: Should contain the gigabit switches resets -- reset-names: Should contain the reset names "gsw" - -Example: - -gsw@10110000 { - compatible = "ralink,mt7620-gsw"; - reg = <0x10110000 8000>; - - resets = <&rstctrl 23>; - reset-names = "gsw"; - - interrupt-parent = <&intc>; - interrupts = <17>; -}; diff --git a/dts/Bindings/net/mediatek,net.yaml b/dts/Bindings/net/mediatek,net.yaml index f5564ecddb..7ef696204c 100644 --- a/dts/Bindings/net/mediatek,net.yaml +++ b/dts/Bindings/net/mediatek,net.yaml @@ -69,6 +69,15 @@ properties: A list of phandle to the syscon node that handles the SGMII setup which is required for those SoCs equipped with SGMII. + mediatek,wed: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 2 + maxItems: 2 + items: + maxItems: 1 + description: + List of phandles to wireless ethernet dispatch nodes. + dma-coherent: true mdio-bus: @@ -112,6 +121,8 @@ allOf: Phandle to the syscon node that handles the ports slew rate and driver current. + mediatek,wed: false + - if: properties: compatible: @@ -144,15 +155,6 @@ allOf: minItems: 1 maxItems: 1 - mediatek,wed: - $ref: /schemas/types.yaml#/definitions/phandle-array - minItems: 2 - maxItems: 2 - items: - maxItems: 1 - description: - List of phandles to wireless ethernet dispatch nodes. - mediatek,pcie-mirror: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -202,6 +204,8 @@ allOf: minItems: 2 maxItems: 2 + mediatek,wed: false + - if: properties: compatible: @@ -238,6 +242,11 @@ allOf: minItems: 2 maxItems: 2 + mediatek,wed-pcie: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the mediatek wed-pcie controller. + patternProperties: "^mac@[0-1]$": type: object diff --git a/dts/Bindings/net/mediatek-dwmac.yaml b/dts/Bindings/net/mediatek-dwmac.yaml index 61b2fb9e14..0fa2132fa4 100644 --- a/dts/Bindings/net/mediatek-dwmac.yaml +++ b/dts/Bindings/net/mediatek-dwmac.yaml @@ -19,6 +19,7 @@ select: contains: enum: - mediatek,mt2712-gmac + - mediatek,mt8188-gmac - mediatek,mt8195-gmac required: - compatible @@ -37,6 +38,11 @@ properties: - enum: - mediatek,mt8195-gmac - const: snps,dwmac-5.10a + - items: + - enum: + - mediatek,mt8188-gmac + - const: mediatek,mt8195-gmac + - const: snps,dwmac-5.10a clocks: minItems: 5 @@ -74,7 +80,7 @@ properties: or will round down. Range 0~31*170. For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550, or will round down. Range 0~31*550. - For MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290, + For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290, or will round down. Range 0~31*290. mediatek,rx-delay-ps: @@ -84,7 +90,7 @@ properties: or will round down. Range 0~31*170. For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550, or will round down. Range 0~31*550. - For MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple + For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290, or will round down. Range 0~31*290. mediatek,rmii-rxc: diff --git a/dts/Bindings/net/microchip,sparx5-switch.yaml b/dts/Bindings/net/microchip,sparx5-switch.yaml index 6c86d3d85e..57ffeb8fc8 100644 --- a/dts/Bindings/net/microchip,sparx5-switch.yaml +++ b/dts/Bindings/net/microchip,sparx5-switch.yaml @@ -74,16 +74,20 @@ properties: ethernet-ports: type: object + additionalProperties: false + + properties: + '#address-cells': + const: 1 + '#size-cells': + const: 0 + patternProperties: "^port@[0-9a-f]+$": - type: object + $ref: /schemas/net/ethernet-controller.yaml# + unevaluatedProperties: false properties: - '#address-cells': - const: 1 - '#size-cells': - const: 0 - reg: description: Switch port number @@ -93,29 +97,11 @@ properties: phandle of a Ethernet SerDes PHY. This defines which SerDes instance will handle the Ethernet traffic. - phy-mode: - description: - This specifies the interface used by the Ethernet SerDes towards - the PHY or SFP. - microchip,bandwidth: description: Specifies bandwidth in Mbit/s allocated to the port. $ref: "/schemas/types.yaml#/definitions/uint32" maximum: 25000 - phy-handle: - description: - phandle of a Ethernet PHY. This is optional and if provided it - points to the cuPHY used by the Ethernet SerDes. - - sfp: - description: - phandle of an SFP. This is optional and used when not specifying - a cuPHY. It points to the SFP node that describes the SFP used by - the Ethernet SerDes. - - managed: true - microchip,sd-sgpio: description: Index of the ports Signal Detect SGPIO in the set of 384 SGPIOs @@ -144,8 +130,6 @@ required: - reg-names - interrupts - interrupt-names - - resets - - reset-names - ethernet-ports additionalProperties: false diff --git a/dts/Bindings/net/nfc/marvell,nci.yaml b/dts/Bindings/net/nfc/marvell,nci.yaml index a191a04e68..308485a8ee 100644 --- a/dts/Bindings/net/nfc/marvell,nci.yaml +++ b/dts/Bindings/net/nfc/marvell,nci.yaml @@ -128,7 +128,7 @@ examples: i2c-int-rising; - reset-n-io = <&gpio3 19 GPIO_ACTIVE_HIGH>; + reset-n-io = <&gpio3 19 GPIO_ACTIVE_LOW>; }; }; @@ -151,7 +151,7 @@ examples: interrupt-parent = <&gpio1>; interrupts = <17 IRQ_TYPE_EDGE_RISING>; - reset-n-io = <&gpio3 19 GPIO_ACTIVE_HIGH>; + reset-n-io = <&gpio3 19 GPIO_ACTIVE_LOW>; }; }; @@ -162,7 +162,7 @@ examples: nfc { compatible = "marvell,nfc-uart"; - reset-n-io = <&gpio3 16 GPIO_ACTIVE_HIGH>; + reset-n-io = <&gpio3 16 GPIO_ACTIVE_LOW>; hci-muxed; flow-control; diff --git a/dts/Bindings/net/nfc/samsung,s3fwrn5.yaml b/dts/Bindings/net/nfc/samsung,s3fwrn5.yaml index 64995cbb0f..41c9760227 100644 --- a/dts/Bindings/net/nfc/samsung,s3fwrn5.yaml +++ b/dts/Bindings/net/nfc/samsung,s3fwrn5.yaml @@ -8,7 +8,6 @@ title: Samsung S3FWRN5 NCI NFC Controller maintainers: - Krzysztof Kozlowski <krzk@kernel.org> - - Krzysztof Opasiak <k.opasiak@samsung.com> properties: compatible: diff --git a/dts/Bindings/net/nvidia,tegra234-mgbe.yaml b/dts/Bindings/net/nvidia,tegra234-mgbe.yaml new file mode 100644 index 0000000000..2bd3efff24 --- /dev/null +++ b/dts/Bindings/net/nvidia,tegra234-mgbe.yaml @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra234 MGBE Multi-Gigabit Ethernet Controller + +maintainers: + - Thierry Reding <treding@nvidia.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + const: nvidia,tegra234-mgbe + + reg: + maxItems: 3 + + reg-names: + items: + - const: hypervisor + - const: mac + - const: xpcs + + interrupts: + minItems: 1 + maxItems: 3 + + interrupt-names: + minItems: 1 + items: + - const: common + - const: macsec-ns + - const: macsec + + clocks: + maxItems: 12 + + clock-names: + items: + - const: mgbe + - const: mac + - const: mac-divider + - const: ptp-ref + - const: rx-input-m + - const: rx-input + - const: tx + - const: eee-pcs + - const: rx-pcs-input + - const: rx-pcs-m + - const: rx-pcs + - const: tx-pcs + + resets: + maxItems: 2 + + reset-names: + items: + - const: mac + - const: pcs + + interconnects: + items: + - description: memory read client + - description: memory write client + + interconnect-names: + items: + - const: dma-mem + - const: write + + iommus: + maxItems: 1 + + power-domains: + maxItems: 1 + + phy-handle: true + + phy-mode: + contains: + enum: + - usxgmii + - 10gbase-kr + + mdio: + $ref: mdio.yaml# + unevaluatedProperties: false + description: + Optional node for embedded MDIO controller. + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - resets + - reset-names + - power-domains + - phy-handle + - phy-mode + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/tegra234-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/memory/tegra234-mc.h> + #include <dt-bindings/power/tegra234-powergate.h> + #include <dt-bindings/reset/tegra234-reset.h> + + ethernet@6800000 { + compatible = "nvidia,tegra234-mgbe"; + reg = <0x06800000 0x10000>, + <0x06810000 0x10000>, + <0x068a0000 0x10000>; + reg-names = "hypervisor", "mac", "xpcs"; + interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "common"; + clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, + <&bpmp TEGRA234_CLK_MGBE0_MAC>, + <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, + <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, + <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, + <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, + <&bpmp TEGRA234_CLK_MGBE0_TX>, + <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, + <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; + clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", + "rx-pcs", "tx-pcs"; + resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, + <&bpmp TEGRA234_RESET_MGBE0_PCS>; + reset-names = "mac", "pcs"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; + + phy-handle = <&mgbe0_phy>; + phy-mode = "usxgmii"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + mgbe0_phy: phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + + #phy-cells = <0>; + }; + }; + }; diff --git a/dts/Bindings/net/nxp,dwmac-imx.yaml b/dts/Bindings/net/nxp,dwmac-imx.yaml index 0113631667..4c155441ac 100644 --- a/dts/Bindings/net/nxp,dwmac-imx.yaml +++ b/dts/Bindings/net/nxp,dwmac-imx.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/net/nxp,dwmac-imx.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: NXP i.MX8 DWMAC glue layer Device Tree Bindings +title: NXP i.MX8 DWMAC glue layer maintainers: - Joakim Zhang <qiangqing.zhang@nxp.com> diff --git a/dts/Bindings/net/nxp,tja11xx.yaml b/dts/Bindings/net/nxp,tja11xx.yaml index d51da24f35..ab8867e693 100644 --- a/dts/Bindings/net/nxp,tja11xx.yaml +++ b/dts/Bindings/net/nxp,tja11xx.yaml @@ -31,6 +31,22 @@ patternProperties: description: The ID number for the child PHY. Should be +1 of parent PHY. + nxp,rmii-refclk-in: + type: boolean + description: | + The REF_CLK is provided for both transmitted and received data + in RMII mode. This clock signal is provided by the PHY and is + typically derived from an external 25MHz crystal. Alternatively, + a 50MHz clock signal generated by an external oscillator can be + connected to pin REF_CLK. A third option is to connect a 25MHz + clock to pin CLK_IN_OUT. So, the REF_CLK should be configured + as input or output according to the actual circuit connection. + If present, indicates that the REF_CLK will be configured as + interface reference clock input when RMII mode enabled. + If not present, the REF_CLK will be configured as interface + reference clock output when RMII mode enabled. + Only supported on TJA1100 and TJA1101. + required: - reg @@ -44,6 +60,7 @@ examples: tja1101_phy0: ethernet-phy@4 { reg = <0x4>; + nxp,rmii-refclk-in; }; }; - | diff --git a/dts/Bindings/net/pse-pd/podl-pse-regulator.yaml b/dts/Bindings/net/pse-pd/podl-pse-regulator.yaml new file mode 100644 index 0000000000..c6b1c188ab --- /dev/null +++ b/dts/Bindings/net/pse-pd/podl-pse-regulator.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/pse-pd/podl-pse-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Regulator based Power Sourcing Equipment + +maintainers: + - Oleksij Rempel <o.rempel@pengutronix.de> + +description: Regulator based PoDL PSE controller. The device must be referenced + by the PHY node to control power injection to the Ethernet cable. + +allOf: + - $ref: "pse-controller.yaml#" + +properties: + compatible: + const: podl-pse-regulator + + '#pse-cells': + const: 0 + + pse-supply: + description: Power supply for the PSE controller + +additionalProperties: false + +required: + - compatible + - pse-supply + +examples: + - | + ethernet-pse { + compatible = "podl-pse-regulator"; + pse-supply = <®_t1l1>; + #pse-cells = <0>; + }; diff --git a/dts/Bindings/net/pse-pd/pse-controller.yaml b/dts/Bindings/net/pse-pd/pse-controller.yaml new file mode 100644 index 0000000000..b110abb425 --- /dev/null +++ b/dts/Bindings/net/pse-pd/pse-controller.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/pse-pd/pse-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Power Sourcing Equipment (PSE). + +description: Binding for the Power Sourcing Equipment (PSE) as defined in the + IEEE 802.3 specification. It is designed for hardware which is delivering + power over twisted pair/ethernet cable. The ethernet-pse nodes should be + used to describe PSE controller and referenced by the ethernet-phy node. + +maintainers: + - Oleksij Rempel <o.rempel@pengutronix.de> + +properties: + $nodename: + pattern: "^ethernet-pse(@.*)?$" + + "#pse-cells": + description: + Used to uniquely identify a PSE instance within an IC. Will be + 0 on PSE nodes with only a single output and at least 1 on nodes + controlling several outputs. + enum: [0, 1] + +required: + - "#pse-cells" + +additionalProperties: true + +... diff --git a/dts/Bindings/net/qca,ar803x.yaml b/dts/Bindings/net/qca,ar803x.yaml index b3d4013b7c..161d289193 100644 --- a/dts/Bindings/net/qca,ar803x.yaml +++ b/dts/Bindings/net/qca,ar803x.yaml @@ -40,6 +40,14 @@ properties: Only supported on the AR8031. type: boolean + qca,disable-hibernation-mode: + description: | + Disable Atheros AR803X PHYs hibernation mode. If present, indicates + that the hardware of PHY will not enter power saving mode when the + cable is disconnected. And the RX_CLK always keeps outputting a + valid clock. + type: boolean + qca,smarteee-tw-us-100m: description: EEE Tw parameter for 100M links. $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/dts/Bindings/net/qcom,ipq4019-mdio.yaml b/dts/Bindings/net/qcom,ipq4019-mdio.yaml index 2af3043417..ad8b2b41c1 100644 --- a/dts/Bindings/net/qcom,ipq4019-mdio.yaml +++ b/dts/Bindings/net/qcom,ipq4019-mdio.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/net/qcom,ipq4019-mdio.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm IPQ40xx MDIO Controller Device Tree Bindings +title: Qualcomm IPQ40xx MDIO Controller maintainers: - Robert Marko <robert.marko@sartura.hr> diff --git a/dts/Bindings/net/ralink,rt2880-net.txt b/dts/Bindings/net/ralink,rt2880-net.txt deleted file mode 100644 index 9fe1a0a22e..0000000000 --- a/dts/Bindings/net/ralink,rt2880-net.txt +++ /dev/null @@ -1,59 +0,0 @@ -Ralink Frame Engine Ethernet controller -======================================= - -The Ralink frame engine ethernet controller can be found on Ralink and -Mediatek SoCs (RT288x, RT3x5x, RT366x, RT388x, rt5350, mt7620, mt7621, mt76x8). - -Depending on the SoC, there is a number of ports connected to the CPU port -directly and/or via a (gigabit-)switch. - -* Ethernet controller node - -Required properties: -- compatible: Should be one of "ralink,rt2880-eth", "ralink,rt3050-eth", - "ralink,rt3050-eth", "ralink,rt3883-eth", "ralink,rt5350-eth", - "mediatek,mt7620-eth", "mediatek,mt7621-eth" -- reg: Address and length of the register set for the device -- interrupts: Should contain the frame engines interrupt -- resets: Should contain the frame engines resets -- reset-names: Should contain the reset names "fe". If a switch is present - "esw" is also required. - - -* Ethernet port node - -Required properties: -- compatible: Should be "ralink,eth-port" -- reg: The number of the physical port -- phy-handle: reference to the node describing the phy - -Example: - -mdio-bus { - ... - phy0: ethernet-phy@0 { - phy-mode = "mii"; - reg = <0>; - }; -}; - -ethernet@400000 { - compatible = "ralink,rt2880-eth"; - reg = <0x00400000 10000>; - - #address-cells = <1>; - #size-cells = <0>; - - resets = <&rstctrl 18>; - reset-names = "fe"; - - interrupt-parent = <&cpuintc>; - interrupts = <5>; - - port@0 { - compatible = "ralink,eth-port"; - reg = <0>; - phy-handle = <&phy0>; - }; - -}; diff --git a/dts/Bindings/net/ralink,rt3050-esw.txt b/dts/Bindings/net/ralink,rt3050-esw.txt deleted file mode 100644 index 87e315856e..0000000000 --- a/dts/Bindings/net/ralink,rt3050-esw.txt +++ /dev/null @@ -1,30 +0,0 @@ -Ralink Fast Ethernet Embedded Switch -==================================== - -The ralink fast ethernet embedded switch can be found on Ralink and Mediatek -SoCs (RT3x5x, RT5350, MT76x8). - -Required properties: -- compatible: Should be "ralink,rt3050-esw" -- reg: Address and length of the register set for the device -- interrupts: Should contain the embedded switches interrupt -- resets: Should contain the embedded switches resets -- reset-names: Should contain the reset names "esw" - -Optional properties: -- ralink,portmap: can be used to choose if the default switch setup is - llllw or wllll -- ralink,led_polarity: override the active high/low settings of the leds - -Example: - -esw@10110000 { - compatible = "ralink,rt3050-esw"; - reg = <0x10110000 8000>; - - resets = <&rstctrl 23>; - reset-names = "esw"; - - interrupt-parent = <&intc>; - interrupts = <17>; -}; diff --git a/dts/Bindings/net/realtek-bluetooth.yaml b/dts/Bindings/net/realtek-bluetooth.yaml index 157d606bf9..e329ef06e1 100644 --- a/dts/Bindings/net/realtek-bluetooth.yaml +++ b/dts/Bindings/net/realtek-bluetooth.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/net/realtek-bluetooth.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: RTL8723BS/RTL8723CS/RTL8822CS Bluetooth Device Tree Bindings +title: RTL8723BS/RTL8723CS/RTL8822CS Bluetooth maintainers: - Vasily Khoruzhick <anarsoul@gmail.com> diff --git a/dts/Bindings/net/renesas,etheravb.yaml b/dts/Bindings/net/renesas,etheravb.yaml index acf347f3cd..3f41294f59 100644 --- a/dts/Bindings/net/renesas,etheravb.yaml +++ b/dts/Bindings/net/renesas,etheravb.yaml @@ -40,11 +40,16 @@ properties: - renesas,etheravb-r8a77980 # R-Car V3H - renesas,etheravb-r8a77990 # R-Car E3 - renesas,etheravb-r8a77995 # R-Car D3 - - renesas,etheravb-r8a779a0 # R-Car V3U - const: renesas,etheravb-rcar-gen3 # R-Car Gen3 and RZ/G2 - items: - enum: + - renesas,etheravb-r8a779a0 # R-Car V3U + - renesas,etheravb-r8a779g0 # R-Car V4H + - const: renesas,etheravb-rcar-gen4 # R-Car Gen4 + + - items: + - enum: - renesas,etheravb-r9a09g011 # RZ/V2M - const: renesas,etheravb-rzv2m # RZ/V2M compatible @@ -207,7 +212,7 @@ allOf: - renesas,etheravb-r8a77965 - renesas,etheravb-r8a77970 - renesas,etheravb-r8a77980 - - renesas,etheravb-r8a779a0 + - renesas,etheravb-rcar-gen4 then: required: - tx-internal-delay-ps diff --git a/dts/Bindings/net/rockchip-dwmac.yaml b/dts/Bindings/net/rockchip-dwmac.yaml index 083623c8d7..42fb72b690 100644 --- a/dts/Bindings/net/rockchip-dwmac.yaml +++ b/dts/Bindings/net/rockchip-dwmac.yaml @@ -25,7 +25,9 @@ select: - rockchip,rk3368-gmac - rockchip,rk3399-gmac - rockchip,rk3568-gmac + - rockchip,rk3588-gmac - rockchip,rv1108-gmac + - rockchip,rv1126-gmac required: - compatible @@ -47,9 +49,11 @@ properties: - rockchip,rk3368-gmac - rockchip,rk3399-gmac - rockchip,rv1108-gmac + - rockchip,rv1126-gmac - items: - enum: - rockchip,rk3568-gmac + - rockchip,rk3588-gmac - const: snps,dwmac-4.20a clocks: @@ -81,6 +85,11 @@ properties: description: The phandle of the syscon node for the general register file. $ref: /schemas/types.yaml#/definitions/phandle + rockchip,php-grf: + description: + The phandle of the syscon node for the peripheral general register file. + $ref: /schemas/types.yaml#/definitions/phandle + tx_delay: description: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default. $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/dts/Bindings/net/snps,dwmac.yaml b/dts/Bindings/net/snps,dwmac.yaml index 491597c02e..13b984076a 100644 --- a/dts/Bindings/net/snps,dwmac.yaml +++ b/dts/Bindings/net/snps,dwmac.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/net/snps,dwmac.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Synopsys DesignWare MAC Device Tree Bindings +title: Synopsys DesignWare MAC maintainers: - Alexandre Torgue <alexandre.torgue@foss.st.com> @@ -74,6 +74,7 @@ properties: - rockchip,rk3328-gmac - rockchip,rk3366-gmac - rockchip,rk3368-gmac + - rockchip,rk3588-gmac - rockchip,rk3399-gmac - rockchip,rv1108-gmac - snps,dwmac @@ -288,6 +289,11 @@ properties: is supported. For example, this is used in case of SGMII and MAC2MAC connection. + snps,clk-csr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Frequency division factor for MDC clock. + mdio: $ref: mdio.yaml# unevaluatedProperties: false @@ -301,6 +307,60 @@ properties: required: - compatible + stmmac-axi-config: + type: object + unevaluatedProperties: false + description: + AXI BUS Mode parameters. + + properties: + snps,lpi_en: + $ref: /schemas/types.yaml#/definitions/flag + description: + enable Low Power Interface + + snps,xit_frm: + $ref: /schemas/types.yaml#/definitions/flag + description: + unlock on WoL + + snps,wr_osr_lmt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + max write outstanding req. limit + + snps,rd_osr_lmt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + max read outstanding req. limit + + snps,kbbe: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + do not cross 1KiB boundary. + + snps,blen: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + this is a vector of supported burst length. + minItems: 7 + maxItems: 7 + + snps,fb: + $ref: /schemas/types.yaml#/definitions/flag + description: + fixed-burst + + snps,mb: + $ref: /schemas/types.yaml#/definitions/flag + description: + mixed-burst + + snps,rb: + $ref: /schemas/types.yaml#/definitions/flag + description: + rebuild INCRx Burst + required: - compatible - reg diff --git a/dts/Bindings/net/sunplus,sp7021-emac.yaml b/dts/Bindings/net/sunplus,sp7021-emac.yaml index 62dffee27c..5b13009744 100644 --- a/dts/Bindings/net/sunplus,sp7021-emac.yaml +++ b/dts/Bindings/net/sunplus,sp7021-emac.yaml @@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/net/sunplus,sp7021-emac.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Sunplus SP7021 Dual Ethernet MAC Device Tree Bindings +title: Sunplus SP7021 Dual Ethernet MAC maintainers: - Wells Lu <wellslutw@gmail.com> @@ -32,6 +32,7 @@ properties: ethernet-ports: type: object + additionalProperties: false description: Ethernet ports to PHY properties: @@ -44,6 +45,7 @@ properties: patternProperties: "^port@[0-1]$": type: object + additionalProperties: false description: Port to PHY properties: diff --git a/dts/Bindings/net/ti,cpsw-switch.yaml b/dts/Bindings/net/ti,cpsw-switch.yaml index 31bf825c65..e36c7817be 100644 --- a/dts/Bindings/net/ti,cpsw-switch.yaml +++ b/dts/Bindings/net/ti,cpsw-switch.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: TI SoC Ethernet Switch Controller (CPSW) Device Tree Bindings +title: TI SoC Ethernet Switch Controller (CPSW) maintainers: - Grygorii Strashko <grygorii.strashko@ti.com> @@ -77,6 +77,8 @@ properties: ethernet-ports: type: object + additionalProperties: false + properties: '#address-cells': const: 1 @@ -89,6 +91,7 @@ properties: description: CPSW external ports $ref: ethernet-controller.yaml# + unevaluatedProperties: false properties: reg: @@ -117,6 +120,7 @@ properties: cpts: type: object + unevaluatedProperties: false description: The Common Platform Time Sync (CPTS) module diff --git a/dts/Bindings/net/ti,k3-am654-cpsw-nuss.yaml b/dts/Bindings/net/ti,k3-am654-cpsw-nuss.yaml index b8281d8be9..821974815d 100644 --- a/dts/Bindings/net/ti,k3-am654-cpsw-nuss.yaml +++ b/dts/Bindings/net/ti,k3-am654-cpsw-nuss.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller) Device Tree Bindings +title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller) maintainers: - Grygorii Strashko <grygorii.strashko@ti.com> @@ -55,6 +55,7 @@ properties: compatible: enum: - ti,am654-cpsw-nuss + - ti,j7200-cpswxg-nuss - ti,j721e-cpsw-nuss - ti,am642-cpsw-nuss @@ -110,16 +111,17 @@ properties: const: 0 patternProperties: - port@[1-2]: + "^port@[1-4]$": type: object description: CPSWxG NUSS external ports $ref: ethernet-controller.yaml# + unevaluatedProperties: false properties: reg: minimum: 1 - maximum: 2 + maximum: 4 description: CPSW port number phys: @@ -178,6 +180,19 @@ required: - '#address-cells' - '#size-cells' +allOf: + - if: + not: + properties: + compatible: + contains: + const: ti,j7200-cpswxg-nuss + then: + properties: + ethernet-ports: + patternProperties: + "^port@[3-4]$": false + additionalProperties: false examples: diff --git a/dts/Bindings/net/ti,k3-am654-cpts.yaml b/dts/Bindings/net/ti,k3-am654-cpts.yaml index b783ad0d1f..6230f57613 100644 --- a/dts/Bindings/net/ti,k3-am654-cpts.yaml +++ b/dts/Bindings/net/ti,k3-am654-cpts.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/net/ti,k3-am654-cpts.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: The TI AM654x/J721E Common Platform Time Sync (CPTS) module Device Tree Bindings +title: The TI AM654x/J721E Common Platform Time Sync (CPTS) module maintainers: - Grygorii Strashko <grygorii.strashko@ti.com> @@ -95,6 +95,7 @@ properties: refclk-mux: type: object + additionalProperties: false description: CPTS reference clock multiplexer clock properties: '#clock-cells': diff --git a/dts/Bindings/net/vertexcom-mse102x.yaml b/dts/Bindings/net/vertexcom-mse102x.yaml index 8156a9aeb5..6a71f694cb 100644 --- a/dts/Bindings/net/vertexcom-mse102x.yaml +++ b/dts/Bindings/net/vertexcom-mse102x.yaml @@ -4,10 +4,10 @@ $id: "http://devicetree.org/schemas/net/vertexcom-mse102x.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: The Vertexcom MSE102x (SPI) Device Tree Bindings +title: The Vertexcom MSE102x (SPI) maintainers: - - Stefan Wahren <stefan.wahren@in-tech.com> + - Stefan Wahren <stefan.wahren@chargebyte.com> description: Vertexcom's MSE102x are a family of HomePlug GreenPHY chips. diff --git a/dts/Bindings/net/wireless/brcm,bcm4329-fmac.yaml b/dts/Bindings/net/wireless/brcm,bcm4329-fmac.yaml index 53b4153d9b..fec1cc9b9a 100644 --- a/dts/Bindings/net/wireless/brcm,bcm4329-fmac.yaml +++ b/dts/Bindings/net/wireless/brcm,bcm4329-fmac.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/net/wireless/brcm,bcm4329-fmac.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Broadcom BCM4329 family fullmac wireless SDIO devices +title: Broadcom BCM4329 family fullmac wireless SDIO/PCIE devices maintainers: - Arend van Spriel <arend@broadcom.com> @@ -41,11 +41,17 @@ properties: - cypress,cyw4373-fmac - cypress,cyw43012-fmac - const: brcm,bcm4329-fmac - - const: brcm,bcm4329-fmac + - enum: + - brcm,bcm4329-fmac + - pci14e4,43dc # BCM4355 + - pci14e4,4464 # BCM4364 + - pci14e4,4488 # BCM4377 + - pci14e4,4425 # BCM4378 + - pci14e4,4433 # BCM4387 reg: - description: SDIO function number for the device, for most cases - this will be 1. + description: SDIO function number for the device (for most cases + this will be 1) or PCI device identifier. interrupts: maxItems: 1 @@ -85,6 +91,31 @@ properties: takes precedence. type: boolean + brcm,cal-blob: + $ref: /schemas/types.yaml#/definitions/uint8-array + description: A per-device calibration blob for the Wi-Fi radio. This + should be filled in by the bootloader from platform configuration + data, if necessary, and will be uploaded to the device if present. + + brcm,board-type: + $ref: /schemas/types.yaml#/definitions/string + description: Overrides the board type, which is normally the compatible of + the root node. This can be used to decouple the overall system board or + device name from the board type for WiFi purposes, which is used to + construct firmware and NVRAM configuration filenames, allowing for + multiple devices that share the same module or characteristics for the + WiFi subsystem to share the same firmware/NVRAM files. On Apple platforms, + this should be the Apple module-instance codename prefixed by "apple,", + e.g. "apple,honshu". + + apple,antenna-sku: + $ref: /schemas/types.yaml#/definitions/string + description: Antenna SKU used to identify a specific antenna configuration + on Apple platforms. This is use to build firmware filenames, to allow + platforms with different antenna configs to have different firmware and/or + NVRAM. This would normally be filled in by the bootloader from platform + configuration data. + required: - compatible - reg diff --git a/dts/Bindings/net/wireless/microchip,wilc1000.yaml b/dts/Bindings/net/wireless/microchip,wilc1000.yaml index 60de78f1bc..b3405f2845 100644 --- a/dts/Bindings/net/wireless/microchip,wilc1000.yaml +++ b/dts/Bindings/net/wireless/microchip,wilc1000.yaml @@ -20,8 +20,6 @@ properties: reg: true - spi-max-frequency: true - interrupts: maxItems: 1 @@ -51,7 +49,10 @@ required: - compatible - interrupts -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/net/wireless/qcom,ath11k.yaml b/dts/Bindings/net/wireless/qcom,ath11k.yaml index a677b056f1..f7cf135aa3 100644 --- a/dts/Bindings/net/wireless/qcom,ath11k.yaml +++ b/dts/Bindings/net/wireless/qcom,ath11k.yaml @@ -66,6 +66,18 @@ properties: required: - iommus + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: State bits used by the AP to signal the WLAN Q6. + items: + - description: Signal bits used to enable/disable low power mode + on WCN6750 in the case of WoW (Wake on Wireless). + + qcom,smem-state-names: + description: The names of the state bits used for SMP2P output. + items: + - const: wlan-smp2p-out + required: - compatible - reg @@ -448,6 +460,8 @@ examples: <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; qcom,rproc = <&remoteproc_wpss>; memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; + qcom,smem-states = <&wlan_smp2p_out 0>; + qcom,smem-state-names = "wlan-smp2p-out"; wifi-firmware { iommus = <&apps_smmu 0x1c02 0x1>; }; diff --git a/dts/Bindings/net/wireless/silabs,wfx.yaml b/dts/Bindings/net/wireless/silabs,wfx.yaml index 76199a67d6..b35d2f3ad1 100644 --- a/dts/Bindings/net/wireless/silabs,wfx.yaml +++ b/dts/Bindings/net/wireless/silabs,wfx.yaml @@ -29,12 +29,6 @@ description: > Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.yaml for more information. - For SPI: - - In add of the properties below, please consult - Documentation/devicetree/bindings/spi/spi-controller.yaml for optional SPI - related properties. - properties: compatible: items: @@ -52,8 +46,6 @@ properties: bindings. maxItems: 1 - spi-max-frequency: true - interrupts: description: The interrupt line. Should be IRQ_TYPE_EDGE_RISING. When SPI is used, this property is required. When SDIO is used, the "in-band" @@ -84,12 +76,15 @@ properties: mac-address: true -additionalProperties: false - required: - compatible - reg +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + examples: - | #include <dt-bindings/gpio/gpio.h> diff --git a/dts/Bindings/net/wireless/ti,wlcore.yaml b/dts/Bindings/net/wireless/ti,wlcore.yaml index d68bb2ec1f..e31456730e 100644 --- a/dts/Bindings/net/wireless/ti,wlcore.yaml +++ b/dts/Bindings/net/wireless/ti,wlcore.yaml @@ -36,8 +36,6 @@ properties: This is required when connected via SPI, and optional when connected via SDIO. - spi-max-frequency: true - interrupts: minItems: 1 maxItems: 2 @@ -69,20 +67,22 @@ required: - compatible - interrupts -if: - properties: - compatible: - contains: - enum: - - ti,wl1271 - - ti,wl1273 - - ti,wl1281 - - ti,wl1283 -then: - required: - - ref-clock-frequency - -additionalProperties: false +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + - if: + properties: + compatible: + contains: + enum: + - ti,wl1271 + - ti,wl1273 + - ti,wl1281 + - ti,wl1283 + then: + required: + - ref-clock-frequency + +unevaluatedProperties: false examples: - | diff --git a/dts/Bindings/nvmem/allwinner,sun4i-a10-sid.yaml b/dts/Bindings/nvmem/allwinner,sun4i-a10-sid.yaml index e558587ff8..14c170c6a8 100644 --- a/dts/Bindings/nvmem/allwinner,sun4i-a10-sid.yaml +++ b/dts/Bindings/nvmem/allwinner,sun4i-a10-sid.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/nvmem/allwinner,sun4i-a10-sid.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Security ID Device Tree Bindings +title: Allwinner A10 Security ID maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/nvmem/imx-iim.yaml b/dts/Bindings/nvmem/imx-iim.yaml index 9cc43e7a4b..7aac1995cf 100644 --- a/dts/Bindings/nvmem/imx-iim.yaml +++ b/dts/Bindings/nvmem/imx-iim.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/nvmem/imx-iim.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Freescale i.MX IC Identification Module (IIM) device tree bindings +title: Freescale i.MX IC Identification Module (IIM) maintainers: - Anson Huang <Anson.Huang@nxp.com> diff --git a/dts/Bindings/nvmem/imx-ocotp.yaml b/dts/Bindings/nvmem/imx-ocotp.yaml index 8a43dc1283..d0a239d7e1 100644 --- a/dts/Bindings/nvmem/imx-ocotp.yaml +++ b/dts/Bindings/nvmem/imx-ocotp.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings +title: Freescale i.MX6 On-Chip OTP Controller (OCOTP) maintainers: - Anson Huang <Anson.Huang@nxp.com> diff --git a/dts/Bindings/nvmem/mediatek,efuse.yaml b/dts/Bindings/nvmem/mediatek,efuse.yaml index b5a1109f2e..75e0a516e5 100644 --- a/dts/Bindings/nvmem/mediatek,efuse.yaml +++ b/dts/Bindings/nvmem/mediatek,efuse.yaml @@ -30,6 +30,7 @@ properties: - mediatek,mt8173-efuse - mediatek,mt8183-efuse - mediatek,mt8186-efuse + - mediatek,mt8188-efuse - mediatek,mt8192-efuse - mediatek,mt8195-efuse - mediatek,mt8516-efuse diff --git a/dts/Bindings/nvmem/microchip,lan9662-otpc.yaml b/dts/Bindings/nvmem/microchip,lan9662-otpc.yaml new file mode 100644 index 0000000000..f97c6beb47 --- /dev/null +++ b/dts/Bindings/nvmem/microchip,lan9662-otpc.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/microchip,lan9662-otpc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip LAN9662 OTP Controller (OTPC) + +maintainers: + - Horatiu Vultur <horatiu.vultur@microchip.com> + +description: | + OTP controller drives a NVMEM memory where system specific data + (e.g. hardware configuration settings, chip identifiers) or + user specific data could be stored. + +allOf: + - $ref: nvmem.yaml# + +properties: + compatible: + oneOf: + - items: + - const: microchip,lan9668-otpc + - const: microchip,lan9662-otpc + - enum: + - microchip,lan9662-otpc + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + otpc: otp@e0021000 { + compatible = "microchip,lan9662-otpc"; + reg = <0xe0021000 0x300>; + }; + +... diff --git a/dts/Bindings/nvmem/nintendo-otp.yaml b/dts/Bindings/nvmem/nintendo-otp.yaml index dbe4ffdd64..f93bc50c40 100644 --- a/dts/Bindings/nvmem/nintendo-otp.yaml +++ b/dts/Bindings/nvmem/nintendo-otp.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/nvmem/nintendo-otp.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Nintendo Wii and Wii U OTP Device Tree Bindings +title: Nintendo Wii and Wii U OTP description: | This binding represents the OTP memory as found on a Nintendo Wii or Wii U, diff --git a/dts/Bindings/nvmem/nvmem-consumer.yaml b/dts/Bindings/nvmem/nvmem-consumer.yaml index b1da238c8b..a26633bf52 100644 --- a/dts/Bindings/nvmem/nvmem-consumer.yaml +++ b/dts/Bindings/nvmem/nvmem-consumer.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/nvmem/nvmem-consumer.yaml# $schema: http://devicetree.org/meta-schemas/base.yaml# -title: NVMEM (Non Volatile Memory) Consumer Device Tree Bindings +title: NVMEM (Non Volatile Memory) Consumer maintainers: - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> diff --git a/dts/Bindings/nvmem/nvmem.yaml b/dts/Bindings/nvmem/nvmem.yaml index 3bb349c634..1eb22dba36 100644 --- a/dts/Bindings/nvmem/nvmem.yaml +++ b/dts/Bindings/nvmem/nvmem.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/nvmem/nvmem.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: NVMEM (Non Volatile Memory) Device Tree Bindings +title: NVMEM (Non Volatile Memory) maintainers: - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> diff --git a/dts/Bindings/nvmem/qcom,qfprom.yaml b/dts/Bindings/nvmem/qcom,qfprom.yaml index dede8892ee..2eab2f46cb 100644 --- a/dts/Bindings/nvmem/qcom,qfprom.yaml +++ b/dts/Bindings/nvmem/qcom,qfprom.yaml @@ -18,6 +18,7 @@ properties: - enum: - qcom,apq8064-qfprom - qcom,apq8084-qfprom + - qcom,ipq8064-qfprom - qcom,msm8974-qfprom - qcom,msm8916-qfprom - qcom,msm8996-qfprom @@ -25,7 +26,9 @@ properties: - qcom,qcs404-qfprom - qcom,sc7180-qfprom - qcom,sc7280-qfprom + - qcom,sdm630-qfprom - qcom,sdm845-qfprom + - qcom,sm6115-qfprom - const: qcom,qfprom reg: diff --git a/dts/Bindings/nvmem/rockchip-efuse.yaml b/dts/Bindings/nvmem/rockchip-efuse.yaml index 104dd50856..febee8129a 100644 --- a/dts/Bindings/nvmem/rockchip-efuse.yaml +++ b/dts/Bindings/nvmem/rockchip-efuse.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/nvmem/rockchip-efuse.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Rockchip eFuse device tree bindings +title: Rockchip eFuse maintainers: - Heiko Stuebner <heiko@sntech.de> diff --git a/dts/Bindings/nvmem/u-boot,env.yaml b/dts/Bindings/nvmem/u-boot,env.yaml index e70b2a60cb..e96bca99f2 100644 --- a/dts/Bindings/nvmem/u-boot,env.yaml +++ b/dts/Bindings/nvmem/u-boot,env.yaml @@ -24,6 +24,8 @@ description: | Right now only flash partition case is covered but it may be extended to e.g. UBI volumes in the future. + Variables can be defined as NVMEM device subnodes. + maintainers: - Rafał Miłecki <rafal@milecki.pl> @@ -40,6 +42,14 @@ properties: reg: maxItems: 1 + bootcmd: + type: object + description: Command to use for automatic booting + + ethaddr: + type: object + description: Ethernet interface's MAC address + additionalProperties: false examples: @@ -58,5 +68,8 @@ examples: env: partition@40000 { compatible = "u-boot,env"; reg = <0x40000 0x10000>; + + mac: ethaddr { + }; }; }; diff --git a/dts/Bindings/opp/allwinner,sun50i-h6-operating-points.yaml b/dts/Bindings/opp/allwinner,sun50i-h6-operating-points.yaml index 729ae97b63..385b069226 100644 --- a/dts/Bindings/opp/allwinner,sun50i-h6-operating-points.yaml +++ b/dts/Bindings/opp/allwinner,sun50i-h6-operating-points.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner H6 CPU OPP Device Tree Bindings +title: Allwinner H6 CPU OPP maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/pci/brcm,stb-pcie.yaml b/dts/Bindings/pci/brcm,stb-pcie.yaml index 0f064e4222..7e15aae7d6 100644 --- a/dts/Bindings/pci/brcm,stb-pcie.yaml +++ b/dts/Bindings/pci/brcm,stb-pcie.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Brcmstb PCIe Host Controller Device Tree Bindings +title: Brcmstb PCIe Host Controller maintainers: - Nicolas Saenz Julienne <nsaenzjulienne@suse.de> diff --git a/dts/Bindings/pci/mediatek-pcie-gen3.yaml b/dts/Bindings/pci/mediatek-pcie-gen3.yaml index 0499b94627..c00be39af6 100644 --- a/dts/Bindings/pci/mediatek-pcie-gen3.yaml +++ b/dts/Bindings/pci/mediatek-pcie-gen3.yaml @@ -48,7 +48,13 @@ allOf: properties: compatible: - const: mediatek,mt8192-pcie + oneOf: + - items: + - enum: + - mediatek,mt8188-pcie + - mediatek,mt8195-pcie + - const: mediatek,mt8192-pcie + - const: mediatek,mt8192-pcie reg: maxItems: 1 @@ -84,7 +90,9 @@ properties: - const: tl_96m - const: tl_32k - const: peri_26m - - const: top_133m + - enum: + - top_133m # for MT8192 + - peri_mem # for MT8188/MT8195 assigned-clocks: maxItems: 1 @@ -126,6 +134,7 @@ required: - interrupts - ranges - clocks + - clock-names - '#interrupt-cells' - interrupt-controller diff --git a/dts/Bindings/pci/microchip,pcie-host.yaml b/dts/Bindings/pci/microchip,pcie-host.yaml index edb4f81253..f7a3c26363 100644 --- a/dts/Bindings/pci/microchip,pcie-host.yaml +++ b/dts/Bindings/pci/microchip,pcie-host.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Microchip PCIe Root Port Bridge Controller Device Tree Bindings +title: Microchip PCIe Root Port Bridge Controller maintainers: - Daire McNamara <daire.mcnamara@microchip.com> @@ -25,6 +25,33 @@ properties: - const: cfg - const: apb + clocks: + description: + Fabric Interface Controllers, FICs, are the interface between the FPGA + fabric and the core complex on PolarFire SoC. The FICs require two clocks, + one from each side of the interface. The "FIC clocks" described by this + property are on the core complex side & communication through a FIC is not + possible unless it's corresponding clock is enabled. A clock must be + enabled for each of the interfaces the root port is connected through. + This could in theory be all 4 interfaces, one interface or any combination + in between. + minItems: 1 + items: + - description: FIC0's clock + - description: FIC1's clock + - description: FIC2's clock + - description: FIC3's clock + + clock-names: + description: + As any FIC connection combination is possible, the names should match the + order in the clocks property and take the form "ficN" where N is a number + 0-3 + minItems: 1 + maxItems: 4 + items: + pattern: '^fic[0-3]$' + interrupts: minItems: 1 items: @@ -40,6 +67,10 @@ properties: ranges: maxItems: 1 + dma-ranges: + minItems: 1 + maxItems: 6 + msi-controller: description: Identifies the node as an MSI controller. diff --git a/dts/Bindings/pci/qcom,pcie-ep.yaml b/dts/Bindings/pci/qcom,pcie-ep.yaml index 3d23599e5e..977c976ea7 100644 --- a/dts/Bindings/pci/qcom,pcie-ep.yaml +++ b/dts/Bindings/pci/qcom,pcie-ep.yaml @@ -9,12 +9,11 @@ title: Qualcomm PCIe Endpoint Controller binding maintainers: - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> -allOf: - - $ref: "pci-ep.yaml#" - properties: compatible: - const: qcom,sdx55-pcie-ep + enum: + - qcom,sdx55-pcie-ep + - qcom,sm8450-pcie-ep reg: items: @@ -35,24 +34,12 @@ properties: - const: mmio clocks: - items: - - description: PCIe Auxiliary clock - - description: PCIe CFG AHB clock - - description: PCIe Master AXI clock - - description: PCIe Slave AXI clock - - description: PCIe Slave Q2A AXI clock - - description: PCIe Sleep clock - - description: PCIe Reference clock + minItems: 7 + maxItems: 8 clock-names: - items: - - const: aux - - const: cfg - - const: bus_master - - const: bus_slave - - const: slave_q2a - - const: sleep - - const: ref + minItems: 7 + maxItems: 8 qcom,perst-regs: description: Reference to a syscon representing TCSR followed by the two @@ -105,7 +92,6 @@ required: - reg-names - clocks - clock-names - - qcom,perst-regs - interrupts - interrupt-names - reset-gpios @@ -113,6 +99,64 @@ required: - reset-names - power-domains +allOf: + - $ref: pci-ep.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sdx55-pcie-ep + then: + properties: + clocks: + items: + - description: PCIe Auxiliary clock + - description: PCIe CFG AHB clock + - description: PCIe Master AXI clock + - description: PCIe Slave AXI clock + - description: PCIe Slave Q2A AXI clock + - description: PCIe Sleep clock + - description: PCIe Reference clock + clock-names: + items: + - const: aux + - const: cfg + - const: bus_master + - const: bus_slave + - const: slave_q2a + - const: sleep + - const: ref + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8450-pcie-ep + then: + properties: + clocks: + items: + - description: PCIe Auxiliary clock + - description: PCIe CFG AHB clock + - description: PCIe Master AXI clock + - description: PCIe Slave AXI clock + - description: PCIe Slave Q2A AXI clock + - description: PCIe Reference clock + - description: PCIe DDRSS SF TBU clock + - description: PCIe AGGRE NOC AXI clock + clock-names: + items: + - const: aux + - const: cfg + - const: bus_master + - const: bus_slave + - const: slave_q2a + - const: ref + - const: ddrss_sf_tbu + - const: aggre_noc_axi + unevaluatedProperties: false examples: diff --git a/dts/Bindings/pci/qcom,pcie.yaml b/dts/Bindings/pci/qcom,pcie.yaml index 7d29e2a451..54f07852d2 100644 --- a/dts/Bindings/pci/qcom,pcie.yaml +++ b/dts/Bindings/pci/qcom,pcie.yaml @@ -25,8 +25,10 @@ properties: - qcom,pcie-ipq4019 - qcom,pcie-ipq8074 - qcom,pcie-qcs404 + - qcom,pcie-sa8540p - qcom,pcie-sc7280 - qcom,pcie-sc8180x + - qcom,pcie-sc8280xp - qcom,pcie-sdm845 - qcom,pcie-sm8150 - qcom,pcie-sm8250 @@ -54,11 +56,11 @@ properties: # Platform constraints are described later. clocks: minItems: 3 - maxItems: 12 + maxItems: 13 clock-names: minItems: 3 - maxItems: 12 + maxItems: 13 resets: minItems: 1 @@ -181,6 +183,7 @@ allOf: enum: - qcom,pcie-sc7280 - qcom,pcie-sc8180x + - qcom,pcie-sc8280xp - qcom,pcie-sm8250 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 @@ -424,8 +427,8 @@ allOf: then: properties: clocks: - minItems: 11 - maxItems: 11 + minItems: 13 + maxItems: 13 clock-names: items: - const: pipe # PIPE clock @@ -439,6 +442,8 @@ allOf: - const: slave_q2a # Slave Q2A clock - const: tbu # PCIe TBU clock - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock resets: maxItems: 1 reset-names: @@ -597,6 +602,36 @@ allOf: - const: pci # PCIe core reset - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sa8540p + - qcom,pcie-sc8280xp + then: + properties: + clocks: + minItems: 8 + maxItems: 9 + clock-names: + minItems: 8 + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: noc_aggr_4 # NoC aggregate 4 clock + - const: noc_aggr_south_sf # NoC aggregate South SF clock + - const: cnoc_qx # Configuration NoC QX clock + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + + - if: not: properties: compatible: @@ -624,8 +659,6 @@ allOf: - resets - reset-names - # Newer chipsets support either 1 or 8 MSI vectors - # On older chipsets it's always 1 MSI vector - if: properties: compatible: @@ -660,7 +693,40 @@ allOf: - const: msi5 - const: msi6 - const: msi7 - else: + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sc8280xp + then: + properties: + interrupts: + minItems: 4 + maxItems: 4 + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-apq8064 + - qcom,pcie-apq8084 + - qcom,pcie-ipq4019 + - qcom,pcie-ipq6018 + - qcom,pcie-ipq8064 + - qcom,pcie-ipq8064-v2 + - qcom,pcie-ipq8074 + - qcom,pcie-qcs404 + - qcom,pcie-sa8540p + then: properties: interrupts: maxItems: 1 diff --git a/dts/Bindings/pci/samsung,exynos-pcie.yaml b/dts/Bindings/pci/samsung,exynos-pcie.yaml index 445eed94b5..f20ed7e709 100644 --- a/dts/Bindings/pci/samsung,exynos-pcie.yaml +++ b/dts/Bindings/pci/samsung,exynos-pcie.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Samsung SoC series PCIe Host Controller Device Tree Bindings +title: Samsung SoC series PCIe Host Controller maintainers: - Marek Szyprowski <m.szyprowski@samsung.com> diff --git a/dts/Bindings/pci/sifive,fu740-pcie.yaml b/dts/Bindings/pci/sifive,fu740-pcie.yaml index 195e6afeb1..844fc71423 100644 --- a/dts/Bindings/pci/sifive,fu740-pcie.yaml +++ b/dts/Bindings/pci/sifive,fu740-pcie.yaml @@ -51,6 +51,12 @@ properties: description: A phandle to the PCIe power up reset line. maxItems: 1 + clocks: + maxItems: 1 + + clock-names: + const: pcie_aux + pwren-gpios: description: Should specify the GPIO for controlling the PCI bus device power on. maxItems: 1 @@ -66,6 +72,7 @@ required: - interrupt-map-mask - interrupt-map - clocks + - clock-names - resets - pwren-gpios - reset-gpios @@ -104,6 +111,7 @@ examples: <0x0 0x0 0x0 0x2 &plic0 58>, <0x0 0x0 0x0 0x3 &plic0 59>, <0x0 0x0 0x0 0x4 &plic0 60>; + clock-names = "pcie_aux"; clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>; resets = <&prci 4>; pwren-gpios = <&gpio 5 0>; diff --git a/dts/Bindings/pci/toshiba,visconti-pcie.yaml b/dts/Bindings/pci/toshiba,visconti-pcie.yaml index 30b6396d83..48ed227fc5 100644 --- a/dts/Bindings/pci/toshiba,visconti-pcie.yaml +++ b/dts/Bindings/pci/toshiba,visconti-pcie.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pci/toshiba,visconti-pcie.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Toshiba Visconti5 SoC PCIe Host Controller Device Tree Bindings +title: Toshiba Visconti5 SoC PCIe Host Controller maintainers: - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> diff --git a/dts/Bindings/peci/peci-aspeed.yaml b/dts/Bindings/peci/peci-aspeed.yaml index 1e68a801a9..b01e0c8b96 100644 --- a/dts/Bindings/peci/peci-aspeed.yaml +++ b/dts/Bindings/peci/peci-aspeed.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/peci/peci-aspeed.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Aspeed PECI Bus Device Tree Bindings +title: Aspeed PECI Bus maintainers: - Iwona Winiarska <iwona.winiarska@intel.com> diff --git a/dts/Bindings/peci/peci-controller.yaml b/dts/Bindings/peci/peci-controller.yaml index bbc3d3f3a9..d7853291b0 100644 --- a/dts/Bindings/peci/peci-controller.yaml +++ b/dts/Bindings/peci/peci-controller.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/peci/peci-controller.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Generic Device Tree Bindings for PECI +title: Generic for PECI maintainers: - Iwona Winiarska <iwona.winiarska@intel.com> diff --git a/dts/Bindings/phy/allwinner,sun4i-a10-usb-phy.yaml b/dts/Bindings/phy/allwinner,sun4i-a10-usb-phy.yaml index 77606c899f..4fff091bd5 100644 --- a/dts/Bindings/phy/allwinner,sun4i-a10-usb-phy.yaml +++ b/dts/Bindings/phy/allwinner,sun4i-a10-usb-phy.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/phy/allwinner,sun4i-a10-usb-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 USB PHY Device Tree Bindings +title: Allwinner A10 USB PHY maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/phy/allwinner,sun50i-a64-usb-phy.yaml b/dts/Bindings/phy/allwinner,sun50i-a64-usb-phy.yaml index 0fa4b32b09..f557feca97 100644 --- a/dts/Bindings/phy/allwinner,sun50i-a64-usb-phy.yaml +++ b/dts/Bindings/phy/allwinner,sun50i-a64-usb-phy.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A64 USB PHY Device Tree Bindings +title: Allwinner A64 USB PHY maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/phy/allwinner,sun50i-h6-usb-phy.yaml b/dts/Bindings/phy/allwinner,sun50i-h6-usb-phy.yaml index e632140722..4480fdedd6 100644 --- a/dts/Bindings/phy/allwinner,sun50i-h6-usb-phy.yaml +++ b/dts/Bindings/phy/allwinner,sun50i-h6-usb-phy.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/phy/allwinner,sun50i-h6-usb-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner H6 USB PHY Device Tree Bindings +title: Allwinner H6 USB PHY maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/phy/allwinner,sun5i-a13-usb-phy.yaml b/dts/Bindings/phy/allwinner,sun5i-a13-usb-phy.yaml index 5bad9b06e2..1563e3df30 100644 --- a/dts/Bindings/phy/allwinner,sun5i-a13-usb-phy.yaml +++ b/dts/Bindings/phy/allwinner,sun5i-a13-usb-phy.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/phy/allwinner,sun5i-a13-usb-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A13 USB PHY Device Tree Bindings +title: Allwinner A13 USB PHY maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/dts/Bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml index 22636c9fda..dfb6a89935 100644 --- a/dts/Bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml +++ b/dts/Bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A31 MIPI D-PHY Controller Device Tree Bindings +title: Allwinner A31 MIPI D-PHY Controller maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/phy/allwinner,sun6i-a31-usb-phy.yaml b/dts/Bindings/phy/allwinner,sun6i-a31-usb-phy.yaml index 922b4665e0..4897a3d2fb 100644 --- a/dts/Bindings/phy/allwinner,sun6i-a31-usb-phy.yaml +++ b/dts/Bindings/phy/allwinner,sun6i-a31-usb-phy.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-usb-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A31 USB PHY Device Tree Bindings +title: Allwinner A31 USB PHY maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/phy/allwinner,sun8i-a23-usb-phy.yaml b/dts/Bindings/phy/allwinner,sun8i-a23-usb-phy.yaml index a94019efc2..99de9c6889 100644 --- a/dts/Bindings/phy/allwinner,sun8i-a23-usb-phy.yaml +++ b/dts/Bindings/phy/allwinner,sun8i-a23-usb-phy.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/phy/allwinner,sun8i-a23-usb-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A23 USB PHY Device Tree Bindings +title: Allwinner A23 USB PHY maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/phy/allwinner,sun8i-a83t-usb-phy.yaml b/dts/Bindings/phy/allwinner,sun8i-a83t-usb-phy.yaml index 33f3ddc049..73438d84de 100644 --- a/dts/Bindings/phy/allwinner,sun8i-a83t-usb-phy.yaml +++ b/dts/Bindings/phy/allwinner,sun8i-a83t-usb-phy.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/phy/allwinner,sun8i-a83t-usb-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A83t USB PHY Device Tree Bindings +title: Allwinner A83t USB PHY maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/phy/allwinner,sun8i-h3-usb-phy.yaml b/dts/Bindings/phy/allwinner,sun8i-h3-usb-phy.yaml index e288450e08..77539b4601 100644 --- a/dts/Bindings/phy/allwinner,sun8i-h3-usb-phy.yaml +++ b/dts/Bindings/phy/allwinner,sun8i-h3-usb-phy.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/phy/allwinner,sun8i-h3-usb-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner H3 USB PHY Device Tree Bindings +title: Allwinner H3 USB PHY maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/phy/allwinner,sun8i-r40-usb-phy.yaml b/dts/Bindings/phy/allwinner,sun8i-r40-usb-phy.yaml index d947e50a49..2dd31630c1 100644 --- a/dts/Bindings/phy/allwinner,sun8i-r40-usb-phy.yaml +++ b/dts/Bindings/phy/allwinner,sun8i-r40-usb-phy.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/phy/allwinner,sun8i-r40-usb-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner R40 USB PHY Device Tree Bindings +title: Allwinner R40 USB PHY maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/phy/allwinner,sun8i-v3s-usb-phy.yaml b/dts/Bindings/phy/allwinner,sun8i-v3s-usb-phy.yaml index a2836c296c..395d33855d 100644 --- a/dts/Bindings/phy/allwinner,sun8i-v3s-usb-phy.yaml +++ b/dts/Bindings/phy/allwinner,sun8i-v3s-usb-phy.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/phy/allwinner,sun8i-v3s-usb-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner V3s USB PHY Device Tree Bindings +title: Allwinner V3s USB PHY maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/phy/allwinner,sun9i-a80-usb-phy.yaml b/dts/Bindings/phy/allwinner,sun9i-a80-usb-phy.yaml index 2eb493fa64..bd9445f6f1 100644 --- a/dts/Bindings/phy/allwinner,sun9i-a80-usb-phy.yaml +++ b/dts/Bindings/phy/allwinner,sun9i-a80-usb-phy.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/phy/allwinner,sun9i-a80-usb-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A80 USB PHY Device Tree Bindings +title: Allwinner A80 USB PHY maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/phy/brcm,cygnus-pcie-phy.yaml b/dts/Bindings/phy/brcm,cygnus-pcie-phy.yaml index 045699c657..808e90b246 100644 --- a/dts/Bindings/phy/brcm,cygnus-pcie-phy.yaml +++ b/dts/Bindings/phy/brcm,cygnus-pcie-phy.yaml @@ -32,6 +32,7 @@ properties: patternProperties: "^pcie-phy@[0-9]+$": type: object + additionalProperties: false description: > PCIe PHY child nodes diff --git a/dts/Bindings/phy/cdns,dphy-rx.yaml b/dts/Bindings/phy/cdns,dphy-rx.yaml index 07be031d82..6fdd46ad5a 100644 --- a/dts/Bindings/phy/cdns,dphy-rx.yaml +++ b/dts/Bindings/phy/cdns,dphy-rx.yaml @@ -4,10 +4,10 @@ $id: http://devicetree.org/schemas/phy/cdns,dphy-rx.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Cadence DPHY Rx Device Tree Bindings +title: Cadence DPHY Rx maintainers: - - Pratyush Yadav <p.yadav@ti.com> + - Pratyush Yadav <pratyush@kernel.org> properties: compatible: diff --git a/dts/Bindings/phy/cdns,dphy.yaml b/dts/Bindings/phy/cdns,dphy.yaml index f0e9ca8427..6cd9b0f388 100644 --- a/dts/Bindings/phy/cdns,dphy.yaml +++ b/dts/Bindings/phy/cdns,dphy.yaml @@ -4,10 +4,10 @@ $id: http://devicetree.org/schemas/phy/cdns,dphy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Cadence DPHY Device Tree Bindings +title: Cadence DPHY maintainers: - - Pratyush Yadav <p.yadav@ti.com> + - Pratyush Yadav <pratyush@kernel.org> properties: compatible: diff --git a/dts/Bindings/phy/fsl,imx8-pcie-phy.yaml b/dts/Bindings/phy/fsl,imx8-pcie-phy.yaml index b6421eedec..0af765ba27 100644 --- a/dts/Bindings/phy/fsl,imx8-pcie-phy.yaml +++ b/dts/Bindings/phy/fsl,imx8-pcie-phy.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Freescale i.MX8 SoC series PCIe PHY Device Tree Bindings +title: Freescale i.MX8 SoC series PCIe PHY maintainers: - Richard Zhu <hongxing.zhu@nxp.com> diff --git a/dts/Bindings/phy/hisilicon,hi3660-usb3.yaml b/dts/Bindings/phy/hisilicon,hi3660-usb3.yaml index c2e073e261..20b79e2e8b 100644 --- a/dts/Bindings/phy/hisilicon,hi3660-usb3.yaml +++ b/dts/Bindings/phy/hisilicon,hi3660-usb3.yaml @@ -41,20 +41,10 @@ additionalProperties: false examples: - | - bus { - #address-cells = <2>; - #size-cells = <2>; - - usb3_otg_bc: usb3_otg_bc@ff200000 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0xff200000 0x0 0x1000>; - - usb-phy { - compatible = "hisilicon,hi3660-usb-phy"; - #phy-cells = <0>; - hisilicon,pericrg-syscon = <&crg_ctrl>; - hisilicon,pctrl-syscon = <&pctrl>; - hisilicon,eye-diagram-param = <0x22466e4>; - }; - }; + usb-phy { + compatible = "hisilicon,hi3660-usb-phy"; + #phy-cells = <0>; + hisilicon,pericrg-syscon = <&crg_ctrl>; + hisilicon,pctrl-syscon = <&pctrl>; + hisilicon,eye-diagram-param = <0x22466e4>; }; diff --git a/dts/Bindings/phy/hisilicon,hi3670-usb3.yaml b/dts/Bindings/phy/hisilicon,hi3670-usb3.yaml index ebd78acfe2..1cb00dbcd4 100644 --- a/dts/Bindings/phy/hisilicon,hi3670-usb3.yaml +++ b/dts/Bindings/phy/hisilicon,hi3670-usb3.yaml @@ -52,22 +52,12 @@ additionalProperties: false examples: - | - bus { - #address-cells = <2>; - #size-cells = <2>; - - usb3_otg_bc: usb3_otg_bc@ff200000 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0xff200000 0x0 0x1000>; - - usb_phy { - compatible = "hisilicon,hi3670-usb-phy"; - #phy-cells = <0>; - hisilicon,pericrg-syscon = <&crg_ctrl>; - hisilicon,pctrl-syscon = <&pctrl>; - hisilicon,sctrl-syscon = <&sctrl>; - hisilicon,eye-diagram-param = <0xfdfee4>; - hisilicon,tx-vboost-lvl = <0x5>; - }; - }; + usb-phy { + compatible = "hisilicon,hi3670-usb-phy"; + #phy-cells = <0>; + hisilicon,pericrg-syscon = <&crg_ctrl>; + hisilicon,pctrl-syscon = <&pctrl>; + hisilicon,sctrl-syscon = <&sctrl>; + hisilicon,eye-diagram-param = <0xfdfee4>; + hisilicon,tx-vboost-lvl = <0x5>; }; diff --git a/dts/Bindings/phy/intel,lgm-emmc-phy.yaml b/dts/Bindings/phy/intel,lgm-emmc-phy.yaml index 954e67571d..ca818f8357 100644 --- a/dts/Bindings/phy/intel,lgm-emmc-phy.yaml +++ b/dts/Bindings/phy/intel,lgm-emmc-phy.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/phy/intel,lgm-emmc-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Intel Lightning Mountain(LGM) eMMC PHY Device Tree Bindings +title: Intel Lightning Mountain(LGM) eMMC PHY maintainers: - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> diff --git a/dts/Bindings/phy/intel,lgm-usb-phy.yaml b/dts/Bindings/phy/intel,lgm-usb-phy.yaml index ce62c0b94d..653a122866 100644 --- a/dts/Bindings/phy/intel,lgm-usb-phy.yaml +++ b/dts/Bindings/phy/intel,lgm-usb-phy.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/phy/intel,lgm-usb-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Intel LGM USB PHY Device Tree Bindings +title: Intel LGM USB PHY maintainers: - Vadivel Murugan Ramuthevar <vadivel.muruganx.ramuthevar@linux.intel.com> diff --git a/dts/Bindings/phy/lantiq,vrx200-pcie-phy.yaml b/dts/Bindings/phy/lantiq,vrx200-pcie-phy.yaml index a97482179c..711de06bb0 100644 --- a/dts/Bindings/phy/lantiq,vrx200-pcie-phy.yaml +++ b/dts/Bindings/phy/lantiq,vrx200-pcie-phy.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Lantiq VRX200 and ARX300 PCIe PHY Device Tree Bindings +title: Lantiq VRX200 and ARX300 PCIe PHY maintainers: - Martin Blumenstingl <martin.blumenstingl@googlemail.com> diff --git a/dts/Bindings/phy/mediatek,mt7621-pci-phy.yaml b/dts/Bindings/phy/mediatek,mt7621-pci-phy.yaml index 29d4123323..c2f4cb0b25 100644 --- a/dts/Bindings/phy/mediatek,mt7621-pci-phy.yaml +++ b/dts/Bindings/phy/mediatek,mt7621-pci-phy.yaml @@ -4,7 +4,7 @@ $id: "http://devicetree.org/schemas/phy/mediatek,mt7621-pci-phy.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: Mediatek Mt7621 PCIe PHY Device Tree Bindings +title: Mediatek Mt7621 PCIe PHY maintainers: - Sergio Paracuellos <sergio.paracuellos@gmail.com> diff --git a/dts/Bindings/phy/mediatek,tphy.yaml b/dts/Bindings/phy/mediatek,tphy.yaml index b3e409988c..5613cc5106 100644 --- a/dts/Bindings/phy/mediatek,tphy.yaml +++ b/dts/Bindings/phy/mediatek,tphy.yaml @@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: MediaTek T-PHY Controller Device Tree Bindings +title: MediaTek T-PHY Controller maintainers: - Chunfeng Yun <chunfeng.yun@mediatek.com> @@ -163,6 +163,7 @@ patternProperties: - PHY_TYPE_USB3 - PHY_TYPE_PCIE - PHY_TYPE_SATA + - PHY_TYPE_SGMII nvmem-cells: items: @@ -218,6 +219,16 @@ patternProperties: minimum: 1 maximum: 15 + mediatek,pre-emphasis: + description: + The level of pre-emphasis which used to widen the eye opening and + boost eye swing, the unit step is about 4.16% increment; e.g. the + level 1 means amplitude increases about 4.16%, the level 2 is about + 8.3% etc. (U2 phy) + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 3 + mediatek,bc12: description: Specify the flag to enable BC1.2 if support it diff --git a/dts/Bindings/phy/mediatek,xsphy.yaml b/dts/Bindings/phy/mediatek,xsphy.yaml index 598fd2b95c..a9e3139fd4 100644 --- a/dts/Bindings/phy/mediatek,xsphy.yaml +++ b/dts/Bindings/phy/mediatek,xsphy.yaml @@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: MediaTek XS-PHY Controller Device Tree Bindings +title: MediaTek XS-PHY Controller maintainers: - Chunfeng Yun <chunfeng.yun@mediatek.com> diff --git a/dts/Bindings/phy/mscc,vsc7514-serdes.yaml b/dts/Bindings/phy/mscc,vsc7514-serdes.yaml new file mode 100644 index 0000000000..3169b87323 --- /dev/null +++ b/dts/Bindings/phy/mscc,vsc7514-serdes.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/mscc,vsc7514-serdes.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microsemi Ocelot SerDes muxing + +maintainers: + - Alexandre Belloni <alexandre.belloni@bootlin.com> + - UNGLinuxDriver@microchip.com + +description: | + On Microsemi Ocelot, there is a handful of registers in HSIO address + space for setting up the SerDes to switch port muxing. + + A SerDes X can be "muxed" to work with switch port Y or Z for example. + One specific SerDes can also be used as a PCIe interface. + + Hence, a SerDes represents an interface, be it an Ethernet or a PCIe one. + + There are two kinds of SerDes: SERDES1G supports 10/100Mbps in + half/full-duplex and 1000Mbps in full-duplex mode while SERDES6G supports + 10/100Mbps in half/full-duplex and 1000/2500Mbps in full-duplex mode. + + Also, SERDES6G number (aka "macro") 0 is the only interface supporting + QSGMII. + + This is a child of the HSIO syscon ("mscc,ocelot-hsio", see + Documentation/devicetree/bindings/mips/mscc.txt) on the Microsemi Ocelot. + +properties: + compatible: + enum: + - mscc,vsc7514-serdes + + "#phy-cells": + const: 2 + description: | + The first number defines the input port to use for a given SerDes macro. + The second defines the macro to use. They are defined in + dt-bindings/phy/phy-ocelot-serdes.h + +required: + - compatible + - "#phy-cells" + +additionalProperties: + false + +examples: + - | + serdes: serdes { + compatible = "mscc,vsc7514-serdes"; + #phy-cells = <2>; + }; diff --git a/dts/Bindings/phy/mxs-usb-phy.txt b/dts/Bindings/phy/mxs-usb-phy.txt index c9e392c64a..70c813b075 100644 --- a/dts/Bindings/phy/mxs-usb-phy.txt +++ b/dts/Bindings/phy/mxs-usb-phy.txt @@ -15,10 +15,10 @@ Required properties: - fsl,anatop: phandle for anatop register, it is only for imx6 SoC series Optional properties: -- fsl,tx-cal-45-dn-ohms: Integer [30-55]. Resistance (in ohms) of switchable +- fsl,tx-cal-45-dn-ohms: Integer [35-54]. Resistance (in ohms) of switchable high-speed trimming resistor connected in parallel with the 45 ohm resistor that terminates the DN output signal. Default: 45 -- fsl,tx-cal-45-dp-ohms: Integer [30-55]. Resistance (in ohms) of switchable +- fsl,tx-cal-45-dp-ohms: Integer [35-54]. Resistance (in ohms) of switchable high-speed trimming resistor connected in parallel with the 45 ohm resistor that terminates the DP output signal. Default: 45 - fsl,tx-d-cal: Integer [79-119]. Current trimming value (as a percentage) of diff --git a/dts/Bindings/phy/phy-ocelot-serdes.txt b/dts/Bindings/phy/phy-ocelot-serdes.txt deleted file mode 100644 index 3322198601..0000000000 --- a/dts/Bindings/phy/phy-ocelot-serdes.txt +++ /dev/null @@ -1,43 +0,0 @@ -Microsemi Ocelot SerDes muxing driver -------------------------------------- - -On Microsemi Ocelot, there is a handful of registers in HSIO address -space for setting up the SerDes to switch port muxing. - -A SerDes X can be "muxed" to work with switch port Y or Z for example. -One specific SerDes can also be used as a PCIe interface. - -Hence, a SerDes represents an interface, be it an Ethernet or a PCIe one. - -There are two kinds of SerDes: SERDES1G supports 10/100Mbps in -half/full-duplex and 1000Mbps in full-duplex mode while SERDES6G supports -10/100Mbps in half/full-duplex and 1000/2500Mbps in full-duplex mode. - -Also, SERDES6G number (aka "macro") 0 is the only interface supporting -QSGMII. - -This is a child of the HSIO syscon ("mscc,ocelot-hsio", see -Documentation/devicetree/bindings/mips/mscc.txt) on the Microsemi Ocelot. - -Required properties: - -- compatible: should be "mscc,vsc7514-serdes" -- #phy-cells : from the generic phy bindings, must be 2. - The first number defines the input port to use for a given - SerDes macro. The second defines the macro to use. They are - defined in dt-bindings/phy/phy-ocelot-serdes.h - -Example: - - serdes: serdes { - compatible = "mscc,vsc7514-serdes"; - #phy-cells = <2>; - }; - - ethernet { - port1 { - phy-handle = <&phy_foo>; - /* Link SERDES1G_5 to port1 */ - phys = <&serdes 1 SERDES1G_5>; - }; - }; diff --git a/dts/Bindings/phy/phy-rockchip-inno-usb2.yaml b/dts/Bindings/phy/phy-rockchip-inno-usb2.yaml index 4b75289735..f71920082f 100644 --- a/dts/Bindings/phy/phy-rockchip-inno-usb2.yaml +++ b/dts/Bindings/phy/phy-rockchip-inno-usb2.yaml @@ -13,6 +13,7 @@ properties: compatible: enum: - rockchip,px30-usb2phy + - rockchip,rk3128-usb2phy - rockchip,rk3228-usb2phy - rockchip,rk3308-usb2phy - rockchip,rk3328-usb2phy diff --git a/dts/Bindings/phy/phy-rockchip-naneng-combphy.yaml b/dts/Bindings/phy/phy-rockchip-naneng-combphy.yaml index f144544014..8d8698412d 100644 --- a/dts/Bindings/phy/phy-rockchip-naneng-combphy.yaml +++ b/dts/Bindings/phy/phy-rockchip-naneng-combphy.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Rockchip SoC Naneng Combo Phy Device Tree Bindings +title: Rockchip SoC Naneng Combo Phy maintainers: - Heiko Stuebner <heiko@sntech.de> diff --git a/dts/Bindings/phy/phy-stm32-usbphyc.yaml b/dts/Bindings/phy/phy-stm32-usbphyc.yaml index dc287d428e..801993813b 100644 --- a/dts/Bindings/phy/phy-stm32-usbphyc.yaml +++ b/dts/Bindings/phy/phy-stm32-usbphyc.yaml @@ -77,6 +77,8 @@ patternProperties: connector: type: object $ref: /schemas/connector/usb-connector.yaml + unevaluatedProperties: false + properties: vbus-supply: true diff --git a/dts/Bindings/phy/qcom,edp-phy.yaml b/dts/Bindings/phy/qcom,edp-phy.yaml index cf9e9b8011..1e104ae76e 100644 --- a/dts/Bindings/phy/qcom,edp-phy.yaml +++ b/dts/Bindings/phy/qcom,edp-phy.yaml @@ -19,6 +19,8 @@ properties: enum: - qcom,sc7280-edp-phy - qcom,sc8180x-edp-phy + - qcom,sc8280xp-dp-phy + - qcom,sc8280xp-edp-phy reg: items: diff --git a/dts/Bindings/phy/qcom,hdmi-phy-qmp.yaml b/dts/Bindings/phy/qcom,hdmi-phy-qmp.yaml index eea2e02678..83fe4b39b5 100644 --- a/dts/Bindings/phy/qcom,hdmi-phy-qmp.yaml +++ b/dts/Bindings/phy/qcom,hdmi-phy-qmp.yaml @@ -28,12 +28,15 @@ properties: - const: hdmi_phy clocks: - maxItems: 2 + minItems: 2 + maxItems: 3 clock-names: + minItems: 2 items: - const: iface - const: ref + - const: xo power-domains: maxItems: 1 @@ -44,6 +47,9 @@ properties: vddio-supply: description: phandle to VDD I/O supply regulator + '#clock-cells': + const: 0 + '#phy-cells': const: 0 @@ -75,9 +81,12 @@ examples: "hdmi_phy"; clocks = <&mmcc 116>, - <&gcc 214>; + <&gcc 214>, + <&xo_board>; clock-names = "iface", - "ref"; + "ref", + "xo"; + #clock-cells = <0>; #phy-cells = <0>; vddio-supply = <&vreg_l12a_1p8>; diff --git a/dts/Bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml b/dts/Bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml new file mode 100644 index 0000000000..4e710ef755 --- /dev/null +++ b/dts/Bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml @@ -0,0 +1,189 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QMP PHY controller (MSM8996 PCIe) + +maintainers: + - Vinod Koul <vkoul@kernel.org> + +description: + QMP PHY controller supports physical layer functionality for a number of + controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. + +properties: + compatible: + const: qcom,msm8996-qmp-pcie-phy + + reg: + items: + - description: serdes + + "#address-cells": + enum: [ 1, 2 ] + + "#size-cells": + enum: [ 1, 2 ] + + ranges: true + + clocks: + maxItems: 3 + + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + + resets: + maxItems: 3 + + reset-names: + items: + - const: phy + - const: common + - const: cfg + + vdda-phy-supply: true + + vdda-pll-supply: true + + vddp-ref-clk-supply: true + +patternProperties: + "^phy@[0-9a-f]+$": + type: object + description: one child node per PHY provided by this block + properties: + reg: + items: + - description: TX + - description: RX + - description: PCS + + clocks: + items: + - description: PIPE clock + + clock-names: + deprecated: true + items: + - enum: + - pipe0 + - pipe1 + - pipe2 + + resets: + items: + - description: PHY reset + + reset-names: + deprecated: true + items: + - enum: + - lane0 + - lane1 + - lane2 + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + + "#phy-cells": + const: 0 + + required: + - reg + - clocks + - resets + - "#clock-cells" + - clock-output-names + - "#phy-cells" + + additionalProperties: false + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + - clocks + - clock-names + - resets + - reset-names + - vdda-phy-supply + - vdda-pll-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-msm8996.h> + pcie_phy: phy-wrapper@34000 { + compatible = "qcom,msm8996-qmp-pcie-phy"; + reg = <0x34000 0x488>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x34000 0x4000>; + + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_CLK>; + clock-names = "aux", "cfg_ahb", "ref"; + + resets = <&gcc GCC_PCIE_PHY_BCR>, + <&gcc GCC_PCIE_PHY_COM_BCR>, + <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; + reset-names = "phy", "common", "cfg"; + + vdda-phy-supply = <&vreg_l28a_0p925>; + vdda-pll-supply = <&vreg_l12a_1p8>; + + pciephy_0: phy@1000 { + reg = <0x1000 0x130>, + <0x1200 0x200>, + <0x1400 0x1dc>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + + #clock-cells = <0>; + clock-output-names = "pcie_0_pipe_clk_src"; + + #phy-cells = <0>; + }; + + pciephy_1: phy@2000 { + reg = <0x2000 0x130>, + <0x2200 0x200>, + <0x2400 0x1dc>; + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + + #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk_src"; + + #phy-cells = <0>; + }; + + pciephy_2: phy@3000 { + reg = <0x3000 0x130>, + <0x3200 0x200>, + <0x3400 0x1dc>; + + clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; + resets = <&gcc GCC_PCIE_2_PHY_BCR>; + + #clock-cells = <0>; + clock-output-names = "pcie_2_pipe_clk_src"; + + #phy-cells = <0>; + }; + }; diff --git a/dts/Bindings/phy/qcom,qmp-pcie-phy.yaml b/dts/Bindings/phy/qcom,qmp-pcie-phy.yaml new file mode 100644 index 0000000000..324ad7d03a --- /dev/null +++ b/dts/Bindings/phy/qcom,qmp-pcie-phy.yaml @@ -0,0 +1,296 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,qmp-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QMP PHY controller (PCIe) + +maintainers: + - Vinod Koul <vkoul@kernel.org> + +description: + QMP PHY controller supports physical layer functionality for a number of + controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. + +properties: + compatible: + enum: + - qcom,ipq6018-qmp-pcie-phy + - qcom,ipq8074-qmp-gen3-pcie-phy + - qcom,ipq8074-qmp-pcie-phy + - qcom,msm8998-qmp-pcie-phy + - qcom,sc8180x-qmp-pcie-phy + - qcom,sdm845-qhp-pcie-phy + - qcom,sdm845-qmp-pcie-phy + - qcom,sdx55-qmp-pcie-phy + - qcom,sm8250-qmp-gen3x1-pcie-phy + - qcom,sm8250-qmp-gen3x2-pcie-phy + - qcom,sm8250-qmp-modem-pcie-phy + - qcom,sm8450-qmp-gen3x1-pcie-phy + - qcom,sm8450-qmp-gen4x2-pcie-phy + + reg: + items: + - description: serdes + + "#address-cells": + enum: [ 1, 2 ] + + "#size-cells": + enum: [ 1, 2 ] + + ranges: true + + clocks: + minItems: 2 + maxItems: 4 + + clock-names: + minItems: 2 + maxItems: 4 + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + maxItems: 2 + + vdda-phy-supply: true + + vdda-pll-supply: true + + vddp-ref-clk-supply: true + +patternProperties: + "^phy@[0-9a-f]+$": + type: object + description: single PHY-provider child node + properties: + reg: + minItems: 3 + maxItems: 6 + + clocks: + items: + - description: PIPE clock + + clock-names: + deprecated: true + items: + - const: pipe0 + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + + "#phy-cells": + const: 0 + + required: + - reg + - clocks + - "#clock-cells" + - clock-output-names + - "#phy-cells" + + additionalProperties: false + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8998-qmp-pcie-phy + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + resets: + maxItems: 2 + reset-names: + items: + - const: phy + - const: common + required: + - vdda-phy-supply + - vdda-pll-supply + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq6018-qmp-pcie-phy + - qcom,ipq8074-qmp-gen3-pcie-phy + - qcom,ipq8074-qmp-pcie-phy + then: + properties: + clocks: + maxItems: 2 + clock-names: + items: + - const: aux + - const: cfg_ahb + resets: + maxItems: 2 + reset-names: + items: + - const: phy + - const: common + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8180x-qmp-pcie-phy + - qcom,sdm845-qhp-pcie-phy + - qcom,sdm845-qmp-pcie-phy + - qcom,sdx55-qmp-pcie-phy + - qcom,sm8250-qmp-gen3x1-pcie-phy + - qcom,sm8250-qmp-gen3x2-pcie-phy + - qcom,sm8250-qmp-modem-pcie-phy + - qcom,sm8450-qmp-gen3x1-pcie-phy + - qcom,sm8450-qmp-gen4x2-pcie-phy + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: refgen + resets: + maxItems: 1 + reset-names: + items: + - const: phy + required: + - vdda-phy-supply + - vdda-pll-supply + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8250-qmp-gen3x2-pcie-phy + - qcom,sm8250-qmp-modem-pcie-phy + - qcom,sm8450-qmp-gen4x2-pcie-phy + then: + patternProperties: + "^phy@[0-9a-f]+$": + properties: + reg: + items: + - description: TX lane 1 + - description: RX lane 1 + - description: PCS + - description: TX lane 2 + - description: RX lane 2 + - description: PCS_MISC + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8180x-qmp-pcie-phy + - qcom,sdm845-qmp-pcie-phy + - qcom,sdx55-qmp-pcie-phy + - qcom,sm8250-qmp-gen3x1-pcie-phy + - qcom,sm8450-qmp-gen3x1-pcie-phy + then: + patternProperties: + "^phy@[0-9a-f]+$": + properties: + reg: + items: + - description: TX + - description: RX + - description: PCS + - description: PCS_MISC + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq6018-qmp-pcie-phy + - qcom,ipq8074-qmp-pcie-phy + - qcom,msm8998-qmp-pcie-phy + - qcom,sdm845-qhp-pcie-phy + then: + patternProperties: + "^phy@[0-9a-f]+$": + properties: + reg: + items: + - description: TX + - description: RX + - description: PCS + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sm8250.h> + phy-wrapper@1c0e000 { + compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; + reg = <0x01c0e000 0x1c0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x01c0e000 0x1000>; + + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + phy@200 { + reg = <0x200 0x170>, + <0x400 0x200>, + <0xa00 0x1f0>, + <0x600 0x170>, + <0x800 0x200>, + <0xe00 0xf4>; + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; + + #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + + #phy-cells = <0>; + }; + }; diff --git a/dts/Bindings/phy/qcom,qmp-phy.yaml b/dts/Bindings/phy/qcom,qmp-phy.yaml deleted file mode 100644 index 220788ce21..0000000000 --- a/dts/Bindings/phy/qcom,qmp-phy.yaml +++ /dev/null @@ -1,502 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) - -%YAML 1.2 ---- -$id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" - -title: Qualcomm QMP PHY controller - -maintainers: - - Vinod Koul <vkoul@kernel.org> - -description: - QMP phy controller supports physical layer functionality for a number of - controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. - -properties: - compatible: - enum: - - qcom,ipq6018-qmp-pcie-phy - - qcom,ipq6018-qmp-usb3-phy - - qcom,ipq8074-qmp-gen3-pcie-phy - - qcom,ipq8074-qmp-pcie-phy - - qcom,ipq8074-qmp-usb3-phy - - qcom,msm8996-qmp-pcie-phy - - qcom,msm8996-qmp-ufs-phy - - qcom,msm8996-qmp-usb3-phy - - qcom,msm8998-qmp-pcie-phy - - qcom,msm8998-qmp-ufs-phy - - qcom,msm8998-qmp-usb3-phy - - qcom,qcm2290-qmp-usb3-phy - - qcom,sc7180-qmp-usb3-phy - - qcom,sc8180x-qmp-pcie-phy - - qcom,sc8180x-qmp-ufs-phy - - qcom,sc8180x-qmp-usb3-phy - - qcom,sc8280xp-qmp-ufs-phy - - qcom,sdm845-qhp-pcie-phy - - qcom,sdm845-qmp-pcie-phy - - qcom,sdm845-qmp-ufs-phy - - qcom,sdm845-qmp-usb3-phy - - qcom,sdm845-qmp-usb3-uni-phy - - qcom,sm6115-qmp-ufs-phy - - qcom,sm6350-qmp-ufs-phy - - qcom,sm8150-qmp-ufs-phy - - qcom,sm8150-qmp-usb3-phy - - qcom,sm8150-qmp-usb3-uni-phy - - qcom,sm8250-qmp-ufs-phy - - qcom,sm8250-qmp-gen3x1-pcie-phy - - qcom,sm8250-qmp-gen3x2-pcie-phy - - qcom,sm8250-qmp-modem-pcie-phy - - qcom,sm8250-qmp-usb3-phy - - qcom,sm8250-qmp-usb3-uni-phy - - qcom,sm8350-qmp-ufs-phy - - qcom,sm8350-qmp-usb3-phy - - qcom,sm8350-qmp-usb3-uni-phy - - qcom,sm8450-qmp-gen3x1-pcie-phy - - qcom,sm8450-qmp-gen4x2-pcie-phy - - qcom,sm8450-qmp-ufs-phy - - qcom,sm8450-qmp-usb3-phy - - qcom,sdx55-qmp-pcie-phy - - qcom,sdx55-qmp-usb3-uni-phy - - qcom,sdx65-qmp-usb3-uni-phy - - reg: - minItems: 1 - items: - - description: Address and length of PHY's common serdes block. - - description: Address and length of PHY's DP_COM control block. - - "#clock-cells": - enum: [ 1, 2 ] - - "#address-cells": - enum: [ 1, 2 ] - - "#size-cells": - enum: [ 1, 2 ] - - ranges: true - - clocks: - minItems: 1 - maxItems: 4 - - clock-names: - minItems: 1 - maxItems: 4 - - resets: - minItems: 1 - maxItems: 3 - - reset-names: - minItems: 1 - maxItems: 3 - - vdda-phy-supply: - description: - Phandle to a regulator supply to PHY core block. - - vdda-pll-supply: - description: - Phandle to 1.8V regulator supply to PHY refclk pll block. - - vddp-ref-clk-supply: - description: - Phandle to a regulator supply to any specific refclk pll block. - -#Required nodes: -patternProperties: - "^phy@[0-9a-f]+$": - type: object - description: - Each device node of QMP phy is required to have as many child nodes as - the number of lanes the PHY has. - -required: - - compatible - - reg - - "#clock-cells" - - "#address-cells" - - "#size-cells" - - ranges - - clocks - - clock-names - - resets - - reset-names - -additionalProperties: false - -allOf: - - if: - properties: - compatible: - contains: - enum: - - qcom,sdm845-qmp-usb3-uni-phy - then: - properties: - clocks: - items: - - description: Phy aux clock. - - description: Phy config clock. - - description: 19.2 MHz ref clk. - - description: Phy common block aux clock. - clock-names: - items: - - const: aux - - const: cfg_ahb - - const: ref - - const: com_aux - resets: - items: - - description: reset of phy block. - - description: phy common block reset. - reset-names: - items: - - const: phy - - const: common - required: - - vdda-phy-supply - - vdda-pll-supply - - if: - properties: - compatible: - contains: - enum: - - qcom,sdx55-qmp-usb3-uni-phy - - qcom,sdx65-qmp-usb3-uni-phy - then: - properties: - clocks: - items: - - description: Phy aux clock. - - description: Phy config clock. - - description: 19.2 MHz ref clk. - clock-names: - items: - - const: aux - - const: cfg_ahb - - const: ref - resets: - items: - - description: reset of phy block. - - description: phy common block reset. - reset-names: - items: - - const: phy - - const: common - required: - - vdda-phy-supply - - vdda-pll-supply - - if: - properties: - compatible: - contains: - enum: - - qcom,msm8996-qmp-pcie-phy - then: - properties: - clocks: - items: - - description: Phy aux clock. - - description: Phy config clock. - - description: 19.2 MHz ref clk. - clock-names: - items: - - const: aux - - const: cfg_ahb - - const: ref - resets: - items: - - description: reset of phy block. - - description: phy common block reset. - - description: phy's ahb cfg block reset. - reset-names: - items: - - const: phy - - const: common - - const: cfg - required: - - vdda-phy-supply - - vdda-pll-supply - - if: - properties: - compatible: - contains: - enum: - - qcom,ipq8074-qmp-usb3-phy - - qcom,msm8996-qmp-usb3-phy - - qcom,msm8998-qmp-pcie-phy - - qcom,msm8998-qmp-usb3-phy - then: - properties: - clocks: - items: - - description: Phy aux clock. - - description: Phy config clock. - - description: 19.2 MHz ref clk. - clock-names: - items: - - const: aux - - const: cfg_ahb - - const: ref - resets: - items: - - description: reset of phy block. - - description: phy common block reset. - reset-names: - items: - - const: phy - - const: common - required: - - vdda-phy-supply - - vdda-pll-supply - - if: - properties: - compatible: - contains: - enum: - - qcom,msm8996-qmp-ufs-phy - then: - properties: - clocks: - items: - - description: 19.2 MHz ref clk. - clock-names: - items: - - const: ref - resets: - items: - - description: PHY reset in the UFS controller. - reset-names: - items: - - const: ufsphy - required: - - vdda-phy-supply - - vdda-pll-supply - - if: - properties: - compatible: - contains: - enum: - - qcom,msm8998-qmp-ufs-phy - - qcom,sdm845-qmp-ufs-phy - - qcom,sm6350-qmp-ufs-phy - - qcom,sm8150-qmp-ufs-phy - - qcom,sm8250-qmp-ufs-phy - - qcom,sc8180x-qmp-ufs-phy - - qcom,sc8280xp-qmp-ufs-phy - then: - properties: - clocks: - items: - - description: 19.2 MHz ref clk. - - description: Phy reference aux clock. - clock-names: - items: - - const: ref - - const: ref_aux - resets: - items: - - description: PHY reset in the UFS controller. - reset-names: - items: - - const: ufsphy - required: - - vdda-phy-supply - - vdda-pll-supply - - if: - properties: - compatible: - contains: - enum: - - qcom,ipq6018-qmp-pcie-phy - - qcom,ipq8074-qmp-gen3-pcie-phy - - qcom,ipq8074-qmp-pcie-phy - then: - properties: - clocks: - items: - - description: Phy aux clock. - - description: Phy config clock. - clock-names: - items: - - const: aux - - const: cfg_ahb - resets: - items: - - description: reset of phy block. - - description: phy common block reset. - reset-names: - items: - - const: phy - - const: common - - if: - properties: - compatible: - contains: - enum: - - qcom,sc8180x-qmp-pcie-phy - - qcom,sdm845-qhp-pcie-phy - - qcom,sdm845-qmp-pcie-phy - - qcom,sdx55-qmp-pcie-phy - - qcom,sm8250-qmp-gen3x1-pcie-phy - - qcom,sm8250-qmp-gen3x2-pcie-phy - - qcom,sm8250-qmp-modem-pcie-phy - - qcom,sm8450-qmp-gen3x1-pcie-phy - - qcom,sm8450-qmp-gen4x2-pcie-phy - then: - properties: - clocks: - items: - - description: Phy aux clock. - - description: Phy config clock. - - description: 19.2 MHz ref clk. - - description: Phy refgen clk. - clock-names: - items: - - const: aux - - const: cfg_ahb - - const: ref - - const: refgen - resets: - items: - - description: reset of phy block. - reset-names: - items: - - const: phy - required: - - vdda-phy-supply - - vdda-pll-supply - - if: - properties: - compatible: - contains: - enum: - - qcom,sm8150-qmp-usb3-phy - - qcom,sm8150-qmp-usb3-uni-phy - - qcom,sm8250-qmp-usb3-uni-phy - - qcom,sm8350-qmp-usb3-uni-phy - then: - properties: - clocks: - items: - - description: Phy aux clock. - - description: 19.2 MHz ref clk source. - - description: 19.2 MHz ref clk. - - description: Phy common block aux clock. - clock-names: - items: - - const: aux - - const: ref_clk_src - - const: ref - - const: com_aux - resets: - items: - - description: reset of phy block. - - description: phy common block reset. - reset-names: - items: - - const: phy - - const: common - required: - - vdda-phy-supply - - vdda-pll-supply - - if: - properties: - compatible: - contains: - enum: - - qcom,sm8250-qmp-usb3-phy - - qcom,sm8350-qmp-usb3-phy - then: - properties: - clocks: - items: - - description: Phy aux clock. - - description: 19.2 MHz ref clk. - - description: Phy common block aux clock. - clock-names: - items: - - const: aux - - const: ref_clk_src - - const: com_aux - resets: - items: - - description: reset of phy block. - - description: phy common block reset. - reset-names: - items: - - const: phy - - const: common - required: - - vdda-phy-supply - - vdda-pll-supply - - if: - properties: - compatible: - contains: - enum: - - qcom,qcm2290-qmp-usb3-phy - then: - properties: - clocks: - items: - - description: Phy config clock. - - description: 19.2 MHz ref clk. - - description: Phy common block aux clock. - clock-names: - items: - - const: cfg_ahb - - const: ref - - const: com_aux - resets: - items: - - description: phy_phy reset. - - description: reset of phy block. - reset-names: - items: - - const: phy_phy - - const: phy - required: - - vdda-phy-supply - - vdda-pll-supply - -examples: - - | - #include <dt-bindings/clock/qcom,gcc-sdm845.h> - usb_2_qmpphy: phy-wrapper@88eb000 { - compatible = "qcom,sdm845-qmp-usb3-uni-phy"; - reg = <0x088eb000 0x18c>; - #clock-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x088eb000 0x2000>; - - clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >, - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_CLK>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "com_aux"; - - resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, - <&gcc GCC_USB3_PHY_SEC_BCR>; - reset-names = "phy", "common"; - - vdda-phy-supply = <&vdda_usb2_ss_1p2>; - vdda-pll-supply = <&vdda_usb2_ss_core>; - - usb_2_ssphy: phy@200 { - reg = <0x200 0x128>, - <0x400 0x1fc>, - <0x800 0x218>, - <0x600 0x70>; - #clock-cells = <0>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_uni_phy_pipe_clk_src"; - }; - }; diff --git a/dts/Bindings/phy/qcom,qmp-ufs-phy.yaml b/dts/Bindings/phy/qcom,qmp-ufs-phy.yaml new file mode 100644 index 0000000000..815c375d0f --- /dev/null +++ b/dts/Bindings/phy/qcom,qmp-ufs-phy.yaml @@ -0,0 +1,240 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,qmp-ufs-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QMP PHY controller (UFS) + +maintainers: + - Vinod Koul <vkoul@kernel.org> + +description: + QMP PHY controller supports physical layer functionality for a number of + controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. + +properties: + compatible: + enum: + - qcom,msm8996-qmp-ufs-phy + - qcom,msm8998-qmp-ufs-phy + - qcom,sc8180x-qmp-ufs-phy + - qcom,sc8280xp-qmp-ufs-phy + - qcom,sdm845-qmp-ufs-phy + - qcom,sm6115-qmp-ufs-phy + - qcom,sm6350-qmp-ufs-phy + - qcom,sm8150-qmp-ufs-phy + - qcom,sm8250-qmp-ufs-phy + - qcom,sm8350-qmp-ufs-phy + - qcom,sm8450-qmp-ufs-phy + + reg: + items: + - description: serdes + + "#address-cells": + enum: [ 1, 2 ] + + "#size-cells": + enum: [ 1, 2 ] + + ranges: true + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + minItems: 1 + maxItems: 3 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + items: + - const: ufsphy + + vdda-phy-supply: true + + vdda-pll-supply: true + + vddp-ref-clk-supply: true + +patternProperties: + "^phy@[0-9a-f]+$": + type: object + description: single PHY-provider child node + properties: + reg: + minItems: 3 + maxItems: 6 + + "#phy-cells": + const: 0 + + required: + - reg + - "#phy-cells" + + additionalProperties: false + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + - clocks + - clock-names + - resets + - reset-names + - vdda-phy-supply + - vdda-pll-supply + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8996-qmp-ufs-phy + then: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: ref + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8998-qmp-ufs-phy + - qcom,sc8180x-qmp-ufs-phy + - qcom,sc8280xp-qmp-ufs-phy + - qcom,sdm845-qmp-ufs-phy + - qcom,sm6115-qmp-ufs-phy + - qcom,sm6350-qmp-ufs-phy + - qcom,sm8150-qmp-ufs-phy + - qcom,sm8250-qmp-ufs-phy + then: + properties: + clocks: + maxItems: 2 + clock-names: + items: + - const: ref + - const: ref_aux + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8450-qmp-ufs-phy + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: ref + - const: ref_aux + - const: qref + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8998-qmp-ufs-phy + - qcom,sc8280xp-qmp-ufs-phy + - qcom,sdm845-qmp-ufs-phy + - qcom,sm6350-qmp-ufs-phy + - qcom,sm8150-qmp-ufs-phy + - qcom,sm8250-qmp-ufs-phy + - qcom,sm8350-qmp-ufs-phy + - qcom,sm8450-qmp-ufs-phy + then: + patternProperties: + "^phy@[0-9a-f]+$": + properties: + reg: + items: + - description: TX lane 1 + - description: RX lane 1 + - description: PCS + - description: TX lane 2 + - description: RX lane 2 + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8180x-qmp-ufs-phy + then: + patternProperties: + "^phy@[0-9a-f]+$": + properties: + reg: + items: + - description: TX + - description: RX + - description: PCS + - description: PCS_MISC + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8996-qmp-ufs-phy + - qcom,sm6115-qmp-ufs-phy + then: + patternProperties: + "^phy@[0-9a-f]+$": + properties: + reg: + items: + - description: TX + - description: RX + - description: PCS + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> + #include <dt-bindings/clock/qcom,rpmh.h> + phy-wrapper@1d87000 { + compatible = "qcom,sc8280xp-qmp-ufs-phy"; + reg = <0x01d87000 0xe10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x01d87000 0x1000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clock-names = "ref", "ref_aux"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + vdda-phy-supply = <&vreg_l6b>; + vdda-pll-supply = <&vreg_l3b>; + + phy@400 { + reg = <0x400 0x108>, + <0x600 0x1e0>, + <0xc00 0x1dc>, + <0x800 0x108>, + <0xa00 0x1e0>; + #phy-cells = <0>; + }; + }; diff --git a/dts/Bindings/phy/qcom,qmp-usb-phy.yaml b/dts/Bindings/phy/qcom,qmp-usb-phy.yaml new file mode 100644 index 0000000000..7acb4b7de7 --- /dev/null +++ b/dts/Bindings/phy/qcom,qmp-usb-phy.yaml @@ -0,0 +1,401 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,qmp-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QMP PHY controller (USB) + +maintainers: + - Vinod Koul <vkoul@kernel.org> + +description: + QMP PHY controller supports physical layer functionality for a number of + controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. + +properties: + compatible: + enum: + - qcom,ipq6018-qmp-usb3-phy + - qcom,ipq8074-qmp-usb3-phy + - qcom,msm8996-qmp-usb3-phy + - qcom,msm8998-qmp-usb3-phy + - qcom,qcm2290-qmp-usb3-phy + - qcom,sc7180-qmp-usb3-phy + - qcom,sc8180x-qmp-usb3-phy + - qcom,sc8280xp-qmp-usb3-uni-phy + - qcom,sdm845-qmp-usb3-phy + - qcom,sdm845-qmp-usb3-uni-phy + - qcom,sdx55-qmp-usb3-uni-phy + - qcom,sdx65-qmp-usb3-uni-phy + - qcom,sm8150-qmp-usb3-phy + - qcom,sm8150-qmp-usb3-uni-phy + - qcom,sm8250-qmp-usb3-phy + - qcom,sm8250-qmp-usb3-uni-phy + - qcom,sm8350-qmp-usb3-phy + - qcom,sm8350-qmp-usb3-uni-phy + - qcom,sm8450-qmp-usb3-phy + + reg: + minItems: 1 + items: + - description: serdes + - description: DP_COM + + "#address-cells": + enum: [ 1, 2 ] + + "#size-cells": + enum: [ 1, 2 ] + + ranges: true + + clocks: + minItems: 3 + maxItems: 4 + + clock-names: + minItems: 3 + maxItems: 4 + + power-domains: + maxItems: 1 + + resets: + maxItems: 2 + + reset-names: + maxItems: 2 + + vdda-phy-supply: true + + vdda-pll-supply: true + + vddp-ref-clk-supply: true + +patternProperties: + "^phy@[0-9a-f]+$": + type: object + description: single PHY-provider child node + properties: + reg: + minItems: 3 + maxItems: 6 + + clocks: + items: + - description: PIPE clock + + clock-names: + deprecated: true + items: + - const: pipe0 + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + + "#phy-cells": + const: 0 + + required: + - reg + - clocks + - "#clock-cells" + - clock-output-names + - "#phy-cells" + + additionalProperties: false + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + - clocks + - clock-names + - resets + - reset-names + - vdda-phy-supply + - vdda-pll-supply + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7180-qmp-usb3-phy + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: com_aux + resets: + maxItems: 1 + reset-names: + items: + - const: phy + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-qmp-usb3-uni-phy + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: com_aux + resets: + maxItems: 2 + reset-names: + items: + - const: phy + - const: common + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq8074-qmp-usb3-phy + - qcom,msm8996-qmp-usb3-phy + - qcom,msm8998-qmp-usb3-phy + - qcom,sdx55-qmp-usb3-uni-phy + - qcom,sdx65-qmp-usb3-uni-phy + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + resets: + maxItems: 2 + reset-names: + items: + - const: phy + - const: common + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-qmp-usb3-uni-phy + - qcom,sm8150-qmp-usb3-phy + - qcom,sm8150-qmp-usb3-uni-phy + - qcom,sm8250-qmp-usb3-uni-phy + - qcom,sm8350-qmp-usb3-uni-phy + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: aux + - const: ref_clk_src + - const: ref + - const: com_aux + resets: + maxItems: 2 + reset-names: + items: + - const: phy + - const: common + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8250-qmp-usb3-phy + - qcom,sm8350-qmp-usb3-phy + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: aux + - const: ref_clk_src + - const: com_aux + resets: + maxItems: 2 + reset-names: + items: + - const: phy + - const: common + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcm2290-qmp-usb3-phy + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: cfg_ahb + - const: ref + - const: com_aux + resets: + maxItems: 2 + reset-names: + items: + - const: phy_phy + - const: phy + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-qmp-usb3-uni-phy + then: + required: + - power-domains + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-qmp-usb3-phy + - qcom,sm8150-qmp-usb3-phy + - qcom,sm8350-qmp-usb3-phy + - qcom,sm8450-qmp-usb3-phy + then: + patternProperties: + "^phy@[0-9a-f]+$": + properties: + reg: + items: + - description: TX lane 1 + - description: RX lane 1 + - description: PCS + - description: TX lane 2 + - description: RX lane 2 + - description: PCS_MISC + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8998-qmp-usb3-phy + then: + patternProperties: + "^phy@[0-9a-f]+$": + properties: + reg: + items: + - description: TX lane 1 + - description: RX lane 1 + - description: PCS + - description: TX lane 2 + - description: RX lane 2 + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq6018-qmp-usb3-phy + - qcom,ipq8074-qmp-usb3-phy + - qcom,qcm2290-qmp-usb3-phy + - qcom,sc7180-qmp-usb3-phy + - qcom,sc8180x-qmp-usb3-phy + - qcom,sdx55-qmp-usb3-uni-phy + - qcom,sdx65-qmp-usb3-uni-phy + - qcom,sm8150-qmp-usb3-uni-phy + - qcom,sm8250-qmp-usb3-phy + then: + patternProperties: + "^phy@[0-9a-f]+$": + properties: + reg: + items: + - description: TX + - description: RX + - description: PCS + - description: PCS_MISC + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8996-qmp-usb3-phy + - qcom,sc8280xp-qmp-usb3-uni-phy + - qcom,sm8250-qmp-usb3-uni-phy + - qcom,sm8350-qmp-usb3-uni-phy + then: + patternProperties: + "^phy@[0-9a-f]+$": + properties: + reg: + items: + - description: TX + - description: RX + - description: PCS + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + usb_2_qmpphy: phy-wrapper@88eb000 { + compatible = "qcom,sdm845-qmp-usb3-uni-phy"; + reg = <0x088eb000 0x18c>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x088eb000 0x2000>; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "com_aux"; + + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, + <&gcc GCC_USB3_PHY_SEC_BCR>; + reset-names = "phy", "common"; + + vdda-phy-supply = <&vdda_usb2_ss_1p2>; + vdda-pll-supply = <&vdda_usb2_ss_core>; + + usb_2_ssphy: phy@200 { + reg = <0x200 0x128>, + <0x400 0x1fc>, + <0x800 0x218>, + <0x600 0x70>; + + clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + + #clock-cells = <0>; + clock-output-names = "usb3_uni_phy_pipe_clk_src"; + + #phy-cells = <0>; + }; + }; diff --git a/dts/Bindings/phy/qcom,qmp-usb3-dp-phy.yaml b/dts/Bindings/phy/qcom,qmp-usb3-dp-phy.yaml index b078009ed5..97a7ecafbf 100644 --- a/dts/Bindings/phy/qcom,qmp-usb3-dp-phy.yaml +++ b/dts/Bindings/phy/qcom,qmp-usb3-dp-phy.yaml @@ -16,6 +16,7 @@ properties: - qcom,sc7180-qmp-usb3-dp-phy - qcom,sc7280-qmp-usb3-dp-phy - qcom,sc8180x-qmp-usb3-dp-phy + - qcom,sc8280xp-qmp-usb43dp-phy - qcom,sdm845-qmp-usb3-dp-phy - qcom,sm8250-qmp-usb3-dp-phy reg: @@ -30,9 +31,6 @@ properties: - const: dp_com - const: dp - "#clock-cells": - enum: [ 1, 2 ] - "#address-cells": enum: [ 1, 2 ] @@ -55,6 +53,9 @@ properties: - const: ref - const: com_aux + power-domains: + maxItems: 1 + resets: items: - description: reset of phy block. @@ -81,6 +82,7 @@ properties: patternProperties: "^usb3-phy@[0-9a-f]+$": type: object + additionalProperties: false description: The USB3 PHY. @@ -99,6 +101,7 @@ patternProperties: - description: pipe clock clock-names: + deprecated: true items: - const: pipe0 @@ -115,12 +118,12 @@ patternProperties: required: - reg - clocks - - clock-names - '#clock-cells' - '#phy-cells' "^dp-phy@[0-9a-f]+$": type: object + additionalProperties: false description: The DP PHY. @@ -147,7 +150,6 @@ patternProperties: required: - compatible - reg - - "#clock-cells" - "#address-cells" - "#size-cells" - ranges @@ -160,6 +162,17 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-qmp-usb43dp-phy + then: + required: + - power-domains + examples: - | #include <dt-bindings/clock/qcom,gcc-sdm845.h> @@ -169,7 +182,6 @@ examples: <0x088e8000 0x10>, <0x088ea000 0x40>; reg-names = "usb", "dp_com", "dp"; - #clock-cells = <1>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x088e9000 0x2000>; @@ -197,7 +209,6 @@ examples: #clock-cells = <0>; #phy-cells = <0>; clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; clock-output-names = "usb3_phy_pipe_clk_src"; }; diff --git a/dts/Bindings/phy/qcom,qusb2-phy.yaml b/dts/Bindings/phy/qcom,qusb2-phy.yaml index d68ab49345..636ea430fb 100644 --- a/dts/Bindings/phy/qcom,qusb2-phy.yaml +++ b/dts/Bindings/phy/qcom,qusb2-phy.yaml @@ -30,6 +30,7 @@ properties: - items: - enum: - qcom,sc7180-qusb2-phy + - qcom,sdm670-qusb2-phy - qcom,sdm845-qusb2-phy - qcom,sm6350-qusb2-phy - const: qcom,qusb2-v2-phy diff --git a/dts/Bindings/phy/qcom,usb-snps-femto-v2.yaml b/dts/Bindings/phy/qcom,usb-snps-femto-v2.yaml index 7a0e6a9854..68e70961be 100644 --- a/dts/Bindings/phy/qcom,usb-snps-femto-v2.yaml +++ b/dts/Bindings/phy/qcom,usb-snps-femto-v2.yaml @@ -20,6 +20,7 @@ properties: - qcom,sc7280-usb-hs-phy - qcom,sc8180x-usb-hs-phy - qcom,sc8280xp-usb-hs-phy + - qcom,sm6375-usb-hs-phy - qcom,sm8150-usb-hs-phy - qcom,sm8250-usb-hs-phy - qcom,sm8350-usb-hs-phy @@ -53,6 +54,94 @@ properties: vdda33-supply: description: phandle to the regulator 3.3V supply node. + qcom,hs-disconnect-bp: + description: + This adjusts the voltage level for the threshold used to + detect a disconnect event at the host. + The hardware accepts only discrete values. The value closest to the + provided input will be chosen as the override value for this param. + minimum: -272 + maximum: 2156 + + qcom,squelch-detector-bp: + description: + This adjusts the voltage level for the threshold used to + detect valid high-speed data. + The hardware accepts only discrete values. The value closest to the + provided input will be chosen as the override value for this param. + minimum: -2090 + maximum: 1590 + + qcom,hs-amplitude-bp: + description: + This adjusts the high-speed DC level voltage. + The hardware accepts only discrete values. The value closest to the + provided input will be chosen as the override value for this param. + minimum: -660 + maximum: 2670 + + qcom,pre-emphasis-duration-bp: + description: + This signal controls the duration for which the + HS pre-emphasis current is sourced onto DP<#> or DM<#>. + The HS Transmitter pre-emphasis duration is defined in terms of + unit amounts. One unit of pre-emphasis duration is approximately + 650 ps and is defined as 1X pre-emphasis duration. + The hardware accepts only discrete values. The value closest to the + provided input will be chosen as the override value for this param. + minimum: 10000 + maximum: 20000 + + qcom,pre-emphasis-amplitude-bp: + description: + This signal controls the amount of current sourced to + DP<#> and DM<#> after a J-to-K or K-to-J transition. + The HS Transmitter pre-emphasis current is defined in terms of unit + amounts. One unit amount is approximately 2 mA and is defined as + 1X pre-emphasis current. + The hardware accepts only discrete values. The value closest to the + provided input will be chosen as the override value for this param. + minimum: 10000 + maximum: 40000 + + qcom,hs-rise-fall-time-bp: + description: + This adjusts the rise/fall times of the high-speed waveform. + The hardware accepts only discrete values. The value closest to the + provided input will be chosen as the override value for this param. + minimum: -4100 + maximum: 5430 + + qcom,hs-crossover-voltage-microvolt: + description: + This adjusts the voltage at which the DP<#> and DM<#> + signals cross while transmitting in HS mode. + The hardware accepts only discrete values. The value closest to the + provided input will be chosen as the override value for this param. + minimum: -31000 + maximum: 28000 + + qcom,hs-output-impedance-micro-ohms: + description: + In some applications, there can be significant series resistance + on the D+ and D- paths between the transceiver and cable. This adjusts + the driver source impedance to compensate for added series + resistance on the USB. The hardware accepts only discrete values. The + value closest to the provided input will be chosen as the override value + for this param. + minimum: -2300000 + maximum: 6100000 + + qcom,ls-fs-output-impedance-bp: + description: + This adjusts the low- and full-speed single-ended source + impedance while driving high. The following adjustment values are based + on nominal process, voltage, and temperature. + The hardware accepts only discrete values. The value closest to the + provided input will be chosen as the override value for this param. + minimum: -1053 + maximum: 1310 + required: - compatible - reg diff --git a/dts/Bindings/phy/rcar-gen2-phy.txt b/dts/Bindings/phy/rcar-gen2-phy.txt deleted file mode 100644 index a3bd1c4499..0000000000 --- a/dts/Bindings/phy/rcar-gen2-phy.txt +++ /dev/null @@ -1,112 +0,0 @@ -* Renesas R-Car generation 2 USB PHY - -This file provides information on what the device node for the R-Car generation -2 USB PHY contains. - -Required properties: -- compatible: "renesas,usb-phy-r8a7742" if the device is a part of R8A7742 SoC. - "renesas,usb-phy-r8a7743" if the device is a part of R8A7743 SoC. - "renesas,usb-phy-r8a7744" if the device is a part of R8A7744 SoC. - "renesas,usb-phy-r8a7745" if the device is a part of R8A7745 SoC. - "renesas,usb-phy-r8a77470" if the device is a part of R8A77470 SoC. - "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC. - "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC. - "renesas,usb-phy-r8a7794" if the device is a part of R8A7794 SoC. - "renesas,rcar-gen2-usb-phy" for a generic R-Car Gen2 or - RZ/G1 compatible device. - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first - followed by the generic version. - -- reg: offset and length of the register block. -- #address-cells: number of address cells for the USB channel subnodes, must - be <1>. -- #size-cells: number of size cells for the USB channel subnodes, must be <0>. -- clocks: clock phandle and specifier pair. -- clock-names: string, clock input name, must be "usbhs". - -The USB PHY device tree node should have the subnodes corresponding to the USB -channels. These subnodes must contain the following properties: -- reg: the USB controller selector; see the table below for the values. -- #phy-cells: see phy-bindings.txt in the same directory, must be <1>. - -The phandle's argument in the PHY specifier is the USB controller selector for -the USB channel other than r8a77470 SoC; see the selector meanings below: - -+-----------+---------------+---------------+ -|\ Selector | | | -+ --------- + 0 | 1 | -| Channel \| | | -+-----------+---------------+---------------+ -| 0 | PCI EHCI/OHCI | HS-USB | -| 2 | PCI EHCI/OHCI | xHCI | -+-----------+---------------+---------------+ - -For r8a77470 SoC;see the selector meaning below: - -+-----------+---------------+---------------+ -|\ Selector | | | -+ --------- + 0 | 1 | -| Channel \| | | -+-----------+---------------+---------------+ -| 0 | EHCI/OHCI | HS-USB | -+-----------+---------------+---------------+ - -Example (Lager board): - - usb-phy@e6590100 { - compatible = "renesas,usb-phy-r8a7790", "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 704>; - - usb0: usb-channel@0 { - reg = <0>; - #phy-cells = <1>; - }; - usb2: usb-channel@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; - -Example (iWave RZ/G1C sbc): - - usbphy0: usb-phy0@e6590100 { - compatible = "renesas,usb-phy-r8a77470", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6590100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 704>; - clock-names = "usbhs"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 704>; - - usb0: usb-channel@0 { - reg = <0>; - #phy-cells = <1>; - }; - }; - - usbphy1: usb-phy@e6598100 { - compatible = "renesas,usb-phy-r8a77470", - "renesas,rcar-gen2-usb-phy"; - reg = <0 0xe6598100 0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cpg CPG_MOD 706>; - clock-names = "usbhs"; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 706>; - - usb1: usb-channel@0 { - reg = <0>; - #phy-cells = <1>; - }; - }; diff --git a/dts/Bindings/phy/renesas,rcar-gen2-usb-phy.yaml b/dts/Bindings/phy/renesas,rcar-gen2-usb-phy.yaml new file mode 100644 index 0000000000..afc09f39b0 --- /dev/null +++ b/dts/Bindings/phy/renesas,rcar-gen2-usb-phy.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/renesas,rcar-gen2-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car Gen2 USB PHY + +maintainers: + - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> + +properties: + compatible: + items: + - enum: + - renesas,usb-phy-r8a7742 # RZ/G1H + - renesas,usb-phy-r8a7743 # RZ/G1M + - renesas,usb-phy-r8a7744 # RZ/G1N + - renesas,usb-phy-r8a7745 # RZ/G1E + - renesas,usb-phy-r8a77470 # RZ/G1C + - renesas,usb-phy-r8a7790 # R-Car H2 + - renesas,usb-phy-r8a7791 # R-Car M2-W + - renesas,usb-phy-r8a7794 # R-Car E2 + - const: renesas,rcar-gen2-usb-phy # R-Car Gen2 or RZ/G1 + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: usbhs + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +patternProperties: + "^usb-phy@[02]$": + type: object + description: Subnode corresponding to a USB channel. + + properties: + reg: + description: FIXME RZ/G1C supports channel 0 only + enum: [0, 2] + + '#phy-cells': + description: | + The phandle's argument in the PHY specifier is the USB controller + selector for the USB channel. + For RZ/G1C: + - 0 for EHCI/OHCI + - 1 for HS-USB + For all other SoCS: + - 0 for PCI EHCI/OHCI + - 1 for HS-USB (channel 0) or xHCI (channel 2) + const: 1 + + required: + - reg + - '#phy-cells' + + additionalProperties: false + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + - clocks + - clock-names + - resets + - power-domains + - usb-phy@0 + +if: + properties: + compatible: + contains: + const: renesas,usb-phy-r8a77470 +then: + properties: + usb-phy@2: false +else: + required: + - usb-phy@2 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r8a7790-cpg-mssr.h> + #include <dt-bindings/power/r8a7790-sysc.h> + usb-phy-controller@e6590100 { + compatible = "renesas,usb-phy-r8a7790", "renesas,rcar-gen2-usb-phy"; + reg = <0xe6590100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 704>; + + usb0: usb-phy@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-phy@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; diff --git a/dts/Bindings/phy/rockchip,pcie3-phy.yaml b/dts/Bindings/phy/rockchip,pcie3-phy.yaml new file mode 100644 index 0000000000..9f2d8d2cc7 --- /dev/null +++ b/dts/Bindings/phy/rockchip,pcie3-phy.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip PCIe v3 phy + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + enum: + - rockchip,rk3568-pcie3-phy + + reg: + maxItems: 1 + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + items: + - const: refclk_m + - const: refclk_n + - const: pclk + + data-lanes: + description: which lanes (by position) should be mapped to which + controller (value). 0 means lane disabled, higher value means used. + (controller-number +1 ) + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 16 + items: + minimum: 0 + maximum: 16 + + "#phy-cells": + const: 0 + + resets: + maxItems: 1 + + reset-names: + const: phy + + rockchip,phy-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the syscon managing the phy "general register files" + + rockchip,pipe-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the syscon managing the pipe "general register files" + +required: + - compatible + - reg + - rockchip,phy-grf + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3568-cru.h> + pcie30phy: phy@fe8c0000 { + compatible = "rockchip,rk3568-pcie3-phy"; + reg = <0xfe8c0000 0x20000>; + #phy-cells = <0>; + clocks = <&pmucru CLK_PCIE30PHY_REF_M>, + <&pmucru CLK_PCIE30PHY_REF_N>, + <&cru PCLK_PCIE30PHY>; + clock-names = "refclk_m", "refclk_n", "pclk"; + resets = <&cru SRST_PCIE30PHY>; + reset-names = "phy"; + rockchip,phy-grf = <&pcie30_phy_grf>; + }; diff --git a/dts/Bindings/phy/rockchip,px30-dsi-dphy.yaml b/dts/Bindings/phy/rockchip,px30-dsi-dphy.yaml index 8a3032a3bd..5c35e5ceec 100644 --- a/dts/Bindings/phy/rockchip,px30-dsi-dphy.yaml +++ b/dts/Bindings/phy/rockchip,px30-dsi-dphy.yaml @@ -18,6 +18,7 @@ properties: - rockchip,px30-dsi-dphy - rockchip,rk3128-dsi-dphy - rockchip,rk3368-dsi-dphy + - rockchip,rk3568-dsi-dphy reg: maxItems: 1 diff --git a/dts/Bindings/phy/rockchip-inno-csi-dphy.yaml b/dts/Bindings/phy/rockchip-inno-csi-dphy.yaml index bb4a2e4b8a..0e6505e9da 100644 --- a/dts/Bindings/phy/rockchip-inno-csi-dphy.yaml +++ b/dts/Bindings/phy/rockchip-inno-csi-dphy.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings +title: Rockchip SoC MIPI RX0 D-PHY maintainers: - Heiko Stuebner <heiko@sntech.de> @@ -20,6 +20,7 @@ properties: - rockchip,rk1808-csi-dphy - rockchip,rk3326-csi-dphy - rockchip,rk3368-csi-dphy + - rockchip,rk3568-csi-dphy reg: maxItems: 1 diff --git a/dts/Bindings/phy/rockchip-mipi-dphy-rx0.yaml b/dts/Bindings/phy/rockchip-mipi-dphy-rx0.yaml index 7d888d3588..5114e99b00 100644 --- a/dts/Bindings/phy/rockchip-mipi-dphy-rx0.yaml +++ b/dts/Bindings/phy/rockchip-mipi-dphy-rx0.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings +title: Rockchip SoC MIPI RX0 D-PHY maintainers: - Helen Koike <helen.koike@collabora.com> diff --git a/dts/Bindings/phy/samsung,exynos-pcie-phy.yaml b/dts/Bindings/phy/samsung,exynos-pcie-phy.yaml index ac0af40be5..28e299a960 100644 --- a/dts/Bindings/phy/samsung,exynos-pcie-phy.yaml +++ b/dts/Bindings/phy/samsung,exynos-pcie-phy.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/phy/samsung,exynos-pcie-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Samsung SoC series PCIe PHY Device Tree Bindings +title: Samsung SoC series PCIe PHY maintainers: - Marek Szyprowski <m.szyprowski@samsung.com> diff --git a/dts/Bindings/phy/samsung,ufs-phy.yaml b/dts/Bindings/phy/samsung,ufs-phy.yaml index 8da99461e8..c5dbb91ac4 100644 --- a/dts/Bindings/phy/samsung,ufs-phy.yaml +++ b/dts/Bindings/phy/samsung,ufs-phy.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Samsung SoC series UFS PHY Device Tree Bindings +title: Samsung SoC series UFS PHY maintainers: - Alim Akhtar <alim.akhtar@samsung.com> @@ -27,18 +27,12 @@ properties: - const: phy-pma clocks: - items: - - description: PLL reference clock - - description: symbol clock for input symbol ( rx0-ch0 symbol clock) - - description: symbol clock for input symbol ( rx1-ch1 symbol clock) - - description: symbol clock for output symbol ( tx0 symbol clock) + minItems: 1 + maxItems: 4 clock-names: - items: - - const: ref_clk - - const: rx1_symbol_clk - - const: rx0_symbol_clk - - const: tx0_symbol_clk + minItems: 1 + maxItems: 4 samsung,pmu-syscon: $ref: '/schemas/types.yaml#/definitions/phandle-array' @@ -62,6 +56,39 @@ required: - clock-names - samsung,pmu-syscon +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos7-ufs-phy + + then: + properties: + clocks: + items: + - description: PLL reference clock + - description: symbol clock for input symbol (rx0-ch0 symbol clock) + - description: symbol clock for input symbol (rx1-ch1 symbol clock) + - description: symbol clock for output symbol (tx0 symbol clock) + + clock-names: + items: + - const: ref_clk + - const: rx1_symbol_clk + - const: rx0_symbol_clk + - const: tx0_symbol_clk + + else: + properties: + clocks: + items: + - description: PLL reference clock + + clock-names: + items: + - const: ref_clk + additionalProperties: false examples: diff --git a/dts/Bindings/phy/sunplus,sp7021-usb2-phy.yaml b/dts/Bindings/phy/sunplus,sp7021-usb2-phy.yaml new file mode 100644 index 0000000000..069d422775 --- /dev/null +++ b/dts/Bindings/phy/sunplus,sp7021-usb2-phy.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/sunplus,sp7021-usb2-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Sunplus SP7021 USB 2.0 PHY Controller + +maintainers: + - Vincent Shih <vincent.sunplus@gmail.com> + +properties: + compatible: + const: sunplus,sp7021-usb2-phy + + reg: + items: + - description: UPHY register region + - description: MOON4 register region + + reg-names: + items: + - const: phy + - const: moon4 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + "#phy-cells": + const: 0 + + nvmem-cell-names: + description: names corresponding to the nvmem cells of disconnect voltage + const: disc_vol + + nvmem-cells: + description: nvmem cell address of disconnect voltage + maxItems: 1 + + sunplus,disc-vol-addr-off: + $ref: /schemas/types.yaml#/definitions/uint32 + description: the otp address offset of disconnect voltage + +required: + - compatible + - reg + - reg-names + - clocks + - resets + - "#phy-cells" + - nvmem-cell-names + - nvmem-cells + - sunplus,disc-vol-addr-off + +additionalProperties: false + +examples: + - | + sp_uphy0: usb-phy@9c004a80 { + compatible = "sunplus,sp7021-usb2-phy"; + reg = <0x9c004a80 0x80>, <0x9c000248 0x10>; + reg-names = "phy", "moon4"; + clocks = <&clkc 0x3d>; + resets = <&rstc 0x2d>; + #phy-cells = <0>; + nvmem-cell-names = "disc_vol"; + nvmem-cells = <&disc_vol>; + sunplus,disc-vol-addr-off = <0>; + }; diff --git a/dts/Bindings/phy/ti,phy-gmii-sel.yaml b/dts/Bindings/phy/ti,phy-gmii-sel.yaml index ff8a6d9eb1..da7cac537e 100644 --- a/dts/Bindings/phy/ti,phy-gmii-sel.yaml +++ b/dts/Bindings/phy/ti,phy-gmii-sel.yaml @@ -53,12 +53,25 @@ properties: - ti,am43xx-phy-gmii-sel - ti,dm814-phy-gmii-sel - ti,am654-phy-gmii-sel + - ti,j7200-cpsw5g-phy-gmii-sel reg: maxItems: 1 '#phy-cells': true + ti,qsgmii-main-ports: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + Required only for QSGMII mode. Array to select the port for + QSGMII main mode. Rest of the ports are selected as QSGMII_SUB + ports automatically. Any one of the 4 CPSW5G ports can act as the + main port with the rest of them being the QSGMII_SUB ports. + maxItems: 1 + items: + minimum: 1 + maximum: 4 + allOf: - if: properties: @@ -73,6 +86,18 @@ allOf: '#phy-cells': const: 1 description: CPSW port number (starting from 1) + + - if: + not: + properties: + compatible: + contains: + enum: + - ti,j7200-cpsw5g-phy-gmii-sel + then: + properties: + ti,qsgmii-main-ports: false + - if: properties: compatible: @@ -97,7 +122,7 @@ additionalProperties: false examples: - | - phy_gmii_sel: phy-gmii-sel@650 { + phy_gmii_sel: phy@650 { compatible = "ti,am3352-phy-gmii-sel"; reg = <0x650 0x4>; #phy-cells = <2>; diff --git a/dts/Bindings/phy/ti,phy-j721e-wiz.yaml b/dts/Bindings/phy/ti,phy-j721e-wiz.yaml index dcd63908ae..2225925b6d 100644 --- a/dts/Bindings/phy/ti,phy-j721e-wiz.yaml +++ b/dts/Bindings/phy/ti,phy-j721e-wiz.yaml @@ -16,19 +16,23 @@ properties: - ti,j721e-wiz-16g - ti,j721e-wiz-10g - ti,am64-wiz-10g + - ti,j7200-wiz-10g power-domains: maxItems: 1 clocks: - maxItems: 3 + minItems: 3 + maxItems: 4 description: clock-specifier to represent input to the WIZ clock-names: + minItems: 3 items: - const: fck - const: core_ref_clk - const: ext_ref_clk + - const: core_ref1_clk num-lanes: minimum: 1 @@ -79,10 +83,12 @@ properties: refclk-dig: type: object + additionalProperties: false description: | WIZ node should have subnode for refclk_dig to select the reference clock source for the reference clock used in the PHY and PMA digital logic. + deprecated: true properties: clocks: minItems: 2 @@ -105,12 +111,19 @@ properties: - assigned-clocks - assigned-clock-parents + ti,scm: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + phandle to System Control Module for syscon regmap access. + patternProperties: "^pll[0|1]-refclk$": type: object + additionalProperties: false description: | WIZ node should have subnodes for each of the PLLs present in the SERDES. + deprecated: true properties: clocks: maxItems: 2 @@ -133,9 +146,11 @@ patternProperties: "^cmn-refclk1?-dig-div$": type: object + additionalProperties: false description: WIZ node should have subnodes for each of the PMA common refclock provided by the SERDES. + deprecated: true properties: clocks: maxItems: 1 @@ -170,6 +185,16 @@ required: - "#reset-cells" - ranges +allOf: + - if: + properties: + compatible: + contains: + const: ti,j7200-wiz-10g + then: + required: + - ti,scm + additionalProperties: false examples: diff --git a/dts/Bindings/phy/xlnx,zynqmp-psgtr.yaml b/dts/Bindings/phy/xlnx,zynqmp-psgtr.yaml index 79906519c6..cefbc8b53a 100644 --- a/dts/Bindings/phy/xlnx,zynqmp-psgtr.yaml +++ b/dts/Bindings/phy/xlnx,zynqmp-psgtr.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Xilinx ZynqMP Gigabit Transceiver PHY Device Tree Bindings +title: Xilinx ZynqMP Gigabit Transceiver PHY maintainers: - Laurent Pinchart <laurent.pinchart@ideasonboard.com> diff --git a/dts/Bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/dts/Bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml index d19d65c870..1e3c8de6ca 100644 --- a/dts/Bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +++ b/dts/Bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/allwinner,sun4i-a10-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Pin Controller Device Tree Bindings +title: Allwinner A10 Pin Controller maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/pinctrl/aspeed,ast2400-pinctrl.yaml b/dts/Bindings/pinctrl/aspeed,ast2400-pinctrl.yaml index d3a8911728..f4f1ee6b11 100644 --- a/dts/Bindings/pinctrl/aspeed,ast2400-pinctrl.yaml +++ b/dts/Bindings/pinctrl/aspeed,ast2400-pinctrl.yaml @@ -63,6 +63,12 @@ examples: syscon: scu@1e6e2000 { compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; reg = <0x1e6e2000 0x1a8>; + #clock-cells = <1>; + #reset-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e6e2000 0x1000>; pinctrl: pinctrl { compatible = "aspeed,ast2400-pinctrl"; diff --git a/dts/Bindings/pinctrl/aspeed,ast2500-pinctrl.yaml b/dts/Bindings/pinctrl/aspeed,ast2500-pinctrl.yaml index 5d2c1b1fb7..8168f00884 100644 --- a/dts/Bindings/pinctrl/aspeed,ast2500-pinctrl.yaml +++ b/dts/Bindings/pinctrl/aspeed,ast2500-pinctrl.yaml @@ -82,6 +82,10 @@ examples: #clock-cells = <1>; #reset-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e6e2000 0x1000>; + pinctrl: pinctrl { compatible = "aspeed,ast2500-pinctrl"; aspeed,external-nodes = <&gfx>, <&lhc>; diff --git a/dts/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml b/dts/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml index e92686d2f0..62424c42c9 100644 --- a/dts/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml +++ b/dts/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml @@ -96,6 +96,12 @@ examples: syscon: scu@1e6e2000 { compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd"; reg = <0x1e6e2000 0xf6c>; + #clock-cells = <1>; + #reset-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e6e2000 0x1000>; pinctrl: pinctrl { compatible = "aspeed,ast2600-pinctrl"; diff --git a/dts/Bindings/pinctrl/brcm,bcm4908-pinctrl.yaml b/dts/Bindings/pinctrl/brcm,bcm4908-pinctrl.yaml index 175a992f15..8a9fb9b433 100644 --- a/dts/Bindings/pinctrl/brcm,bcm4908-pinctrl.yaml +++ b/dts/Bindings/pinctrl/brcm,bcm4908-pinctrl.yaml @@ -23,6 +23,7 @@ patternProperties: '-pins$': type: object $ref: pinmux-node.yaml# + additionalProperties: false properties: function: diff --git a/dts/Bindings/pinctrl/canaan,k210-fpioa.yaml b/dts/Bindings/pinctrl/canaan,k210-fpioa.yaml index 533b4cfe33..a78cb27960 100644 --- a/dts/Bindings/pinctrl/canaan,k210-fpioa.yaml +++ b/dts/Bindings/pinctrl/canaan,k210-fpioa.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/canaan,k210-fpioa.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Canaan Kendryte K210 FPIOA Device Tree Bindings +title: Canaan Kendryte K210 FPIOA maintainers: - Damien Le Moal <damien.lemoal@wdc.com> diff --git a/dts/Bindings/pinctrl/cypress,cy8c95x0.yaml b/dts/Bindings/pinctrl/cypress,cy8c95x0.yaml new file mode 100644 index 0000000000..915cbbcc35 --- /dev/null +++ b/dts/Bindings/pinctrl/cypress,cy8c95x0.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/cypress,cy8c95x0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cypress CY8C95X0 I2C GPIO expander + +maintainers: + - Patrick Rudolph <patrick.rudolph@9elements.com> + +description: | + This supports the 20/40/60 pin Cypress CYC95x0 GPIO I2C expanders. + Pin function configuration is performed on a per-pin basis. + +properties: + compatible: + enum: + - cypress,cy8c9520 + - cypress,cy8c9540 + - cypress,cy8c9560 + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + description: + The first cell is the GPIO number and the second cell specifies GPIO + flags, as defined in <dt-bindings/gpio/gpio.h>. + const: 2 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-line-names: true + + gpio-ranges: + maxItems: 1 + + gpio-reserved-ranges: + maxItems: 1 + + vdd-supply: + description: + Optional power supply. + +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: pincfg-node.yaml# + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: '^gp([0-7][0-7])$' + minItems: 1 + maxItems: 60 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, pwm ] + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + drive-push-pull: true + + drive-open-drain: true + + drive-open-source: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +allOf: + - $ref: "pinctrl.yaml#" + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pinctrl@20 { + compatible = "cypress,cy8c9520"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + vdd-supply = <&p3v3>; + gpio-reserved-ranges = <5 1>; + }; + }; diff --git a/dts/Bindings/pinctrl/intel,pinctrl-keembay.yaml b/dts/Bindings/pinctrl/intel,pinctrl-keembay.yaml index 5e99d79499..005d95a9e4 100644 --- a/dts/Bindings/pinctrl/intel,pinctrl-keembay.yaml +++ b/dts/Bindings/pinctrl/intel,pinctrl-keembay.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Intel Keem Bay pin controller Device Tree Bindings +title: Intel Keem Bay pin controller maintainers: - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> @@ -44,6 +44,7 @@ properties: patternProperties: '^gpio@[0-9a-f]*$': type: object + additionalProperties: false description: Child nodes can be specified to contain pin configuration information, diff --git a/dts/Bindings/pinctrl/intel,pinctrl-thunderbay.yaml b/dts/Bindings/pinctrl/intel,pinctrl-thunderbay.yaml index 0ec476248f..f001add168 100644 --- a/dts/Bindings/pinctrl/intel,pinctrl-thunderbay.yaml +++ b/dts/Bindings/pinctrl/intel,pinctrl-thunderbay.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-thunderbay.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Intel Thunder Bay pin controller Device Tree Bindings +title: Intel Thunder Bay pin controller maintainers: - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> @@ -42,6 +42,7 @@ properties: patternProperties: '^gpio@[0-9a-f]*$': type: object + additionalProperties: false description: Child nodes can be specified to contain pin configuration information, diff --git a/dts/Bindings/pinctrl/marvell,ac5-pinctrl.yaml b/dts/Bindings/pinctrl/marvell,ac5-pinctrl.yaml index a651b2744c..491f67e7cc 100644 --- a/dts/Bindings/pinctrl/marvell,ac5-pinctrl.yaml +++ b/dts/Bindings/pinctrl/marvell,ac5-pinctrl.yaml @@ -24,6 +24,7 @@ patternProperties: '-pins$': type: object $ref: pinmux-node.yaml# + additionalProperties: false properties: marvell,function: diff --git a/dts/Bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/dts/Bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml index 161088a8be..33b5f79e74 100644 --- a/dts/Bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/dts/Bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT65xx Pin Controller Device Tree Bindings +title: Mediatek MT65xx Pin Controller maintainers: - Sean Wang <sean.wang@kernel.org> diff --git a/dts/Bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/dts/Bindings/pinctrl/mediatek,mt6779-pinctrl.yaml index e7601c0f5a..8c79fcef7c 100644 --- a/dts/Bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/dts/Bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT6779 Pin Controller Device Tree Bindings +title: Mediatek MT6779 Pin Controller maintainers: - Andy Teng <andy.teng@mediatek.com> @@ -76,6 +76,8 @@ required: patternProperties: '-[0-9]*$': type: object + additionalProperties: false + patternProperties: '-pins*$': type: object diff --git a/dts/Bindings/pinctrl/mediatek,mt6797-pinctrl.yaml b/dts/Bindings/pinctrl/mediatek,mt6797-pinctrl.yaml index d42215f59a..637a8386e2 100644 --- a/dts/Bindings/pinctrl/mediatek,mt6797-pinctrl.yaml +++ b/dts/Bindings/pinctrl/mediatek,mt6797-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6797-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT6797 Pin Controller Device Tree Bindings +title: Mediatek MT6797 Pin Controller maintainers: - Sean Wang <sean.wang@kernel.org> diff --git a/dts/Bindings/pinctrl/mediatek,mt7622-pinctrl.yaml b/dts/Bindings/pinctrl/mediatek,mt7622-pinctrl.yaml index 78a0175cec..c9ea0cad48 100644 --- a/dts/Bindings/pinctrl/mediatek,mt7622-pinctrl.yaml +++ b/dts/Bindings/pinctrl/mediatek,mt7622-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7622-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT7622 Pin Controller Device Tree Bindings +title: Mediatek MT7622 Pin Controller maintainers: - Sean Wang <sean.wang@kernel.org> diff --git a/dts/Bindings/pinctrl/mediatek,mt7986-pinctrl.yaml b/dts/Bindings/pinctrl/mediatek,mt7986-pinctrl.yaml index 4eadea55df..89b8f3dd67 100644 --- a/dts/Bindings/pinctrl/mediatek,mt7986-pinctrl.yaml +++ b/dts/Bindings/pinctrl/mediatek,mt7986-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7986-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT7986 Pin Controller Device Tree Bindings +title: Mediatek MT7986 Pin Controller maintainers: - Sean Wang <sean.wang@kernel.org> @@ -117,6 +117,10 @@ patternProperties: "i2s" "audio" 62, 63, 64, 65 "switch_int" "eth" 66 "mdc_mdio" "eth" 67 + "wf_2g" "wifi" 74, 75, 76, 77, 78, 79, 80, 81, 82, 83 + "wf_5g" "wifi" 91, 92, 93, 94, 95, 96, 97, 98, 99, 100 + "wf_dbdc" "wifi" 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, + 84, 85 $ref: "/schemas/pinctrl/pinmux-node.yaml" properties: @@ -234,7 +238,9 @@ patternProperties: then: properties: groups: - enum: [wf_2g, wf_5g, wf_dbdc] + items: + enum: [wf_2g, wf_5g, wf_dbdc] + maxItems: 3 '.*conf.*': type: object additionalProperties: false @@ -248,25 +254,27 @@ patternProperties: An array of strings. Each string contains the name of a pin. There is no PIN 41 to PIN 65 above on mt7686b, you can only use those pins on mt7986a. - enum: [SYS_WATCHDOG, WF2G_LED, WF5G_LED, I2C_SCL, I2C_SDA, GPIO_0, - GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, GPIO_7, - GPIO_8, GPIO_9, GPIO_10, GPIO_11, GPIO_12, GPIO_13, GPIO_14, - GPIO_15, PWM0, PWM1, SPI0_CLK, SPI0_MOSI, SPI0_MISO, SPI0_CS, - SPI0_HOLD, SPI0_WP, SPI1_CLK, SPI1_MOSI, SPI1_MISO, SPI1_CS, - SPI2_CLK, SPI2_MOSI, SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP, - UART0_RXD, UART0_TXD, PCIE_PERESET_N, UART1_RXD, UART1_TXD, - UART1_CTS, UART1_RTS, UART2_RXD, UART2_TXD, UART2_CTS, - UART2_RTS, EMMC_DATA_0, EMMC_DATA_1, EMMC_DATA_2, - EMMC_DATA_3, EMMC_DATA_4, EMMC_DATA_5, EMMC_DATA_6, - EMMC_DATA_7, EMMC_CMD, EMMC_CK, EMMC_DSL, EMMC_RSTB, PCM_DTX, - PCM_DRX, PCM_CLK, PCM_FS, MT7531_INT, SMI_MDC, SMI_MDIO, - WF0_DIG_RESETB, WF0_CBA_RESETB, WF0_XO_REQ, WF0_TOP_CLK, - WF0_TOP_DATA, WF0_HB1, WF0_HB2, WF0_HB3, WF0_HB4, WF0_HB0, - WF0_HB0_B, WF0_HB5, WF0_HB6, WF0_HB7, WF0_HB8, WF0_HB9, - WF0_HB10, WF1_DIG_RESETB, WF1_CBA_RESETB, WF1_XO_REQ, - WF1_TOP_CLK, WF1_TOP_DATA, WF1_HB1, WF1_HB2, WF1_HB3, - WF1_HB4, WF1_HB0, WF1_HB0_B, WF1_HB5, WF1_HB6, WF1_HB7, - WF1_HB8] + items: + enum: [SYS_WATCHDOG, WF2G_LED, WF5G_LED, I2C_SCL, I2C_SDA, GPIO_0, + GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, GPIO_7, + GPIO_8, GPIO_9, GPIO_10, GPIO_11, GPIO_12, GPIO_13, GPIO_14, + GPIO_15, PWM0, PWM1, SPI0_CLK, SPI0_MOSI, SPI0_MISO, SPI0_CS, + SPI0_HOLD, SPI0_WP, SPI1_CLK, SPI1_MOSI, SPI1_MISO, SPI1_CS, + SPI2_CLK, SPI2_MOSI, SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP, + UART0_RXD, UART0_TXD, PCIE_PERESET_N, UART1_RXD, UART1_TXD, + UART1_CTS, UART1_RTS, UART2_RXD, UART2_TXD, UART2_CTS, + UART2_RTS, EMMC_DATA_0, EMMC_DATA_1, EMMC_DATA_2, + EMMC_DATA_3, EMMC_DATA_4, EMMC_DATA_5, EMMC_DATA_6, + EMMC_DATA_7, EMMC_CMD, EMMC_CK, EMMC_DSL, EMMC_RSTB, PCM_DTX, + PCM_DRX, PCM_CLK, PCM_FS, MT7531_INT, SMI_MDC, SMI_MDIO, + WF0_DIG_RESETB, WF0_CBA_RESETB, WF0_XO_REQ, WF0_TOP_CLK, + WF0_TOP_DATA, WF0_HB1, WF0_HB2, WF0_HB3, WF0_HB4, WF0_HB0, + WF0_HB0_B, WF0_HB5, WF0_HB6, WF0_HB7, WF0_HB8, WF0_HB9, + WF0_HB10, WF1_DIG_RESETB, WF1_CBA_RESETB, WF1_XO_REQ, + WF1_TOP_CLK, WF1_TOP_DATA, WF1_HB1, WF1_HB2, WF1_HB3, + WF1_HB4, WF1_HB0, WF1_HB0_B, WF1_HB5, WF1_HB6, WF1_HB7, + WF1_HB8] + maxItems: 101 bias-disable: true diff --git a/dts/Bindings/pinctrl/mediatek,mt8183-pinctrl.yaml b/dts/Bindings/pinctrl/mediatek,mt8183-pinctrl.yaml index 2d13a57b89..0d2484056a 100644 --- a/dts/Bindings/pinctrl/mediatek,mt8183-pinctrl.yaml +++ b/dts/Bindings/pinctrl/mediatek,mt8183-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8183-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT8183 Pin Controller Device Tree Bindings +title: Mediatek MT8183 Pin Controller maintainers: - Sean Wang <sean.wang@kernel.org> diff --git a/dts/Bindings/pinctrl/mediatek,mt8188-pinctrl.yaml b/dts/Bindings/pinctrl/mediatek,mt8188-pinctrl.yaml new file mode 100644 index 0000000000..7e750f1e64 --- /dev/null +++ b/dts/Bindings/pinctrl/mediatek,mt8188-pinctrl.yaml @@ -0,0 +1,226 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8188-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8188 Pin Controller + +maintainers: + - Hui Liu <hui.liu@mediatek.com> + +description: | + The MediaTek's MT8188 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8188-pinctrl + + gpio-controller: true + + '#gpio-cells': + description: | + Number of cells in GPIO specifier, should be two. The first cell + is the pin number, the second cell is used to specify optional + parameters which are defined in <dt-bindings/gpio/gpio.h>. + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-line-names: true + + reg: + items: + - description: gpio registers base address + - description: rm group io configuration registers base address + - description: lt group io configuration registers base address + - description: lm group io configuration registers base address + - description: rt group io configuration registers base address + - description: eint registers base address + + reg-names: + items: + - const: iocfg0 + - const: iocfg_rm + - const: iocfg_lt + - const: iocfg_lm + - const: iocfg_rt + - const: eint + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + description: The interrupt outputs to sysirq. + maxItems: 1 + + mediatek,rsel-resistance-in-si-unit: + type: boolean + description: | + We provide two methods to select the resistance for I2C when pull up or pull down. + The first is by RSEL definition value, another one is by resistance value(ohm). + This flag is used to identify if the method is resistance(si unit) value. + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^pins': + type: object + $ref: "/schemas/pinctrl/pincfg-node.yaml" + additionalProperties: false + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and + input schmitt. + + properties: + pinmux: + description: | + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in dt-bindings/pinctrl/mediatek,<soc>-pinfunc.h + directly. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + drive-strength-microamp: + enum: [125, 250, 500, 1000] + + bias-pull-down: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8188 pull down PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203, 204, 205, 206, 207] + description: mt8188 pull down RSEL type define value. + - enum: [75000, 5000] + description: mt8188 pull down RSEL type si unit value(ohm). + description: | + For pull down type is normal, it doesn't need add RSEL & R1R0 define + and resistance value. + For pull down type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_SET_R1R0_11" + define in mt8188. + For pull down type is RSEL, it can add RSEL define & resistance value(ohm) + to set different resistance by identifying property "mediatek,rsel-resistance-in-si-unit". + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" + & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_PULL_SET_RSEL_100" + & "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" + define in mt8188. It can also support resistance value(ohm) "75000" & "5000" in mt8188. + + bias-pull-up: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8188 pull up PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203, 204, 205, 206, 207] + description: mt8188 pull up RSEL type define value. + - enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000] + description: mt8188 pull up RSEL type si unit value(ohm). + description: | + For pull up type is normal, it don't need add RSEL & R1R0 define + and resistance value. + For pull up type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_SET_R1R0_11" + define in mt8188. + For pull up type is RSEL, it can add RSEL define & resistance value(ohm) + to set different resistance by identifying property "mediatek,rsel-resistance-in-si-unit". + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" + & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_PULL_SET_RSEL_100" + & "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" + define in mt8188. It can also support resistance value(ohm) + "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" & "75000" in mt8188. + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8188-pinctrl"; + reg = <0x10005000 0x1000>, + <0x11c00000 0x1000>, + <0x11e10000 0x1000>, + <0x11e20000 0x1000>, + <0x11ea0000 0x1000>, + <0x1000b000 0x1000>; + reg-names = "iocfg0", "iocfg_rm", + "iocfg_lt", "iocfg_lm", "iocfg_rt", + "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 176>; + interrupt-controller; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>; + #interrupt-cells = <2>; + + pio-pins { + pins { + pinmux = <PINMUX_GPIO0__FUNC_B_GPIO0>; + output-low; + }; + }; + + spi0-pins { + pins-spi { + pinmux = <PINMUX_GPIO75__FUNC_O_SPIM1_CSB>, + <PINMUX_GPIO76__FUNC_O_SPIM1_CLK>, + <PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI>; + drive-strength = <6>; + }; + pins-spi-mi { + pinmux = <PINMUX_GPIO78__FUNC_B0_SPIM1_MISO>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + }; + + i2c0-pins { + pins { + pinmux = <PINMUX_GPIO55__FUNC_B1_SCL0>, + <PINMUX_GPIO56__FUNC_B1_SDA0>; + bias-disable; + drive-strength-microamp = <1000>; + }; + }; + }; diff --git a/dts/Bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml b/dts/Bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml index 7a11beb8f2..7b7f840ffc 100644 --- a/dts/Bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml +++ b/dts/Bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml @@ -30,6 +30,7 @@ patternProperties: "^gpio@[0-7]$": type: object + additionalProperties: false description: Eight GPIO banks (gpio@0 to gpio@7), that each contain between 14 and 18 diff --git a/dts/Bindings/pinctrl/pinctrl-mt8186.yaml b/dts/Bindings/pinctrl/pinctrl-mt8186.yaml index 1eeb885ce0..26573a793b 100644 --- a/dts/Bindings/pinctrl/pinctrl-mt8186.yaml +++ b/dts/Bindings/pinctrl/pinctrl-mt8186.yaml @@ -41,12 +41,12 @@ properties: Gpio base register names. items: - const: iocfg0 - - const: iocfg_bm - - const: iocfg_bl - - const: iocfg_br + - const: iocfg_lt - const: iocfg_lm + - const: iocfg_lb + - const: iocfg_bl - const: iocfg_rb - - const: iocfg_tl + - const: iocfg_rt - const: eint interrupt-controller: true @@ -235,9 +235,9 @@ examples: <0x10002A00 0x0200>, <0x10002c00 0x0200>, <0x1000b000 0x1000>; - reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", - "iocfg_br", "iocfg_lm", "iocfg_rb", - "iocfg_tl", "eint"; + reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", + "iocfg_lb", "iocfg_bl", "iocfg_rb", + "iocfg_rt", "eint"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pio 0 0 185>; diff --git a/dts/Bindings/pinctrl/qcom,pmic-gpio.yaml b/dts/Bindings/pinctrl/qcom,pmic-gpio.yaml index 694898f382..29dd503f95 100644 --- a/dts/Bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/dts/Bindings/pinctrl/qcom,pmic-gpio.yaml @@ -24,6 +24,7 @@ properties: - qcom,pm6150-gpio - qcom,pm6150l-gpio - qcom,pm6350-gpio + - qcom,pm7250b-gpio - qcom,pm7325-gpio - qcom,pm8005-gpio - qcom,pm8008-gpio @@ -231,6 +232,7 @@ allOf: enum: - qcom,pm660l-gpio - qcom,pm6150l-gpio + - qcom,pm7250b-gpio - qcom,pm8038-gpio - qcom,pm8150b-gpio - qcom,pm8150l-gpio @@ -392,6 +394,7 @@ $defs: - gpio1-gpio10 for pm6150 - gpio1-gpio12 for pm6150l - gpio1-gpio9 for pm6350 + - gpio1-gpio12 for pm7250b - gpio1-gpio10 for pm7325 - gpio1-gpio4 for pm8005 - gpio1-gpio2 for pm8008 @@ -407,6 +410,7 @@ $defs: - gpio1-gpio10 for pm8350 - gpio1-gpio8 for pm8350b - gpio1-gpio9 for pm8350c + - gpio1-gpio4 for pm8450 - gpio1-gpio38 for pm8917 - gpio1-gpio44 for pm8921 - gpio1-gpio36 for pm8941 diff --git a/dts/Bindings/pinctrl/qcom,sc7280-pinctrl.yaml b/dts/Bindings/pinctrl/qcom,sc7280-pinctrl.yaml index 2bd60c49a4..ad34967846 100644 --- a/dts/Bindings/pinctrl/qcom,sc7280-pinctrl.yaml +++ b/dts/Bindings/pinctrl/qcom,sc7280-pinctrl.yaml @@ -42,6 +42,9 @@ properties: gpio-ranges: maxItems: 1 + gpio-line-names: + maxItems: 174 + wakeup-parent: true #PIN CONFIGURATION NODES @@ -51,7 +54,6 @@ patternProperties: description: Pinctrl node's client devices use subnodes for desired pin configuration. Client device subnodes use below standard properties. - $ref: "/schemas/pinctrl/pincfg-node.yaml" properties: pins: @@ -60,7 +62,7 @@ patternProperties: subnode. items: oneOf: - - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-4])$" + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-2])$" - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] minItems: 1 @@ -118,12 +120,21 @@ patternProperties: required: - pins - - function + + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - if: + properties: + pins: + pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-2])$" + then: + required: + - function additionalProperties: false allOf: - - $ref: "pinctrl.yaml#" + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# required: - compatible @@ -139,22 +150,22 @@ additionalProperties: false examples: - | - #include <dt-bindings/interrupt-controller/arm-gic.h> - tlmm: pinctrl@f000000 { - compatible = "qcom,sc7280-pinctrl"; - reg = <0xf000000 0x1000000>; - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 175>; - wakeup-parent = <&pdc>; - - qup_uart5_default: qup-uart5-pins { - pins = "gpio46", "gpio47"; - function = "qup13"; - drive-strength = <2>; - bias-disable; - }; + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@f000000 { + compatible = "qcom,sc7280-pinctrl"; + reg = <0xf000000 0x1000000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 175>; + wakeup-parent = <&pdc>; + + qup_uart5_default: qup-uart5-pins { + pins = "gpio46", "gpio47"; + function = "qup13"; + drive-strength = <2>; + bias-disable; }; + }; diff --git a/dts/Bindings/pinctrl/qcom,sc8180x-pinctrl.yaml b/dts/Bindings/pinctrl/qcom,sc8180x-pinctrl.yaml index 8650917260..b98eeba2c5 100644 --- a/dts/Bindings/pinctrl/qcom,sc8180x-pinctrl.yaml +++ b/dts/Bindings/pinctrl/qcom,sc8180x-pinctrl.yaml @@ -51,8 +51,9 @@ patternProperties: oneOf: - $ref: "#/$defs/qcom-sc8180x-tlmm-state" - patternProperties: - ".*": + "-pins$": $ref: "#/$defs/qcom-sc8180x-tlmm-state" + additionalProperties: false '$defs': qcom-sc8180x-tlmm-state: @@ -60,7 +61,6 @@ patternProperties: description: Pinctrl node's client devices use subnodes for desired pin configuration. Client device subnodes use below standard properties. - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" properties: pins: @@ -111,43 +111,52 @@ patternProperties: required: - pins - - function + + allOf: + - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + - if: + properties: + pins: + pattern: "^gpio([0-9]|[1-9][0-9]|1[0-8][0-9])$" + then: + required: + - function additionalProperties: false examples: - | - #include <dt-bindings/interrupt-controller/arm-gic.h> - pinctrl@3100000 { - compatible = "qcom,sc8180x-tlmm"; - reg = <0x03100000 0x300000>, - <0x03500000 0x700000>, - <0x03d00000 0x300000>; - reg-names = "west", "east", "south"; - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 190>; - - gpio-wo-subnode-state { - pins = "gpio1"; - function = "gpio"; - }; - - uart-w-subnodes-state { - rx { - pins = "gpio4"; - function = "qup6"; - bias-pull-up; - }; - - tx { - pins = "gpio5"; - function = "qup6"; - bias-disable; - }; - }; + #include <dt-bindings/interrupt-controller/arm-gic.h> + pinctrl@3100000 { + compatible = "qcom,sc8180x-tlmm"; + reg = <0x03100000 0x300000>, + <0x03500000 0x700000>, + <0x03d00000 0x300000>; + reg-names = "west", "east", "south"; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 190>; + + gpio-wo-subnode-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-subnodes-state { + rx-pins { + pins = "gpio4"; + function = "qup6"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio5"; + function = "qup6"; + bias-disable; + }; }; + }; ... diff --git a/dts/Bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml b/dts/Bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml new file mode 100644 index 0000000000..1f468303bb --- /dev/null +++ b/dts/Bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS) + Low Power Island (LPI) TLMM block + +maintainers: + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + LPASS LPI IP on most Qualcomm SoCs + +properties: + compatible: + const: qcom,sc8280xp-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + - description: LPASS LPI pins SLEW registers + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-1]|1[0-8]])$" + + function: + enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data, + dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic4_clk, + dmic4_data, i2s2_clk, i2s2_ws, dmic3_clk, dmic3_data, + qua_mi2s_sclk, qua_mi2s_ws, qua_mi2s_data, i2s1_clk, i2s1_ws, + i2s1_data, wsa_swr_clk, wsa_swr_data, wsa2_swr_clk, + wsa2_swr_data, i2s2_data, i2s3_clk, i2s3_ws, i2s3_data, + ext_mclk1_c, ext_mclk1_b, ext_mclk1_a ] + description: + Specify the alternative function to be configured for the specified + pins. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + slew-rate: + enum: [0, 1, 2, 3] + default: 0 + description: | + 0: No adjustments + 1: Higher Slew rate (faster edges) + 2: Lower Slew rate (slower edges) + 3: Reserved (No adjustments) + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/sound/qcom,q6afe.h> + pinctrl@33c0000 { + compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; + reg = <0x33c0000 0x20000>, + <0x3550000 0x10000>; + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpi_tlmm 0 0 18>; + }; diff --git a/dts/Bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml b/dts/Bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml index 87a381c9a1..b9ab130cd5 100644 --- a/dts/Bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml +++ b/dts/Bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml @@ -43,8 +43,9 @@ patternProperties: oneOf: - $ref: "#/$defs/qcom-sc8280xp-tlmm-state" - patternProperties: - ".*": + "-pins$": $ref: "#/$defs/qcom-sc8280xp-tlmm-state" + additionalProperties: false '$defs': qcom-sc8280xp-tlmm-state: @@ -52,7 +53,6 @@ patternProperties: description: Pinctrl node's client devices use subnodes for desired pin configuration. Client device subnodes use below standard properties. - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" properties: pins: @@ -112,40 +112,49 @@ patternProperties: required: - pins - - function + + allOf: + - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + - if: + properties: + pins: + pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-1][0-9]|22[0-7])$" + then: + required: + - function additionalProperties: false examples: - | - #include <dt-bindings/interrupt-controller/arm-gic.h> - pinctrl@f100000 { - compatible = "qcom,sc8280xp-tlmm"; - reg = <0x0f100000 0x300000>; - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 230>; - - gpio-wo-subnode-state { - pins = "gpio1"; - function = "gpio"; - }; - - uart-w-subnodes-state { - rx { - pins = "gpio4"; - function = "qup14"; - bias-pull-up; - }; - - tx { - pins = "gpio5"; - function = "qup14"; - bias-disable; - }; - }; + #include <dt-bindings/interrupt-controller/arm-gic.h> + pinctrl@f100000 { + compatible = "qcom,sc8280xp-tlmm"; + reg = <0x0f100000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 230>; + + gpio-wo-subnode-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-subnodes-state { + rx-pins { + pins = "gpio4"; + function = "qup14"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio5"; + function = "qup14"; + bias-disable; + }; }; + }; ... diff --git a/dts/Bindings/pinctrl/qcom,sm6115-pinctrl.yaml b/dts/Bindings/pinctrl/qcom,sm6115-pinctrl.yaml index a7a2bb8bff..e39fbb36d8 100644 --- a/dts/Bindings/pinctrl/qcom,sm6115-pinctrl.yaml +++ b/dts/Bindings/pinctrl/qcom,sm6115-pinctrl.yaml @@ -49,6 +49,8 @@ properties: gpio-ranges: maxItems: 1 + gpio-reserved-ranges: true + wakeup-parent: true #PIN CONFIGURATION NODES @@ -57,8 +59,9 @@ patternProperties: oneOf: - $ref: "#/$defs/qcom-sm6115-tlmm-state" - patternProperties: - ".*": + "-pins$": $ref: "#/$defs/qcom-sm6115-tlmm-state" + additionalProperties: false '$defs': qcom-sm6115-tlmm-state: @@ -66,7 +69,6 @@ patternProperties: description: Pinctrl node's client devices use subnodes for desired pin configuration. Client device subnodes use below standard properties. - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" properties: pins: @@ -118,6 +120,16 @@ patternProperties: required: - pins + allOf: + - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + - if: + properties: + pins: + pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$" + then: + required: + - function + additionalProperties: false allOf: @@ -138,44 +150,44 @@ additionalProperties: false examples: - | - #include <dt-bindings/interrupt-controller/arm-gic.h> - tlmm: pinctrl@500000 { - compatible = "qcom,sm6115-tlmm"; - reg = <0x500000 0x400000>, - <0x900000 0x400000>, - <0xd00000 0x400000>; - reg-names = "west", "south", "east"; - interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 114>; - - sdc2_on_state: sdc2-on-state { - clk { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <16>; - }; - - cmd { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - data { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <10>; - }; - - sd-cd { - pins = "gpio88"; - function = "gpio"; - bias-pull-up; - drive-strength = <2>; - }; - }; + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@500000 { + compatible = "qcom,sm6115-tlmm"; + reg = <0x500000 0x400000>, + <0x900000 0x400000>, + <0xd00000 0x400000>; + reg-names = "west", "south", "east"; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 114>; + + sdc2_on_state: sdc2-on-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd-pins { + pins = "gpio88"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; }; + }; diff --git a/dts/Bindings/pinctrl/qcom,sm6125-pinctrl.yaml b/dts/Bindings/pinctrl/qcom,sm6125-pinctrl.yaml index c8eec845ad..5cb8b272cb 100644 --- a/dts/Bindings/pinctrl/qcom,sm6125-pinctrl.yaml +++ b/dts/Bindings/pinctrl/qcom,sm6125-pinctrl.yaml @@ -51,8 +51,9 @@ patternProperties: oneOf: - $ref: "#/$defs/qcom-sm6125-tlmm-state" - patternProperties: - ".*": + "-pins$": $ref: "#/$defs/qcom-sm6125-tlmm-state" + additionalProperties: false $defs: qcom-sm6125-tlmm-state: @@ -60,7 +61,6 @@ $defs: description: Pinctrl node's client devices use subnodes for desired pin configuration. Client device subnodes use below standard properties. - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" properties: pins: @@ -111,23 +111,52 @@ $defs: required: - pins - - function + + allOf: + - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + - if: + properties: + pins: + pattern: "^gpio[0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2]$" + then: + required: + - function additionalProperties: false examples: - | - #include <dt-bindings/interrupt-controller/arm-gic.h> - pinctrl@500000 { - compatible = "qcom,sm6125-tlmm"; - reg = <0x00500000 0x400000>, - <0x00900000 0x400000>, - <0x00d00000 0x400000>; - reg-names = "west", "south", "east"; - interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - gpio-ranges = <&tlmm 0 0 134>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; + #include <dt-bindings/interrupt-controller/arm-gic.h> + pinctrl@500000 { + compatible = "qcom,sm6125-tlmm"; + reg = <0x00500000 0x400000>, + <0x00900000 0x400000>, + <0x00d00000 0x400000>; + reg-names = "west", "south", "east"; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + gpio-ranges = <&tlmm 0 0 134>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + sdc2-off-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; }; + }; diff --git a/dts/Bindings/pinctrl/qcom,sm6350-pinctrl.yaml b/dts/Bindings/pinctrl/qcom,sm6350-pinctrl.yaml index 898608671c..856b9c567e 100644 --- a/dts/Bindings/pinctrl/qcom,sm6350-pinctrl.yaml +++ b/dts/Bindings/pinctrl/qcom,sm6350-pinctrl.yaml @@ -44,8 +44,9 @@ patternProperties: oneOf: - $ref: "#/$defs/qcom-sm6350-tlmm-state" - patternProperties: - ".*": + "-pins$": $ref: "#/$defs/qcom-sm6350-tlmm-state" + additionalProperties: false $defs: qcom-sm6350-tlmm-state: @@ -53,7 +54,6 @@ $defs: description: Pinctrl node's client devices use subnodes for desired pin configuration. Client device subnodes use below standard properties. - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" properties: pins: @@ -110,40 +110,49 @@ $defs: required: - pins - - function + + allOf: + - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + - if: + properties: + pins: + pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-7])$" + then: + required: + - function additionalProperties: false examples: - | - #include <dt-bindings/interrupt-controller/arm-gic.h> - pinctrl@f100000 { - compatible = "qcom,sm6350-tlmm"; - reg = <0x0f100000 0x300000>; - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 157>; - - gpio-wo-subnode-state { - pins = "gpio1"; - function = "gpio"; - }; - - uart-w-subnodes-state { - rx { - pins = "gpio25"; - function = "qup13_f2"; - bias-disable; - }; - - tx { - pins = "gpio26"; - function = "qup13_f2"; - bias-disable; - }; - }; + #include <dt-bindings/interrupt-controller/arm-gic.h> + pinctrl@f100000 { + compatible = "qcom,sm6350-tlmm"; + reg = <0x0f100000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 157>; + + gpio-wo-subnode-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-subnodes-state { + rx-pins { + pins = "gpio25"; + function = "qup13_f2"; + bias-disable; + }; + + tx-pins { + pins = "gpio26"; + function = "qup13_f2"; + bias-disable; + }; }; + }; ... diff --git a/dts/Bindings/pinctrl/qcom,sm6375-tlmm.yaml b/dts/Bindings/pinctrl/qcom,sm6375-tlmm.yaml index 3908807a83..025faf87d1 100644 --- a/dts/Bindings/pinctrl/qcom,sm6375-tlmm.yaml +++ b/dts/Bindings/pinctrl/qcom,sm6375-tlmm.yaml @@ -44,8 +44,9 @@ patternProperties: oneOf: - $ref: "#/$defs/qcom-sm6375-tlmm-state" - patternProperties: - ".*": + "-pins$": $ref: "#/$defs/qcom-sm6375-tlmm-state" + additionalProperties: false $defs: qcom-sm6375-tlmm-state: @@ -53,7 +54,6 @@ $defs: description: Pinctrl node's client devices use subnodes for desired pin configuration. Client device subnodes use below standard properties. - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" properties: pins: @@ -119,40 +119,49 @@ $defs: required: - pins - - function + + allOf: + - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + - if: + properties: + pins: + pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-6])$" + then: + required: + - function additionalProperties: false examples: - | - #include <dt-bindings/interrupt-controller/arm-gic.h> - pinctrl@500000 { - compatible = "qcom,sm6375-tlmm"; - reg = <0x00500000 0x800000>; - interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 157>; - - gpio-wo-subnode-state { - pins = "gpio1"; - function = "gpio"; - }; - - uart-w-subnodes-state { - rx { - pins = "gpio18"; - function = "qup13_f2"; - bias-pull-up; - }; - - tx { - pins = "gpio19"; - function = "qup13_f2"; - bias-disable; - }; - }; + #include <dt-bindings/interrupt-controller/arm-gic.h> + pinctrl@500000 { + compatible = "qcom,sm6375-tlmm"; + reg = <0x00500000 0x800000>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 157>; + + gpio-wo-subnode-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-subnodes-state { + rx-pins { + pins = "gpio18"; + function = "qup13_f2"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio19"; + function = "qup13_f2"; + bias-disable; + }; }; + }; ... diff --git a/dts/Bindings/pinctrl/qcom,sm8250-pinctrl.yaml b/dts/Bindings/pinctrl/qcom,sm8250-pinctrl.yaml index 15bb1018cf..c44d02d28b 100644 --- a/dts/Bindings/pinctrl/qcom,sm8250-pinctrl.yaml +++ b/dts/Bindings/pinctrl/qcom,sm8250-pinctrl.yaml @@ -110,7 +110,16 @@ patternProperties: required: - pins - - function + + allOf: + - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + - if: + properties: + pins: + pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$" + then: + required: + - function additionalProperties: false @@ -132,18 +141,18 @@ additionalProperties: false examples: - | - #include <dt-bindings/interrupt-controller/arm-gic.h> - pinctrl@1f00000 { - compatible = "qcom,sm8250-pinctrl"; - reg = <0x0f100000 0x300000>, - <0x0f500000 0x300000>, - <0x0f900000 0x300000>; - reg-names = "west", "south", "north"; - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 180>; - wakeup-parent = <&pdc>; - }; + #include <dt-bindings/interrupt-controller/arm-gic.h> + pinctrl@1f00000 { + compatible = "qcom,sm8250-pinctrl"; + reg = <0x0f100000 0x300000>, + <0x0f500000 0x300000>, + <0x0f900000 0x300000>; + reg-names = "west", "south", "north"; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 180>; + wakeup-parent = <&pdc>; + }; diff --git a/dts/Bindings/pinctrl/qcom,sm8350-pinctrl.yaml b/dts/Bindings/pinctrl/qcom,sm8350-pinctrl.yaml index 6b7789db2f..6ae5571f60 100644 --- a/dts/Bindings/pinctrl/qcom,sm8350-pinctrl.yaml +++ b/dts/Bindings/pinctrl/qcom,sm8350-pinctrl.yaml @@ -44,8 +44,9 @@ patternProperties: oneOf: - $ref: "#/$defs/qcom-sm8350-tlmm-state" - patternProperties: - ".*": + "-pins$": $ref: "#/$defs/qcom-sm8350-tlmm-state" + additionalProperties: false $defs: qcom-sm8350-tlmm-state: @@ -53,7 +54,6 @@ $defs: description: Pinctrl node's client devices use subnodes for desired pin configuration. Client device subnodes use below standard properties. - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" properties: pins: @@ -107,40 +107,49 @@ $defs: required: - pins - - function + + allOf: + - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + - if: + properties: + pins: + pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-3])$" + then: + required: + - function additionalProperties: false examples: - | - #include <dt-bindings/interrupt-controller/arm-gic.h> - pinctrl@f100000 { - compatible = "qcom,sm8350-tlmm"; - reg = <0x0f100000 0x300000>; - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 203>; - - gpio-wo-subnode-state { - pins = "gpio1"; - function = "gpio"; - }; - - uart-w-subnodes-state { - rx { - pins = "gpio18"; - function = "qup3"; - bias-pull-up; - }; - - tx { - pins = "gpio19"; - function = "qup3"; - bias-disable; - }; - }; + #include <dt-bindings/interrupt-controller/arm-gic.h> + pinctrl@f100000 { + compatible = "qcom,sm8350-tlmm"; + reg = <0x0f100000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 203>; + + gpio-wo-subnode-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-subnodes-state { + rx-pins { + pins = "gpio18"; + function = "qup3"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio19"; + function = "qup3"; + bias-disable; + }; }; + }; ... diff --git a/dts/Bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml b/dts/Bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml new file mode 100644 index 0000000000..3694795ec7 --- /dev/null +++ b/dts/Bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS) + Low Power Island (LPI) TLMM block + +maintainers: + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + LPASS LPI IP on most Qualcomm SoCs + +properties: + compatible: + const: qcom,sm8450-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + - description: LPASS LPI pins SLEW registers + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-2][0-9]])$" + + function: + enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data, + dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic4_clk, + dmic4_data, i2s2_clk, i2s2_ws, dmic3_clk, dmic3_data, + qua_mi2s_sclk, qua_mi2s_ws, qua_mi2s_data, i2s1_clk, i2s1_ws, + i2s1_data, wsa_swr_clk, wsa_swr_data, wsa2_swr_clk, + wsa2_swr_data, i2s2_data, i2s4_ws, i2s4_clk, i2s4_data, + slimbus_clk, i2s3_clk, i2s3_ws, i2s3_data, slimbus_data, + ext_mclk1_c, ext_mclk1_b, ext_mclk1_a, ext_mclk1_d, + ext_mclk1_e ] + description: + Specify the alternative function to be configured for the specified + pins. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + slew-rate: + enum: [0, 1, 2, 3] + default: 0 + description: | + 0: No adjustments + 1: Higher Slew rate (faster edges) + 2: Lower Slew rate (slower edges) + 3: Reserved (No adjustments) + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/sound/qcom,q6afe.h> + pinctrl@3440000 { + compatible = "qcom,sm8450-lpass-lpi-pinctrl"; + reg = <0x3440000 0x20000>, + <0x34d0000 0x10000>; + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpi_tlmm 0 0 23>; + }; diff --git a/dts/Bindings/pinctrl/qcom,sm8450-pinctrl.yaml b/dts/Bindings/pinctrl/qcom,sm8450-pinctrl.yaml index 9c89124624..9cd97a4676 100644 --- a/dts/Bindings/pinctrl/qcom,sm8450-pinctrl.yaml +++ b/dts/Bindings/pinctrl/qcom,sm8450-pinctrl.yaml @@ -27,7 +27,14 @@ properties: interrupt-controller: true '#interrupt-cells': true gpio-controller: true - gpio-reserved-ranges: true + + gpio-reserved-ranges: + minItems: 1 + maxItems: 105 + + gpio-line-names: + maxItems: 209 + '#gpio-cells': true gpio-ranges: true wakeup-parent: true @@ -43,8 +50,9 @@ patternProperties: oneOf: - $ref: "#/$defs/qcom-sm8450-tlmm-state" - patternProperties: - ".*": + "-pins$": $ref: "#/$defs/qcom-sm8450-tlmm-state" + additionalProperties: false $defs: qcom-sm8450-tlmm-state: @@ -52,7 +60,6 @@ $defs: description: Pinctrl node's client devices use subnodes for desired pin configuration. Client device subnodes use below standard properties. - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" properties: pins: @@ -104,40 +111,49 @@ $defs: required: - pins - - function + + allOf: + - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + - if: + properties: + pins: + pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$" + then: + required: + - function additionalProperties: false examples: - | - #include <dt-bindings/interrupt-controller/arm-gic.h> - pinctrl@f100000 { - compatible = "qcom,sm8450-tlmm"; - reg = <0x0f100000 0x300000>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 0 211>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; - - gpio-wo-subnode-state { - pins = "gpio1"; - function = "gpio"; - }; - - uart-w-subnodes-state { - rx { - pins = "gpio26"; - function = "qup7"; - bias-pull-up; - }; - - tx { - pins = "gpio27"; - function = "qup7"; - bias-disable; - }; - }; + #include <dt-bindings/interrupt-controller/arm-gic.h> + pinctrl@f100000 { + compatible = "qcom,sm8450-tlmm"; + reg = <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 211>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-state { + rx-pins { + pins = "gpio26"; + function = "qup7"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio27"; + function = "qup7"; + bias-disable; + }; }; + }; ... diff --git a/dts/Bindings/pinctrl/renesas,rza1-ports.yaml b/dts/Bindings/pinctrl/renesas,rza1-ports.yaml index 8ed4b98a16..9083040c99 100644 --- a/dts/Bindings/pinctrl/renesas,rza1-ports.yaml +++ b/dts/Bindings/pinctrl/renesas,rza1-ports.yaml @@ -41,6 +41,7 @@ required: patternProperties: "^gpio-[0-9]*$": type: object + additionalProperties: false description: Each port of the r7s72100 pin controller hardware is itself a GPIO diff --git a/dts/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/dts/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 997b746391..f081acb7ba 100644 --- a/dts/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/dts/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -23,7 +23,7 @@ properties: oneOf: - items: - enum: - - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} + - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} - items: diff --git a/dts/Bindings/pinctrl/rockchip,pinctrl.yaml b/dts/Bindings/pinctrl/rockchip,pinctrl.yaml index 677a285ca4..b486f41df6 100644 --- a/dts/Bindings/pinctrl/rockchip,pinctrl.yaml +++ b/dts/Bindings/pinctrl/rockchip,pinctrl.yaml @@ -47,6 +47,7 @@ properties: - rockchip,rk3568-pinctrl - rockchip,rk3588-pinctrl - rockchip,rv1108-pinctrl + - rockchip,rv1126-pinctrl rockchip,grf: $ref: "/schemas/types.yaml#/definitions/phandle" diff --git a/dts/Bindings/pinctrl/samsung,pinctrl-pins-cfg.yaml b/dts/Bindings/pinctrl/samsung,pinctrl-pins-cfg.yaml index 9869d4dced..f796f27bf0 100644 --- a/dts/Bindings/pinctrl/samsung,pinctrl-pins-cfg.yaml +++ b/dts/Bindings/pinctrl/samsung,pinctrl-pins-cfg.yaml @@ -20,7 +20,6 @@ description: | The values used for config properties should be derived from the hardware manual and these values are programmed as-is into the pin pull up/down and driver strength register of the pin-controller. - See also include/dt-bindings/pinctrl/samsung.h with useful constants. See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for additional information and example. diff --git a/dts/Bindings/pinctrl/samsung,pinctrl.yaml b/dts/Bindings/pinctrl/samsung,pinctrl.yaml index 3a65c66ca7..eb2b269260 100644 --- a/dts/Bindings/pinctrl/samsung,pinctrl.yaml +++ b/dts/Bindings/pinctrl/samsung,pinctrl.yaml @@ -15,9 +15,6 @@ description: | This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin controller. - Pin group settings (like drive strength, pull up/down) are available as - macros in include/dt-bindings/pinctrl/samsung.h. - All the pin controller nodes should be represented in the aliases node using the following format 'pinctrl{n}' where n is a unique number for the alias. @@ -97,6 +94,9 @@ patternProperties: additionalProperties: false "^(initial|sleep)-state$": + type: object + additionalProperties: false + patternProperties: "^(pin-[a-z0-9-]+|[a-z0-9-]+-pin)$": $ref: samsung,pinctrl-pins-cfg.yaml @@ -138,8 +138,6 @@ additionalProperties: false examples: - | - #include <dt-bindings/pinctrl/samsung.h> - pinctrl@7f008000 { compatible = "samsung,s3c64xx-pinctrl"; reg = <0x7f008000 0x1000>; @@ -166,8 +164,8 @@ examples: uart0-data-pins { samsung,pins = "gpa-0", "gpa-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; }; // ... @@ -175,7 +173,6 @@ examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/pinctrl/samsung.h> pinctrl@11400000 { compatible = "samsung,exynos4210-pinctrl"; @@ -197,9 +194,9 @@ examples: uart0-data-pins { samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; }; // ... @@ -207,14 +204,14 @@ examples: sleep0: sleep-state { gpa0-0-pin { samsung,pins = "gpa0-0"; - samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>; - samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-con-pdn = <2>; + samsung,pin-pud-pdn = <0>; }; gpa0-1-pin { samsung,pins = "gpa0-1"; - samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT0>; - samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-con-pdn = <0>; + samsung,pin-pud-pdn = <0>; }; // ... @@ -223,7 +220,6 @@ examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/pinctrl/samsung.h> pinctrl@11000000 { compatible = "samsung,exynos4210-pinctrl"; @@ -272,26 +268,26 @@ examples: sd0-clk-pins { samsung,pins = "gpk0-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; }; sd4-bus-width8-pins { part-1-pins { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_3>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; }; part-2-pins { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_4>; - samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; }; }; @@ -299,16 +295,15 @@ examples: otg-gp-pins { samsung,pins = "gpx3-3"; - samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; samsung,pin-val = <0>; }; }; - | #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/pinctrl/samsung.h> pinctrl@10580000 { compatible = "samsung,exynos5433-pinctrl"; @@ -352,9 +347,9 @@ examples: initial_alive: initial-state { gpa0-0-pin { samsung,pins = "gpa0-0"; - samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; - samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; - samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; }; // ... @@ -363,7 +358,6 @@ examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/pinctrl/samsung.h> pinctrl@114b0000 { compatible = "samsung,exynos5433-pinctrl"; @@ -384,9 +378,9 @@ examples: i2s0-bus-pins { samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3", "gpz0-4", "gpz0-5", "gpz0-6"; - samsung,pin-function = <EXYNOS_PIN_FUNC_2>; - samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; - samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; }; // ... diff --git a/dts/Bindings/pinctrl/st,stm32-pinctrl.yaml b/dts/Bindings/pinctrl/st,stm32-pinctrl.yaml index d35dcc4f02..9d59208d83 100644 --- a/dts/Bindings/pinctrl/st,stm32-pinctrl.yaml +++ b/dts/Bindings/pinctrl/st,stm32-pinctrl.yaml @@ -64,6 +64,9 @@ patternProperties: gpio-controller: true '#gpio-cells': const: 2 + interrupt-controller: true + '#interrupt-cells': + const: 2 reg: maxItems: 1 @@ -71,6 +74,7 @@ patternProperties: maxItems: 1 resets: maxItems: 1 + gpio-line-names: true gpio-ranges: minItems: 1 maxItems: 16 @@ -106,6 +110,12 @@ patternProperties: minimum: 0 maximum: 11 + patternProperties: + "^(.+-hog(-[0-9]+)?)$": + type: object + required: + - gpio-hog + required: - gpio-controller - '#gpio-cells' @@ -115,9 +125,12 @@ patternProperties: '-[0-9]*$': type: object + additionalProperties: false + patternProperties: '^pins': type: object + additionalProperties: false description: | A pinctrl node should contain at least one subnode representing the pinctrl group available on the machine. Each subnode will list the diff --git a/dts/Bindings/pinctrl/starfive,jh7100-pinctrl.yaml b/dts/Bindings/pinctrl/starfive,jh7100-pinctrl.yaml index 9296360442..69c0dd9998 100644 --- a/dts/Bindings/pinctrl/starfive,jh7100-pinctrl.yaml +++ b/dts/Bindings/pinctrl/starfive,jh7100-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: StarFive JH7100 Pin Controller Device Tree Bindings +title: StarFive JH7100 Pin Controller description: | Bindings for the JH7100 RISC-V SoC from StarFive Ltd. @@ -165,7 +165,7 @@ examples: - | #include <dt-bindings/clock/starfive-jh7100.h> #include <dt-bindings/reset/starfive-jh7100.h> - #include <dt-bindings/pinctrl/pinctrl-starfive.h> + #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h> soc { #address-cells = <2>; diff --git a/dts/Bindings/pinctrl/sunplus,sp7021-pinctrl.yaml b/dts/Bindings/pinctrl/sunplus,sp7021-pinctrl.yaml index 15092fdd4b..347061eece 100644 --- a/dts/Bindings/pinctrl/sunplus,sp7021-pinctrl.yaml +++ b/dts/Bindings/pinctrl/sunplus,sp7021-pinctrl.yaml @@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Sunplus SP7021 Pin Controller Device Tree Bindings +title: Sunplus SP7021 Pin Controller maintainers: - Dvorkin Dmitry <dvorkin@tibbo.com> diff --git a/dts/Bindings/pinctrl/toshiba,visconti-pinctrl.yaml b/dts/Bindings/pinctrl/toshiba,visconti-pinctrl.yaml index 306524885a..98b4663f97 100644 --- a/dts/Bindings/pinctrl/toshiba,visconti-pinctrl.yaml +++ b/dts/Bindings/pinctrl/toshiba,visconti-pinctrl.yaml @@ -36,6 +36,7 @@ patternProperties: pins it needs, and how they should be configured, with regard to muxer configuration, pullups, drive strength. $ref: "pinmux-node.yaml" + additionalProperties: false properties: function: diff --git a/dts/Bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml b/dts/Bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml index 1e2b9b627b..2722dc7bb0 100644 --- a/dts/Bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml +++ b/dts/Bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml @@ -274,10 +274,6 @@ patternProperties: slew-rate: enum: [0, 1] - output-enable: - description: - This will internally disable the tri-state for MIO pins. - drive-strength: description: Selects the drive strength for MIO pins, in mA. diff --git a/dts/Bindings/power/domain-idle-state.yaml b/dts/Bindings/power/domain-idle-state.yaml index 6a12efdf43..4ee920a1de 100644 --- a/dts/Bindings/power/domain-idle-state.yaml +++ b/dts/Bindings/power/domain-idle-state.yaml @@ -20,6 +20,7 @@ properties: patternProperties: "^(cpu|cluster|domain)-": type: object + additionalProperties: false description: Each state node represents a domain idle state description. @@ -44,6 +45,15 @@ patternProperties: state will yield power benefits, after overcoming the overhead while entering the idle state. + arm,psci-suspend-param: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + power_state parameter to pass to the ARM PSCI suspend call. + + Device tree nodes that require usage of PSCI CPU_SUSPEND function + (i.e. idle states node with entry-method property is set to "psci") + must specify this property. + required: - compatible - entry-latency-us diff --git a/dts/Bindings/power/fsl,imx-gpc.yaml b/dts/Bindings/power/fsl,imx-gpc.yaml index a055b3e819..777e1d852d 100644 --- a/dts/Bindings/power/fsl,imx-gpc.yaml +++ b/dts/Bindings/power/fsl,imx-gpc.yaml @@ -43,11 +43,21 @@ properties: pgc: type: object + additionalProperties: false description: list of power domains provided by this controller. + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + patternProperties: "power-domain@[0-9]$": type: object + additionalProperties: false + properties: '#power-domain-cells': @@ -78,6 +88,10 @@ properties: - '#power-domain-cells' - reg + required: + - '#address-cells' + - '#size-cells' + required: - compatible - reg diff --git a/dts/Bindings/power/fsl,imx-gpcv2.yaml b/dts/Bindings/power/fsl,imx-gpcv2.yaml index 747622bdc5..dfdb8dfb6b 100644 --- a/dts/Bindings/power/fsl,imx-gpcv2.yaml +++ b/dts/Bindings/power/fsl,imx-gpcv2.yaml @@ -42,11 +42,21 @@ properties: pgc: type: object + additionalProperties: false description: list of power domains provided by this controller. + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + patternProperties: - "power-domain@[0-9]$": + "power-domain@[0-9a-f]+$": type: object + additionalProperties: false + properties: '#power-domain-cells': @@ -71,6 +81,9 @@ properties: power-supply: true + power-domains: + maxItems: 1 + resets: description: | A number of phandles to resets that need to be asserted during @@ -85,6 +98,10 @@ properties: - '#power-domain-cells' - reg + required: + - '#address-cells' + - '#size-cells' + required: - compatible - reg diff --git a/dts/Bindings/power/mediatek,power-controller.yaml b/dts/Bindings/power/mediatek,power-controller.yaml index b448101fac..605ec7ab5f 100644 --- a/dts/Bindings/power/mediatek,power-controller.yaml +++ b/dts/Bindings/power/mediatek,power-controller.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Mediatek Power Domains Controller maintainers: - - Weiyi Lu <weiyi.lu@mediatek.com> + - MandyJH Liu <mandyjh.liu@mediatek.com> - Matthias Brugger <mbrugger@suse.com> description: | @@ -19,7 +19,7 @@ description: | properties: $nodename: - const: power-controller + pattern: '^power-controller(@[0-9a-f]+)?$' compatible: enum: @@ -42,6 +42,23 @@ properties: patternProperties: "^power-domain@[0-9a-f]+$": + $ref: "#/$defs/power-domain-node" + patternProperties: + "^power-domain@[0-9a-f]+$": + $ref: "#/$defs/power-domain-node" + patternProperties: + "^power-domain@[0-9a-f]+$": + $ref: "#/$defs/power-domain-node" + patternProperties: + "^power-domain@[0-9a-f]+$": + $ref: "#/$defs/power-domain-node" + unevaluatedProperties: false + unevaluatedProperties: false + unevaluatedProperties: false + unevaluatedProperties: false + +$defs: + power-domain-node: type: object description: | Represents the power domains within the power controller node as documented @@ -100,123 +117,9 @@ patternProperties: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the device containing the SMI register range. - patternProperties: - "^power-domain@[0-9a-f]+$": - type: object - description: | - Represents a power domain child within a power domain parent node. - - properties: - - '#power-domain-cells': - description: - Must be 0 for nodes representing a single PM domain and 1 for nodes - providing multiple PM domains. - - '#address-cells': - const: 1 - - '#size-cells': - const: 0 - - reg: - maxItems: 1 - - clocks: - description: | - A number of phandles to clocks that need to be enabled during domain - power-up sequencing. - - clock-names: - description: | - List of names of clocks, in order to match the power-up sequencing - for each power domain we need to group the clocks by name. BASIC - clocks need to be enabled before enabling the corresponding power - domain, and should not have a '-' in their name (i.e mm, mfg, venc). - SUSBYS clocks need to be enabled before releasing the bus protection, - and should contain a '-' in their name (i.e mm-0, isp-0, cam-0). - - In order to follow properly the power-up sequencing, the clocks must - be specified by order, adding first the BASIC clocks followed by the - SUSBSYS clocks. - - domain-supply: - description: domain regulator supply. - - mediatek,infracfg: - $ref: /schemas/types.yaml#/definitions/phandle - description: phandle to the device containing the INFRACFG register range. - - mediatek,smi: - $ref: /schemas/types.yaml#/definitions/phandle - description: phandle to the device containing the SMI register range. - - patternProperties: - "^power-domain@[0-9a-f]+$": - type: object - description: | - Represents a power domain child within a power domain parent node. - - properties: - - '#power-domain-cells': - description: - Must be 0 for nodes representing a single PM domain and 1 for nodes - providing multiple PM domains. - - '#address-cells': - const: 1 - - '#size-cells': - const: 0 - - reg: - maxItems: 1 - - clocks: - description: | - A number of phandles to clocks that need to be enabled during domain - power-up sequencing. - - clock-names: - description: | - List of names of clocks, in order to match the power-up sequencing - for each power domain we need to group the clocks by name. BASIC - clocks need to be enabled before enabling the corresponding power - domain, and should not have a '-' in their name (i.e mm, mfg, venc). - SUSBYS clocks need to be enabled before releasing the bus protection, - and should contain a '-' in their name (i.e mm-0, isp-0, cam-0). - - In order to follow properly the power-up sequencing, the clocks must - be specified by order, adding first the BASIC clocks followed by the - SUSBSYS clocks. - - domain-supply: - description: domain regulator supply. - - mediatek,infracfg: - $ref: /schemas/types.yaml#/definitions/phandle - description: phandle to the device containing the INFRACFG register range. - - mediatek,smi: - $ref: /schemas/types.yaml#/definitions/phandle - description: phandle to the device containing the SMI register range. - - required: - - reg - - additionalProperties: false - - required: - - reg - - additionalProperties: false - required: - reg - additionalProperties: false - required: - compatible @@ -232,7 +135,7 @@ examples: #size-cells = <2>; scpsys: syscon@10006000 { - compatible = "syscon", "simple-mfd"; + compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd"; reg = <0 0x10006000 0 0x1000>; spm: power-controller { diff --git a/dts/Bindings/power/qcom,rpmpd.yaml b/dts/Bindings/power/qcom,rpmpd.yaml index 3934a2b448..5b4eda9199 100644 --- a/dts/Bindings/power/qcom,rpmpd.yaml +++ b/dts/Bindings/power/qcom,rpmpd.yaml @@ -40,6 +40,7 @@ properties: - qcom,sm6115-rpmpd - qcom,sm6125-rpmpd - qcom,sm6350-rpmhpd + - qcom,sm6375-rpmpd - qcom,sm8150-rpmhpd - qcom,sm8250-rpmhpd - qcom,sm8350-rpmhpd diff --git a/dts/Bindings/power/reset/qcom,pon.yaml b/dts/Bindings/power/reset/qcom,pon.yaml index e7b436d2e7..d96170eecb 100644 --- a/dts/Bindings/power/reset/qcom,pon.yaml +++ b/dts/Bindings/power/reset/qcom,pon.yaml @@ -15,18 +15,27 @@ description: | This DT node has pwrkey and resin as sub nodes. -allOf: - - $ref: reboot-mode.yaml# - properties: compatible: enum: - qcom,pm8916-pon - qcom,pms405-pon - qcom,pm8998-pon + - qcom,pmk8350-pon reg: - maxItems: 1 + description: | + Specifies the SPMI base address for the PON (power-on) peripheral. For + PMICs that have the PON peripheral (GEN3) split into PON_HLOS and PON_PBS + (e.g. PMK8350), this can hold addresses of both PON_HLOS and PON_PBS + peripherals. In that case, the PON_PBS address needs to be specified to + facilitate software debouncing on some PMIC. + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + maxItems: 2 pwrkey: type: object @@ -46,6 +55,39 @@ required: unevaluatedProperties: false +allOf: + - $ref: reboot-mode.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8916-pon + - qcom,pms405-pon + - qcom,pm8998-pon + then: + properties: + reg: + maxItems: 1 + reg-names: + items: + - const: pon + - if: + properties: + compatible: + contains: + const: qcom,pmk8350-pon + then: + properties: + reg: + minItems: 1 + maxItems: 2 + reg-names: + minItems: 1 + items: + - const: hlos + - const: pbs + examples: - | #include <dt-bindings/interrupt-controller/irq.h> diff --git a/dts/Bindings/power/rockchip,power-controller.yaml b/dts/Bindings/power/rockchip,power-controller.yaml index 3deb0fc8df..0d5e999a58 100644 --- a/dts/Bindings/power/rockchip,power-controller.yaml +++ b/dts/Bindings/power/rockchip,power-controller.yaml @@ -41,6 +41,8 @@ properties: - rockchip,rk3368-power-controller - rockchip,rk3399-power-controller - rockchip,rk3568-power-controller + - rockchip,rk3588-power-controller + - rockchip,rv1126-power-controller "#power-domain-cells": const: 1 @@ -119,6 +121,8 @@ $defs: "include/dt-bindings/power/rk3368-power.h" "include/dt-bindings/power/rk3399-power.h" "include/dt-bindings/power/rk3568-power.h" + "include/dt-bindings/power/rk3588-power.h" + "include/dt-bindings/power/rockchip,rv1126-power.h" clocks: minItems: 1 diff --git a/dts/Bindings/power/rockchip-io-domain.yaml b/dts/Bindings/power/rockchip-io-domain.yaml index 1727bf1089..d71fc72d44 100644 --- a/dts/Bindings/power/rockchip-io-domain.yaml +++ b/dts/Bindings/power/rockchip-io-domain.yaml @@ -58,6 +58,7 @@ properties: - rockchip,rk3568-pmu-io-voltage-domain - rockchip,rv1108-io-voltage-domain - rockchip,rv1108-pmu-io-voltage-domain + - rockchip,rv1126-pmu-io-voltage-domain required: - compatible @@ -78,6 +79,7 @@ allOf: - $ref: "#/$defs/rk3568-pmu" - $ref: "#/$defs/rv1108" - $ref: "#/$defs/rv1108-pmu" + - $ref: "#/$defs/rv1126-pmu" $defs: px30: @@ -344,6 +346,34 @@ $defs: pmu-supply: description: The supply connected to PMUIO_VDD. + rv1126-pmu: + if: + properties: + compatible: + contains: + const: rockchip,rv1126-pmu-io-voltage-domain + + then: + properties: + vccio1-supply: + description: The supply connected to VCCIO1. + vccio2-supply: + description: The supply connected to VCCIO2. + vccio3-supply: + description: The supply connected to VCCIO3. + vccio4-supply: + description: The supply connected to VCCIO4. + vccio5-supply: + description: The supply connected to VCCIO5. + vccio6-supply: + description: The supply connected to VCCIO6. + vccio7-supply: + description: The supply connected to VCCIO7. + pmuio0-supply: + description: The supply connected to PMUIO0. + pmuio1-supply: + description: The supply connected to PMUIO1. + examples: - | io-domains { diff --git a/dts/Bindings/power/supply/mediatek,mt6370-charger.yaml b/dts/Bindings/power/supply/mediatek,mt6370-charger.yaml new file mode 100644 index 0000000000..fd491c598a --- /dev/null +++ b/dts/Bindings/power/supply/mediatek,mt6370-charger.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/mediatek,mt6370-charger.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6370 Battery Charger + +maintainers: + - ChiaEn Wu <chiaen_wu@richtek.com> + +description: | + This module is part of the MT6370 MFD device. + Provides Battery Charger, Boost for OTG devices and BC1.2 detection. + +properties: + compatible: + const: mediatek,mt6370-charger + + interrupts: + description: | + Specify what irqs are needed to be handled by MT6370 Charger driver. + We need to use the IRQ "MT6370_IRQ_OVPCTRL_UVP_D" to know when USB + is plugged in, and then the driver will enable BC1.2 detection. + After the hardware of MT6370 completes the BC1.2 detection, + IRQ "MT6370_IRQ_ATTACH" will be triggered, and the driver will know + the result of BC1.2 detection. + When the IRQ "MT6370_IRQ_CHG_MIVR" is triggered, it means that the + hardware enters the "Minimum Input Voltage Regulation loop" and + a workaround needs to be applied at this time. + In summary, "MT6370_IRQ_OVPCTRL_UVP_D", "MT6370_IRQ_ATTACH" and + "MT6370_IRQ_CHG_MIVR" are required in this charger driver. + items: + - description: irq of "USB is plugged in" + - description: irq of "BC1.2 is done" + - description: irq of "Minimum Input Voltage Regulation loop is active" + + interrupt-names: + items: + - const: uvp_d_evt + - const: attach_i + - const: mivr + + io-channels: + description: | + Use ADC channel to read VBUS, IBUS, IBAT, etc., info. + minItems: 1 + items: + - description: | + VBUS voltage with lower accuracy (+-75mV) but higher measure + range (1~22V) + - description: | + VBUS voltage with higher accuracy (+-30mV) but lower measure + range (1~9.76V) + - description: the main system input voltage + - description: battery voltage + - description: battery temperature-sense input voltage + - description: IBUS current (required) + - description: battery current + - description: | + regulated output voltage to supply for the PWM low-side gate driver + and the bootstrap capacitor + - description: IC junction temperature + + io-channel-names: + minItems: 1 + items: + - const: vbusdiv5 + - const: vbusdiv2 + - const: vsys + - const: vbat + - const: ts_bat + - const: ibus + - const: ibat + - const: chg_vddp + - const: temp_jc + + usb-otg-vbus-regulator: + type: object + description: OTG boost regulator. + unevaluatedProperties: false + $ref: /schemas/regulator/regulator.yaml# + + properties: + enable-gpios: + maxItems: 1 + +required: + - compatible + - interrupts + - interrupt-names + - io-channels + +additionalProperties: false + +... diff --git a/dts/Bindings/ptp/ptp-idt82p33.yaml b/dts/Bindings/ptp/ptp-idt82p33.yaml index 9bc664f414..51381e4cbb 100644 --- a/dts/Bindings/ptp/ptp-idt82p33.yaml +++ b/dts/Bindings/ptp/ptp-idt82p33.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/ptp/ptp-idt82p33.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: IDT 82P33 PTP Clock Device Tree Bindings +title: IDT 82P33 PTP Clock description: | IDT 82P33XXX Synchronization Management Unit (SMU) based PTP clock diff --git a/dts/Bindings/ptp/ptp-idtcm.yaml b/dts/Bindings/ptp/ptp-idtcm.yaml index 658cec6774..7cf32663c8 100644 --- a/dts/Bindings/ptp/ptp-idtcm.yaml +++ b/dts/Bindings/ptp/ptp-idtcm.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/ptp/ptp-idtcm.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: IDT ClockMatrix (TM) PTP Clock Device Tree Bindings +title: IDT ClockMatrix (TM) PTP Clock maintainers: - Vincent Cheng <vincent.cheng.xh@renesas.com> diff --git a/dts/Bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/dts/Bindings/pwm/allwinner,sun4i-a10-pwm.yaml index e93e935564..4cc3cc7c50 100644 --- a/dts/Bindings/pwm/allwinner,sun4i-a10-pwm.yaml +++ b/dts/Bindings/pwm/allwinner,sun4i-a10-pwm.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pwm/allwinner,sun4i-a10-pwm.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 PWM Device Tree Bindings +title: Allwinner A10 PWM maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/pwm/intel,keembay-pwm.yaml b/dts/Bindings/pwm/intel,keembay-pwm.yaml index ec9f6bab79..5b18a5913e 100644 --- a/dts/Bindings/pwm/intel,keembay-pwm.yaml +++ b/dts/Bindings/pwm/intel,keembay-pwm.yaml @@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/pwm/intel,keembay-pwm.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Intel Keem Bay PWM Device Tree Bindings +title: Intel Keem Bay PWM maintainers: - Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> diff --git a/dts/Bindings/pwm/mediatek,pwm-disp.yaml b/dts/Bindings/pwm/mediatek,pwm-disp.yaml index e4fe2d1bfe..0088bc8e7c 100644 --- a/dts/Bindings/pwm/mediatek,pwm-disp.yaml +++ b/dts/Bindings/pwm/mediatek,pwm-disp.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: MediaTek DISP_PWM Controller Device Tree Bindings +title: MediaTek DISP_PWM Controller maintainers: - Jitao Shi <jitao.shi@mediatek.com> @@ -27,6 +27,7 @@ properties: - items: - enum: - mediatek,mt8186-disp-pwm + - mediatek,mt8188-disp-pwm - mediatek,mt8192-disp-pwm - mediatek,mt8195-disp-pwm - const: mediatek,mt8183-disp-pwm diff --git a/dts/Bindings/pwm/pwm-rockchip.yaml b/dts/Bindings/pwm/pwm-rockchip.yaml index a336ff9364..f2d1dc7e7b 100644 --- a/dts/Bindings/pwm/pwm-rockchip.yaml +++ b/dts/Bindings/pwm/pwm-rockchip.yaml @@ -21,6 +21,7 @@ properties: - const: rockchip,rk2928-pwm - items: - enum: + - rockchip,rk3128-pwm - rockchip,rk3368-pwm - rockchip,rk3399-pwm - rockchip,rv1108-pwm @@ -30,6 +31,7 @@ properties: - rockchip,px30-pwm - rockchip,rk3308-pwm - rockchip,rk3568-pwm + - rockchip,rk3588-pwm - const: rockchip,rk3328-pwm reg: diff --git a/dts/Bindings/regulator/dlg,da9121.yaml b/dts/Bindings/regulator/dlg,da9121.yaml index 24ace6e1e5..63e1161a87 100644 --- a/dts/Bindings/regulator/dlg,da9121.yaml +++ b/dts/Bindings/regulator/dlg,da9121.yaml @@ -83,6 +83,7 @@ properties: regulators: type: object + additionalProperties: false description: | List of regulators provided by the device diff --git a/dts/Bindings/regulator/gpio-regulator.yaml b/dts/Bindings/regulator/gpio-regulator.yaml index f7e3d8fd3b..6c3371d706 100644 --- a/dts/Bindings/regulator/gpio-regulator.yaml +++ b/dts/Bindings/regulator/gpio-regulator.yaml @@ -85,6 +85,9 @@ properties: - current default: voltage + vin-supply: + description: Input supply phandle. + required: - compatible - regulator-name diff --git a/dts/Bindings/regulator/maxim,max77802.yaml b/dts/Bindings/regulator/maxim,max77802.yaml index 236348c471..71138c611b 100644 --- a/dts/Bindings/regulator/maxim,max77802.yaml +++ b/dts/Bindings/regulator/maxim,max77802.yaml @@ -79,6 +79,7 @@ patternProperties: patternProperties: regulator-state-(standby|mem|disk): type: object + additionalProperties: true properties: regulator-mode: false diff --git a/dts/Bindings/regulator/maxim,max8997.yaml b/dts/Bindings/regulator/maxim,max8997.yaml index 4321f061a7..2b266ea437 100644 --- a/dts/Bindings/regulator/maxim,max8997.yaml +++ b/dts/Bindings/regulator/maxim,max8997.yaml @@ -111,6 +111,7 @@ properties: regulators: type: object + additionalProperties: false description: List of child nodes that specify the regulators. diff --git a/dts/Bindings/regulator/mediatek,mt6331-regulator.yaml b/dts/Bindings/regulator/mediatek,mt6331-regulator.yaml new file mode 100644 index 0000000000..771cc13439 --- /dev/null +++ b/dts/Bindings/regulator/mediatek,mt6331-regulator.yaml @@ -0,0 +1,273 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/mediatek,mt6331-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MT6331 Regulator from MediaTek Integrated + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + +description: | + The MT6331 PMIC provides 6 BUCK and 21 LDO (Low Dropout) regulators + and nodes are named according to the regulator type: + buck-<name> and ldo-<name>. + MT6331 regulators node should be sub node of the MT6397 MFD node. + +patternProperties: + "^buck-v(core2|io18|dvfs11|dvfs12|dvfs13|dvfs14)$": + type: object + $ref: "regulator.yaml#" + + properties: + regulator-name: + pattern: "^v(core2|io18|dvfs11|dvfs12|dvfs13|dvfs14)$" + + unevaluatedProperties: false + + "^ldo-v(avdd32aud|auxa32)$": + type: object + $ref: "regulator.yaml#" + + properties: + regulator-name: + pattern: "^v(avdd32aud|auxa32)$" + + unevaluatedProperties: false + + "^ldo-v(dig18|emc33|ibr|mc|mch|mipi|rtc|sram|usb10)$": + type: object + $ref: "regulator.yaml#" + + properties: + regulator-name: + pattern: "^v(dig18|emc33|ibr|mc|mch|mipi|rtc|sram|usb10)$" + + unevaluatedProperties: false + + "^ldo-vcam(a|af|d|io)$": + type: object + $ref: "regulator.yaml#" + + properties: + regulator-name: + pattern: "^vcam(a|af|d|io)$" + + unevaluatedProperties: false + + "^ldo-vtcxo[12]$": + type: object + $ref: "regulator.yaml#" + + properties: + regulator-name: + pattern: "^vtcxo[12]$" + + required: + - regulator-name + + unevaluatedProperties: false + + "^ldo-vgp[1234]$": + type: object + $ref: "regulator.yaml#" + + properties: + regulator-name: + pattern: "^vgp[12]$" + + required: + - regulator-name + + unevaluatedProperties: false + +additionalProperties: false + +examples: + - | + pmic { + regulators { + mt6331_vdvfs11_reg: buck-vdvfs11 { + regulator-name = "vdvfs11"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1493750>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <1>; + regulator-allowed-modes = <0 1>; + }; + mt6331_vdvfs12_reg: buck-vdvfs12 { + regulator-name = "vdvfs12"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1493750>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <1>; + regulator-allowed-modes = <0 1>; + }; + mt6331_vdvfs13_reg: buck-vdvfs13 { + regulator-name = "vdvfs13"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1493750>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <1>; + regulator-allowed-modes = <0 1>; + }; + mt6331_vdvfs14_reg: buck-vdvfs14 { + regulator-name = "vdvfs14"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1493750>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <1>; + regulator-allowed-modes = <0 1>; + }; + mt6331_vcore2_reg: buck-vcore2 { + regulator-name = "vcore2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1493750>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <1>; + regulator-allowed-modes = <0 1>; + }; + mt6331_vio18_reg: buck-vio18 { + regulator-name = "vio18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-allowed-modes = <0 1>; + }; + mt6331_vtcxo1_reg: ldo-vtcxo1 { + regulator-name = "vtcxo1"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + mt6331_vtcxo2_reg: ldo-vtcxo2 { + regulator-name = "vtcxo2"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + mt6331_avdd32_aud_reg: ldo-avdd32aud { + regulator-name = "avdd32_aud"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3200000>; + }; + mt6331_vauxa32_reg: ldo-vauxa32 { + regulator-name = "vauxa32"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3200000>; + }; + mt6331_vcama_reg: ldo-vcama { + regulator-name = "vcama"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + mt6331_vio28_reg: ldo-vio28 { + regulator-name = "vio28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + mt6331_vcamaf_reg: ldo-vcamaf { + regulator-name = "vcam_af"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + }; + mt6331_vmc_reg: ldo-vmc { + regulator-name = "vmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + mt6331_vmch_reg: ldo-vmch { + regulator-name = "vmch"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + mt6331_vemc33_reg: ldo-vemc33 { + regulator-name = "vemc33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + mt6331_vgp1_reg: ldo-vgp1 { + regulator-name = "vgp1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + }; + mt6331_vsim1_reg: ldo-vsim1 { + regulator-name = "vsim1"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + }; + mt6331_vsim2_reg: ldo-vsim2 { + regulator-name = "vsim2"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + }; + mt6331_vmipi_reg: ldo-vmipi { + regulator-name = "vmipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + }; + mt6331_vibr_reg: ldo-vibr { + regulator-name = "vibr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + }; + mt6331_vgp4_reg: ldo-vgp4 { + regulator-name = "vgp4"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <2200000>; + }; + mt6331_vcamd_reg: ldo-vcamd { + regulator-name = "vcamd"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1500000>; + }; + mt6331_vusb10_reg: ldo-vusb10 { + regulator-name = "vusb"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + }; + mt6331_vcamio_reg: ldo-vcamio { + regulator-name = "vcam_io"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + }; + mt6331_vsram_reg: ldo-vsram { + regulator-name = "vsram"; + regulator-min-microvolt = <1012500>; + regulator-max-microvolt = <1012500>; + regulator-always-on; + regulator-boot-on; + }; + mt6331_vgp2_reg: ldo-vgp2 { + regulator-name = "vgp2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + }; + mt6331_vgp3_reg: ldo-vgp3 { + regulator-name = "vgp3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + }; + mt6331_vrtc_reg: ldo-vrtc { + regulator-name = "vrtc"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + mt6331_vdig18_reg: ldo-vdig18 { + regulator-name = "dvdd18_dig"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; +... diff --git a/dts/Bindings/regulator/mediatek,mt6332-regulator.yaml b/dts/Bindings/regulator/mediatek,mt6332-regulator.yaml new file mode 100644 index 0000000000..3218f43e69 --- /dev/null +++ b/dts/Bindings/regulator/mediatek,mt6332-regulator.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/mediatek,mt6332-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MT6332 Regulator from MediaTek Integrated + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + +description: | + The MT6332 Companion PMIC provides 6 BUCK and 4 LDO (Low Dropout) + regulators and nodes are named according to the regulator type: + buck-<name> and ldo-<name>. + MT6332 regulators node should be sub node of the MT6397 MFD node. + +patternProperties: + "^buck-v(dram|dvfs2|pa|rf18a|rf18b|sbst)$": + type: object + $ref: "regulator.yaml#" + + properties: + regulator-name: + pattern: "^v(dram|dvfs2|pa|rf18a|rf18b|sbst)$" + + unevaluatedProperties: false + + "^ldo-v(bif28|dig18|sram|usb33)$": + type: object + $ref: "regulator.yaml#" + + properties: + regulator-name: + pattern: "^v(bif28|dig18|sram|usb33)$" + + unevaluatedProperties: false + +additionalProperties: false + +examples: + - | + pmic { + regulators { + mt6332_vdram_reg: buck-vdram { + regulator-name = "vdram"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1493750>; + regulator-ramp-delay = <12500>; + regulator-allowed-modes = <0 1>; + regulator-always-on; + }; + mt6332_vdvfs2_reg: buck-vdvfs2 { + regulator-name = "vdvfs2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1312500>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <1>; + regulator-allowed-modes = <0 1>; + }; + mt6332_vpa_reg: buck-vpa { + regulator-name = "vpa"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + mt6332_vrf18a_reg: buck-vrf18a { + regulator-name = "vrf18a"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <2240625>; + regulator-allowed-modes = <0 1>; + }; + mt6332_vrf18b_reg: buck-vrf18b { + regulator-name = "vrf18b"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <2240625>; + regulator-allowed-modes = <0 1>; + }; + mt6332_vsbst_reg: buck-vsbst { + regulator-name = "vsbst"; + regulator-min-microvolt = <3500000>; + regulator-max-microvolt = <7468750>; + }; + mt6332_vauxb32_reg: ldo-vauxb32 { + regulator-name = "vauxb32"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3200000>; + }; + mt6332_vbif28_reg: ldo-vbif28 { + regulator-name = "vbif28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + mt6332_vdig18_reg: ldo-vdig18 { + regulator-name = "vdig18"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + mt6332_vsram_reg: ldo-vsram { + regulator-name = "vauxa32"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1493750>; + regulator-always-on; + }; + mt6332_vusb33_reg: ldo-vusb33 { + regulator-name = "vusb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +... diff --git a/dts/Bindings/regulator/mt6315-regulator.yaml b/dts/Bindings/regulator/mt6315-regulator.yaml index 37402c370f..364b58730b 100644 --- a/dts/Bindings/regulator/mt6315-regulator.yaml +++ b/dts/Bindings/regulator/mt6315-regulator.yaml @@ -29,6 +29,7 @@ properties: "^vbuck[1-4]$": type: object $ref: "regulator.yaml#" + unevaluatedProperties: false properties: regulator-compatible: diff --git a/dts/Bindings/regulator/qcom,rpmh-regulator.yaml b/dts/Bindings/regulator/qcom,rpmh-regulator.yaml index 9a36bee750..90c3bda31c 100644 --- a/dts/Bindings/regulator/qcom,rpmh-regulator.yaml +++ b/dts/Bindings/regulator/qcom,rpmh-regulator.yaml @@ -37,6 +37,8 @@ description: | For PM6150, smps1 - smps5, ldo1 - ldo19 For PM6150L, smps1 - smps8, ldo1 - ldo11, bob For PM6350, smps1 - smps5, ldo1 - ldo22 + For PM660, smps1 - smps6, ldo1 - ldo3, ldo5 - ldo19 + For PM660L, smps1 - smps3, smps5, ldo1 - ldo8, bob For PM7325, smps1 - smps8, ldo1 - ldo19 For PM8005, smps1 - smps4 For PM8009, smps1 - smps2, ldo1 - ldo7 @@ -57,6 +59,8 @@ properties: - qcom,pm6150-rpmh-regulators - qcom,pm6150l-rpmh-regulators - qcom,pm6350-rpmh-regulators + - qcom,pm660-rpmh-regulators + - qcom,pm660l-rpmh-regulators - qcom,pm7325-rpmh-regulators - qcom,pm8005-rpmh-regulators - qcom,pm8009-rpmh-regulators @@ -99,12 +103,16 @@ properties: type: object $ref: "regulator.yaml#" description: BOB regulator node. + dependencies: + regulator-allow-set-load: ["regulator-allowed-modes"] patternProperties: "^(smps|ldo|lvs)[0-9]+$": type: object $ref: "regulator.yaml#" description: smps/ldo regulator nodes(s). + dependencies: + regulator-allow-set-load: ["regulator-allowed-modes"] required: - compatible @@ -148,6 +156,38 @@ allOf: properties: compatible: enum: + - qcom,pm660-rpmh-regulators + then: + properties: + vdd-l1-l6-l7-supply: true + vdd-l2-l3-supply: true + vdd-l5-supply: true + vdd-l8-l9-l10-l11-l12-l13-l14-supply: true + vdd-l15-l16-l17-l18-l19-supply: true + patternProperties: + "^vdd-s[1-6]-supply$": true + + - if: + properties: + compatible: + enum: + - qcom,pm660l-rpmh-regulators + then: + properties: + vdd-bob-supply: + description: BOB regulator parent supply phandle. + vdd-l1-l9-l10-supply: true + vdd-l2-supply: true + vdd-l3-l5-l7-l8-supply: true + vdd-l4-l6-supply: true + vdd-s3-s4-supply: true + patternProperties: + "^vdd-s[125]-supply$": true + + - if: + properties: + compatible: + enum: - qcom,pm7325-rpmh-regulators then: properties: diff --git a/dts/Bindings/regulator/qcom,smd-rpm-regulator.yaml b/dts/Bindings/regulator/qcom,smd-rpm-regulator.yaml index c233461cc9..961eed5191 100644 --- a/dts/Bindings/regulator/qcom,smd-rpm-regulator.yaml +++ b/dts/Bindings/regulator/qcom,smd-rpm-regulator.yaml @@ -24,6 +24,17 @@ description: For mp5496, s2 + For pm2250, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, + l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22 + + For pm6125 s1, s2, s3, s4, s5, s6, s7, s8, l1, l2, l3, l5, l6, l7, l8, l9, + l10, l22, l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24 + + For pm660, s1, s2, s3, s4, s5, s6, l1, l2, l3, l5, l6, l7, l8, l9, l10, l22, + l12, l13, l14, l15, l16, l17, l18, l19 + + For pm660l s1, s2, s3, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, bob + For pm8226, s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, l25, l26, l27, l28, lvs1 @@ -52,11 +63,6 @@ description: l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, l25, l26, l27, l28, lvs1, lvs2 - For pm660, s1, s2, s3, s4, s5, s6, l1, l2, l3, l5, l6, l7, l8, l9, l10, l22, - l12, l13, l14, l15, l16, l17, l18, l19 - - For pm660l s1, s2, s3, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, bob - For pma8084, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, l25, l26, l27, lvs1, lvs2, lvs3, lvs4, 5vs1 @@ -68,9 +74,6 @@ description: For pms405, s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13 - For pm2250, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, - l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22 - maintainers: - Andy Gross <agross@kernel.org> - Bjorn Andersson <bjorn.andersson@linaro.org> @@ -79,6 +82,10 @@ properties: compatible: enum: - qcom,rpm-mp5496-regulators + - qcom,rpm-pm2250-regulators + - qcom,rpm-pm6125-regulators + - qcom,rpm-pm660-regulators + - qcom,rpm-pm660l-regulators - qcom,rpm-pm8226-regulators - qcom,rpm-pm8841-regulators - qcom,rpm-pm8909-regulators @@ -88,13 +95,10 @@ properties: - qcom,rpm-pm8953-regulators - qcom,rpm-pm8994-regulators - qcom,rpm-pm8998-regulators - - qcom,rpm-pm660-regulators - - qcom,rpm-pm660l-regulators - qcom,rpm-pma8084-regulators - qcom,rpm-pmi8994-regulators - qcom,rpm-pmi8998-regulators - qcom,rpm-pms405-regulators - - qcom,rpm-pm2250-regulators patternProperties: ".*-supply$": diff --git a/dts/Bindings/regulator/qcom,spmi-regulator.yaml b/dts/Bindings/regulator/qcom,spmi-regulator.yaml index faa4af9fd0..bdf34c2de9 100644 --- a/dts/Bindings/regulator/qcom,spmi-regulator.yaml +++ b/dts/Bindings/regulator/qcom,spmi-regulator.yaml @@ -12,6 +12,7 @@ maintainers: properties: compatible: enum: + - qcom,pm6125-regulators - qcom,pm660-regulators - qcom,pm660l-regulators - qcom,pm8004-regulators @@ -110,6 +111,25 @@ allOf: compatible: contains: enum: + - qcom,pm6125-regulators + then: + properties: + vdd_l1_l7_l17_l18-supply: true + vdd_l2_l3_l4-supply: true + vdd_l5_l15_l19_l20_l21_l22-supply: true + vdd_l6_l8-supply: true + vdd_l9_l11-supply: true + vdd_l10_l13_l14-supply: true + vdd_l12_l16-supply: true + vdd_l23_l24-supply: true + patternProperties: + "^vdd_s[1-8]-supply$": true + + - if: + properties: + compatible: + contains: + enum: - qcom,pm660-regulators then: properties: @@ -120,6 +140,7 @@ allOf: vdd_l8_l9_l10_l11_l12_l13_l14-supply: true patternProperties: "^vdd_s[1-6]-supply$": true + - if: properties: compatible: @@ -134,6 +155,7 @@ allOf: vdd_l4_l6-supply: true patternProperties: "^vdd_s[1-5]-supply$": true + - if: properties: compatible: @@ -143,6 +165,7 @@ allOf: then: patternProperties: "^vdd_s[25]-supply$": true + - if: properties: compatible: @@ -152,6 +175,7 @@ allOf: then: patternProperties: "^vdd_s[1-4]-supply$": true + - if: properties: compatible: @@ -171,6 +195,7 @@ allOf: vdd_lvs1-supply: true patternProperties: "^vdd_s[1-5]-supply$": true + - if: properties: compatible: @@ -180,6 +205,7 @@ allOf: then: patternProperties: "^vdd_s[1-8]-supply$": true + - if: properties: compatible: @@ -195,6 +221,7 @@ allOf: patternProperties: "^vdd_l[27]-supply$": true "^vdd_s[1-4]-supply$": true + - if: properties: compatible: @@ -223,6 +250,7 @@ allOf: vin_5vs-supply: true patternProperties: "^vdd_s[1-3]-supply$": true + - if: properties: compatible: @@ -241,6 +269,7 @@ allOf: vdd_l9_l10_l13_l14_l15_l18-supply: true patternProperties: "^vdd_s[1-6]-supply$": true + - if: properties: compatible: @@ -265,6 +294,7 @@ allOf: vdd_lvs_1_2-supply: true patternProperties: "^vdd_s[1-9][0-2]?-supply$": true + - if: properties: compatible: @@ -276,6 +306,7 @@ allOf: vdd_l1-supply: true patternProperties: "^vdd_s[1-3]-supply$": true + - if: properties: compatible: @@ -291,6 +322,7 @@ allOf: patternProperties: "^vdd_l[479]-supply$": true "^vdd_s[1-5]-supply$": true + - if: properties: compatible: diff --git a/dts/Bindings/regulator/qcom-labibb-regulator.yaml b/dts/Bindings/regulator/qcom-labibb-regulator.yaml index 1ddc1efd19..f97b808367 100644 --- a/dts/Bindings/regulator/qcom-labibb-regulator.yaml +++ b/dts/Bindings/regulator/qcom-labibb-regulator.yaml @@ -20,6 +20,7 @@ properties: lab: type: object + additionalProperties: false properties: qcom,soft-start-us: @@ -33,11 +34,19 @@ properties: description: Short-circuit and over-current interrupts for lab. + interrupt-names: + minItems: 1 + items: + - const: sc-err + - const: ocp + required: - interrupts + - interrupt-names ibb: type: object + additionalProperties: false properties: qcom,discharge-resistor-kohms: @@ -52,8 +61,15 @@ properties: description: Short-circuit and over-current interrupts for ibb. + interrupt-names: + minItems: 1 + items: + - const: sc-err + - const: ocp + required: - interrupts + - interrupt-names required: - compatible diff --git a/dts/Bindings/regulator/richtek,rt4801-regulator.yaml b/dts/Bindings/regulator/richtek,rt4801-regulator.yaml index 091150c4e5..4a8a221bc9 100644 --- a/dts/Bindings/regulator/richtek,rt4801-regulator.yaml +++ b/dts/Bindings/regulator/richtek,rt4801-regulator.yaml @@ -42,6 +42,7 @@ patternProperties: "^DSV(P|N)$": type: object $ref: regulator.yaml# + unevaluatedProperties: false description: Properties for single display bias regulator. diff --git a/dts/Bindings/regulator/rohm,bd71815-regulator.yaml b/dts/Bindings/regulator/rohm,bd71815-regulator.yaml index 7d0adb74a3..d61e8675f0 100644 --- a/dts/Bindings/regulator/rohm,bd71815-regulator.yaml +++ b/dts/Bindings/regulator/rohm,bd71815-regulator.yaml @@ -27,6 +27,7 @@ properties: description: properties for wled regulator $ref: regulator.yaml# + unevaluatedProperties: false properties: regulator-name: diff --git a/dts/Bindings/regulator/silergy,sy8106a.yaml b/dts/Bindings/regulator/silergy,sy8106a.yaml index a52a67c869..c3a902e11b 100644 --- a/dts/Bindings/regulator/silergy,sy8106a.yaml +++ b/dts/Bindings/regulator/silergy,sy8106a.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/regulator/silergy,sy8106a.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Silergy SY8106A Voltage Regulator Device Tree Bindings +title: Silergy SY8106A Voltage Regulator maintainers: - Ondrej Jirman <megous@megous.com> diff --git a/dts/Bindings/regulator/ti,tps65219.yaml b/dts/Bindings/regulator/ti,tps65219.yaml new file mode 100644 index 0000000000..78be79930f --- /dev/null +++ b/dts/Bindings/regulator/ti,tps65219.yaml @@ -0,0 +1,173 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/ti,tps65219.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI tps65219 Power Management Integrated Circuit regulators + +maintainers: + - Jerome Neanne <jerome.neanne@baylibre.com> + +description: | + Regulator nodes should be named to buck<number> and ldo<number>. + +properties: + compatible: + enum: + - ti,tps65219 + + reg: + maxItems: 1 + + system-power-controller: + type: boolean + description: Optional property that indicates that this device is + controlling system power. + + interrupts: + description: Short-circuit, over-current, under-voltage for regulators, PB interrupts. + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: Specifies the PIN numbers and Flags, as defined in + include/dt-bindings/interrupt-controller/irq.h + const: 1 + + ti,power-button: + type: boolean + description: | + Optional property that sets the EN/PB/VSENSE pin to be a + power-button. + TPS65219 has a multipurpose pin called EN/PB/VSENSE that can be either + 1. EN in which case it functions as an enable pin. + 2. VSENSE which compares the voltages and triggers an automatic + on/off request. + 3. PB in which case it can be configured to trigger an interrupt + to the SoC. + ti,power-button reflects the last one of those options + where the board has a button wired to the pin and triggers + an interrupt on pressing it. + +patternProperties: + "^buck[1-3]-supply$": + description: Input supply phandle of one regulator. + + "^ldo[1-4]-supply$": + description: Input supply phandle of one regulator. + + regulators: + type: object + description: | + list of regulators provided by this controller + + patternProperties: + "^ldo[1-4]$": + type: object + $ref: regulator.yaml# + description: + Properties for single LDO regulator. + + unevaluatedProperties: false + + "^buck[1-3]$": + type: object + $ref: regulator.yaml# + description: + Properties for single BUCK regulator. + + unevaluatedProperties: false + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - regulators + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + tps65219: pmic@30 { + compatible = "ti,tps65219"; + reg = <0x30>; + buck1-supply = <&vcc_3v3_sys>; + buck2-supply = <&vcc_3v3_sys>; + buck3-supply = <&vcc_3v3_sys>; + ldo1-supply = <&vcc_3v3_sys>; + ldo2-supply = <&buck2_reg>; + ldo3-supply = <&vcc_3v3_sys>; + ldo4-supply = <&vcc_3v3_sys>; + + pinctrl-0 = <&pmic_irq_pins_default>; + + interrupt-parent = <&gic500>; + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + ti,power-button; + + regulators { + buck1_reg: buck1 { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-boot-on; + regulator-always-on; + }; + + buck2_reg: buck2 { + regulator-name = "VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck3_reg: buck3 { + regulator-name = "VDD_LPDDR4"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "VDDSHV_SD_IO_PMIC"; + regulator-min-microvolt = <33000000>; + regulator-max-microvolt = <33000000>; + }; + + ldo2_reg: ldo2 { + regulator-name = "VDDAR_CORE"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <18000000>; + regulator-max-microvolt = <18000000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: ldo4 { + regulator-name = "VDD_PHY_2V5"; + regulator-min-microvolt = <25000000>; + regulator-max-microvolt = <25000000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + }; diff --git a/dts/Bindings/remoteproc/qcom,adsp.yaml b/dts/Bindings/remoteproc/qcom,adsp.yaml index 3072af5f9d..db9e0f0c2b 100644 --- a/dts/Bindings/remoteproc/qcom,adsp.yaml +++ b/dts/Bindings/remoteproc/qcom,adsp.yaml @@ -152,6 +152,7 @@ properties: description: Qualcomm Shared Memory subnode which represents communication edge, channels and devices related to the ADSP. + unevaluatedProperties: false glink-edge: $ref: /schemas/remoteproc/qcom,glink-edge.yaml# diff --git a/dts/Bindings/remoteproc/qcom,glink-edge.yaml b/dts/Bindings/remoteproc/qcom,glink-edge.yaml index fa69f7b21e..25c27464ef 100644 --- a/dts/Bindings/remoteproc/qcom,glink-edge.yaml +++ b/dts/Bindings/remoteproc/qcom,glink-edge.yaml @@ -19,13 +19,17 @@ properties: apr: $ref: /schemas/soc/qcom/qcom,apr.yaml# + required: + - qcom,glink-channels description: Qualcomm APR/GPR (Asynchronous/Generic Packet Router) fastrpc: - type: object + $ref: /schemas/misc/qcom,fastrpc.yaml# + required: + - qcom,glink-channels description: - See Documentation/devicetree/bindings/misc/qcom,fastrpc.txt + Qualcomm FastRPC interrupts: maxItems: 1 diff --git a/dts/Bindings/remoteproc/qcom,pil-info.yaml b/dts/Bindings/remoteproc/qcom,pil-info.yaml index 9282837d64..a7711e3c99 100644 --- a/dts/Bindings/remoteproc/qcom,pil-info.yaml +++ b/dts/Bindings/remoteproc/qcom,pil-info.yaml @@ -30,7 +30,7 @@ additionalProperties: false examples: - | imem@146bf000 { - compatible = "syscon", "simple-mfd"; + compatible = "qcom,sdm630-imem", "syscon", "simple-mfd"; reg = <0x146bf000 0x1000>; #address-cells = <1>; diff --git a/dts/Bindings/remoteproc/qcom,sc7180-mss-pil.yaml b/dts/Bindings/remoteproc/qcom,sc7180-mss-pil.yaml index e76c861165..e4a7da8020 100644 --- a/dts/Bindings/remoteproc/qcom,sc7180-mss-pil.yaml +++ b/dts/Bindings/remoteproc/qcom,sc7180-mss-pil.yaml @@ -140,6 +140,7 @@ properties: glink-edge: $ref: qcom,glink-edge.yaml# + unevaluatedProperties: false description: Qualcomm G-Link subnode which represents communication edge, channels and devices related to the DSP. diff --git a/dts/Bindings/remoteproc/qcom,sc7280-mss-pil.yaml b/dts/Bindings/remoteproc/qcom,sc7280-mss-pil.yaml index da1a5de3d3..b4de0521a8 100644 --- a/dts/Bindings/remoteproc/qcom,sc7280-mss-pil.yaml +++ b/dts/Bindings/remoteproc/qcom,sc7280-mss-pil.yaml @@ -154,6 +154,7 @@ properties: glink-edge: $ref: qcom,glink-edge.yaml# + unevaluatedProperties: false description: Qualcomm G-Link subnode which represents communication edge, channels and devices related to the DSP. diff --git a/dts/Bindings/remoteproc/qcom,sc7280-wpss-pil.yaml b/dts/Bindings/remoteproc/qcom,sc7280-wpss-pil.yaml index 3f06d66cbe..b6bd334385 100644 --- a/dts/Bindings/remoteproc/qcom,sc7280-wpss-pil.yaml +++ b/dts/Bindings/remoteproc/qcom,sc7280-wpss-pil.yaml @@ -107,6 +107,7 @@ properties: glink-edge: $ref: qcom,glink-edge.yaml# + unevaluatedProperties: false description: Qualcomm G-Link subnode which represents communication edge, channels and devices related to the ADSP. diff --git a/dts/Bindings/remoteproc/qcom,smd-edge.yaml b/dts/Bindings/remoteproc/qcom,smd-edge.yaml index 06eebf791e..7ec8a6b668 100644 --- a/dts/Bindings/remoteproc/qcom,smd-edge.yaml +++ b/dts/Bindings/remoteproc/qcom,smd-edge.yaml @@ -13,12 +13,30 @@ description: Qualcomm SMD subnode represents a remote subsystem or a remote processor of some sort - or in SMD language an "edge". The name of the edges are not important. + + In turn, subnodes of the "edges" represent devices tied to SMD channels on + that "edge". The names of the devices are not important. The properties of + these nodes are defined by the individual bindings for the SMD devices. See also Documentation/devicetree/bindings/soc/qcom/qcom,smd.yaml properties: $nodename: const: "smd-edge" + apr: + $ref: /schemas/soc/qcom/qcom,apr.yaml# + required: + - qcom,smd-channels + description: + Qualcomm APR/GPR (Asynchronous/Generic Packet Router) + + fastrpc: + $ref: /schemas/misc/qcom,fastrpc.yaml# + required: + - qcom,smd-channels + description: + Qualcomm FastRPC + interrupts: maxItems: 1 @@ -56,6 +74,20 @@ properties: The identifier for the remote processor as known by the rest of the system. + rpm-requests: + $ref: /schemas/soc/qcom/qcom,smd-rpm.yaml# + required: + - qcom,smd-channels + description: + Qualcomm Resource Power Manager (RPM) over SMD. + + wcnss: + $ref: /schemas/soc/qcom/qcom,wcnss.yaml + required: + - qcom,smd-channels + description: + Qualcomm WCNSS for Bluetooth, WiFi and FM radio. + required: - interrupts - qcom,smd-edge @@ -66,7 +98,7 @@ oneOf: - required: - qcom,ipc -additionalProperties: true +additionalProperties: false examples: - | diff --git a/dts/Bindings/reserved-memory/google,open-dice.yaml b/dts/Bindings/reserved-memory/google,open-dice.yaml index 257a0b5199..a924fcfca0 100644 --- a/dts/Bindings/reserved-memory/google,open-dice.yaml +++ b/dts/Bindings/reserved-memory/google,open-dice.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/reserved-memory/google,open-dice.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Open Profile for DICE Device Tree Bindings +title: Open Profile for DICE description: | This binding represents a reserved memory region containing data diff --git a/dts/Bindings/reserved-memory/memory-region.yaml b/dts/Bindings/reserved-memory/memory-region.yaml index 83dfe499a2..592f180e6b 100644 --- a/dts/Bindings/reserved-memory/memory-region.yaml +++ b/dts/Bindings/reserved-memory/memory-region.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/reserved-memory/memory-region.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Reserved Memory Region Device Tree Binding +title: Reserved Memory Region maintainers: - devicetree-spec@vger.kernel.org diff --git a/dts/Bindings/reserved-memory/nvidia,tegra210-emc-table.yaml b/dts/Bindings/reserved-memory/nvidia,tegra210-emc-table.yaml index 035a50fe3e..b1b0421a42 100644 --- a/dts/Bindings/reserved-memory/nvidia,tegra210-emc-table.yaml +++ b/dts/Bindings/reserved-memory/nvidia,tegra210-emc-table.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/reserved-memory/nvidia,tegra210-emc-table.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: NVIDIA Tegra210 EMC Frequency Table Device Tree Bindings +title: NVIDIA Tegra210 EMC Frequency Table maintainers: - Thierry Reding <thierry.reding@gmail.com> diff --git a/dts/Bindings/reserved-memory/reserved-memory.yaml b/dts/Bindings/reserved-memory/reserved-memory.yaml index 7a0744052f..44f72bcf17 100644 --- a/dts/Bindings/reserved-memory/reserved-memory.yaml +++ b/dts/Bindings/reserved-memory/reserved-memory.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/reserved-memory/reserved-memory.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: /reserved-memory Child Node Common Device Tree Bindings +title: /reserved-memory Child Node Common maintainers: - devicetree-spec@vger.kernel.org diff --git a/dts/Bindings/reset/allwinner,sun6i-a31-clock-reset.yaml b/dts/Bindings/reset/allwinner,sun6i-a31-clock-reset.yaml index 001c0d2a8c..2a248e511c 100644 --- a/dts/Bindings/reset/allwinner,sun6i-a31-clock-reset.yaml +++ b/dts/Bindings/reset/allwinner,sun6i-a31-clock-reset.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/reset/allwinner,sun6i-a31-clock-reset.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A31 Peripheral Reset Controller Device Tree Bindings +title: Allwinner A31 Peripheral Reset Controller maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/reset/canaan,k210-rst.yaml b/dts/Bindings/reset/canaan,k210-rst.yaml index 53e4ede9c0..ee8a2dcf5d 100644 --- a/dts/Bindings/reset/canaan,k210-rst.yaml +++ b/dts/Bindings/reset/canaan,k210-rst.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/reset/canaan,k210-rst.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Canaan Kendryte K210 Reset Controller Device Tree Bindings +title: Canaan Kendryte K210 Reset Controller maintainers: - Damien Le Moal <damien.lemoal@wdc.com> diff --git a/dts/Bindings/reset/starfive,jh7100-reset.yaml b/dts/Bindings/reset/starfive,jh7100-reset.yaml index 300359a5e1..2f5bd616b7 100644 --- a/dts/Bindings/reset/starfive,jh7100-reset.yaml +++ b/dts/Bindings/reset/starfive,jh7100-reset.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/reset/starfive,jh7100-reset.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: StarFive JH7100 SoC Reset Controller Device Tree Bindings +title: StarFive JH7100 SoC Reset Controller maintainers: - Emil Renner Berthing <kernel@esmil.dk> diff --git a/dts/Bindings/riscv/cpus.yaml b/dts/Bindings/riscv/cpus.yaml index 873dd12f6e..90a7cabf58 100644 --- a/dts/Bindings/riscv/cpus.yaml +++ b/dts/Bindings/riscv/cpus.yaml @@ -9,6 +9,7 @@ title: RISC-V bindings for 'cpus' DT nodes maintainers: - Paul Walmsley <paul.walmsley@sifive.com> - Palmer Dabbelt <palmer@sifive.com> + - Conor Dooley <conor@kernel.org> description: | This document uses some terminology common to the RISC-V community @@ -79,9 +80,7 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" - enum: - - rv64imac - - rv64imafdc + pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$ # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false diff --git a/dts/Bindings/riscv/microchip.yaml b/dts/Bindings/riscv/microchip.yaml index 1aa7336a96..714d0fcab3 100644 --- a/dts/Bindings/riscv/microchip.yaml +++ b/dts/Bindings/riscv/microchip.yaml @@ -4,11 +4,11 @@ $id: http://devicetree.org/schemas/riscv/microchip.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Microchip PolarFire SoC-based boards device tree bindings +title: Microchip PolarFire SoC-based boards maintainers: - - Cyril Jean <Cyril.Jean@microchip.com> - - Lewis Hanly <lewis.hanly@microchip.com> + - Conor Dooley <conor.dooley@microchip.com> + - Daire McNamara <daire.mcnamara@microchip.com> description: Microchip PolarFire SoC-based boards @@ -17,12 +17,20 @@ properties: $nodename: const: '/' compatible: - items: - - enum: - - microchip,mpfs-icicle-kit - - microchip,mpfs-icicle-reference-rtlv2203 - - sundance,polarberry - - const: microchip,mpfs + oneOf: + - items: + - enum: + - microchip,mpfs-icicle-reference-rtlv2203 + - microchip,mpfs-icicle-reference-rtlv2210 + - const: microchip,mpfs-icicle-kit + - const: microchip,mpfs + + - items: + - enum: + - aries,m100pfsevp + - microchip,mpfs-sev-kit + - sundance,polarberry + - const: microchip,mpfs additionalProperties: true diff --git a/dts/Bindings/riscv/sifive-l2-cache.yaml b/dts/Bindings/riscv/sifive,ccache0.yaml index ca3b9be580..bf3f07421f 100644 --- a/dts/Bindings/riscv/sifive-l2-cache.yaml +++ b/dts/Bindings/riscv/sifive,ccache0.yaml @@ -2,18 +2,18 @@ # Copyright (C) 2020 SiFive, Inc. %YAML 1.2 --- -$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml# +$id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: SiFive L2 Cache Controller +title: SiFive Composable Cache Controller maintainers: - Sagar Kadam <sagar.kadam@sifive.com> - Paul Walmsley <paul.walmsley@sifive.com> description: - The SiFive Level 2 Cache Controller is used to provide access to fast copies - of memory for masters in a Core Complex. The Level 2 Cache Controller also + The SiFive Composable Cache Controller is used to provide access to fast copies + of memory for masters in a Core Complex. The Composable Cache Controller also acts as directory-based coherency manager. All the properties in ePAPR/DeviceTree specification applies for this platform. @@ -22,6 +22,7 @@ select: compatible: contains: enum: + - sifive,ccache0 - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache @@ -33,6 +34,7 @@ properties: oneOf: - items: - enum: + - sifive,ccache0 - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache - const: cache @@ -45,7 +47,7 @@ properties: const: 64 cache-level: - const: 2 + enum: [2, 3] cache-sets: enum: [1024, 2048] @@ -115,6 +117,22 @@ allOf: cache-sets: const: 1024 + - if: + properties: + compatible: + contains: + const: sifive,ccache0 + + then: + properties: + cache-level: + enum: [2, 3] + + else: + properties: + cache-level: + const: 2 + additionalProperties: false required: diff --git a/dts/Bindings/rng/omap_rng.yaml b/dts/Bindings/rng/omap_rng.yaml index 010188cdbe..ccf54fae83 100644 --- a/dts/Bindings/rng/omap_rng.yaml +++ b/dts/Bindings/rng/omap_rng.yaml @@ -53,17 +53,6 @@ allOf: required: - interrupts - - if: - properties: - compatible: - contains: - enum: - - inside-secure,safexcel-eip76 - - then: - required: - - clocks - required: - compatible diff --git a/dts/Bindings/rtc/allwinner,sun4i-a10-rtc.yaml b/dts/Bindings/rtc/allwinner,sun4i-a10-rtc.yaml index 478b0234e8..dede494317 100644 --- a/dts/Bindings/rtc/allwinner,sun4i-a10-rtc.yaml +++ b/dts/Bindings/rtc/allwinner,sun4i-a10-rtc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/rtc/allwinner,sun4i-a10-rtc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 RTC Device Tree Bindings +title: Allwinner A10 RTC allOf: - $ref: "rtc.yaml#" diff --git a/dts/Bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/dts/Bindings/rtc/allwinner,sun6i-a31-rtc.yaml index 6b38bd7eb3..04947e166c 100644 --- a/dts/Bindings/rtc/allwinner,sun6i-a31-rtc.yaml +++ b/dts/Bindings/rtc/allwinner,sun6i-a31-rtc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/rtc/allwinner,sun6i-a31-rtc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A31 RTC Device Tree Bindings +title: Allwinner A31 RTC maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/rtc/atmel,at91rm9200-rtc.yaml b/dts/Bindings/rtc/atmel,at91rm9200-rtc.yaml index 994de43d17..0e5f0fcc26 100644 --- a/dts/Bindings/rtc/atmel,at91rm9200-rtc.yaml +++ b/dts/Bindings/rtc/atmel,at91rm9200-rtc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/rtc/atmel,at91rm9200-rtc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Atmel AT91 RTC Device Tree Bindings +title: Atmel AT91 RTC allOf: - $ref: "rtc.yaml#" diff --git a/dts/Bindings/rtc/atmel,at91sam9260-rtt.yaml b/dts/Bindings/rtc/atmel,at91sam9260-rtt.yaml index 0ef1b7ff4a..b5cd20e89d 100644 --- a/dts/Bindings/rtc/atmel,at91sam9260-rtt.yaml +++ b/dts/Bindings/rtc/atmel,at91sam9260-rtt.yaml @@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/rtc/atmel,at91sam9260-rtt.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Atmel AT91 RTT Device Tree Bindings +title: Atmel AT91 RTT allOf: - $ref: "rtc.yaml#" diff --git a/dts/Bindings/rtc/microchip,mfps-rtc.yaml b/dts/Bindings/rtc/microchip,mfps-rtc.yaml index 500c62becd..7742465b93 100644 --- a/dts/Bindings/rtc/microchip,mfps-rtc.yaml +++ b/dts/Bindings/rtc/microchip,mfps-rtc.yaml @@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings +title: Microchip PolarFire Soc (MPFS) RTC allOf: - $ref: rtc.yaml# diff --git a/dts/Bindings/rtc/microcrystal,rv3032.yaml b/dts/Bindings/rtc/microcrystal,rv3032.yaml index 60f9027e82..dd6eebf06e 100644 --- a/dts/Bindings/rtc/microcrystal,rv3032.yaml +++ b/dts/Bindings/rtc/microcrystal,rv3032.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/rtc/microcrystal,rv3032.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Microchip RV-3032 RTC Device Tree Bindings +title: Microchip RV-3032 RTC allOf: - $ref: "rtc.yaml#" diff --git a/dts/Bindings/rtc/mstar,msc313-rtc.yaml b/dts/Bindings/rtc/mstar,msc313-rtc.yaml index 114199cf4d..585c185d1e 100644 --- a/dts/Bindings/rtc/mstar,msc313-rtc.yaml +++ b/dts/Bindings/rtc/mstar,msc313-rtc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/rtc/mstar,msc313-rtc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mstar MSC313e RTC Device Tree Bindings +title: Mstar MSC313e RTC allOf: - $ref: "rtc.yaml#" diff --git a/dts/Bindings/serial/atmel,at91-usart.yaml b/dts/Bindings/serial/atmel,at91-usart.yaml new file mode 100644 index 0000000000..30b2131b58 --- /dev/null +++ b/dts/Bindings/serial/atmel,at91-usart.yaml @@ -0,0 +1,190 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/atmel,at91-usart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART) + +maintainers: + - Richard Genoud <richard.genoud@gmail.com> + +properties: + compatible: + oneOf: + - enum: + - atmel,at91rm9200-usart + - atmel,at91sam9260-usart + - microchip,sam9x60-usart + - items: + - const: atmel,at91rm9200-dbgu + - const: atmel,at91rm9200-usart + - items: + - const: atmel,at91sam9260-dbgu + - const: atmel,at91sam9260-usart + - items: + - const: microchip,sam9x60-dbgu + - const: microchip,sam9x60-usart + - const: atmel,at91sam9260-dbgu + - const: atmel,at91sam9260-usart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-names: + minItems: 1 + items: + - const: usart + - const: gclk + + clocks: + minItems: 1 + items: + - description: USART Peripheral Clock + - description: USART Generic Clock + + dmas: + items: + - description: TX DMA Channel + - description: RX DMA Channel + + dma-names: + items: + - const: tx + - const: rx + + atmel,usart-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Must be either <AT91_USART_MODE_SPI> for SPI or + <AT91_USART_MODE_SERIAL> for USART (found in dt-bindings/mfd/at91-usart.h). + enum: [ 0, 1 ] + + atmel,use-dma-rx: + type: boolean + description: use of PDC or DMA for receiving data + + atmel,use-dma-tx: + type: boolean + description: use of PDC or DMA for transmitting data + + atmel,fifo-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Maximum number of data the RX and TX FIFOs can store for FIFO + capable USARTS. + enum: [ 16, 32 ] + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + - atmel,usart-mode + +allOf: + - if: + properties: + atmel,usart-mode: + const: 1 + then: + allOf: + - $ref: /schemas/spi/spi-controller.yaml# + + properties: + atmel,use-dma-rx: false + + atmel,use-dma-tx: false + + atmel,fifo-size: false + + "#size-cells": + const: 0 + + "#address-cells": + const: 1 + + required: + - "#size-cells" + - "#address-cells" + + else: + allOf: + - $ref: /schemas/serial/serial.yaml# + - $ref: /schemas/serial/rs485.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/mfd/at91-usart.h> + #include <dt-bindings/dma/at91.h> + + /* use PDC */ + usart0: serial@fff8c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff8c000 0x4000>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; + interrupts = <7>; + clocks = <&usart0_clk>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + rts-gpios = <&pioD 15 GPIO_ACTIVE_LOW>; + cts-gpios = <&pioD 16 GPIO_ACTIVE_LOW>; + dtr-gpios = <&pioD 17 GPIO_ACTIVE_LOW>; + dsr-gpios = <&pioD 18 GPIO_ACTIVE_LOW>; + dcd-gpios = <&pioD 20 GPIO_ACTIVE_LOW>; + rng-gpios = <&pioD 19 GPIO_ACTIVE_LOW>; + }; + + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/mfd/at91-usart.h> + #include <dt-bindings/dma/at91.h> + + /* use DMA */ + usart1: serial@f001c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf001c000 0x100>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&usart0_clk>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + }; + + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/mfd/at91-usart.h> + #include <dt-bindings/dma/at91.h> + + /* SPI mode */ + spi0: spi@f001c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf001c000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + atmel,usart-mode = <AT91_USART_MODE_SPI>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&usart0_clk>; + clock-names = "usart"; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>; + }; diff --git a/dts/Bindings/serial/cdns,uart.yaml b/dts/Bindings/serial/cdns,uart.yaml index fcdbe6f87e..876b8cf1ca 100644 --- a/dts/Bindings/serial/cdns,uart.yaml +++ b/dts/Bindings/serial/cdns,uart.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/serial/cdns,uart.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Cadence UART Controller Device Tree Bindings +title: Cadence UART Controller maintainers: - Michal Simek <michal.simek@xilinx.com> diff --git a/dts/Bindings/serial/mediatek,uart.yaml b/dts/Bindings/serial/mediatek,uart.yaml index 4ff27d6d4d..fe098d98af 100644 --- a/dts/Bindings/serial/mediatek,uart.yaml +++ b/dts/Bindings/serial/mediatek,uart.yaml @@ -42,6 +42,7 @@ properties: - mediatek,mt8173-uart - mediatek,mt8183-uart - mediatek,mt8186-uart + - mediatek,mt8188-uart - mediatek,mt8192-uart - mediatek,mt8195-uart - mediatek,mt8516-uart diff --git a/dts/Bindings/serial/pl011.yaml b/dts/Bindings/serial/pl011.yaml index d8aed84abc..80af728598 100644 --- a/dts/Bindings/serial/pl011.yaml +++ b/dts/Bindings/serial/pl011.yaml @@ -94,6 +94,12 @@ properties: resets: maxItems: 1 + reg-io-width: + description: + The size (in bytes) of the IO accesses that should be performed + on the device. + enum: [1, 4] + required: - compatible - reg diff --git a/dts/Bindings/serial/renesas,scif.yaml b/dts/Bindings/serial/renesas,scif.yaml index 90fe45265f..f930e7f134 100644 --- a/dts/Bindings/serial/renesas,scif.yaml +++ b/dts/Bindings/serial/renesas,scif.yaml @@ -76,7 +76,7 @@ properties: - items: - enum: - - renesas,scif-r9a07g043 # RZ/G2UL + - renesas,scif-r9a07g043 # RZ/G2UL and RZ/Five - renesas,scif-r9a07g054 # RZ/V2L - const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback diff --git a/dts/Bindings/serial/samsung_uart.yaml b/dts/Bindings/serial/samsung_uart.yaml index 901c1e2cea..8bd88d5cbb 100644 --- a/dts/Bindings/serial/samsung_uart.yaml +++ b/dts/Bindings/serial/samsung_uart.yaml @@ -17,7 +17,10 @@ description: |+ properties: compatible: - items: + oneOf: + - items: + - const: samsung,exynosautov9-uart + - const: samsung,exynos850-uart - enum: - apple,s5l-uart - axis,artpec8-uart @@ -37,7 +40,6 @@ properties: description: | The size (in bytes) of the IO accesses that should be performed on the device. - $ref: /schemas/types.yaml#/definitions/uint32 enum: [ 1, 4 ] clocks: @@ -69,6 +71,9 @@ properties: minItems: 1 maxItems: 2 + power-domains: + maxItems: 1 + samsung,uart-fifosize: description: The fifo size supported by the UART channel. $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/dts/Bindings/serial/snps-dw-apb-uart.yaml b/dts/Bindings/serial/snps-dw-apb-uart.yaml index dc74643ae7..b9c2287c5d 100644 --- a/dts/Bindings/serial/snps-dw-apb-uart.yaml +++ b/dts/Bindings/serial/snps-dw-apb-uart.yaml @@ -26,6 +26,7 @@ properties: - rockchip,rk1808-uart - rockchip,rk3036-uart - rockchip,rk3066-uart + - rockchip,rk3128-uart - rockchip,rk3188-uart - rockchip,rk3288-uart - rockchip,rk3308-uart diff --git a/dts/Bindings/serial/sunplus,sp7021-uart.yaml b/dts/Bindings/serial/sunplus,sp7021-uart.yaml index 2e9b64abde..ea1e637661 100644 --- a/dts/Bindings/serial/sunplus,sp7021-uart.yaml +++ b/dts/Bindings/serial/sunplus,sp7021-uart.yaml @@ -5,7 +5,7 @@ $id: "http://devicetree.org/schemas/serial/sunplus,sp7021-uart.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: Sunplus SoC SP7021 UART Controller Device Tree Bindings +title: Sunplus SoC SP7021 UART Controller maintainers: - Hammer Hsieh <hammerh0314@gmail.com> diff --git a/dts/Bindings/serio/allwinner,sun4i-a10-ps2.yaml b/dts/Bindings/serio/allwinner,sun4i-a10-ps2.yaml index 2ecab8ed70..7fa70fd1f2 100644 --- a/dts/Bindings/serio/allwinner,sun4i-a10-ps2.yaml +++ b/dts/Bindings/serio/allwinner,sun4i-a10-ps2.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/serio/allwinner,sun4i-a10-ps2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 PS2 Host Controller Device Tree Bindings +title: Allwinner A10 PS2 Host Controller maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml b/dts/Bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml index 26487daa64..d71bb20d49 100644 --- a/dts/Bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml +++ b/dts/Bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml @@ -27,25 +27,22 @@ properties: const: 1 power-domains: - minItems: 4 maxItems: 4 power-domain-names: - items: - - const: bus - - const: g1 - - const: g2 - - const: h1 + maxItems: 4 clocks: - minItems: 3 maxItems: 3 clock-names: - items: - - const: g1 - - const: g2 - - const: h1 + maxItems: 3 + + interconnects: + maxItems: 3 + + interconnect-names: + maxItems: 3 required: - compatible @@ -55,6 +52,97 @@ required: - clocks - clock-names +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx8mm-vpu-blk-ctrl + then: + properties: + power-domains: + items: + - description: bus power domain + - description: G1 decoder power domain + - description: G2 decoder power domain + - description: H1 encoder power domain + + power-domain-names: + items: + - const: bus + - const: g1 + - const: g2 + - const: h1 + + clocks: + items: + - description: G1 decoder clk + - description: G2 decoder clk + - description: H1 encoder clk + + clock-names: + items: + - const: g1 + - const: g2 + - const: h1 + + interconnects: + items: + - description: G1 decoder interconnect + - description: G2 decoder interconnect + - description: H1 encoder power domain + + interconnect-names: + items: + - const: g1 + - const: g2 + - const: h1 + + - if: + properties: + compatible: + contains: + const: fsl,imx8mp-vpu-blk-ctrl + then: + properties: + power-domains: + items: + - description: bus power domain + - description: G1 decoder power domain + - description: G2 decoder power domain + - description: VC8000E encoder power domain + + power-domain-names: + items: + - const: bus + - const: g1 + - const: g2 + - const: vc8000e + + clocks: + items: + - description: G1 decoder clk + - description: G2 decoder clk + - description: VC8000E encoder clk + + clock-names: + items: + - const: g1 + - const: g2 + - const: vc8000e + + interconnects: + items: + - description: G1 decoder interconnect + - description: G2 decoder interconnect + - description: VC8000E encoder interconnect + + interconnect-names: + items: + - const: g1 + - const: g2 + - const: vc8000e + additionalProperties: false examples: diff --git a/dts/Bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml b/dts/Bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml index 563e1d0e32..1be4ce2a45 100644 --- a/dts/Bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml +++ b/dts/Bindings/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml @@ -52,6 +52,15 @@ properties: - const: ref_266m - const: ref_24m + interconnects: + maxItems: 3 + + interconnect-names: + items: + - const: hrv + - const: lcdif-hdmi + - const: hdcp + required: - compatible - reg diff --git a/dts/Bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml b/dts/Bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml index c1e29d94f4..c29181a974 100644 --- a/dts/Bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml +++ b/dts/Bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml @@ -48,6 +48,16 @@ properties: - const: usb - const: pcie + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: noc-pcie + - const: usb1 + - const: usb2 + - const: pcie + required: - compatible - reg diff --git a/dts/Bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml b/dts/Bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml index b246d8386b..dadb6108e3 100644 --- a/dts/Bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml +++ b/dts/Bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml @@ -64,6 +64,20 @@ properties: - const: isp - const: phy + interconnects: + maxItems: 8 + + interconnect-names: + items: + - const: lcdif-rd + - const: lcdif-wr + - const: isi0 + - const: isi1 + - const: isi2 + - const: isp0 + - const: isp1 + - const: dwe + required: - compatible - reg diff --git a/dts/Bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml b/dts/Bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml new file mode 100644 index 0000000000..792ebecec2 --- /dev/null +++ b/dts/Bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx93-media-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX93 Media blk-ctrl + +maintainers: + - Peng Fan <peng.fan@nxp.com> + +description: + The i.MX93 MEDIAMIX domain contains control and status registers known + as MEDIAMIX Block Control (MEDIAMIX BLK_CTRL). These registers include + clocking, reset, and miscellaneous top-level controls for peripherals + within the MEDIAMIX domain + +properties: + compatible: + items: + - const: fsl,imx93-media-blk-ctrl + - const: syscon + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + maxItems: 1 + + clocks: + maxItems: 10 + + clock-names: + items: + - const: apb + - const: axi + - const: nic + - const: disp + - const: cam + - const: pxp + - const: lcdif + - const: isi + - const: csi + - const: dsi + +required: + - compatible + - reg + - power-domains + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx93-clock.h> + #include <dt-bindings/power/fsl,imx93-power.h> + + media_blk_ctrl: system-controller@4ac10000 { + compatible = "fsl,imx93-media-blk-ctrl", "syscon"; + reg = <0x4ac10000 0x10000>; + power-domains = <&mediamix>; + clocks = <&clk IMX93_CLK_MEDIA_APB>, + <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_NIC_MEDIA_GATE>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_CAM_PIX>, + <&clk IMX93_CLK_PXP_GATE>, + <&clk IMX93_CLK_LCDIF_GATE>, + <&clk IMX93_CLK_ISI_GATE>, + <&clk IMX93_CLK_MIPI_CSI_GATE>, + <&clk IMX93_CLK_MIPI_DSI_GATE>; + clock-names = "apb", "axi", "nic", "disp", "cam", + "pxp", "lcdif", "isi", "csi", "dsi"; + #power-domain-cells = <1>; + }; diff --git a/dts/Bindings/soc/imx/fsl,imx93-src.yaml b/dts/Bindings/soc/imx/fsl,imx93-src.yaml new file mode 100644 index 0000000000..c1cc69b519 --- /dev/null +++ b/dts/Bindings/soc/imx/fsl,imx93-src.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx93-src.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX93 System Reset Controller + +maintainers: + - Peng Fan <peng.fan@nxp.com> + +description: | + The System Reset Controller (SRC) is responsible for the generation of + all the system reset signals and boot argument latching. + + Its main functions are as follows, + - Deals with all global system reset sources from other modules, + and generates global system reset. + - Responsible for power gating of MIXs (Slices) and their memory + low power control. + +properties: + compatible: + items: + - const: fsl,imx93-src + - const: syscon + + reg: + maxItems: 1 + + ranges: true + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + +patternProperties: + "power-domain@[0-9a-f]+$": + + type: object + properties: + compatible: + items: + - const: fsl,imx93-src-slice + + '#power-domain-cells': + const: 0 + + reg: + items: + - description: mix slice register region + - description: mem slice register region + + clocks: + description: | + A number of phandles to clocks that need to be enabled + during domain power-up sequencing to ensure reset + propagation into devices located inside this power domain. + minItems: 1 + maxItems: 5 + + required: + - compatible + - '#power-domain-cells' + - reg + +required: + - compatible + - reg + - ranges + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx93-clock.h> + + system-controller@44460000 { + compatible = "fsl,imx93-src", "syscon"; + reg = <0x44460000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mediamix: power-domain@0 { + compatible = "fsl,imx93-src-slice"; + reg = <0x44462400 0x400>, <0x44465800 0x400>; + #power-domain-cells = <0>; + clocks = <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_MEDIA_APB>; + }; + }; diff --git a/dts/Bindings/soc/mediatek/mediatek,ccorr.yaml b/dts/Bindings/soc/mediatek/mediatek,ccorr.yaml new file mode 100644 index 0000000000..4380b98b0d --- /dev/null +++ b/dts/Bindings/soc/mediatek/mediatek,ccorr.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,ccorr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek color correction + +maintainers: + - Matthias Brugger <matthias.bgg@gmail.com> + - Moudy Ho <moudy.ho@mediatek.com> + +description: | + MediaTek color correction with 3X3 matrix. + +properties: + compatible: + items: + - enum: + - mediatek,mt8183-mdp3-ccorr + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + description: The register of client driver can be configured by gce with + 4 arguments defined in this property. Each GCE subsys id is mapping to + a client defined in the header include/dt-bindings/gce/<chip>-gce.h. + + mediatek,gce-events: + description: + The event id which is mapping to the specific hardware event signal + to gce. The event id is defined in the gce header + include/dt-bindings/gce/<chip>-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/uint32-array + + clocks: + minItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - mediatek,gce-events + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8183-clk.h> + #include <dt-bindings/gce/mt8183-gce.h> + + mdp3_ccorr: mdp3-ccorr@1401c000 { + compatible = "mediatek,mt8183-mdp3-ccorr"; + reg = <0x1401c000 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>, + <CMDQ_EVENT_MDP_CCORR_EOF>; + clocks = <&mmsys CLK_MM_MDP_CCORR>; + }; diff --git a/dts/Bindings/soc/mediatek/mediatek,mutex.yaml b/dts/Bindings/soc/mediatek/mediatek,mutex.yaml index 627dcc3e8b..9241e5fc7c 100644 --- a/dts/Bindings/soc/mediatek/mediatek,mutex.yaml +++ b/dts/Bindings/soc/mediatek/mediatek,mutex.yaml @@ -26,10 +26,12 @@ properties: enum: - mediatek,mt2701-disp-mutex - mediatek,mt2712-disp-mutex + - mediatek,mt6795-disp-mutex - mediatek,mt8167-disp-mutex - mediatek,mt8173-disp-mutex - mediatek,mt8183-disp-mutex - mediatek,mt8186-disp-mutex + - mediatek,mt8186-mdp3-mutex - mediatek,mt8192-disp-mutex - mediatek,mt8195-disp-mutex diff --git a/dts/Bindings/soc/mediatek/mediatek,wdma.yaml b/dts/Bindings/soc/mediatek/mediatek,wdma.yaml new file mode 100644 index 0000000000..69afb329e5 --- /dev/null +++ b/dts/Bindings/soc/mediatek/mediatek,wdma.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,wdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Write Direct Memory Access + +maintainers: + - Matthias Brugger <matthias.bgg@gmail.com> + - Moudy Ho <moudy.ho@mediatek.com> + +description: | + MediaTek Write Direct Memory Access(WDMA) component used to write + the data into DMA. + +properties: + compatible: + items: + - enum: + - mediatek,mt8183-mdp3-wdma + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + description: The register of client driver can be configured by gce with + 4 arguments defined in this property. Each GCE subsys id is mapping to + a client defined in the header include/dt-bindings/gce/<chip>-gce.h. + + mediatek,gce-events: + description: + The event id which is mapping to the specific hardware event signal + to gce. The event id is defined in the gce header + include/dt-bindings/gce/<chip>-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/uint32-array + + power-domains: + maxItems: 1 + + clocks: + minItems: 1 + + iommus: + maxItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - mediatek,gce-events + - power-domains + - clocks + - iommus + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8183-clk.h> + #include <dt-bindings/gce/mt8183-gce.h> + #include <dt-bindings/power/mt8183-power.h> + #include <dt-bindings/memory/mt8183-larb-port.h> + + mdp3_wdma: mdp3-wdma@14006000 { + compatible = "mediatek,mt8183-mdp3-wdma"; + reg = <0x14006000 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>, + <CMDQ_EVENT_MDP_WDMA0_EOF>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_WDMA0>; + iommus = <&iommu>; + }; diff --git a/dts/Bindings/soc/mediatek/pwrap.txt b/dts/Bindings/soc/mediatek/pwrap.txt index 0581dbda48..d24e2bc444 100644 --- a/dts/Bindings/soc/mediatek/pwrap.txt +++ b/dts/Bindings/soc/mediatek/pwrap.txt @@ -28,6 +28,7 @@ Required properties in pwrap device node. "mediatek,mt8173-pwrap" for MT8173 SoCs "mediatek,mt8183-pwrap" for MT8183 SoCs "mediatek,mt8186-pwrap" for MT8186 SoCs + "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap" for MT8188 SoCs "mediatek,mt8195-pwrap" for MT8195 SoCs "mediatek,mt8516-pwrap" for MT8516 SoCs - interrupts: IRQ for pwrap in SOC diff --git a/dts/Bindings/soc/qcom/qcom,apr.yaml b/dts/Bindings/soc/qcom/qcom,apr.yaml index 028c5d105a..f47491aab3 100644 --- a/dts/Bindings/soc/qcom/qcom,apr.yaml +++ b/dts/Bindings/soc/qcom/qcom,apr.yaml @@ -20,6 +20,9 @@ properties: - qcom,apr-v2 - qcom,gpr + power-domains: + maxItems: 1 + qcom,apr-domain: $ref: /schemas/types.yaml#/definitions/uint32 enum: [1, 2, 3, 4, 5, 6, 7] @@ -52,6 +55,26 @@ properties: 2 = Audio DSP Domain 3 = Application Processor Domain + qcom,glink-channels: + $ref: /schemas/types.yaml#/definitions/string-array + description: Channel name used for the communication + items: + - const: apr_audio_svc + + qcom,intents: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + List of (size, amount) pairs describing what intents should be + preallocated for this virtual channel. This can be used to tweak the + default intents available for the channel to meet expectations of the + remote. + + qcom,smd-channels: + $ref: /schemas/types.yaml#/definitions/string-array + description: Channel name used for the communication + items: + - const: apr_audio_svc + '#address-cells': const: 1 @@ -97,6 +120,26 @@ patternProperties: 3 = AMDB Service. 4 = Voice processing manager. + clock-controller: + $ref: /schemas/sound/qcom,q6dsp-lpass-clocks.yaml# + description: Qualcomm DSP LPASS clock controller + unevaluatedProperties: false + + dais: + type: object + oneOf: + - $ref: /schemas/sound/qcom,q6apm-dai.yaml# + - $ref: /schemas/sound/qcom,q6dsp-lpass-ports.yaml# + - $ref: /schemas/sound/qcom,q6asm-dais.yaml# + unevaluatedProperties: false + description: Qualcomm DSP audio ports + + routing: + type: object + $ref: /schemas/sound/qcom,q6adm-routing.yaml# + unevaluatedProperties: false + description: Qualcomm DSP LPASS audio routing + qcom,protection-domain: $ref: /schemas/types.yaml#/definitions/string-array description: protection domain service name and path for apr service @@ -107,17 +150,44 @@ patternProperties: "tms/servreg", "msm/modem/wlan_pd". "tms/servreg", "msm/slpi/sensor_pd". - '#address-cells': - const: 1 + allOf: + - if: + properties: + compatible: + enum: + - qcom,q6afe + then: + properties: + dais: + properties: + compatible: + const: qcom,q6afe-dais - '#size-cells': - const: 0 + - if: + properties: + compatible: + enum: + - qcom,q6apm + then: + properties: + dais: + properties: + compatible: + enum: + - qcom,q6apm-dais + - qcom,q6apm-lpass-dais - patternProperties: - "^.*@[0-9a-f]+$": - type: object - description: - Service based devices like clock controllers or digital audio interfaces. + - if: + properties: + compatible: + enum: + - qcom,q6asm + then: + properties: + dais: + properties: + compatible: + const: qcom,q6asm-dais additionalProperties: false @@ -125,6 +195,30 @@ required: - compatible - qcom,domain +allOf: + - if: + properties: + compatible: + enum: + - qcom,gpr + then: + properties: + power-domains: false + + - if: + required: + - qcom,glink-channels + then: + properties: + qcom,smd-channels: false + + - if: + required: + - qcom,smd-channels + then: + properties: + qcom,glink-channels: false + additionalProperties: false examples: diff --git a/dts/Bindings/soc/qcom/qcom,smd.yaml b/dts/Bindings/soc/qcom/qcom,smd.yaml index 9b3efe97f4..063e595c12 100644 --- a/dts/Bindings/soc/qcom/qcom,smd.yaml +++ b/dts/Bindings/soc/qcom/qcom,smd.yaml @@ -20,39 +20,14 @@ properties: const: qcom,smd patternProperties: - "^.*-edge|rpm$": + "^smd-edge|rpm$": $ref: /schemas/remoteproc/qcom,smd-edge.yaml# + unevaluatedProperties: false description: Each subnode of the SMD node represents a remote subsystem or a remote processor of some sort - or in SMD language an "edge". The name of the edges are not important. - properties: - rpm-requests: - type: object - description: - In turn, subnodes of the "edges" represent devices tied to SMD - channels on that "edge". The names of the devices are not - important. The properties of these nodes are defined by the - individual bindings for the SMD devices. - - properties: - qcom,smd-channels: - $ref: /schemas/types.yaml#/definitions/string-array - minItems: 1 - maxItems: 32 - description: - A list of channels tied to this device, used for matching the - device to channels. - - required: - - compatible - - qcom,smd-channels - - additionalProperties: true - - unevaluatedProperties: false - required: - compatible diff --git a/dts/Bindings/soc/qcom/qcom-stats.yaml b/dts/Bindings/soc/qcom/qcom-stats.yaml index 473adca4e9..48eda4d0d3 100644 --- a/dts/Bindings/soc/qcom/qcom-stats.yaml +++ b/dts/Bindings/soc/qcom/qcom-stats.yaml @@ -20,6 +20,7 @@ properties: compatible: enum: - qcom,rpmh-stats + - qcom,sdm845-rpmh-stats - qcom,rpm-stats # For older RPM firmware versions with fixed offset for the sleep stats - qcom,apq8084-rpm-stats diff --git a/dts/Bindings/soc/renesas/renesas,rzg2l-sysc.yaml b/dts/Bindings/soc/renesas/renesas,rzg2l-sysc.yaml index ce2875c893..398663d21a 100644 --- a/dts/Bindings/soc/renesas/renesas,rzg2l-sysc.yaml +++ b/dts/Bindings/soc/renesas/renesas,rzg2l-sysc.yaml @@ -20,7 +20,7 @@ description: properties: compatible: enum: - - renesas,r9a07g043-sysc # RZ/G2UL + - renesas,r9a07g043-sysc # RZ/G2UL and RZ/Five - renesas,r9a07g044-sysc # RZ/G2{L,LC} - renesas,r9a07g054-sysc # RZ/V2L @@ -44,8 +44,6 @@ properties: required: - compatible - reg - - interrupts - - interrupt-names additionalProperties: false diff --git a/dts/Bindings/soc/rockchip/grf.yaml b/dts/Bindings/soc/rockchip/grf.yaml index 75a2b8bb25..2ed8cca79b 100644 --- a/dts/Bindings/soc/rockchip/grf.yaml +++ b/dts/Bindings/soc/rockchip/grf.yaml @@ -16,9 +16,12 @@ properties: - enum: - rockchip,rk3288-sgrf - rockchip,rk3566-pipe-grf + - rockchip,rk3568-pcie3-phy-grf - rockchip,rk3568-pipe-grf - rockchip,rk3568-pipe-phy-grf - rockchip,rk3568-usb2phy-grf + - rockchip,rk3588-pcie3-phy-grf + - rockchip,rk3588-pcie3-pipe-grf - rockchip,rv1108-usbgrf - const: syscon - items: @@ -28,6 +31,7 @@ properties: - rockchip,px30-usb2phy-grf - rockchip,rk3036-grf - rockchip,rk3066-grf + - rockchip,rk3128-grf - rockchip,rk3188-grf - rockchip,rk3228-grf - rockchip,rk3288-grf @@ -45,6 +49,8 @@ properties: - rockchip,rk3568-pmugrf - rockchip,rv1108-grf - rockchip,rv1108-pmugrf + - rockchip,rv1126-grf + - rockchip,rv1126-pmugrf - const: syscon - const: simple-mfd @@ -178,6 +184,7 @@ allOf: contains: enum: - rockchip,px30-usb2phy-grf + - rockchip,rk3128-grf - rockchip,rk3228-grf - rockchip,rk3308-usb2phy-grf - rockchip,rk3328-usb2phy-grf diff --git a/dts/Bindings/sound/adi,max98396.yaml b/dts/Bindings/sound/adi,max98396.yaml index 8d2ef991db..fd5aa61b46 100644 --- a/dts/Bindings/sound/adi,max98396.yaml +++ b/dts/Bindings/sound/adi,max98396.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/adi,max98396.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Analog Devices MAX98396 Speaker Amplifier Device Tree Bindings +title: Analog Devices MAX98396 Speaker Amplifier maintainers: - Ryan Lee <ryans.lee@analog.com> @@ -78,6 +78,40 @@ properties: interleaved on a single output channel. type: boolean + adi,dmon-stuck-enable: + description: + Enables the "data monitor stuck" feature. Once the data monitor is + enabled, it actively monitors the selected input data (from DIN) to the + speaker amplifier. Once a data error is detected, the data monitor + automatically places the device into software shutdown. + type: boolean + + adi,dmon-stuck-threshold-bits: + description: + Sets the threshold for the "data monitor stuck" feature, in bits. + enum: [9, 11, 13, 15] + default: 15 + + adi,dmon-magnitude-enable: + description: + Enables the "data monitor magnitude" feature. Once the data monitor is + enabled, it actively monitors the selected input data (from DIN) to the + speaker amplifier. Once a data error is detected, the data monitor + automatically places the device into software shutdown. + type: boolean + + adi,dmon-magnitude-threshold-bits: + description: + Sets the threshold for the "data monitor magnitude" feature, in bits. + enum: [2, 3, 4, 5] + default: 5 + + adi,dmon-duration-ms: + description: + Sets the duration for the "data monitor" feature, in milliseconds. + enum: [64, 256, 1024, 4096] + default: 64 + reset-gpios: maxItems: 1 diff --git a/dts/Bindings/sound/ak4375.yaml b/dts/Bindings/sound/ak4375.yaml index f1d5074a02..5f0fc584bb 100644 --- a/dts/Bindings/sound/ak4375.yaml +++ b/dts/Bindings/sound/ak4375.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/ak4375.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: AK4375 DAC and headphones amplifier Device Tree Bindings +title: AK4375 DAC and headphones amplifier maintainers: - Vincent Knecht <vincent.knecht@mailoo.org> diff --git a/dts/Bindings/sound/ak4613.yaml b/dts/Bindings/sound/ak4613.yaml index ef4055ef0c..aa8a258a9f 100644 --- a/dts/Bindings/sound/ak4613.yaml +++ b/dts/Bindings/sound/ak4613.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/ak4613.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: AK4613 I2C transmitter Device Tree Bindings +title: AK4613 I2C transmitter maintainers: - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> diff --git a/dts/Bindings/sound/ak4642.yaml b/dts/Bindings/sound/ak4642.yaml index 1e2caa2979..48a5b2c393 100644 --- a/dts/Bindings/sound/ak4642.yaml +++ b/dts/Bindings/sound/ak4642.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/ak4642.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: AK4642 I2C transmitter Device Tree Bindings +title: AK4642 I2C transmitter maintainers: - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> diff --git a/dts/Bindings/sound/allwinner,sun4i-a10-codec.yaml b/dts/Bindings/sound/allwinner,sun4i-a10-codec.yaml index 559aff13ae..292fcb6439 100644 --- a/dts/Bindings/sound/allwinner,sun4i-a10-codec.yaml +++ b/dts/Bindings/sound/allwinner,sun4i-a10-codec.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/allwinner,sun4i-a10-codec.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Codec Device Tree Bindings +title: Allwinner A10 Codec maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/sound/allwinner,sun4i-a10-i2s.yaml b/dts/Bindings/sound/allwinner,sun4i-a10-i2s.yaml index 34f6ee9de3..dd30881ad2 100644 --- a/dts/Bindings/sound/allwinner,sun4i-a10-i2s.yaml +++ b/dts/Bindings/sound/allwinner,sun4i-a10-i2s.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/allwinner,sun4i-a10-i2s.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 I2S Controller Device Tree Bindings +title: Allwinner A10 I2S Controller maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/sound/allwinner,sun4i-a10-spdif.yaml b/dts/Bindings/sound/allwinner,sun4i-a10-spdif.yaml index 444a432912..68c84e29ce 100644 --- a/dts/Bindings/sound/allwinner,sun4i-a10-spdif.yaml +++ b/dts/Bindings/sound/allwinner,sun4i-a10-spdif.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/allwinner,sun4i-a10-spdif.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 S/PDIF Controller Device Tree Bindings +title: Allwinner A10 S/PDIF Controller maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/sound/allwinner,sun50i-a64-codec-analog.yaml b/dts/Bindings/sound/allwinner,sun50i-a64-codec-analog.yaml index 66859eb8f7..5800de63fc 100644 --- a/dts/Bindings/sound/allwinner,sun50i-a64-codec-analog.yaml +++ b/dts/Bindings/sound/allwinner,sun50i-a64-codec-analog.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/allwinner,sun50i-a64-codec-analog.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A64 Analog Codec Device Tree Bindings +title: Allwinner A64 Analog Codec maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/sound/allwinner,sun50i-h6-dmic.yaml b/dts/Bindings/sound/allwinner,sun50i-h6-dmic.yaml new file mode 100644 index 0000000000..2f12cabe4c --- /dev/null +++ b/dts/Bindings/sound/allwinner,sun50i-h6-dmic.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/allwinner,sun50i-h6-dmic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner H6 DMIC + +maintainers: + - Ban Tao <fengzheng923@gmail.com> + +properties: + compatible: + const: allwinner,sun50i-h6-dmic + + "#sound-dai-cells": + const: 0 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Bus Clock + - description: Module Clock + + clock-names: + items: + - const: bus + - const: mod + + dmas: + items: + - description: RX DMA Channel + + dma-names: + items: + - const: rx + + resets: + maxItems: 1 + +required: + - "#sound-dai-cells" + - compatible + - reg + - interrupts + - clocks + - clock-names + - dmas + - dma-names + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + #include <dt-bindings/clock/sun50i-h6-ccu.h> + #include <dt-bindings/reset/sun50i-h6-ccu.h> + + dmic: dmic@5095000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun50i-h6-dmic"; + reg = <0x05095000 0x400>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_DMIC>, <&ccu CLK_DMIC>; + clock-names = "bus", "mod"; + dmas = <&dma 7>; + dma-names = "rx"; + resets = <&ccu RST_BUS_DMIC>; + }; + +... diff --git a/dts/Bindings/sound/allwinner,sun8i-a23-codec-analog.yaml b/dts/Bindings/sound/allwinner,sun8i-a23-codec-analog.yaml index 26eca21e1f..1c21a1b390 100644 --- a/dts/Bindings/sound/allwinner,sun8i-a23-codec-analog.yaml +++ b/dts/Bindings/sound/allwinner,sun8i-a23-codec-analog.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/allwinner,sun8i-a23-codec-analog.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A23 Analog Codec Device Tree Bindings +title: Allwinner A23 Analog Codec maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/sound/allwinner,sun8i-a33-codec.yaml b/dts/Bindings/sound/allwinner,sun8i-a33-codec.yaml index 19f111f402..4eb11a8e62 100644 --- a/dts/Bindings/sound/allwinner,sun8i-a33-codec.yaml +++ b/dts/Bindings/sound/allwinner,sun8i-a33-codec.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/allwinner,sun8i-a33-codec.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A33 Codec Device Tree Bindings +title: Allwinner A33 Codec maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/sound/amlogic,gx-sound-card.yaml b/dts/Bindings/sound/amlogic,gx-sound-card.yaml index b4b35edcb4..5b8d59245f 100644 --- a/dts/Bindings/sound/amlogic,gx-sound-card.yaml +++ b/dts/Bindings/sound/amlogic,gx-sound-card.yaml @@ -40,6 +40,7 @@ properties: patternProperties: "^dai-link-[0-9]+$": type: object + additionalProperties: false description: |- dai-link child nodes: Container for dai-link level properties and the CODEC sub-nodes. @@ -63,6 +64,7 @@ patternProperties: patternProperties: "^codec-[0-9]+$": type: object + additionalProperties: false description: |- Codecs: dai-link representing backend links should have at least one subnode. diff --git a/dts/Bindings/sound/apple,mca.yaml b/dts/Bindings/sound/apple,mca.yaml new file mode 100644 index 0000000000..d5dc92b5b6 --- /dev/null +++ b/dts/Bindings/sound/apple,mca.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/apple,mca.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple MCA I2S transceiver + +description: | + MCA is an I2S transceiver peripheral found on M1 and other Apple chips. It is + composed of a number of identical clusters which can operate independently + or in an interlinked fashion. Up to 6 clusters have been seen on an MCA. + +maintainers: + - Martin Povišer <povik+lin@cutebit.org> + +properties: + compatible: + items: + - enum: + - apple,t6000-mca + - apple,t8103-mca + - const: apple,mca + + reg: + items: + - description: Register region of the MCA clusters proper + - description: Register region of the DMA glue and its FIFOs + + interrupts: + minItems: 4 + maxItems: 6 + description: + One interrupt per each cluster + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + dmas: + minItems: 16 + maxItems: 24 + description: + DMA channels corresponding to the SERDES units in the peripheral. They are + listed in groups of four per cluster, and within the group they are given + as associated to the TXA, RXA, TXB, RXB units. + + dma-names: + minItems: 16 + items: + - const: tx0a + - const: rx0a + - const: tx0b + - const: rx0b + - const: tx1a + - const: rx1a + - const: tx1b + - const: rx1b + - const: tx2a + - const: rx2a + - const: tx2b + - const: rx2b + - const: tx3a + - const: rx3a + - const: tx3b + - const: rx3b + - const: tx4a + - const: rx4a + - const: tx4b + - const: rx4b + - const: tx5a + - const: rx5a + - const: tx5b + - const: rx5b + description: | + Names for the DMA channels: 'tx'/'rx', then cluster number, then 'a'/'b' + based on the associated SERDES unit. + + clocks: + minItems: 4 + maxItems: 6 + description: + Clusters' input reference clock. + + resets: + maxItems: 1 + + power-domains: + minItems: 5 + maxItems: 7 + description: + First a general power domain for register access, then the power + domains of individual clusters for their operation. + + '#sound-dai-cells': + const: 1 + +required: + - compatible + - reg + - dmas + - dma-names + - clocks + - power-domains + - '#sound-dai-cells' + +additionalProperties: false + +examples: + - | + mca: i2s@9b600000 { + compatible = "apple,t6000-mca", "apple,mca"; + reg = <0x9b600000 0x10000>, + <0x9b200000 0x20000>; + + clocks = <&nco 0>, <&nco 1>, <&nco 2>, <&nco 3>; + power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>, + <&ps_mca2>, <&ps_mca3>; + dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>, + <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>, + <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>, + <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>; + dma-names = "tx0a", "rx0a", "tx0b", "rx0b", + "tx1a", "rx1a", "tx1b", "rx1b", + "tx2a", "rx2a", "tx2b", "rx2b", + "tx3a", "rx3a", "tx3b", "rx3b"; + + #sound-dai-cells = <1>; + }; diff --git a/dts/Bindings/sound/audio-graph-card.yaml b/dts/Bindings/sound/audio-graph-card.yaml index 109e55f9e5..274092ef36 100644 --- a/dts/Bindings/sound/audio-graph-card.yaml +++ b/dts/Bindings/sound/audio-graph-card.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/audio-graph-card.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Audio Graph Card Device Tree Bindings +title: Audio Graph Card maintainers: - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> diff --git a/dts/Bindings/sound/audio-graph-card2.yaml b/dts/Bindings/sound/audio-graph-card2.yaml index 7416067c94..3de7b36829 100644 --- a/dts/Bindings/sound/audio-graph-card2.yaml +++ b/dts/Bindings/sound/audio-graph-card2.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/audio-graph-card2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Audio Graph Card2 Device Tree Bindings +title: Audio Graph Card2 maintainers: - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> diff --git a/dts/Bindings/sound/audio-graph-port.yaml b/dts/Bindings/sound/audio-graph-port.yaml index 5c368674d1..64654ceef2 100644 --- a/dts/Bindings/sound/audio-graph-port.yaml +++ b/dts/Bindings/sound/audio-graph-port.yaml @@ -19,14 +19,17 @@ properties: description: "device name prefix" $ref: /schemas/types.yaml#/definitions/string convert-rate: - description: CPU to Codec rate convert. - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: "/schemas/sound/dai-params.yaml#/$defs/dai-sample-rate" convert-channels: - description: CPU to Codec rate channels. - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: "/schemas/sound/dai-params.yaml#/$defs/dai-channels" + convert-sample-format: + $ref: "/schemas/sound/dai-params.yaml#/$defs/dai-sample-format" + patternProperties: "^endpoint(@[0-9a-f]+)?": $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false + properties: mclk-fs: description: | @@ -65,12 +68,18 @@ patternProperties: - msb - lsb convert-rate: - description: CPU to Codec rate convert. - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: "/schemas/sound/dai-params.yaml#/$defs/dai-sample-rate" convert-channels: - description: CPU to Codec rate channels. - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: "/schemas/sound/dai-params.yaml#/$defs/dai-channels" + convert-sample-format: + $ref: "/schemas/sound/dai-params.yaml#/$defs/dai-sample-format" + dai-tdm-slot-num: + description: Number of slots in use. + $ref: /schemas/types.yaml#/definitions/uint32 + dai-tdm-slot-width: + description: Width in bits for each slot. + $ref: /schemas/types.yaml#/definitions/uint32 dai-tdm-slot-width-map: description: Mapping of sample widths to slot widths. For hardware that cannot support a fixed slot width or a slot width always diff --git a/dts/Bindings/sound/audio-graph.yaml b/dts/Bindings/sound/audio-graph.yaml index 4b46794e51..d59baedee1 100644 --- a/dts/Bindings/sound/audio-graph.yaml +++ b/dts/Bindings/sound/audio-graph.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/audio-graph.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Audio Graph Device Tree Bindings +title: Audio Graph maintainers: - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> @@ -27,11 +27,12 @@ properties: description: User specified audio sound widgets. $ref: /schemas/types.yaml#/definitions/non-unique-string-array convert-rate: - description: CPU to Codec rate convert. - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: "/schemas/sound/dai-params.yaml#/$defs/dai-sample-rate" convert-channels: - description: CPU to Codec rate channels. - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: "/schemas/sound/dai-params.yaml#/$defs/dai-channels" + convert-sample-format: + $ref: "/schemas/sound/dai-params.yaml#/$defs/dai-sample-format" + pa-gpios: maxItems: 1 hp-det-gpio: diff --git a/dts/Bindings/sound/cirrus,cs42l42.yaml b/dts/Bindings/sound/cirrus,cs42l42.yaml index 31800f70e9..7356084a2c 100644 --- a/dts/Bindings/sound/cirrus,cs42l42.yaml +++ b/dts/Bindings/sound/cirrus,cs42l42.yaml @@ -19,6 +19,7 @@ properties: compatible: enum: - cirrus,cs42l42 + - cirrus,cs42l83 reg: description: diff --git a/dts/Bindings/sound/dai-params.yaml b/dts/Bindings/sound/dai-params.yaml new file mode 100644 index 0000000000..f5fb71f9b6 --- /dev/null +++ b/dts/Bindings/sound/dai-params.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/dai-params.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Digital Audio Interface (DAI) Stream Parameters + +maintainers: + - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + +select: false + +$defs: + + dai-channels: + description: Number of audio channels used by DAI + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 32 + + dai-sample-format: + description: Audio sample format used by DAI + $ref: /schemas/types.yaml#/definitions/string + enum: + - s8 + - s16_le + - s24_le + - s24_3le + - s32_le + + dai-sample-rate: + description: Audio sample rate used by DAI + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 8000 + maximum: 192000 + +properties: {} + +additionalProperties: true diff --git a/dts/Bindings/sound/everest,es8326.yaml b/dts/Bindings/sound/everest,es8326.yaml new file mode 100755 index 0000000000..07781408e7 --- /dev/null +++ b/dts/Bindings/sound/everest,es8326.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/everest,es8326.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Everest ES8326 audio CODEC + +maintainers: + - David Yang <yangxiaohua@everest-semi.com> + +properties: + compatible: + const: everest,es8326 + + reg: + maxItems: 1 + + clocks: + items: + - description: clock for master clock (MCLK) + + clock-names: + items: + - const: mclk + + "#sound-dai-cells": + const: 0 + + everest,jack-pol: + $ref: /schemas/types.yaml#/definitions/uint8 + description: | + just the value of reg 57. Bit(3) decides whether the jack polarity is inverted. + Bit(2) decides whether the button on the headset is inverted. + Bit(1)/(0) decides the mic properity to be OMTP/CTIA or auto. + minimum: 0x00 + maximum: 0x0f + default: 0x0f + + everest,mic1-src: + $ref: /schemas/types.yaml#/definitions/uint8 + description: + the value of reg 2A when headset plugged. + minimum: 0x00 + maximum: 0x77 + default: 0x22 + + everest,mic2-src: + $ref: /schemas/types.yaml#/definitions/uint8 + description: + the value of reg 2A when headset unplugged. + minimum: 0x00 + maximum: 0x77 + default: 0x44 + + everest,jack-detect-inverted: + $ref: /schemas/types.yaml#/definitions/flag + description: + Defined to invert the jack detection. + + everest,interrupt-src: + $ref: /schemas/types.yaml#/definitions/uint8 + description: | + value of reg 0x58, Defines the interrupt source. + Bit(2) 1 means button press triggers irq, 0 means not. + Bit(3) 1 means PIN9 is the irq source for jack detection. When set to 0, + bias change on PIN9 do not triggers irq. + Bit(4) 1 means PIN27 is the irq source for jack detection. + Bit(5) 1 means PIN9 is the irq source after MIC detect. + Bit(6) 1 means PIN27 is the irq source after MIC detect. + minimum: 0 + maximum: 0x3c + default: 0x08 + + everest,interrupt-clk: + $ref: /schemas/types.yaml#/definitions/uint8 + description: | + value of reg 0x59, Defines the interrupt output behavior. + Bit(0-3) 0 means irq pulse equals 512*internal clock + 1 means irq pulse equals 1024*internal clock + 2 means ... + 7 means irq pulse equals 65536*internal clock + 8 means irq mutes PA + 9 means irq mutes PA and DAC output + Bit(4) 1 means we invert the interrupt output. + Bit(6) 1 means the chip do not detect jack type after button released. + 0 means the chip detect jack type again after button released. + minimum: 0 + maximum: 0x7f + default: 0x45 + +required: + - compatible + - reg + - "#sound-dai-cells" + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + es8326: codec@19 { + compatible = "everest,es8326"; + reg = <0x19>; + clocks = <&clks 10>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + everest,mic1-src = [22]; + everest,mic2-src = [44]; + everest,jack-pol = [0e]; + everest,interrupt-src = [08]; + everest,interrupt-clk = [45]; + }; + }; diff --git a/dts/Bindings/sound/fsl,sai.yaml b/dts/Bindings/sound/fsl,sai.yaml new file mode 100644 index 0000000000..70c4111d59 --- /dev/null +++ b/dts/Bindings/sound/fsl,sai.yaml @@ -0,0 +1,216 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/fsl,sai.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Synchronous Audio Interface (SAI). + +maintainers: + - Shengjiu Wang <shengjiu.wang@nxp.com> + +description: | + The SAI is based on I2S module that used communicating with audio codecs, + which provides a synchronous audio interface that supports fullduplex + serial interfaces with frame synchronization such as I2S, AC97, TDM, and + codec/DSP interfaces. + +properties: + compatible: + oneOf: + - enum: + - fsl,vf610-sai + - fsl,imx6sx-sai + - fsl,imx6ul-sai + - fsl,imx7ulp-sai + - fsl,imx8mq-sai + - fsl,imx8qm-sai + - fsl,imx8ulp-sai + - items: + - enum: + - fsl,imx8mm-sai + - fsl,imx8mn-sai + - fsl,imx8mp-sai + - const: fsl,imx8mq-sai + + reg: + maxItems: 1 + + interrupts: + items: + - description: receive and transmit interrupt + + dmas: + maxItems: 2 + + dma-names: + maxItems: 2 + + clocks: + items: + - description: The ipg clock for register access + - description: master clock source 0 (obsoleted) + - description: master clock source 1 + - description: master clock source 2 + - description: master clock source 3 + - description: PLL clock source for 8kHz series + - description: PLL clock source for 11kHz series + minItems: 4 + + clock-names: + oneOf: + - items: + - const: bus + - const: mclk0 + - const: mclk1 + - const: mclk2 + - const: mclk3 + - const: pll8k + - const: pll11k + minItems: 4 + - items: + - const: bus + - const: mclk1 + - const: mclk2 + - const: mclk3 + - const: pll8k + - const: pll11k + minItems: 4 + + lsb-first: + description: | + Configures whether the LSB or the MSB is transmitted + first for the fifo data. If this property is absent, + the MSB is transmitted first as default, or the LSB + is transmitted first. + type: boolean + + big-endian: + description: | + required if all the SAI registers are big-endian rather than little-endian. + type: boolean + + fsl,sai-synchronous-rx: + description: | + SAI will work in the synchronous mode (sync Tx with Rx) which means + both the transmitter and the receiver will send and receive data by + following receiver's bit clocks and frame sync clocks. + type: boolean + + fsl,sai-asynchronous: + description: | + SAI will work in the asynchronous mode, which means both transmitter + and receiver will send and receive data by following their own bit clocks + and frame sync clocks separately. + If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the + default synchronous mode (sync Rx with Tx) will be used, which means both + transmitter and receiver will send and receive data by following clocks + of transmitter. + type: boolean + + fsl,dataline: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: | + Configure the dataline. It has 3 value for each configuration + maxItems: 16 + items: + items: + - description: format Default(0), I2S(1) or PDM(2) + enum: [0, 1, 2] + - description: dataline mask for 'rx' + - description: dataline mask for 'tx' + + fsl,sai-mclk-direction-output: + description: SAI will output the SAI MCLK clock. + type: boolean + + fsl,shared-interrupt: + description: Interrupt is shared with other modules. + type: boolean + + "#sound-dai-cells": + const: 0 + description: optional, some dts node didn't add it. + +allOf: + - if: + properties: + compatible: + contains: + const: fsl,vf610-sai + then: + properties: + dmas: + items: + - description: DMA controller phandle and request line for TX + - description: DMA controller phandle and request line for RX + dma-names: + items: + - const: tx + - const: rx + else: + properties: + dmas: + items: + - description: DMA controller phandle and request line for RX + - description: DMA controller phandle and request line for TX + dma-names: + items: + - const: rx + - const: tx + - if: + required: + - fsl,sai-asynchronous + then: + properties: + fsl,sai-synchronous-rx: false + +required: + - compatible + - reg + - interrupts + - dmas + - dma-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/vf610-clock.h> + sai2: sai@40031000 { + compatible = "fsl,vf610-sai"; + reg = <0x40031000 0x1000>; + interrupts = <86 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2_1>; + clocks = <&clks VF610_CLK_PLATFORM_BUS>, + <&clks VF610_CLK_SAI2>, + <&clks 0>, <&clks 0>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "tx", "rx"; + dmas = <&edma0 0 21>, + <&edma0 0 20>; + big-endian; + lsb-first; + }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/imx8mm-clock.h> + sai1: sai@30010000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30010000 0x10000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_SAI1_IPG>, + <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI1_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; + dma-names = "rx", "tx"; + fsl,dataline = <1 0xff 0xff 2 0xff 0x11>; + #sound-dai-cells = <0>; + }; diff --git a/dts/Bindings/sound/fsl-sai.txt b/dts/Bindings/sound/fsl-sai.txt deleted file mode 100644 index fbdefc3fad..0000000000 --- a/dts/Bindings/sound/fsl-sai.txt +++ /dev/null @@ -1,95 +0,0 @@ -Freescale Synchronous Audio Interface (SAI). - -The SAI is based on I2S module that used communicating with audio codecs, -which provides a synchronous audio interface that supports fullduplex -serial interfaces with frame synchronization such as I2S, AC97, TDM, and -codec/DSP interfaces. - -Required properties: - - - compatible : Compatible list, contains "fsl,vf610-sai", - "fsl,imx6sx-sai", "fsl,imx6ul-sai", - "fsl,imx7ulp-sai", "fsl,imx8mq-sai", - "fsl,imx8qm-sai", "fsl,imx8mm-sai", - "fsl,imx8mn-sai", "fsl,imx8mp-sai", or - "fsl,imx8ulp-sai". - - - reg : Offset and length of the register set for the device. - - - clocks : Must contain an entry for each entry in clock-names. - - - clock-names : Must include the "bus" for register access and - "mclk1", "mclk2", "mclk3" for bit clock and frame - clock providing. - "pll8k", "pll11k" are optional, they are the clock - source for root clock, one is for 8kHz series rates - another one is for 11kHz series rates. - - dmas : Generic dma devicetree binding as described in - Documentation/devicetree/bindings/dma/dma.txt. - - - dma-names : Two dmas have to be defined, "tx" and "rx". - - - pinctrl-names : Must contain a "default" entry. - - - pinctrl-NNN : One property must exist for each entry in - pinctrl-names. See ../pinctrl/pinctrl-bindings.txt - for details of the property values. - - - lsb-first : Configures whether the LSB or the MSB is transmitted - first for the fifo data. If this property is absent, - the MSB is transmitted first as default, or the LSB - is transmitted first. - - - fsl,sai-synchronous-rx: This is a boolean property. If present, indicating - that SAI will work in the synchronous mode (sync Tx - with Rx) which means both the transmitter and the - receiver will send and receive data by following - receiver's bit clocks and frame sync clocks. - - - fsl,sai-asynchronous: This is a boolean property. If present, indicating - that SAI will work in the asynchronous mode, which - means both transmitter and receiver will send and - receive data by following their own bit clocks and - frame sync clocks separately. - - - fsl,dataline : configure the dataline. it has 3 value for each configuration - first one means the type: I2S(1) or PDM(2) - second one is dataline mask for 'rx' - third one is dataline mask for 'tx'. - for example: fsl,dataline = <1 0xff 0xff 2 0xff 0x11>; - it means I2S type rx mask is 0xff, tx mask is 0xff, PDM type - rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled). - -Optional properties: - - - big-endian : Boolean property, required if all the SAI - registers are big-endian rather than little-endian. - -Optional properties (for mx6ul): - - - fsl,sai-mclk-direction-output: This is a boolean property. If present, - indicates that SAI will output the SAI MCLK clock. - -Note: -- If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the - default synchronous mode (sync Rx with Tx) will be used, which means both - transmitter and receiver will send and receive data by following clocks - of transmitter. -- fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive. - -Example: -sai2: sai@40031000 { - compatible = "fsl,vf610-sai"; - reg = <0x40031000 0x1000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2_1>; - clocks = <&clks VF610_CLK_PLATFORM_BUS>, - <&clks VF610_CLK_SAI2>, - <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>, - <&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>; - big-endian; - lsb-first; -}; diff --git a/dts/Bindings/sound/google,sc7180-trogdor.yaml b/dts/Bindings/sound/google,sc7180-trogdor.yaml index 233caa0ade..67ccddd444 100644 --- a/dts/Bindings/sound/google,sc7180-trogdor.yaml +++ b/dts/Bindings/sound/google,sc7180-trogdor.yaml @@ -61,6 +61,8 @@ patternProperties: cpu: description: Holds subnode which indicates cpu dai. type: object + additionalProperties: false + properties: sound-dai: maxItems: 1 @@ -68,6 +70,8 @@ patternProperties: codec: description: Holds subnode which indicates codec dai. type: object + additionalProperties: false + properties: sound-dai: maxItems: 1 diff --git a/dts/Bindings/sound/imx-audio-card.yaml b/dts/Bindings/sound/imx-audio-card.yaml index bb3a435722..b6f5d48660 100644 --- a/dts/Bindings/sound/imx-audio-card.yaml +++ b/dts/Bindings/sound/imx-audio-card.yaml @@ -58,6 +58,7 @@ patternProperties: cpu: description: Holds subnode which indicates cpu dai. type: object + additionalProperties: false properties: sound-dai: maxItems: 1 @@ -65,6 +66,7 @@ patternProperties: codec: description: Holds subnode which indicates codec dai. type: object + additionalProperties: false properties: sound-dai: minItems: 1 diff --git a/dts/Bindings/sound/intel,keembay-i2s.yaml b/dts/Bindings/sound/intel,keembay-i2s.yaml index 803627e984..b2603f611a 100644 --- a/dts/Bindings/sound/intel,keembay-i2s.yaml +++ b/dts/Bindings/sound/intel,keembay-i2s.yaml @@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/sound/intel,keembay-i2s.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Intel KeemBay I2S Device Tree Bindings +title: Intel KeemBay I2S maintainers: - Sia, Jee Heng <jee.heng.sia@intel.com> diff --git a/dts/Bindings/sound/linux,bt-sco.yaml b/dts/Bindings/sound/linux,bt-sco.yaml index e3a1f485f6..b97e0fcbdb 100644 --- a/dts/Bindings/sound/linux,bt-sco.yaml +++ b/dts/Bindings/sound/linux,bt-sco.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/linux,bt-sco.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Bluetooth SCO Audio Codec Device Tree Bindings +title: Bluetooth SCO Audio Codec maintainers: - Mark Brown <broonie@kernel.org> diff --git a/dts/Bindings/sound/linux,spdif-dit.yaml b/dts/Bindings/sound/linux,spdif-dit.yaml index a4f9257e31..808f6d2736 100644 --- a/dts/Bindings/sound/linux,spdif-dit.yaml +++ b/dts/Bindings/sound/linux,spdif-dit.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/linux,spdif-dit.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Dummy SPDIF Transmitter Device Tree Bindings +title: Dummy SPDIF Transmitter maintainers: - Mark Brown <broonie@kernel.org> diff --git a/dts/Bindings/sound/mchp,spdifrx.yaml b/dts/Bindings/sound/mchp,spdifrx.yaml index 9703111432..70a47c6823 100644 --- a/dts/Bindings/sound/mchp,spdifrx.yaml +++ b/dts/Bindings/sound/mchp,spdifrx.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/mchp,spdifrx.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Microchip S/PDIF Rx Controller Device Tree Bindings +title: Microchip S/PDIF Rx Controller maintainers: - Codrin Ciubotariu <codrin.ciubotariu@microchip.com> diff --git a/dts/Bindings/sound/mchp,spdiftx.yaml b/dts/Bindings/sound/mchp,spdiftx.yaml index d5c022e495..d218e4ab9a 100644 --- a/dts/Bindings/sound/mchp,spdiftx.yaml +++ b/dts/Bindings/sound/mchp,spdiftx.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/mchp,spdiftx.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Microchip S/PDIF Tx Controller Device Tree Bindings +title: Microchip S/PDIF Tx Controller maintainers: - Codrin Ciubotariu <codrin.ciubotariu@microchip.com> diff --git a/dts/Bindings/sound/mt6359.yaml b/dts/Bindings/sound/mt6359.yaml index a54f466f76..23d411fc42 100644 --- a/dts/Bindings/sound/mt6359.yaml +++ b/dts/Bindings/sound/mt6359.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/mt6359.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT6359 Codec Device Tree Bindings +title: Mediatek MT6359 Codec maintainers: - Eason Yen <eason.yen@mediatek.com> diff --git a/dts/Bindings/sound/mt8186-mt6366-da7219-max98357.yaml b/dts/Bindings/sound/mt8186-mt6366-da7219-max98357.yaml index 513cd28b20..d427f7f623 100644 --- a/dts/Bindings/sound/mt8186-mt6366-da7219-max98357.yaml +++ b/dts/Bindings/sound/mt8186-mt6366-da7219-max98357.yaml @@ -43,6 +43,16 @@ properties: required: - sound-dai + mediatek,adsp: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of MT8186 ADSP platform. + + mediatek,dai-link: + $ref: /schemas/types.yaml#/definitions/string-array + description: + A list of the desired dai-links in the sound card. Each entry is a + name defined in the machine driver. + additionalProperties: false required: diff --git a/dts/Bindings/sound/mt8186-mt6366-rt1019-rt5682s.yaml b/dts/Bindings/sound/mt8186-mt6366-rt1019-rt5682s.yaml index 059a7629b2..4fc5b045d3 100644 --- a/dts/Bindings/sound/mt8186-mt6366-rt1019-rt5682s.yaml +++ b/dts/Bindings/sound/mt8186-mt6366-rt1019-rt5682s.yaml @@ -43,6 +43,16 @@ properties: required: - sound-dai + mediatek,adsp: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of MT8186 ADSP platform. + + mediatek,dai-link: + $ref: /schemas/types.yaml#/definitions/string-array + description: + A list of the desired dai-links in the sound card. Each entry is a + name defined in the machine driver. + additionalProperties: false required: diff --git a/dts/Bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml b/dts/Bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml index 4fa179909c..478be7e3fa 100644 --- a/dts/Bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml +++ b/dts/Bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml @@ -30,6 +30,8 @@ properties: headset-codec: type: object + additionalProperties: false + properties: sound-dai: $ref: /schemas/types.yaml#/definitions/phandle @@ -38,6 +40,8 @@ properties: speaker-codecs: type: object + additionalProperties: false + properties: sound-dai: minItems: 1 diff --git a/dts/Bindings/sound/nau8825.txt b/dts/Bindings/sound/nau8825.txt index 388a7bc60b..cb861aca8d 100644 --- a/dts/Bindings/sound/nau8825.txt +++ b/dts/Bindings/sound/nau8825.txt @@ -71,6 +71,9 @@ Optional properties: - nuvoton,crosstalk-enable: make crosstalk function enable if set. + - nuvoton,adcout-drive-strong: make the drive strength of ADCOUT IO PIN strong if set. + Otherwise, the drive keeps normal strength. + - clocks: list of phandle and clock specifier pairs according to common clock bindings for the clocks described in clock-names - clock-names: should include "mclk" for the MCLK master clock diff --git a/dts/Bindings/sound/nvidia,tegra186-asrc.yaml b/dts/Bindings/sound/nvidia,tegra186-asrc.yaml index 520d0d063d..d82415c212 100644 --- a/dts/Bindings/sound/nvidia,tegra186-asrc.yaml +++ b/dts/Bindings/sound/nvidia,tegra186-asrc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/nvidia,tegra186-asrc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Tegra186 ASRC Device Tree Bindings +title: Tegra186 ASRC description: | Asynchronous Sample Rate Converter (ASRC) converts the sampling frequency diff --git a/dts/Bindings/sound/nvidia,tegra186-dspk.yaml b/dts/Bindings/sound/nvidia,tegra186-dspk.yaml index 73b98b2f35..3d538df878 100644 --- a/dts/Bindings/sound/nvidia,tegra186-dspk.yaml +++ b/dts/Bindings/sound/nvidia,tegra186-dspk.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/nvidia,tegra186-dspk.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Tegra186 DSPK Controller Device Tree Bindings +title: Tegra186 DSPK Controller description: | The Digital Speaker Controller (DSPK) can be viewed as a Pulse diff --git a/dts/Bindings/sound/nvidia,tegra210-admaif.yaml b/dts/Bindings/sound/nvidia,tegra210-admaif.yaml index 372043edd9..15ab40aeab 100644 --- a/dts/Bindings/sound/nvidia,tegra210-admaif.yaml +++ b/dts/Bindings/sound/nvidia,tegra210-admaif.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/nvidia,tegra210-admaif.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Tegra210 ADMAIF Device Tree Bindings +title: Tegra210 ADMAIF description: | ADMAIF is the interface between ADMA and AHUB. Each ADMA channel diff --git a/dts/Bindings/sound/nvidia,tegra210-adx.yaml b/dts/Bindings/sound/nvidia,tegra210-adx.yaml index 8d8dc7fb3f..ea0dc0ece1 100644 --- a/dts/Bindings/sound/nvidia,tegra210-adx.yaml +++ b/dts/Bindings/sound/nvidia,tegra210-adx.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/nvidia,tegra210-adx.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Tegra210 ADX Device Tree Bindings +title: Tegra210 ADX description: | The Audio Demultiplexer (ADX) block takes an input stream with up to diff --git a/dts/Bindings/sound/nvidia,tegra210-ahub.yaml b/dts/Bindings/sound/nvidia,tegra210-ahub.yaml index 47b6e712e4..89f7805de2 100644 --- a/dts/Bindings/sound/nvidia,tegra210-ahub.yaml +++ b/dts/Bindings/sound/nvidia,tegra210-ahub.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Tegra210 AHUB Device Tree Bindings +title: Tegra210 AHUB description: | The Audio Hub (AHUB) comprises a collection of hardware accelerators diff --git a/dts/Bindings/sound/nvidia,tegra210-amx.yaml b/dts/Bindings/sound/nvidia,tegra210-amx.yaml index f9e4fc6e0c..1aff61f072 100644 --- a/dts/Bindings/sound/nvidia,tegra210-amx.yaml +++ b/dts/Bindings/sound/nvidia,tegra210-amx.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/nvidia,tegra210-amx.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Tegra210 AMX Device Tree Bindings +title: Tegra210 AMX description: | The Audio Multiplexer (AMX) block can multiplex up to four input streams diff --git a/dts/Bindings/sound/nvidia,tegra210-dmic.yaml b/dts/Bindings/sound/nvidia,tegra210-dmic.yaml index bcb496d3ac..0f9d2b461e 100644 --- a/dts/Bindings/sound/nvidia,tegra210-dmic.yaml +++ b/dts/Bindings/sound/nvidia,tegra210-dmic.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/nvidia,tegra210-dmic.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Tegra210 DMIC Controller Device Tree Bindings +title: Tegra210 DMIC Controller description: | The Digital MIC (DMIC) Controller is used to interface with Pulse diff --git a/dts/Bindings/sound/nvidia,tegra210-i2s.yaml b/dts/Bindings/sound/nvidia,tegra210-i2s.yaml index 6188f561f8..12cd17eede 100644 --- a/dts/Bindings/sound/nvidia,tegra210-i2s.yaml +++ b/dts/Bindings/sound/nvidia,tegra210-i2s.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/nvidia,tegra210-i2s.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Tegra210 I2S Controller Device Tree Bindings +title: Tegra210 I2S Controller description: | The Inter-IC Sound (I2S) controller implements full-duplex, diff --git a/dts/Bindings/sound/nvidia,tegra210-mixer.yaml b/dts/Bindings/sound/nvidia,tegra210-mixer.yaml index ee1e1d2da7..570b03282a 100644 --- a/dts/Bindings/sound/nvidia,tegra210-mixer.yaml +++ b/dts/Bindings/sound/nvidia,tegra210-mixer.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/nvidia,tegra210-mixer.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Tegra210 Mixer Device Tree Bindings +title: Tegra210 Mixer description: | The Mixer supports mixing of up to ten 7.1 audio input streams and diff --git a/dts/Bindings/sound/nvidia,tegra210-mvc.yaml b/dts/Bindings/sound/nvidia,tegra210-mvc.yaml index c9888c553e..4aecbc847b 100644 --- a/dts/Bindings/sound/nvidia,tegra210-mvc.yaml +++ b/dts/Bindings/sound/nvidia,tegra210-mvc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/nvidia,tegra210-mvc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Tegra210 MVC Device Tree Bindings +title: Tegra210 MVC description: | The Master Volume Control (MVC) provides gain or attenuation to a digital diff --git a/dts/Bindings/sound/nvidia,tegra210-sfc.yaml b/dts/Bindings/sound/nvidia,tegra210-sfc.yaml index 8579306fc5..694f890d63 100644 --- a/dts/Bindings/sound/nvidia,tegra210-sfc.yaml +++ b/dts/Bindings/sound/nvidia,tegra210-sfc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/nvidia,tegra210-sfc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Tegra210 SFC Device Tree Bindings +title: Tegra210 SFC description: | The Sampling Frequency Converter (SFC) converts the sampling frequency diff --git a/dts/Bindings/sound/qcom,lpass-rx-macro.yaml b/dts/Bindings/sound/qcom,lpass-rx-macro.yaml index a6905bcf89..1de11e7f33 100644 --- a/dts/Bindings/sound/qcom,lpass-rx-macro.yaml +++ b/dts/Bindings/sound/qcom,lpass-rx-macro.yaml @@ -14,6 +14,8 @@ properties: enum: - qcom,sc7280-lpass-rx-macro - qcom,sm8250-lpass-rx-macro + - qcom,sm8450-lpass-rx-macro + - qcom,sc8280xp-lpass-rx-macro reg: maxItems: 1 diff --git a/dts/Bindings/sound/qcom,lpass-tx-macro.yaml b/dts/Bindings/sound/qcom,lpass-tx-macro.yaml index 324595a62a..de8297b358 100644 --- a/dts/Bindings/sound/qcom,lpass-tx-macro.yaml +++ b/dts/Bindings/sound/qcom,lpass-tx-macro.yaml @@ -14,6 +14,8 @@ properties: enum: - qcom,sc7280-lpass-tx-macro - qcom,sm8250-lpass-tx-macro + - qcom,sm8450-lpass-tx-macro + - qcom,sc8280xp-lpass-tx-macro reg: maxItems: 1 diff --git a/dts/Bindings/sound/qcom,lpass-va-macro.yaml b/dts/Bindings/sound/qcom,lpass-va-macro.yaml index 7b4cc84eda..9f473c08cb 100644 --- a/dts/Bindings/sound/qcom,lpass-va-macro.yaml +++ b/dts/Bindings/sound/qcom,lpass-va-macro.yaml @@ -14,6 +14,8 @@ properties: enum: - qcom,sc7280-lpass-va-macro - qcom,sm8250-lpass-va-macro + - qcom,sm8450-lpass-va-macro + - qcom,sc8280xp-lpass-va-macro reg: maxItems: 1 diff --git a/dts/Bindings/sound/qcom,lpass-wsa-macro.yaml b/dts/Bindings/sound/qcom,lpass-wsa-macro.yaml index 13cdb8a106..4959ad658e 100644 --- a/dts/Bindings/sound/qcom,lpass-wsa-macro.yaml +++ b/dts/Bindings/sound/qcom,lpass-wsa-macro.yaml @@ -14,6 +14,8 @@ properties: enum: - qcom,sc7280-lpass-wsa-macro - qcom,sm8250-lpass-wsa-macro + - qcom,sm8450-lpass-wsa-macro + - qcom,sc8280xp-lpass-wsa-macro reg: maxItems: 1 diff --git a/dts/Bindings/sound/qcom,q6adm-routing.yaml b/dts/Bindings/sound/qcom,q6adm-routing.yaml new file mode 100644 index 0000000000..d0f7a79e24 --- /dev/null +++ b/dts/Bindings/sound/qcom,q6adm-routing.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,q6adm-routing.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Audio Device Manager (Q6ADM) routing + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: + Qualcomm Audio Device Manager (Q6ADM) routing node represents routing + specific configuration. + +properties: + compatible: + enum: + - qcom,q6adm-routing + + "#sound-dai-cells": + const: 0 + +required: + - compatible + - "#sound-dai-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/soc/qcom,apr.h> + #include <dt-bindings/sound/qcom,q6asm.h> + + apr { + compatible = "qcom,apr-v2"; + qcom,domain = <APR_DOMAIN_ADSP>; + #address-cells = <1>; + #size-cells = <0>; + + service@8 { + compatible = "qcom,q6adm"; + reg = <APR_SVC_ADM>; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + + routing { + compatible = "qcom,q6adm-routing"; + #sound-dai-cells = <0>; + }; + }; + }; diff --git a/dts/Bindings/sound/qcom,q6adm.txt b/dts/Bindings/sound/qcom,q6adm.txt deleted file mode 100644 index 15c353a20d..0000000000 --- a/dts/Bindings/sound/qcom,q6adm.txt +++ /dev/null @@ -1,39 +0,0 @@ -Qualcomm Audio Device Manager (Q6ADM) binding - -Q6ADM is one of the APR audio service on Q6DSP. -Please refer to qcom,apr.txt for details of the coommon apr service bindings -used by the apr service device. - -- but must contain the following property: - -- compatible: - Usage: required - Value type: <stringlist> - Definition: must be "qcom,q6adm-v<MAJOR-NUMBER>.<MINOR-NUMBER>". - Or "qcom,q6adm" where the version number can be queried - from DSP. - example "qcom,q6adm-v2.0" - - -= ADM routing -"routing" subnode of the ADM node represents adm routing specific configuration - -- compatible: - Usage: required - Value type: <stringlist> - Definition: must be "qcom,q6adm-routing". - -- #sound-dai-cells - Usage: required - Value type: <u32> - Definition: Must be 0 - -= EXAMPLE -apr-service@8 { - compatible = "qcom,q6adm"; - reg = <APR_SVC_ADM>; - q6routing: routing { - compatible = "qcom,q6adm-routing"; - #sound-dai-cells = <0>; - }; -}; diff --git a/dts/Bindings/sound/qcom,q6afe.txt b/dts/Bindings/sound/qcom,q6afe.txt deleted file mode 100644 index bc6b5f1fe4..0000000000 --- a/dts/Bindings/sound/qcom,q6afe.txt +++ /dev/null @@ -1,20 +0,0 @@ -Qualcomm Audio Front End (Q6AFE) binding - -AFE is one of the APR audio service on Q6DSP -Please refer to qcom,apr.txt for details of the common apr service bindings -used by all apr services. Must contain the following properties. - -- compatible: - Usage: required - Value type: <stringlist> - Definition: must be "qcom,q6afe-v<MAJOR-NUMBER>.<MINOR-NUMBER>" - Or "qcom,q6afe" where the version number can be queried - from DSP. - example "qcom,q6afe" - -= EXAMPLE - -apr-service@4 { - compatible = "qcom,q6afe"; - reg = <APR_SVC_AFE>; -}; diff --git a/dts/Bindings/sound/qcom,q6apm-dai.yaml b/dts/Bindings/sound/qcom,q6apm-dai.yaml index 5d97278432..24f7bf2bfd 100644 --- a/dts/Bindings/sound/qcom,q6apm-dai.yaml +++ b/dts/Bindings/sound/qcom,q6apm-dai.yaml @@ -16,16 +16,12 @@ properties: compatible: const: qcom,q6apm-dais - reg: - maxItems: 1 - iommus: maxItems: 1 required: - compatible - iommus - - reg additionalProperties: false @@ -37,17 +33,14 @@ examples: #address-cells = <1>; #size-cells = <0>; qcom,domain = <GPR_DOMAIN_ID_ADSP>; - service@1 { - compatible = "qcom,q6apm"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - apm-dai@1 { - compatible = "qcom,q6apm-dais"; - iommus = <&apps_smmu 0x1801 0x0>; + service@1 { + compatible = "qcom,q6apm"; reg = <1>; - }; + + dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1801 0x0>; + }; }; }; diff --git a/dts/Bindings/sound/qcom,q6asm-dais.yaml b/dts/Bindings/sound/qcom,q6asm-dais.yaml new file mode 100644 index 0000000000..8deb8ffb14 --- /dev/null +++ b/dts/Bindings/sound/qcom,q6asm-dais.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,q6asm-dais.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Audio Stream Manager (Q6ASM) + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: + Q6ASM is one of the APR audio services on Q6DSP. Each of its subnodes + represent a dai with board specific configuration. + +properties: + compatible: + enum: + - qcom,q6asm-dais + + iommus: + maxItems: 1 + + "#sound-dai-cells": + const: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^dai@[0-9]+$": + type: object + description: + Q6ASM Digital Audio Interface + + properties: + reg: + maxItems: 1 + + direction: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + description: | + The direction of the dai stream:: + - Q6ASM_DAI_TX_RX (0) for both tx and rx + - Q6ASM_DAI_TX (1) for only tx (Capture/Encode) + - Q6ASM_DAI_RX (2) for only rx (Playback/Decode) + + is-compress-dai: + type: boolean + description: + Compress offload dai. + + dependencies: + is-compress-dai: ["direction"] + + required: + - reg + + additionalProperties: false + +required: + - compatible + - "#sound-dai-cells" + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/soc/qcom,apr.h> + #include <dt-bindings/sound/qcom,q6asm.h> + + apr { + compatible = "qcom,apr-v2"; + qcom,domain = <APR_DOMAIN_ADSP>; + #address-cells = <1>; + #size-cells = <0>; + + service@7 { + compatible = "qcom,q6asm"; + reg = <APR_SVC_ASM>; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + + dais { + compatible = "qcom,q6asm-dais"; + iommus = <&apps_smmu 0x1821 0x0>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + + dai@0 { + reg = <0>; + }; + + dai@1 { + reg = <1>; + }; + + dai@2 { + reg = <2>; + is-compress-dai; + direction = <1>; + }; + }; + }; + }; diff --git a/dts/Bindings/sound/qcom,q6asm.txt b/dts/Bindings/sound/qcom,q6asm.txt deleted file mode 100644 index 0d00751252..0000000000 --- a/dts/Bindings/sound/qcom,q6asm.txt +++ /dev/null @@ -1,70 +0,0 @@ -Qualcomm Audio Stream Manager (Q6ASM) binding - -Q6ASM is one of the APR audio service on Q6DSP. -Please refer to qcom,apr.txt for details of the common apr service bindings -used by the apr service device. - -- but must contain the following property: - -- compatible: - Usage: required - Value type: <stringlist> - Definition: must be "qcom,q6asm-v<MAJOR-NUMBER>.<MINOR-NUMBER>". - Or "qcom,q6asm" where the version number can be queried - from DSP. - example "qcom,q6asm-v2.0" - -= ASM DAIs (Digital Audio Interface) -"dais" subnode of the ASM node represents dai specific configuration - -- compatible: - Usage: required - Value type: <stringlist> - Definition: must be "qcom,q6asm-dais". - -- #sound-dai-cells - Usage: required - Value type: <u32> - Definition: Must be 1 - -== ASM DAI is subnode of "dais" and represent a dai, it includes board specific -configuration of each dai. Must contain the following properties. - -- reg - Usage: required - Value type: <u32> - Definition: Must be dai id - -- direction: - Usage: Required for Compress offload dais - Value type: <u32> - Definition: Specifies the direction of the dai stream - Q6ASM_DAI_TX_RX (0) for both tx and rx - Q6ASM_DAI_TX (1) for only tx (Capture/Encode) - Q6ASM_DAI_RX (2) for only rx (Playback/Decode) - -- is-compress-dai: - Usage: Required for Compress offload dais - Value type: <boolean> - Definition: present for Compress offload dais - - -= EXAMPLE -#include <dt-bindings/sound/qcom,q6asm.h> - -apr-service@7 { - compatible = "qcom,q6asm"; - reg = <APR_SVC_ASM>; - q6asmdai: dais { - compatible = "qcom,q6asm-dais"; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <1>; - - dai@0 { - reg = <0>; - direction = <Q6ASM_DAI_RX>; - is-compress-dai; - }; - }; -}; diff --git a/dts/Bindings/sound/qcom,q6core.txt b/dts/Bindings/sound/qcom,q6core.txt deleted file mode 100644 index 5cd4cc9b1f..0000000000 --- a/dts/Bindings/sound/qcom,q6core.txt +++ /dev/null @@ -1,21 +0,0 @@ -Qualcomm ADSP Core service binding - -Q6CORE is one of the APR audio service on Q6DSP. -Please refer to qcom,apr.txt for details of the common apr service bindings -used by the apr service device. - -- but must contain the following property: - -- compatible: - Usage: required - Value type: <stringlist> - Definition: must be "qcom,q6core-v<MAJOR-NUMBER>.<MINOR-NUMBER>". - Or "qcom,q6core" where the version number can be queried - from DSP. - example "qcom,q6core-v2.0" - -= EXAMPLE -apr-service@3 { - compatible = "qcom,q6core"; - reg = <APR_SVC_ADSP_CORE>; -}; diff --git a/dts/Bindings/sound/qcom,q6dsp-lpass-clocks.yaml b/dts/Bindings/sound/qcom,q6dsp-lpass-clocks.yaml index f83f00737a..fd567d2041 100644 --- a/dts/Bindings/sound/qcom,q6dsp-lpass-clocks.yaml +++ b/dts/Bindings/sound/qcom,q6dsp-lpass-clocks.yaml @@ -18,9 +18,6 @@ properties: - qcom,q6afe-clocks - qcom,q6prm-lpass-clocks - reg: - maxItems: 1 - '#clock-cells': const: 2 description: @@ -32,7 +29,6 @@ properties: required: - compatible - - reg - "#clock-cells" additionalProperties: false @@ -42,19 +38,22 @@ examples: #include <dt-bindings/soc/qcom,apr.h> #include <dt-bindings/sound/qcom,q6afe.h> apr { + compatible = "qcom,apr-v2"; + qcom,domain = <APR_DOMAIN_ADSP>; #address-cells = <1>; #size-cells = <0>; - apr-service@4 { + + service@4 { + compatible = "qcom,q6afe"; reg = <APR_SVC_AFE>; - #address-cells = <1>; - #size-cells = <0>; - clock-controller@2 { - compatible = "qcom,q6afe-clocks"; - reg = <2>; - #clock-cells = <2>; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + + clock-controller { + compatible = "qcom,q6afe-clocks"; + #clock-cells = <2>; }; }; - }; + }; - | #include <dt-bindings/soc/qcom,gpr.h> @@ -63,15 +62,14 @@ examples: qcom,domain = <GPR_DOMAIN_ID_ADSP>; #address-cells = <1>; #size-cells = <0>; + service@2 { reg = <GPR_PRM_MODULE_IID>; compatible = "qcom,q6prm"; - #address-cells = <1>; - #size-cells = <0>; - clock-controller@2 { - compatible = "qcom,q6prm-lpass-clocks"; - reg = <2>; - #clock-cells = <2>; + + clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; }; }; - }; + }; diff --git a/dts/Bindings/sound/qcom,q6dsp-lpass-ports.yaml b/dts/Bindings/sound/qcom,q6dsp-lpass-ports.yaml index dc7fba7b92..e53fc0960a 100644 --- a/dts/Bindings/sound/qcom,q6dsp-lpass-ports.yaml +++ b/dts/Bindings/sound/qcom,q6dsp-lpass-ports.yaml @@ -18,9 +18,6 @@ properties: - qcom,q6afe-dais - qcom,q6apm-lpass-dais - reg: - maxItems: 1 - '#sound-dai-cells': const: 1 @@ -145,7 +142,6 @@ patternProperties: required: - compatible - - reg - "#sound-dai-cells" - "#address-cells" - "#size-cells" @@ -157,26 +153,29 @@ examples: #include <dt-bindings/soc/qcom,apr.h> #include <dt-bindings/sound/qcom,q6afe.h> apr { + compatible = "qcom,apr-v2"; #address-cells = <1>; #size-cells = <0>; - apr-service@4 { + qcom,domain = <APR_DOMAIN_ADSP>; + + service@4 { + compatible = "qcom,q6afe"; reg = <APR_SVC_AFE>; - #address-cells = <1>; - #size-cells = <0>; - q6afedai@1 { - compatible = "qcom,q6afe-dais"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <1>; - - dai@22 { - reg = <QUATERNARY_MI2S_RX>; - qcom,sd-lines = <0 1 2 3>; - }; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + + dais { + compatible = "qcom,q6afe-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + + dai@22 { + reg = <QUATERNARY_MI2S_RX>; + qcom,sd-lines = <0 1 2 3>; + }; }; }; - }; + }; - | #include <dt-bindings/soc/qcom,gpr.h> gpr { @@ -184,22 +183,21 @@ examples: #address-cells = <1>; #size-cells = <0>; qcom,domain = <GPR_DOMAIN_ID_ADSP>; + service@1 { compatible = "qcom,q6apm"; reg = <GPR_APM_MODULE_IID>; - #address-cells = <1>; - #size-cells = <0>; - q6apmdai@1 { - compatible = "qcom,q6apm-lpass-dais"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <1>; - - dai@22 { - reg = <QUATERNARY_MI2S_RX>; - qcom,sd-lines = <0 1 2 3>; - }; + + dais { + compatible = "qcom,q6apm-lpass-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + + dai@22 { + reg = <QUATERNARY_MI2S_RX>; + qcom,sd-lines = <0 1 2 3>; + }; }; }; - }; + }; diff --git a/dts/Bindings/sound/qcom,sm8250.yaml b/dts/Bindings/sound/qcom,sm8250.yaml index e6e27d0978..70080d04dd 100644 --- a/dts/Bindings/sound/qcom,sm8250.yaml +++ b/dts/Bindings/sound/qcom,sm8250.yaml @@ -20,9 +20,11 @@ properties: - qcom,apq8016-sbc-sndcard - qcom,db845c-sndcard - qcom,msm8916-qdsp6-sndcard + - qcom,qrb5165-rb5-sndcard + - qcom,sc8280xp-sndcard - qcom,sdm845-sndcard - qcom,sm8250-sndcard - - qcom,qrb5165-rb5-sndcard + - qcom,sm8450-sndcard audio-routing: $ref: /schemas/types.yaml#/definitions/non-unique-string-array @@ -71,6 +73,8 @@ patternProperties: cpu: description: Holds subnode which indicates cpu dai. type: object + additionalProperties: false + properties: sound-dai: maxItems: 1 @@ -78,6 +82,8 @@ patternProperties: platform: description: Holds subnode which indicates platform dai. type: object + additionalProperties: false + properties: sound-dai: maxItems: 1 @@ -85,6 +91,8 @@ patternProperties: codec: description: Holds subnode which indicates codec dai. type: object + additionalProperties: false + properties: sound-dai: minItems: 1 diff --git a/dts/Bindings/sound/renesas,rsnd.yaml b/dts/Bindings/sound/renesas,rsnd.yaml index e17c0245f7..679a246dd6 100644 --- a/dts/Bindings/sound/renesas,rsnd.yaml +++ b/dts/Bindings/sound/renesas,rsnd.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/renesas,rsnd.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas R-Car Sound Driver Device Tree Bindings +title: Renesas R-Car Sound Driver maintainers: - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> @@ -129,6 +129,8 @@ properties: patternProperties: "^dvc-[0-1]$": type: object + additionalProperties: false + properties: dmas: maxItems: 1 @@ -145,7 +147,7 @@ properties: patternProperties: "^mix-[0-1]$": type: object - # no properties + additionalProperties: false additionalProperties: false rcar_sound,ctu: @@ -154,7 +156,7 @@ properties: patternProperties: "^ctu-[0-7]$": type: object - # no properties + additionalProperties: false additionalProperties: false rcar_sound,src: @@ -163,6 +165,8 @@ properties: patternProperties: "^src-[0-9]$": type: object + additionalProperties: false + properties: interrupts: maxItems: 1 @@ -186,6 +190,8 @@ properties: patternProperties: "^ssiu-[0-9]+$": type: object + additionalProperties: false + properties: dmas: maxItems: 2 @@ -206,6 +212,8 @@ properties: patternProperties: "^ssi-[0-9]$": type: object + additionalProperties: false + properties: interrupts: maxItems: 1 @@ -243,6 +251,8 @@ properties: patternProperties: "^dai([0-9]+)?$": type: object + additionalProperties: false + properties: playback: $ref: /schemas/types.yaml#/definitions/phandle-array diff --git a/dts/Bindings/sound/samsung,aries-wm8994.yaml b/dts/Bindings/sound/samsung,aries-wm8994.yaml index a01c4ad929..447e013f6e 100644 --- a/dts/Bindings/sound/samsung,aries-wm8994.yaml +++ b/dts/Bindings/sound/samsung,aries-wm8994.yaml @@ -23,6 +23,7 @@ properties: cpu: type: object + additionalProperties: false properties: sound-dai: minItems: 2 @@ -34,6 +35,7 @@ properties: - sound-dai codec: + additionalProperties: false type: object properties: sound-dai: diff --git a/dts/Bindings/sound/samsung,midas-audio.yaml b/dts/Bindings/sound/samsung,midas-audio.yaml index ec50bcb4af..31095913e3 100644 --- a/dts/Bindings/sound/samsung,midas-audio.yaml +++ b/dts/Bindings/sound/samsung,midas-audio.yaml @@ -19,6 +19,7 @@ properties: cpu: type: object + additionalProperties: false properties: sound-dai: maxItems: 1 @@ -28,6 +29,7 @@ properties: codec: type: object + additionalProperties: false properties: sound-dai: maxItems: 1 diff --git a/dts/Bindings/sound/samsung,snow.yaml b/dts/Bindings/sound/samsung,snow.yaml index 51a83d3c72..3d49aa4c9b 100644 --- a/dts/Bindings/sound/samsung,snow.yaml +++ b/dts/Bindings/sound/samsung,snow.yaml @@ -19,6 +19,7 @@ properties: codec: type: object + additionalProperties: false properties: sound-dai: description: List of phandles to the CODEC and HDMI IP nodes. @@ -30,6 +31,7 @@ properties: cpu: type: object + additionalProperties: false properties: sound-dai: description: Phandle to the Samsung I2S controller. diff --git a/dts/Bindings/sound/simple-audio-amplifier.yaml b/dts/Bindings/sound/simple-audio-amplifier.yaml index 8327846356..5428ba9e23 100644 --- a/dts/Bindings/sound/simple-audio-amplifier.yaml +++ b/dts/Bindings/sound/simple-audio-amplifier.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/simple-audio-amplifier.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Simple Audio Amplifier Device Tree Bindings +title: Simple Audio Amplifier maintainers: - Jerome Brunet <jbrunet@baylibre.com> diff --git a/dts/Bindings/sound/simple-card.yaml b/dts/Bindings/sound/simple-card.yaml index b261d49b9d..ed19899bc9 100644 --- a/dts/Bindings/sound/simple-card.yaml +++ b/dts/Bindings/sound/simple-card.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/simple-card.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Simple Audio Card Driver Device Tree Bindings +title: Simple Audio Card Driver maintainers: - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> diff --git a/dts/Bindings/sound/sound-dai.yaml b/dts/Bindings/sound/sound-dai.yaml index 61c6f7abc4..ff9036e43c 100644 --- a/dts/Bindings/sound/sound-dai.yaml +++ b/dts/Bindings/sound/sound-dai.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/sound-dai.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Digital Audio Interface consumer Device Tree Bindings +title: Digital Audio Interface consumer maintainers: - Rob Herring <robh@kernel.org> diff --git a/dts/Bindings/sound/st,stm32-sai.yaml b/dts/Bindings/sound/st,stm32-sai.yaml index fe2e15504e..56d206f97a 100644 --- a/dts/Bindings/sound/st,stm32-sai.yaml +++ b/dts/Bindings/sound/st,stm32-sai.yaml @@ -60,6 +60,7 @@ required: patternProperties: "^audio-controller@[0-9a-f]+$": type: object + additionalProperties: false description: Two subnodes corresponding to SAI sub-block instances A et B can be defined. Subnode can be omitted for unsused sub-block. @@ -121,6 +122,10 @@ patternProperties: description: Configure the SAI device as master clock provider. const: 0 + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + required: - compatible - "#sound-dai-cells" diff --git a/dts/Bindings/sound/test-component.yaml b/dts/Bindings/sound/test-component.yaml index 17fdb43172..9c40a2122d 100644 --- a/dts/Bindings/sound/test-component.yaml +++ b/dts/Bindings/sound/test-component.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/test-component.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Test Component Device Tree Bindings +title: Test Component maintainers: - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> diff --git a/dts/Bindings/sound/ti,src4xxx.yaml b/dts/Bindings/sound/ti,src4xxx.yaml new file mode 100644 index 0000000000..9681b72b49 --- /dev/null +++ b/dts/Bindings/sound/ti,src4xxx.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/ti,src4xxx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments SRC4392 Device Tree Bindings + +description: | + The SRC4392 is a digital audio codec that can be connected via + I2C or SPI. Currently, only I2C bus is supported. + +maintainers: + - Matt Flax <flatmax@flatmax.com> + +allOf: + - $ref: name-prefix.yaml# + +properties: + compatible: + const: ti,src4392 + + "#sound-dai-cells": + const: 0 + + reg: + maxItems: 1 + +required: + - "#sound-dai-cells" + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + audio-codec@70 { + #sound-dai-cells = <0>; + compatible = "ti,src4392"; + reg = <0x70>; + }; + }; +... diff --git a/dts/Bindings/sound/ti,ts3a227e.yaml b/dts/Bindings/sound/ti,ts3a227e.yaml new file mode 100644 index 0000000000..7859306580 --- /dev/null +++ b/dts/Bindings/sound/ti,ts3a227e.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/ti,ts3a227e.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments TS3A227E + Autonomous Audio Accessory Detection and Configuration Switch + +maintainers: + - Dylan Reid <dgreid@chromium.org> + +description: | + The TS3A227E detect headsets of 3-ring and 4-ring standards and + switches automatically to route the microphone correctly. It also + handles key press detection in accordance with the Android audio + headset specification v1.0. + +properties: + compatible: + enum: + - ti,ts3a227e + + reg: + const: 0x3b + + interrupts: + maxItems: 1 + + ti,micbias: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Intended MICBIAS voltage (datasheet section 9.6.7). + enum: + - 0 # 2.1 V + - 1 # 2.2 V + - 2 # 2.3 V + - 3 # 2.4 V + - 4 # 2.5 V + - 5 # 2.6 V + - 6 # 2.7 V + - 7 # 2.8 V + default: 1 + + ti,debounce-release-ms: + description: key release debounce time in ms (datasheet section 9.6.7). + enum: + - 0 + - 20 + default: 20 + + ti,debounce-press-ms: + description: key press debounce time in ms (datasheet section 9.6.7). + enum: + - 2 + - 40 + - 80 + - 120 + default: 80 + + ti,debounce-insertion-ms: + description: headset insertion debounce time in ms (datasheet section 9.6.5). + enum: + - 2 + - 30 + - 60 + - 90 + - 120 + - 150 + - 1000 + - 2000 + default: 90 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + codec: audio-controller@3b { + compatible = "ti,ts3a227e"; + reg = <0x3b>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + }; + }; + +... diff --git a/dts/Bindings/sound/ts3a227e.txt b/dts/Bindings/sound/ts3a227e.txt deleted file mode 100644 index 21ab45bc7e..0000000000 --- a/dts/Bindings/sound/ts3a227e.txt +++ /dev/null @@ -1,30 +0,0 @@ -Texas Instruments TS3A227E -Autonomous Audio Accessory Detection and Configuration Switch - -The TS3A227E detect headsets of 3-ring and 4-ring standards and -switches automatically to route the microphone correctly. It also -handles key press detection in accordance with the Android audio -headset specification v1.0. - -Required properties: - - - compatible: Should contain "ti,ts3a227e". - - reg: The i2c address. Should contain <0x3b>. - - interrupts: Interrupt number for /INT pin from the 227e - -Optional properies: - - ti,micbias: Intended MICBIAS voltage (datasheet section 9.6.7). - Select 0/1/2/3/4/5/6/7 to specify MICBIAS voltage - 2.1V/2.2V/2.3V/2.4V/2.5V/2.6V/2.7V/2.8V - Default value is "1" (2.2V). - -Examples: - - i2c { - ts3a227e@3b { - compatible = "ti,ts3a227e"; - reg = <0x3b>; - interrupt-parent = <&gpio>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - }; - }; diff --git a/dts/Bindings/sound/wlf,wm8940.yaml b/dts/Bindings/sound/wlf,wm8940.yaml index 8aadcbeed5..7386abb3a2 100644 --- a/dts/Bindings/sound/wlf,wm8940.yaml +++ b/dts/Bindings/sound/wlf,wm8940.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/wlf,wm8940.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Wolfson WM8940 Codec Device Tree Bindings +title: Wolfson WM8940 Codec maintainers: - patches@opensource.cirrus.com diff --git a/dts/Bindings/sound/wlf,wm8978.yaml b/dts/Bindings/sound/wlf,wm8978.yaml index 96cf9fc9c8..1c8985d4dd 100644 --- a/dts/Bindings/sound/wlf,wm8978.yaml +++ b/dts/Bindings/sound/wlf,wm8978.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/wlf,wm8978.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Wolfson WM8978 Codec Device Tree Bindings +title: Wolfson WM8978 Codec maintainers: - patches@opensource.cirrus.com diff --git a/dts/Bindings/spi/allwinner,sun4i-a10-spi.yaml b/dts/Bindings/spi/allwinner,sun4i-a10-spi.yaml index 8036499112..f1176a28fd 100644 --- a/dts/Bindings/spi/allwinner,sun4i-a10-spi.yaml +++ b/dts/Bindings/spi/allwinner,sun4i-a10-spi.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/spi/allwinner,sun4i-a10-spi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 SPI Controller Device Tree Bindings +title: Allwinner A10 SPI Controller allOf: - $ref: "spi-controller.yaml" diff --git a/dts/Bindings/spi/allwinner,sun6i-a31-spi.yaml b/dts/Bindings/spi/allwinner,sun6i-a31-spi.yaml index ca4c95345a..58b7056f4a 100644 --- a/dts/Bindings/spi/allwinner,sun6i-a31-spi.yaml +++ b/dts/Bindings/spi/allwinner,sun6i-a31-spi.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/spi/allwinner,sun6i-a31-spi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A31 SPI Controller Device Tree Bindings +title: Allwinner A31 SPI Controller allOf: - $ref: "spi-controller.yaml" diff --git a/dts/Bindings/spi/atmel,at91rm9200-spi.yaml b/dts/Bindings/spi/atmel,at91rm9200-spi.yaml index d85d54024b..4dd973e341 100644 --- a/dts/Bindings/spi/atmel,at91rm9200-spi.yaml +++ b/dts/Bindings/spi/atmel,at91rm9200-spi.yaml @@ -34,6 +34,16 @@ properties: clocks: maxItems: 1 + dmas: + items: + - description: TX DMA Channel + - description: RX DMA Channel + + dma-names: + items: + - const: tx + - const: rx + atmel,fifo-size: $ref: /schemas/types.yaml#/definitions/uint32 description: | diff --git a/dts/Bindings/spi/mediatek,spi-mtk-nor.yaml b/dts/Bindings/spi/mediatek,spi-mtk-nor.yaml index 970b111989..a453996c13 100644 --- a/dts/Bindings/spi/mediatek,spi-mtk-nor.yaml +++ b/dts/Bindings/spi/mediatek,spi-mtk-nor.yaml @@ -85,8 +85,9 @@ examples: compatible = "mediatek,mt8173-nor"; reg = <0 0x1100d000 0 0xe0>; interrupts = <1>; - clocks = <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_SEL>; - clock-names = "spi", "sf"; + clocks = <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_SEL>, + <&pericfg CLK_PERI_NFI>; + clock-names = "spi", "sf", "axi"; #address-cells = <1>; #size-cells = <0>; diff --git a/dts/Bindings/spi/microchip,mpfs-spi.yaml b/dts/Bindings/spi/microchip,mpfs-spi.yaml index 7326c0a28d..1051690e37 100644 --- a/dts/Bindings/spi/microchip,mpfs-spi.yaml +++ b/dts/Bindings/spi/microchip,mpfs-spi.yaml @@ -4,7 +4,11 @@ $id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Microchip MPFS {Q,}SPI Controller Device Tree Bindings +title: Microchip FPGA {Q,}SPI Controllers + +description: + SPI and QSPI controllers on Microchip PolarFire SoC and the "soft"/ + fabric IP cores they are based on maintainers: - Conor Dooley <conor.dooley@microchip.com> @@ -14,9 +18,12 @@ allOf: properties: compatible: - enum: - - microchip,mpfs-spi - - microchip,mpfs-qspi + oneOf: + - items: + - const: microchip,mpfs-qspi + - const: microchip,coreqspi-rtl-v2 + - const: microchip,coreqspi-rtl-v2 #FPGA QSPI + - const: microchip,mpfs-spi reg: maxItems: 1 diff --git a/dts/Bindings/spi/mxicy,mx25f0a-spi.yaml b/dts/Bindings/spi/mxicy,mx25f0a-spi.yaml index 9202c44b44..a3aa5e07c0 100644 --- a/dts/Bindings/spi/mxicy,mx25f0a-spi.yaml +++ b/dts/Bindings/spi/mxicy,mx25f0a-spi.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/spi/mxicy,mx25f0a-spi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Macronix SPI controller device tree bindings +title: Macronix SPI controller maintainers: - Miquel Raynal <miquel.raynal@bootlin.com> diff --git a/dts/Bindings/spi/nuvoton,npcm-pspi.txt b/dts/Bindings/spi/nuvoton,npcm-pspi.txt index b98203ca65..a4e72e52af 100644 --- a/dts/Bindings/spi/nuvoton,npcm-pspi.txt +++ b/dts/Bindings/spi/nuvoton,npcm-pspi.txt @@ -3,7 +3,8 @@ Nuvoton NPCM Peripheral Serial Peripheral Interface(PSPI) controller driver Nuvoton NPCM7xx SOC support two PSPI channels. Required properties: - - compatible : "nuvoton,npcm750-pspi" for NPCM7XX BMC + - compatible : "nuvoton,npcm750-pspi" for Poleg NPCM7XX. + "nuvoton,npcm845-pspi" for Arbel NPCM8XX. - #address-cells : should be 1. see spi-bus.txt - #size-cells : should be 0. see spi-bus.txt - specifies physical base address and size of the register. diff --git a/dts/Bindings/spi/nvidia,tegra210-quad-peripheral-props.yaml b/dts/Bindings/spi/nvidia,tegra210-quad-peripheral-props.yaml index 24e0c2181d..2c3cada753 100644 --- a/dts/Bindings/spi/nvidia,tegra210-quad-peripheral-props.yaml +++ b/dts/Bindings/spi/nvidia,tegra210-quad-peripheral-props.yaml @@ -29,5 +29,4 @@ properties: minimum: 0 maximum: 255 -unevaluatedProperties: true - +additionalProperties: true diff --git a/dts/Bindings/spi/ralink,mt7621-spi.yaml b/dts/Bindings/spi/ralink,mt7621-spi.yaml new file mode 100644 index 0000000000..22879f7dcb --- /dev/null +++ b/dts/Bindings/spi/ralink,mt7621-spi.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/ralink,mt7621-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +maintainers: + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +title: Mediatek MT7621/MT7628 SPI controller + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + const: ralink,mt7621-spi + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: spi + + resets: + maxItems: 1 + + reset-names: + const: spi + +required: + - compatible + - reg + - resets + - "#address-cells" + - "#size-cells" + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/mt7621-clk.h> + #include <dt-bindings/reset/mt7621-reset.h> + + spi@b00 { + compatible = "ralink,mt7621-spi"; + reg = <0xb00 0x100>; + clocks = <&sysc MT7621_CLK_SPI>; + clock-names = "spi"; + resets = <&sysc MT7621_RST_SPI>; + reset-names = "spi"; + + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins>; + }; diff --git a/dts/Bindings/spi/renesas,sh-msiof.yaml b/dts/Bindings/spi/renesas,sh-msiof.yaml index 5de710adfa..491a695a2d 100644 --- a/dts/Bindings/spi/renesas,sh-msiof.yaml +++ b/dts/Bindings/spi/renesas,sh-msiof.yaml @@ -47,10 +47,16 @@ properties: - renesas,msiof-r8a77980 # R-Car V3H - renesas,msiof-r8a77990 # R-Car E3 - renesas,msiof-r8a77995 # R-Car D3 - - renesas,msiof-r8a779a0 # R-Car V3U - const: renesas,rcar-gen3-msiof # generic R-Car Gen3 and RZ/G2 # compatible device - items: + - enum: + - renesas,msiof-r8a779a0 # R-Car V3U + - renesas,msiof-r8a779f0 # R-Car S4-8 + - renesas,msiof-r8a779g0 # R-Car V4H + - const: renesas,rcar-gen4-msiof # generic R-Car Gen4 + # compatible device + - items: - const: renesas,sh-msiof # deprecated reg: @@ -69,6 +75,12 @@ properties: clocks: maxItems: 1 + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + num-cs: description: | Total number of chip selects (default is 1). diff --git a/dts/Bindings/spi/snps,dw-apb-ssi.yaml b/dts/Bindings/spi/snps,dw-apb-ssi.yaml index 37c3c27240..d33b72fabc 100644 --- a/dts/Bindings/spi/snps,dw-apb-ssi.yaml +++ b/dts/Bindings/spi/snps,dw-apb-ssi.yaml @@ -104,7 +104,6 @@ properties: const: spi reg-io-width: - $ref: /schemas/types.yaml#/definitions/uint32 description: I/O register width (in bytes) implemented by this device default: 4 enum: [ 2, 4 ] diff --git a/dts/Bindings/spi/spi-cadence.yaml b/dts/Bindings/spi/spi-cadence.yaml index 82d0ca5c00..64bf4e6211 100644 --- a/dts/Bindings/spi/spi-cadence.yaml +++ b/dts/Bindings/spi/spi-cadence.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/spi/spi-cadence.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Cadence SPI controller Device Tree Bindings +title: Cadence SPI controller maintainers: - Michal Simek <michal.simek@xilinx.com> diff --git a/dts/Bindings/spi/spi-controller.yaml b/dts/Bindings/spi/spi-controller.yaml index 655713fba7..01042a7f38 100644 --- a/dts/Bindings/spi/spi-controller.yaml +++ b/dts/Bindings/spi/spi-controller.yaml @@ -96,6 +96,11 @@ patternProperties: $ref: spi-peripheral-props.yaml properties: + spi-3wire: + $ref: /schemas/types.yaml#/definitions/flag + description: + The device requires 3-wire mode. + spi-cpha: $ref: /schemas/types.yaml#/definitions/flag description: diff --git a/dts/Bindings/spi/spi-fsl-lpspi.yaml b/dts/Bindings/spi/spi-fsl-lpspi.yaml index 1d46877fe4..8b44284d30 100644 --- a/dts/Bindings/spi/spi-fsl-lpspi.yaml +++ b/dts/Bindings/spi/spi-fsl-lpspi.yaml @@ -19,7 +19,9 @@ properties: - fsl,imx7ulp-spi - fsl,imx8qxp-spi - items: - - const: fsl,imx8ulp-spi + - enum: + - fsl,imx8ulp-spi + - fsl,imx93-spi - const: fsl,imx7ulp-spi reg: maxItems: 1 @@ -37,6 +39,16 @@ properties: - const: per - const: ipg + dmas: + items: + - description: TX DMA Channel + - description: RX DMA Channel + + dma-names: + items: + - const: tx + - const: rx + fsl,spi-only-use-cs1-sel: description: spi common code does not support use of CS signals discontinuously. diff --git a/dts/Bindings/spi/spi-mt7621.txt b/dts/Bindings/spi/spi-mt7621.txt deleted file mode 100644 index d5baec0fa5..0000000000 --- a/dts/Bindings/spi/spi-mt7621.txt +++ /dev/null @@ -1,26 +0,0 @@ -Binding for MTK SPI controller (MT7621 MIPS) - -Required properties: -- compatible: Should be one of the following: - - "ralink,mt7621-spi": for mt7621/mt7628/mt7688 platforms -- #address-cells: should be 1. -- #size-cells: should be 0. -- reg: Address and length of the register set for the device -- resets: phandle to the reset controller asserting this device in - reset - See ../reset/reset.txt for details. - -Optional properties: -- cs-gpios: see spi-bus.txt. - -Example: - -- SoC Specific Portion: -spi0: spi@b00 { - compatible = "ralink,mt7621-spi"; - reg = <0xb00 0x100>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&rstctrl 18>; - reset-names = "spi"; -}; diff --git a/dts/Bindings/spi/spi-peripheral-props.yaml b/dts/Bindings/spi/spi-peripheral-props.yaml index a4abe15880..dca677f9e1 100644 --- a/dts/Bindings/spi/spi-peripheral-props.yaml +++ b/dts/Bindings/spi/spi-peripheral-props.yaml @@ -29,11 +29,6 @@ properties: description: Chip select used by the device. - spi-3wire: - $ref: /schemas/types.yaml#/definitions/flag - description: - The device requires 3-wire mode. - spi-cs-high: $ref: /schemas/types.yaml#/definitions/flag description: diff --git a/dts/Bindings/spi/spi-rockchip.yaml b/dts/Bindings/spi/spi-rockchip.yaml index 52a78a2e36..66e49947b7 100644 --- a/dts/Bindings/spi/spi-rockchip.yaml +++ b/dts/Bindings/spi/spi-rockchip.yaml @@ -27,6 +27,7 @@ properties: - items: - enum: - rockchip,px30-spi + - rockchip,rk3128-spi - rockchip,rk3188-spi - rockchip,rk3288-spi - rockchip,rk3308-spi @@ -34,6 +35,7 @@ properties: - rockchip,rk3368-spi - rockchip,rk3399-spi - rockchip,rk3568-spi + - rockchip,rk3588-spi - rockchip,rv1126-spi - const: rockchip,rk3066-spi @@ -80,6 +82,9 @@ properties: where the "sleep" configuration may describe the state the pins should be in during system suspend. + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/dts/Bindings/spi/spi-xilinx.yaml b/dts/Bindings/spi/spi-xilinx.yaml index 03e5dca7e9..bbb735603f 100644 --- a/dts/Bindings/spi/spi-xilinx.yaml +++ b/dts/Bindings/spi/spi-xilinx.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/spi/spi-xilinx.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Xilinx SPI controller Device Tree Bindings +title: Xilinx SPI controller maintainers: - Michal Simek <michal.simek@xilinx.com> diff --git a/dts/Bindings/spi/spi-zynqmp-qspi.yaml b/dts/Bindings/spi/spi-zynqmp-qspi.yaml index fafde1c06b..6bf0edc57f 100644 --- a/dts/Bindings/spi/spi-zynqmp-qspi.yaml +++ b/dts/Bindings/spi/spi-zynqmp-qspi.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings +title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller maintainers: - Michal Simek <michal.simek@xilinx.com> diff --git a/dts/Bindings/spmi/mtk,spmi-mtk-pmif.yaml b/dts/Bindings/spmi/mtk,spmi-mtk-pmif.yaml index 2445c5e0b0..abcbbe1372 100644 --- a/dts/Bindings/spmi/mtk,spmi-mtk-pmif.yaml +++ b/dts/Bindings/spmi/mtk,spmi-mtk-pmif.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/spmi/mtk,spmi-mtk-pmif.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek SPMI Controller Device Tree Bindings +title: Mediatek SPMI Controller maintainers: - Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> diff --git a/dts/Bindings/sram/allwinner,sun4i-a10-system-control.yaml b/dts/Bindings/sram/allwinner,sun4i-a10-system-control.yaml index 1c426c211e..98a7dc7f46 100644 --- a/dts/Bindings/sram/allwinner,sun4i-a10-system-control.yaml +++ b/dts/Bindings/sram/allwinner,sun4i-a10-system-control.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 System Control Device Tree Bindings +title: Allwinner A10 System Control maintainers: - Chen-Yu Tsai <wens@csie.org> @@ -24,32 +24,31 @@ properties: compatible: oneOf: - - const: allwinner,sun4i-a10-sram-controller + - enum: + - allwinner,sun4i-a10-sram-controller + - allwinner,sun50i-a64-sram-controller deprecated: true - - const: allwinner,sun4i-a10-system-control - - const: allwinner,sun5i-a13-system-control + - enum: + - allwinner,sun4i-a10-system-control + - allwinner,sun5i-a13-system-control + - allwinner,sun8i-a23-system-control + - allwinner,sun8i-h3-system-control + - allwinner,sun20i-d1-system-control + - allwinner,sun50i-a64-system-control + - allwinner,sun50i-h5-system-control + - allwinner,sun50i-h616-system-control - items: - - const: allwinner,sun7i-a20-system-control + - enum: + - allwinner,suniv-f1c100s-system-control + - allwinner,sun7i-a20-system-control + - allwinner,sun8i-r40-system-control - const: allwinner,sun4i-a10-system-control - - const: allwinner,sun8i-a23-system-control - - const: allwinner,sun8i-h3-system-control - items: - const: allwinner,sun8i-v3s-system-control - const: allwinner,sun8i-h3-system-control - items: - - const: allwinner,sun8i-r40-system-control - - const: allwinner,sun4i-a10-system-control - - const: allwinner,sun50i-a64-sram-controller - deprecated: true - - const: allwinner,sun50i-a64-system-control - - const: allwinner,sun50i-h5-system-control - - items: - const: allwinner,sun50i-h6-system-control - const: allwinner,sun50i-a64-system-control - - items: - - const: allwinner,suniv-f1c100s-system-control - - const: allwinner,sun4i-a10-system-control - - const: allwinner,sun50i-h616-system-control reg: maxItems: 1 @@ -76,43 +75,26 @@ patternProperties: - const: allwinner,sun4i-a10-sram-d - const: allwinner,sun50i-a64-sram-c - items: - - const: allwinner,sun5i-a13-sram-a3-a4 - - const: allwinner,sun4i-a10-sram-a3-a4 - - items: - - const: allwinner,sun7i-a20-sram-a3-a4 + - enum: + - allwinner,sun5i-a13-sram-a3-a4 + - allwinner,sun7i-a20-sram-a3-a4 - const: allwinner,sun4i-a10-sram-a3-a4 - items: - - const: allwinner,sun5i-a13-sram-c1 - - const: allwinner,sun4i-a10-sram-c1 - - items: - - const: allwinner,sun7i-a20-sram-c1 - - const: allwinner,sun4i-a10-sram-c1 - - items: - - const: allwinner,sun8i-a23-sram-c1 - - const: allwinner,sun4i-a10-sram-c1 - - items: - - const: allwinner,sun8i-h3-sram-c1 + - enum: + - allwinner,sun5i-a13-sram-c1 + - allwinner,sun7i-a20-sram-c1 + - allwinner,sun8i-a23-sram-c1 + - allwinner,sun8i-h3-sram-c1 + - allwinner,sun8i-r40-sram-c1 + - allwinner,sun50i-a64-sram-c1 + - allwinner,sun50i-h5-sram-c1 + - allwinner,sun50i-h6-sram-c1 - const: allwinner,sun4i-a10-sram-c1 - items: - - const: allwinner,sun8i-r40-sram-c1 - - const: allwinner,sun4i-a10-sram-c1 - - items: - - const: allwinner,sun50i-a64-sram-c1 - - const: allwinner,sun4i-a10-sram-c1 - - items: - - const: allwinner,sun50i-h5-sram-c1 - - const: allwinner,sun4i-a10-sram-c1 - - items: - - const: allwinner,sun50i-h6-sram-c1 - - const: allwinner,sun4i-a10-sram-c1 - - items: - - const: allwinner,sun5i-a13-sram-d - - const: allwinner,sun4i-a10-sram-d - - items: - - const: allwinner,sun7i-a20-sram-d - - const: allwinner,sun4i-a10-sram-d - - items: - - const: allwinner,suniv-f1c100s-sram-d + - enum: + - allwinner,suniv-f1c100s-sram-d + - allwinner,sun5i-a13-sram-d + - allwinner,sun7i-a20-sram-d - const: allwinner,sun4i-a10-sram-d - items: - const: allwinner,sun50i-h6-sram-c diff --git a/dts/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml b/dts/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml index 6e0b110153..fbd4212285 100644 --- a/dts/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml +++ b/dts/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/thermal/allwinner,sun8i-a83t-ths.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner SUN8I Thermal Controller Device Tree Bindings +title: Allwinner SUN8I Thermal Controller maintainers: - Vasily Khoruzhick <anarsoul@gmail.com> diff --git a/dts/Bindings/timer/allwinner,sun4i-a10-timer.yaml b/dts/Bindings/timer/allwinner,sun4i-a10-timer.yaml index 3711872b6b..b3538fac1a 100644 --- a/dts/Bindings/timer/allwinner,sun4i-a10-timer.yaml +++ b/dts/Bindings/timer/allwinner,sun4i-a10-timer.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/timer/allwinner,sun4i-a10-timer.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Timer Device Tree Bindings +title: Allwinner A10 Timer maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/timer/allwinner,sun5i-a13-hstimer.yaml b/dts/Bindings/timer/allwinner,sun5i-a13-hstimer.yaml index 2ecac754e1..f1853daec2 100644 --- a/dts/Bindings/timer/allwinner,sun5i-a13-hstimer.yaml +++ b/dts/Bindings/timer/allwinner,sun5i-a13-hstimer.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/timer/allwinner,sun5i-a13-hstimer.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A13 High-Speed Timer Device Tree Bindings +title: Allwinner A13 High-Speed Timer maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/timer/arm,arch_timer.yaml b/dts/Bindings/timer/arm,arch_timer.yaml index df8ce87fd5..c5fc3b6c8b 100644 --- a/dts/Bindings/timer/arm,arch_timer.yaml +++ b/dts/Bindings/timer/arm,arch_timer.yaml @@ -22,16 +22,15 @@ properties: compatible: oneOf: - items: - - enum: - - arm,cortex-a15-timer - - enum: - - arm,armv7-timer + - const: arm,cortex-a15-timer + - const: arm,armv7-timer - items: - enum: - arm,armv7-timer - - items: - - enum: - arm,armv8-timer + - items: + - const: arm,armv8-timer + - const: arm,armv7-timer interrupts: minItems: 1 diff --git a/dts/Bindings/timer/arm,arch_timer_mmio.yaml b/dts/Bindings/timer/arm,arch_timer_mmio.yaml index cd2176cad5..f6efa48c42 100644 --- a/dts/Bindings/timer/arm,arch_timer_mmio.yaml +++ b/dts/Bindings/timer/arm,arch_timer_mmio.yaml @@ -62,6 +62,7 @@ properties: patternProperties: '^frame@[0-9a-z]*$': type: object + additionalProperties: false description: A timer node has up to 8 frame sub-nodes, each with the following properties. properties: frame-number: diff --git a/dts/Bindings/timer/ingenic,tcu.yaml b/dts/Bindings/timer/ingenic,tcu.yaml index 0a01e4f5ed..a84fef0fe6 100644 --- a/dts/Bindings/timer/ingenic,tcu.yaml +++ b/dts/Bindings/timer/ingenic,tcu.yaml @@ -114,6 +114,8 @@ patternProperties: "^watchdog@[a-f0-9]+$": type: object $ref: /schemas/watchdog/watchdog.yaml# + unevaluatedProperties: false + properties: compatible: oneOf: @@ -146,6 +148,8 @@ patternProperties: "^pwm@[a-f0-9]+$": type: object $ref: /schemas/pwm/pwm.yaml# + unevaluatedProperties: false + properties: compatible: oneOf: diff --git a/dts/Bindings/timer/mediatek,mtk-timer.txt b/dts/Bindings/timer/mediatek,mtk-timer.txt index f1c848af91..8bbb6e9450 100644 --- a/dts/Bindings/timer/mediatek,mtk-timer.txt +++ b/dts/Bindings/timer/mediatek,mtk-timer.txt @@ -25,6 +25,7 @@ Required properties: For those SoCs that use SYST * "mediatek,mt8183-timer" for MT8183 compatible timers (SYST) * "mediatek,mt8186-timer" for MT8186 compatible timers (SYST) + * "mediatek,mt8188-timer" for MT8188 compatible timers (SYST) * "mediatek,mt8192-timer" for MT8192 compatible timers (SYST) * "mediatek,mt8195-timer" for MT8195 compatible timers (SYST) * "mediatek,mt7629-timer" for MT7629 compatible timers (SYST) diff --git a/dts/Bindings/timer/mstar,msc313e-timer.yaml b/dts/Bindings/timer/mstar,msc313e-timer.yaml index 03d5dba5d5..f118ca423e 100644 --- a/dts/Bindings/timer/mstar,msc313e-timer.yaml +++ b/dts/Bindings/timer/mstar,msc313e-timer.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/timer/mstar,msc313e-timer.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mstar MSC313e Timer Device Tree Bindings +title: Mstar MSC313e Timer maintainers: - Daniel Palmer <daniel@0x0f.com> diff --git a/dts/Bindings/timer/nxp,sysctr-timer.yaml b/dts/Bindings/timer/nxp,sysctr-timer.yaml index 830211c55b..2b9653dafa 100644 --- a/dts/Bindings/timer/nxp,sysctr-timer.yaml +++ b/dts/Bindings/timer/nxp,sysctr-timer.yaml @@ -32,6 +32,10 @@ properties: clock-names: const: per + nxp,no-divider: + description: if present, means there is no internal base clk divider. + type: boolean + required: - compatible - reg diff --git a/dts/Bindings/timer/renesas,tmu.yaml b/dts/Bindings/timer/renesas,tmu.yaml index c57169118b..60f4c059bc 100644 --- a/dts/Bindings/timer/renesas,tmu.yaml +++ b/dts/Bindings/timer/renesas,tmu.yaml @@ -37,6 +37,7 @@ properties: - renesas,tmu-r8a77990 # R-Car E3 - renesas,tmu-r8a77995 # R-Car D3 - renesas,tmu-r8a779a0 # R-Car V3U + - renesas,tmu-r8a779f0 # R-Car S4-8 - const: renesas,tmu reg: diff --git a/dts/Bindings/timer/rockchip,rk-timer.yaml b/dts/Bindings/timer/rockchip,rk-timer.yaml index 5d157d87da..dc3bc1e62f 100644 --- a/dts/Bindings/timer/rockchip,rk-timer.yaml +++ b/dts/Bindings/timer/rockchip,rk-timer.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/timer/rockchip,rk-timer.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Rockchip Timer Device Tree Bindings +title: Rockchip Timer maintainers: - Daniel Lezcano <daniel.lezcano@linaro.org> diff --git a/dts/Bindings/timer/samsung,exynos4210-mct.yaml b/dts/Bindings/timer/samsung,exynos4210-mct.yaml index 9c81d00b12..829bd2227f 100644 --- a/dts/Bindings/timer/samsung,exynos4210-mct.yaml +++ b/dts/Bindings/timer/samsung,exynos4210-mct.yaml @@ -25,6 +25,7 @@ properties: - samsung,exynos4412-mct - items: - enum: + - axis,artpec8-mct - samsung,exynos3250-mct - samsung,exynos5250-mct - samsung,exynos5260-mct @@ -45,6 +46,19 @@ properties: reg: maxItems: 1 + samsung,frc-shared: + type: boolean + description: | + Indicates that the hardware requires that this processor share the + free-running counter with a different (main) processor. + + samsung,local-timers: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 16 + description: | + List of indices of local timers usable from this processor. + interrupts: description: | Interrupts should be put in specific order. This is, the local timer @@ -75,6 +89,17 @@ required: allOf: - if: + not: + properties: + compatible: + contains: + enum: + - axis,artpec8-mct + then: + properties: + samsung,local-timers: false + samsung,frc-shared: false + - if: properties: compatible: contains: @@ -101,6 +126,7 @@ allOf: compatible: contains: enum: + - axis,artpec8-mct - samsung,exynos5260-mct - samsung,exynos5420-mct - samsung,exynos5433-mct diff --git a/dts/Bindings/timer/sifive,clint.yaml b/dts/Bindings/timer/sifive,clint.yaml index e64f463390..bbad241658 100644 --- a/dts/Bindings/timer/sifive,clint.yaml +++ b/dts/Bindings/timer/sifive,clint.yaml @@ -22,12 +22,18 @@ description: properties: compatible: - items: - - enum: - - sifive,fu540-c000-clint - - starfive,jh7100-clint - - canaan,k210-clint - - const: sifive,clint0 + oneOf: + - items: + - enum: + - sifive,fu540-c000-clint + - starfive,jh7100-clint + - canaan,k210-clint + - const: sifive,clint0 + - items: + - const: sifive,clint0 + - const: riscv,clint0 + deprecated: true + description: For the QEMU virt machine only description: Should be "<vendor>,<chip>-clint" and "sifive,clint<version>". diff --git a/dts/Bindings/timer/ti,timer-dm.yaml b/dts/Bindings/timer/ti,timer-dm.yaml index e32df21e63..acbb6f8997 100644 --- a/dts/Bindings/timer/ti,timer-dm.yaml +++ b/dts/Bindings/timer/ti,timer-dm.yaml @@ -51,6 +51,11 @@ properties: - const: timer_sys_ck minItems: 1 + power-domains: + description: + Power domain if available + maxItems: 1 + interrupts: description: Interrupt if available. The timer PWM features may be usable @@ -94,13 +99,15 @@ additionalProperties: false allOf: - if: - not: - properties: - compatible: - contains: - const: ti,am654-timer + properties: + compatible: + contains: + const: ti,am654-timer then: required: + - power-domains + else: + required: - interrupts - if: diff --git a/dts/Bindings/timer/xlnx,xps-timer.yaml b/dts/Bindings/timer/xlnx,xps-timer.yaml index dd168d41d2..b1597db042 100644 --- a/dts/Bindings/timer/xlnx,xps-timer.yaml +++ b/dts/Bindings/timer/xlnx,xps-timer.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Xilinx LogiCORE IP AXI Timer Device Tree Binding +title: Xilinx LogiCORE IP AXI Timer maintainers: - Sean Anderson <sean.anderson@seco.com> diff --git a/dts/Bindings/timestamp/hte-consumer.yaml b/dts/Bindings/timestamp/hte-consumer.yaml index 6456515c3d..5142d6d4fc 100644 --- a/dts/Bindings/timestamp/hte-consumer.yaml +++ b/dts/Bindings/timestamp/hte-consumer.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/timestamp/hte-consumer.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: HTE Consumer Device Tree Bindings +title: HTE Consumer maintainers: - Dipen Patel <dipenp@nvidia.com> diff --git a/dts/Bindings/ufs/samsung,exynos-ufs.yaml b/dts/Bindings/ufs/samsung,exynos-ufs.yaml index 2c715eec48..a998879889 100644 --- a/dts/Bindings/ufs/samsung,exynos-ufs.yaml +++ b/dts/Bindings/ufs/samsung,exynos-ufs.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Samsung SoC series UFS host controller Device Tree Bindings +title: Samsung SoC series UFS host controller maintainers: - Alim Akhtar <alim.akhtar@samsung.com> diff --git a/dts/Bindings/usb/allwinner,sun4i-a10-musb.yaml b/dts/Bindings/usb/allwinner,sun4i-a10-musb.yaml index e5dbf4169b..8992eff6ce 100644 --- a/dts/Bindings/usb/allwinner,sun4i-a10-musb.yaml +++ b/dts/Bindings/usb/allwinner,sun4i-a10-musb.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/usb/allwinner,sun4i-a10-musb.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 mUSB OTG Controller Device Tree Bindings +title: Allwinner A10 mUSB OTG Controller maintainers: - Chen-Yu Tsai <wens@csie.org> diff --git a/dts/Bindings/usb/analogix,anx7411.yaml b/dts/Bindings/usb/analogix,anx7411.yaml index ee436308e5..0e72c08e65 100644 --- a/dts/Bindings/usb/analogix,anx7411.yaml +++ b/dts/Bindings/usb/analogix,anx7411.yaml @@ -23,6 +23,8 @@ properties: connector: type: object $ref: ../connector/usb-connector.yaml + unevaluatedProperties: false + description: Properties for usb c connector. diff --git a/dts/Bindings/usb/aspeed,usb-vhub.yaml b/dts/Bindings/usb/aspeed,usb-vhub.yaml index 8b019ac05b..a86bcd9510 100644 --- a/dts/Bindings/usb/aspeed,usb-vhub.yaml +++ b/dts/Bindings/usb/aspeed,usb-vhub.yaml @@ -67,6 +67,7 @@ properties: vhub-strings: type: object + additionalProperties: false properties: '#address-cells': @@ -78,6 +79,7 @@ properties: patternProperties: '^string@[0-9a-f]+$': type: object + additionalProperties: false description: string descriptors of the specific language properties: diff --git a/dts/Bindings/usb/brcm,bcm7445-ehci.yaml b/dts/Bindings/usb/brcm,bcm7445-ehci.yaml index 2a9acf2b5a..ad075407d8 100644 --- a/dts/Bindings/usb/brcm,bcm7445-ehci.yaml +++ b/dts/Bindings/usb/brcm,bcm7445-ehci.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/usb/brcm,bcm7445-ehci.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Broadcom STB USB EHCI Controller Device Tree Bindings +title: Broadcom STB USB EHCI Controller allOf: - $ref: "usb-hcd.yaml" diff --git a/dts/Bindings/usb/brcm,usb-pinmap.yaml b/dts/Bindings/usb/brcm,usb-pinmap.yaml index d4618d15ec..5cc81ced58 100644 --- a/dts/Bindings/usb/brcm,usb-pinmap.yaml +++ b/dts/Bindings/usb/brcm,usb-pinmap.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/usb/brcm,usb-pinmap.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Broadcom USB pin map Controller Device Tree Bindings +title: Broadcom USB pin map Controller maintainers: - Al Cooper <alcooperx@gmail.com> diff --git a/dts/Bindings/usb/dwc2.yaml b/dts/Bindings/usb/dwc2.yaml index 1bfbc6ef16..dc4988c000 100644 --- a/dts/Bindings/usb/dwc2.yaml +++ b/dts/Bindings/usb/dwc2.yaml @@ -32,6 +32,7 @@ properties: - enum: - rockchip,px30-usb - rockchip,rk3036-usb + - rockchip,rk3128-usb - rockchip,rk3188-usb - rockchip,rk3228-usb - rockchip,rk3288-usb diff --git a/dts/Bindings/usb/faraday,fotg210.txt b/dts/Bindings/usb/faraday,fotg210.txt deleted file mode 100644 index 06a2286e20..0000000000 --- a/dts/Bindings/usb/faraday,fotg210.txt +++ /dev/null @@ -1,35 +0,0 @@ -Faraday FOTG Host controller - -This OTG-capable USB host controller is found in Cortina Systems -Gemini and other SoC products. - -Required properties: -- compatible: should be one of: - "faraday,fotg210" - "cortina,gemini-usb", "faraday,fotg210" -- reg: should contain one register range i.e. start and length -- interrupts: description of the interrupt line - -Optional properties: -- clocks: should contain the IP block clock -- clock-names: should be "PCLK" for the IP block clock - -Required properties for "cortina,gemini-usb" compatible: -- syscon: a phandle to the system controller to access PHY registers - -Optional properties for "cortina,gemini-usb" compatible: -- cortina,gemini-mini-b: boolean property that indicates that a Mini-B - OTG connector is in use -- wakeup-source: see power/wakeup-source.txt - -Example for Gemini: - -usb@68000000 { - compatible = "cortina,gemini-usb", "faraday,fotg210"; - reg = <0x68000000 0x1000>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cc 12>; - clock-names = "PCLK"; - syscon = <&syscon>; - wakeup-source; -}; diff --git a/dts/Bindings/usb/faraday,fotg210.yaml b/dts/Bindings/usb/faraday,fotg210.yaml new file mode 100644 index 0000000000..c69bbfbcf7 --- /dev/null +++ b/dts/Bindings/usb/faraday,fotg210.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2022 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/faraday,fotg210.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Faraday Technology FOTG210 HS OTG USB 2.0 controller Bindings + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +allOf: + - $ref: usb-drd.yaml# + - $ref: usb-hcd.yaml# + +properties: + compatible: + oneOf: + - const: faraday,fotg210 + - items: + - const: cortina,gemini-usb + - const: faraday,fotg210 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: PCLK + + resets: + maxItems: 1 + + syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: a phandle to the global Gemini system controller on + Gemini systems + + dr_mode: true + + phys: + maxItems: 1 + + phy-names: + const: usb2-phy + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/cortina,gemini-clock.h> + #include <dt-bindings/reset/cortina,gemini-reset.h> + usb0: usb@68000000 { + compatible = "cortina,gemini-usb", "faraday,fotg210"; + reg = <0x68000000 0x1000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + resets = <&syscon GEMINI_RESET_USB0>; + clocks = <&syscon GEMINI_CLK_GATE_USB0>; + clock-names = "PCLK"; + syscon = <&syscon>; + dr_mode = "host"; + }; diff --git a/dts/Bindings/usb/generic-ehci.yaml b/dts/Bindings/usb/generic-ehci.yaml index 079f7cff0c..c5f629c5bc 100644 --- a/dts/Bindings/usb/generic-ehci.yaml +++ b/dts/Bindings/usb/generic-ehci.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/usb/generic-ehci.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: USB EHCI Controller Device Tree Bindings +title: USB EHCI Controller maintainers: - Greg Kroah-Hartman <gregkh@linuxfoundation.org> diff --git a/dts/Bindings/usb/generic-ohci.yaml b/dts/Bindings/usb/generic-ohci.yaml index 180361b79f..f838f78d61 100644 --- a/dts/Bindings/usb/generic-ohci.yaml +++ b/dts/Bindings/usb/generic-ohci.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/usb/generic-ohci.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: USB OHCI Controller Device Tree Bindings +title: USB OHCI Controller allOf: - $ref: "usb-hcd.yaml" diff --git a/dts/Bindings/usb/generic-xhci.yaml b/dts/Bindings/usb/generic-xhci.yaml index 23d73df96e..db841589fc 100644 --- a/dts/Bindings/usb/generic-xhci.yaml +++ b/dts/Bindings/usb/generic-xhci.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/usb/generic-xhci.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: USB xHCI Controller Device Tree Bindings +title: USB xHCI Controller maintainers: - Mathias Nyman <mathias.nyman@intel.com> diff --git a/dts/Bindings/usb/mediatek,mt6370-tcpc.yaml b/dts/Bindings/usb/mediatek,mt6370-tcpc.yaml new file mode 100644 index 0000000000..72f56cc884 --- /dev/null +++ b/dts/Bindings/usb/mediatek,mt6370-tcpc.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/usb/mediatek,mt6370-tcpc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediatTek MT6370 Type-C Port Switch and Power Delivery controller + +maintainers: + - ChiYuan Huang <cy_huang@richtek.com> + +description: | + MediaTek MT6370 is a multi-functional device. + It integrates charger, ADC, flash, RGB indicators, + regulators (DSV/VIBLDO), and TypeC Port Switch with Power Delivery controller. + This document only describes MT6370 Type-C Port Switch and + Power Delivery controller. + +properties: + compatible: + enum: + - mediatek,mt6370-tcpc + + interrupts: + maxItems: 1 + + connector: + type: object + $ref: /schemas/connector/usb-connector.yaml# + unevaluatedProperties: false + +additionalProperties: false + +required: + - compatible + - interrupts diff --git a/dts/Bindings/usb/mediatek,mtk-xhci.yaml b/dts/Bindings/usb/mediatek,mtk-xhci.yaml index b0e58b15b9..939623867a 100644 --- a/dts/Bindings/usb/mediatek,mtk-xhci.yaml +++ b/dts/Bindings/usb/mediatek,mtk-xhci.yaml @@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: MediaTek USB3 xHCI Device Tree Bindings +title: MediaTek USB3 xHCI maintainers: - Chunfeng Yun <chunfeng.yun@mediatek.com> diff --git a/dts/Bindings/usb/mediatek,mtu3.yaml b/dts/Bindings/usb/mediatek,mtu3.yaml index b019d49017..80750b0f45 100644 --- a/dts/Bindings/usb/mediatek,mtu3.yaml +++ b/dts/Bindings/usb/mediatek,mtu3.yaml @@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/usb/mediatek,mtu3.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: MediaTek USB3 DRD Controller Device Tree Bindings +title: MediaTek USB3 DRD Controller maintainers: - Chunfeng Yun <chunfeng.yun@mediatek.com> diff --git a/dts/Bindings/usb/mediatek,musb.yaml b/dts/Bindings/usb/mediatek,musb.yaml index 11a33f9b1f..f16ab30a95 100644 --- a/dts/Bindings/usb/mediatek,musb.yaml +++ b/dts/Bindings/usb/mediatek,musb.yaml @@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/usb/mediatek,musb.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: MediaTek MUSB DRD/OTG Controller Device Tree Bindings +title: MediaTek MUSB DRD/OTG Controller maintainers: - Min Guo <min.guo@mediatek.com> diff --git a/dts/Bindings/usb/microchip,mpfs-musb.yaml b/dts/Bindings/usb/microchip,mpfs-musb.yaml index 48c458c658..c5e9ce2e7b 100644 --- a/dts/Bindings/usb/microchip,mpfs-musb.yaml +++ b/dts/Bindings/usb/microchip,mpfs-musb.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/usb/microchip,mpfs-musb.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Microchip MPFS USB Controller Device Tree Bindings +title: Microchip MPFS USB Controller allOf: - $ref: usb-drd.yaml# diff --git a/dts/Bindings/usb/npcm7xx-usb.txt b/dts/Bindings/usb/npcm7xx-usb.txt index 5a0f1f14fb..352a0a1e2f 100644 --- a/dts/Bindings/usb/npcm7xx-usb.txt +++ b/dts/Bindings/usb/npcm7xx-usb.txt @@ -5,7 +5,9 @@ EHCI: ----- Required properties: -- compatible: "nuvoton,npcm750-ehci" +- compatible: should be one of + "nuvoton,npcm750-ehci" + "nuvoton,npcm845-ehci" - interrupts: Should contain the EHCI interrupt - reg: Physical address and length of the register set for the device diff --git a/dts/Bindings/usb/qcom,dwc3.yaml b/dts/Bindings/usb/qcom,dwc3.yaml index cd2f7cb674..a6e6abb4df 100644 --- a/dts/Bindings/usb/qcom,dwc3.yaml +++ b/dts/Bindings/usb/qcom,dwc3.yaml @@ -26,6 +26,7 @@ properties: - qcom,sc7280-dwc3 - qcom,sc8280xp-dwc3 - qcom,sdm660-dwc3 + - qcom,sdm670-dwc3 - qcom,sdm845-dwc3 - qcom,sdx55-dwc3 - qcom,sdx65-dwc3 @@ -175,6 +176,7 @@ allOf: - qcom,msm8998-dwc3 - qcom,sc7180-dwc3 - qcom,sc7280-dwc3 + - qcom,sdm670-dwc3 - qcom,sdm845-dwc3 - qcom,sdx55-dwc3 - qcom,sm6350-dwc3 @@ -294,6 +296,7 @@ allOf: compatible: contains: enum: + - qcom,sm6115-dwc3 - qcom,sm6125-dwc3 - qcom,sm8150-dwc3 - qcom,sm8250-dwc3 @@ -344,11 +347,11 @@ allOf: - qcom,msm8994-dwc3 - qcom,qcs404-dwc3 - qcom,sc7180-dwc3 + - qcom,sdm670-dwc3 - qcom,sdm845-dwc3 - qcom,sdx55-dwc3 - qcom,sdx65-dwc3 - qcom,sm4250-dwc3 - - qcom,sm6115-dwc3 - qcom,sm6125-dwc3 - qcom,sm6350-dwc3 - qcom,sm8150-dwc3 @@ -380,6 +383,7 @@ allOf: - qcom,msm8953-dwc3 - qcom,msm8996-dwc3 - qcom,msm8998-dwc3 + - qcom,sm6115-dwc3 then: properties: interrupts: diff --git a/dts/Bindings/usb/renesas,usb3-peri.yaml b/dts/Bindings/usb/renesas,usb3-peri.yaml index 9fcf54b10b..55dfd121b5 100644 --- a/dts/Bindings/usb/renesas,usb3-peri.yaml +++ b/dts/Bindings/usb/renesas,usb3-peri.yaml @@ -11,27 +11,55 @@ maintainers: properties: compatible: - items: - - enum: - - renesas,r8a774a1-usb3-peri # RZ/G2M - - renesas,r8a774b1-usb3-peri # RZ/G2N - - renesas,r8a774c0-usb3-peri # RZ/G2E - - renesas,r8a774e1-usb3-peri # RZ/G2H - - renesas,r8a7795-usb3-peri # R-Car H3 - - renesas,r8a7796-usb3-peri # R-Car M3-W - - renesas,r8a77961-usb3-peri # R-Car M3-W+ - - renesas,r8a77965-usb3-peri # R-Car M3-N - - renesas,r8a77990-usb3-peri # R-Car E3 - - const: renesas,rcar-gen3-usb3-peri + oneOf: + - items: + - enum: + - renesas,r8a774a1-usb3-peri # RZ/G2M + - renesas,r8a774b1-usb3-peri # RZ/G2N + - renesas,r8a774c0-usb3-peri # RZ/G2E + - renesas,r8a774e1-usb3-peri # RZ/G2H + - renesas,r8a7795-usb3-peri # R-Car H3 + - renesas,r8a7796-usb3-peri # R-Car M3-W + - renesas,r8a77961-usb3-peri # R-Car M3-W+ + - renesas,r8a77965-usb3-peri # R-Car M3-N + - renesas,r8a77990-usb3-peri # R-Car E3 + - const: renesas,rcar-gen3-usb3-peri + + - items: + - enum: + - renesas,r9a09g011-usb3-peri # RZ/V2M + - const: renesas,rzv2m-usb3-peri reg: maxItems: 1 interrupts: - maxItems: 1 + minItems: 1 + items: + - description: Combined interrupt for DMA, SYS and ERR + - description: Dual Role Device (DRD) + - description: Battery Charging + - description: Global Purpose Input + + interrupt-names: + minItems: 1 + items: + - const: all_p + - const: drd + - const: bc + - const: gpi clocks: - maxItems: 1 + minItems: 1 + items: + - description: Main clock + - description: Register access clock + + clock-names: + minItems: 1 + items: + - const: aclk + - const: reg phys: maxItems: 1 @@ -43,7 +71,15 @@ properties: maxItems: 1 resets: - maxItems: 1 + minItems: 1 + items: + - description: Peripheral reset + - description: DRD reset + + reset-names: + items: + - const: aresetn_p + - const: drd_reset usb-role-switch: $ref: /schemas/types.yaml#/definitions/flag @@ -78,6 +114,39 @@ required: - interrupts - clocks +allOf: + - if: + properties: + compatible: + contains: + enum: + - renesas,rzv2m-usb3-peri + then: + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + interrupts: + minItems: 4 + interrupt-names: + minItems: 4 + resets: + minItems: 2 + required: + - clock-names + - interrupt-names + - resets + - reset-names + else: + properties: + clocks: + maxItems: 1 + interrupts: + maxItems: 1 + resets: + maxItems: 1 + additionalProperties: false examples: diff --git a/dts/Bindings/usb/richtek,rt1711h.yaml b/dts/Bindings/usb/richtek,rt1711h.yaml new file mode 100644 index 0000000000..1999f614c8 --- /dev/null +++ b/dts/Bindings/usb/richtek,rt1711h.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/usb/richtek,rt1711h.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Richtek RT1711H Type-C Port Switch and Power Delivery controller + +maintainers: + - Gene Chen <gene_chen@richtek.com> + +description: | + The RT1711H is a USB Type-C controller that complies with the latest + USB Type-C and PD standards. It does the USB Type-C detection including attach + and orientation. It integrates the physical layer of the USB BMC power + delivery protocol to allow up to 100W of power. The BMC PD block enables full + support for alternative interfaces of the Type-C specification. + +properties: + compatible: + enum: + - richtek,rt1711h + - richtek,rt1715 + description: + RT1711H support PD20, RT1715 support PD30 except Fast Role Swap. + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + wakeup-source: + type: boolean + + connector: + type: object + $ref: /schemas/connector/usb-connector.yaml# + description: + Properties for usb c connector. + +additionalProperties: false + +required: + - compatible + - reg + - connector + - interrupts + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/usb/pd.h> + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + rt1711h@4e { + compatible = "richtek,rt1711h"; + reg = <0x4e>; + interrupts-extended = <&gpio26 3 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)>; + sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)>; + op-sink-microwatt = <10000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&usb_hs>; + }; + }; + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&usb_ss>; + }; + }; + port@2 { + reg = <2>; + endpoint { + remote-endpoint = <&dp_aux>; + }; + }; + }; + }; + }; + }; +... diff --git a/dts/Bindings/usb/smsc,usb3503.yaml b/dts/Bindings/usb/smsc,usb3503.yaml index 321b6f1661..a09f4528ae 100644 --- a/dts/Bindings/usb/smsc,usb3503.yaml +++ b/dts/Bindings/usb/smsc,usb3503.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/usb/smsc,usb3503.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: SMSC USB3503 High-Speed Hub Controller Device Tree Bindings +title: SMSC USB3503 High-Speed Hub Controller maintainers: - Dongjin Kim <tobetter@gmail.com> diff --git a/dts/Bindings/usb/snps,dwc3.yaml b/dts/Bindings/usb/snps,dwc3.yaml index 1779d08ba1..6d78048c46 100644 --- a/dts/Bindings/usb/snps,dwc3.yaml +++ b/dts/Bindings/usb/snps,dwc3.yaml @@ -234,6 +234,18 @@ properties: avoid -EPROTO errors with usbhid on some devices (Hikey 970). type: boolean + snps,gfladj-refclk-lpm-sel-quirk: + description: + When set, run the SOF/ITP counter based on ref_clk. + type: boolean + + snps,resume-hs-terminations: + description: + Fix the issue of HS terminations CRC error on resume by enabling this + quirk. When set, all the termsel, xcvrsel, opmode becomes 0 during end + of resume. This option is to support certain legacy ULPI PHYs. + type: boolean + snps,is-utmi-l1-suspend: description: True when DWC3 asserts output signal utmi_l1_suspend_n, false when diff --git a/dts/Bindings/usb/st,stusb160x.yaml b/dts/Bindings/usb/st,stusb160x.yaml index b5a8c9814d..b8974807b6 100644 --- a/dts/Bindings/usb/st,stusb160x.yaml +++ b/dts/Bindings/usb/st,stusb160x.yaml @@ -33,6 +33,7 @@ properties: connector: type: object $ref: /schemas/connector/usb-connector.yaml# + unevaluatedProperties: false properties: compatible: @@ -74,9 +75,14 @@ examples: data-role = "dual"; typec-power-opmode = "default"; - port { - typec_con_ep: endpoint { - remote-endpoint = <&usbotg_hs_ep>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec_con_ep: endpoint { + remote-endpoint = <&usbotg_hs_ep>; + }; }; }; }; diff --git a/dts/Bindings/usb/usb-drd.yaml b/dts/Bindings/usb/usb-drd.yaml index f229fc8068..1567549b05 100644 --- a/dts/Bindings/usb/usb-drd.yaml +++ b/dts/Bindings/usb/usb-drd.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/usb/usb-drd.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Generic USB OTG Controller Device Tree Bindings +title: Generic USB OTG Controller maintainers: - Greg Kroah-Hartman <gregkh@linuxfoundation.org> diff --git a/dts/Bindings/usb/usb-hcd.yaml b/dts/Bindings/usb/usb-hcd.yaml index 1dc3d5d7b4..692dd60e3f 100644 --- a/dts/Bindings/usb/usb-hcd.yaml +++ b/dts/Bindings/usb/usb-hcd.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/usb/usb-hcd.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Generic USB Host Controller Device Tree Bindings +title: Generic USB Host Controller maintainers: - Greg Kroah-Hartman <gregkh@linuxfoundation.org> diff --git a/dts/Bindings/usb/usb-xhci.yaml b/dts/Bindings/usb/usb-xhci.yaml index 965f87fef7..f2139a9f35 100644 --- a/dts/Bindings/usb/usb-xhci.yaml +++ b/dts/Bindings/usb/usb-xhci.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/usb/usb-xhci.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Generic USB xHCI Controller Device Tree Bindings +title: Generic USB xHCI Controller maintainers: - Mathias Nyman <mathias.nyman@intel.com> diff --git a/dts/Bindings/usb/usb.yaml b/dts/Bindings/usb/usb.yaml index 939f217b8c..326b14f05d 100644 --- a/dts/Bindings/usb/usb.yaml +++ b/dts/Bindings/usb/usb.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/usb/usb.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Generic USB Controller Device Tree Bindings +title: Generic USB Controller maintainers: - Greg Kroah-Hartman <gregkh@linuxfoundation.org> diff --git a/dts/Bindings/usb/willsemi,wusb3801.yaml b/dts/Bindings/usb/willsemi,wusb3801.yaml index c2b2243c78..5aa4ffd671 100644 --- a/dts/Bindings/usb/willsemi,wusb3801.yaml +++ b/dts/Bindings/usb/willsemi,wusb3801.yaml @@ -28,6 +28,7 @@ properties: connector: type: object $ref: ../connector/usb-connector.yaml# + unevaluatedProperties: false description: The managed USB Type-C connector. Since WUSB3801 does not support Power Delivery, the node should have the "pd-disable" property. diff --git a/dts/Bindings/vendor-prefixes.yaml b/dts/Bindings/vendor-prefixes.yaml index 2f0151e9f6..6e323a3802 100644 --- a/dts/Bindings/vendor-prefixes.yaml +++ b/dts/Bindings/vendor-prefixes.yaml @@ -105,6 +105,8 @@ patternProperties: description: AMS-Taos Inc. "^analogix,.*": description: Analogix Semiconductor, Inc. + "^anbernic,.*": + description: Anbernic "^andestech,.*": description: Andes Technology Corporation "^anvo,.*": @@ -328,6 +330,8 @@ patternProperties: description: Digi International Inc. "^digilent,.*": description: Diglent, Inc. + "^diodes,.*": + description: Diodes, Inc. "^dioo,.*": description: Dioo Microcircuit Co., Ltd "^dlc,.*": @@ -777,6 +781,8 @@ patternProperties: description: MELFAS Inc. "^mellanox,.*": description: Mellanox Technologies + "^memsensing,.*": + description: MEMSensing Microsystems Co., Ltd. "^memsic,.*": description: MEMSIC Inc. "^menlo,.*": @@ -787,6 +793,8 @@ patternProperties: description: Cisco Meraki, LLC "^merrii,.*": description: Merrii Technology Co., Ltd. + "^methode,.*": + description: Methode Electronics, Inc. "^micrel,.*": description: Micrel Inc. "^microchip,.*": @@ -819,6 +827,8 @@ patternProperties: description: MNT Research GmbH "^modtronix,.*": description: Modtronix Engineering + "^moortec,.*": + description: Moortec Semiconductor Ltd. "^mosaixtech,.*": description: Mosaix Technologies, Inc. "^motorola,.*": @@ -925,6 +935,8 @@ patternProperties: description: On Tat Industrial Company "^opalkelly,.*": description: Opal Kelly Incorporated + "^openailab,.*": + description: openailab.com "^opencores,.*": description: OpenCores.org "^openembed,.*": diff --git a/dts/Bindings/virtio/iommu.txt b/dts/Bindings/virtio/iommu.txt deleted file mode 100644 index 2407fea065..0000000000 --- a/dts/Bindings/virtio/iommu.txt +++ /dev/null @@ -1,66 +0,0 @@ -* virtio IOMMU PCI device - -When virtio-iommu uses the PCI transport, its programming interface is -discovered dynamically by the PCI probing infrastructure. However the -device tree statically describes the relation between IOMMU and DMA -masters. Therefore, the PCI root complex that hosts the virtio-iommu -contains a child node representing the IOMMU device explicitly. - -Required properties: - -- compatible: Should be "virtio,pci-iommu" -- reg: PCI address of the IOMMU. As defined in the PCI Bus - Binding reference [1], the reg property is a five-cell - address encoded as (phys.hi phys.mid phys.lo size.hi - size.lo). phys.hi should contain the device's BDF as - 0b00000000 bbbbbbbb dddddfff 00000000. The other cells - should be zero. -- #iommu-cells: Each platform DMA master managed by the IOMMU is assigned - an endpoint ID, described by the "iommus" property [2]. - For virtio-iommu, #iommu-cells must be 1. - -Notes: - -- DMA from the IOMMU device isn't managed by another IOMMU. Therefore the - virtio-iommu node doesn't have an "iommus" property, and is omitted from - the iommu-map property of the root complex. - -Example: - -pcie@10000000 { - compatible = "pci-host-ecam-generic"; - ... - - /* The IOMMU programming interface uses slot 00:01.0 */ - iommu0: iommu@0008 { - compatible = "virtio,pci-iommu"; - reg = <0x00000800 0 0 0 0>; - #iommu-cells = <1>; - }; - - /* - * The IOMMU manages all functions in this PCI domain except - * itself. Omit BDF 00:01.0. - */ - iommu-map = <0x0 &iommu0 0x0 0x8> - <0x9 &iommu0 0x9 0xfff7>; -}; - -pcie@20000000 { - compatible = "pci-host-ecam-generic"; - ... - /* - * The IOMMU also manages all functions from this domain, - * with endpoint IDs 0x10000 - 0x1ffff - */ - iommu-map = <0x0 &iommu0 0x10000 0x10000>; -}; - -ethernet@fe001000 { - ... - /* The IOMMU manages this platform device with endpoint ID 0x20000 */ - iommus = <&iommu0 0x20000>; -}; - -[1] Documentation/devicetree/bindings/pci/pci.txt -[2] Documentation/devicetree/bindings/iommu/iommu.txt diff --git a/dts/Bindings/virtio/pci-iommu.yaml b/dts/Bindings/virtio/pci-iommu.yaml new file mode 100644 index 0000000000..972a785a42 --- /dev/null +++ b/dts/Bindings/virtio/pci-iommu.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/virtio/pci-iommu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: virtio-iommu device using the virtio-pci transport + +maintainers: + - Jean-Philippe Brucker <jean-philippe@linaro.org> + +description: | + When virtio-iommu uses the PCI transport, its programming interface is + discovered dynamically by the PCI probing infrastructure. However the + device tree statically describes the relation between IOMMU and DMA + masters. Therefore, the PCI root complex that hosts the virtio-iommu + contains a child node representing the IOMMU device explicitly. + + DMA from the IOMMU device isn't managed by another IOMMU. Therefore the + virtio-iommu node doesn't have an "iommus" property, and is omitted from + the iommu-map property of the root complex. + +properties: + # If compatible is present, it should contain the vendor and device ID + # according to the PCI Bus Binding specification. Since PCI provides + # built-in identification methods, compatible is not actually required. + compatible: + oneOf: + - items: + - const: virtio,pci-iommu + - const: pci1af4,1057 + - items: + - const: pci1af4,1057 + + reg: + description: | + PCI address of the IOMMU. As defined in the PCI Bus Binding + reference, the reg property is a five-cell address encoded as (phys.hi + phys.mid phys.lo size.hi size.lo). phys.hi should contain the device's + BDF as 0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be + zero. See Documentation/devicetree/bindings/pci/pci.txt + + '#iommu-cells': + const: 1 + +required: + - compatible + - reg + - '#iommu-cells' + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie@40000000 { + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x40000000 0x0 0x1000000>; + ranges = <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x0f000000>; + + /* + * The IOMMU manages all functions in this PCI domain except + * itself. Omit BDF 00:01.0. + */ + iommu-map = <0x0 &iommu0 0x0 0x8 + 0x9 &iommu0 0x9 0xfff7>; + + /* The IOMMU programming interface uses slot 00:01.0 */ + iommu0: iommu@1,0 { + compatible = "pci1af4,1057"; + reg = <0x800 0 0 0 0>; + #iommu-cells = <1>; + }; + }; + + pcie@50000000 { + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x50000000 0x0 0x1000000>; + ranges = <0x02000000 0x0 0x51000000 0x0 0x51000000 0x0 0x0f000000>; + + /* + * The IOMMU also manages all functions from this domain, + * with endpoint IDs 0x10000 - 0x1ffff + */ + iommu-map = <0x0 &iommu0 0x10000 0x10000>; + }; + + ethernet { + /* The IOMMU manages this platform device with endpoint ID 0x20000 */ + iommus = <&iommu0 0x20000>; + }; + }; + +... diff --git a/dts/Bindings/w1/w1-gpio.yaml b/dts/Bindings/w1/w1-gpio.yaml index 8eef238016..b02b022370 100644 --- a/dts/Bindings/w1/w1-gpio.yaml +++ b/dts/Bindings/w1/w1-gpio.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/w1/w1-gpio.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Bitbanged GPIO 1-Wire Bus Device Tree Bindings +title: Bitbanged GPIO 1-Wire Bus maintainers: - Daniel Mack <zonque@gmail.com> diff --git a/dts/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/dts/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index ed6c1ca80d..026c2e5e77 100644 --- a/dts/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/dts/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/watchdog/allwinner,sun4i-a10-wdt.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Allwinner A10 Watchdog Device Tree Bindings +title: Allwinner A10 Watchdog allOf: - $ref: "watchdog.yaml#" diff --git a/dts/Bindings/watchdog/atmel,at91sam9-wdt.yaml b/dts/Bindings/watchdog/atmel,at91sam9-wdt.yaml new file mode 100644 index 0000000000..ad27bc5186 --- /dev/null +++ b/dts/Bindings/watchdog/atmel,at91sam9-wdt.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/atmel,at91sam9-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel Watchdog Timers + +maintainers: + - Eugen Hristev <eugen.hristev@microchip.com> + +properties: + compatible: + const: atmel,at91sam9260-wdt + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + atmel,max-heartbeat-sec: + description: + Should contain the maximum heartbeat value in seconds. This value + should be less or equal to 16. It is used to compute the WDV field. + maximum: 16 + + atmel,min-heartbeat-sec: + description: + Should contain the minimum heartbeat value in seconds. This value + must be smaller than the max-heartbeat-sec value. It is used to + compute the WDD field. + maximum: 16 + + atmel,watchdog-type: + $ref: /schemas/types.yaml#/definitions/string + description: | + Should be hardware or software. + oneOf: + - description: + Hardware watchdog uses the at91 watchdog reset. + const: hardware + - description: | + Software watchdog uses the watchdog interrupt + to trigger a software reset. + const: software + default: hardware + + atmel,reset-type: + $ref: /schemas/types.yaml#/definitions/string + description: | + Should be proc or all. This is valid only when using hardware watchdog. + oneOf: + - description: + Assert peripherals and processor reset signals. + const: all + - description: + Assert the processor reset signal. + const: proc + default: all + + atmel,disable: + $ref: /schemas/types.yaml#/definitions/flag + description: + Should be present if you want to stop the watchdog. + + atmel,idle-halt: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Should be present if you want to stop the watchdog when + entering idle state. + CAUTION: This property should be used with care, it actually makes the + watchdog not counting when the CPU is in idle state, therefore the + watchdog reset time depends on mean CPU usage and will not reset at all + if the CPU stops working while it is in idle state, which is probably + not what you want. + + atmel,dbg-halt: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Should be present if you want to stop the watchdog when + entering debug state. + +required: + - compatible + - reg + - clocks + +allOf: + - $ref: watchdog.yaml# + - if: + properties: + atmel,reset-type: + enum: + - all + - proc + then: + properties: + atmel,watchdog-type: + const: hardware + +dependencies: + atmel,reset-type: ['atmel,watchdog-type'] + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + watchdog@fffffd40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffd40 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + timeout-sec = <15>; + atmel,watchdog-type = "hardware"; + atmel,reset-type = "all"; + atmel,dbg-halt; + atmel,idle-halt; + atmel,max-heartbeat-sec = <16>; + atmel,min-heartbeat-sec = <0>; + }; diff --git a/dts/Bindings/watchdog/atmel-wdt.txt b/dts/Bindings/watchdog/atmel-wdt.txt deleted file mode 100644 index 711a880b3d..0000000000 --- a/dts/Bindings/watchdog/atmel-wdt.txt +++ /dev/null @@ -1,51 +0,0 @@ -* Atmel Watchdog Timers - -** at91sam9-wdt - -Required properties: -- compatible: must be "atmel,at91sam9260-wdt". -- reg: physical base address of the controller and length of memory mapped - region. -- clocks: phandle to input clock. - -Optional properties: -- timeout-sec: contains the watchdog timeout in seconds. -- interrupts : Should contain WDT interrupt. -- atmel,max-heartbeat-sec : Should contain the maximum heartbeat value in - seconds. This value should be less or equal to 16. It is used to - compute the WDV field. -- atmel,min-heartbeat-sec : Should contain the minimum heartbeat value in - seconds. This value must be smaller than the max-heartbeat-sec value. - It is used to compute the WDD field. -- atmel,watchdog-type : Should be "hardware" or "software". Hardware watchdog - use the at91 watchdog reset. Software watchdog use the watchdog - interrupt to trigger a software reset. -- atmel,reset-type : Should be "proc" or "all". - "all" : assert peripherals and processor reset signals - "proc" : assert the processor reset signal - This is valid only when using "hardware" watchdog. -- atmel,disable : Should be present if you want to disable the watchdog. -- atmel,idle-halt : Should be present if you want to stop the watchdog when - entering idle state. - CAUTION: This property should be used with care, it actually makes the - watchdog not counting when the CPU is in idle state, therefore the - watchdog reset time depends on mean CPU usage and will not reset at all - if the CPU stop working while it is in idle state, which is probably - not what you want. -- atmel,dbg-halt : Should be present if you want to stop the watchdog when - entering debug state. - -Example: - watchdog@fffffd40 { - compatible = "atmel,at91sam9260-wdt"; - reg = <0xfffffd40 0x10>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&clk32k>; - timeout-sec = <15>; - atmel,watchdog-type = "hardware"; - atmel,reset-type = "all"; - atmel,dbg-halt; - atmel,idle-halt; - atmel,max-heartbeat-sec = <16>; - atmel,min-heartbeat-sec = <0>; - }; diff --git a/dts/Bindings/watchdog/mediatek,mt7621-wdt.yaml b/dts/Bindings/watchdog/mediatek,mt7621-wdt.yaml new file mode 100644 index 0000000000..b2b17fdf4e --- /dev/null +++ b/dts/Bindings/watchdog/mediatek,mt7621-wdt.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/mediatek,mt7621-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink Watchdog Timers + +maintainers: + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + const: mediatek,mt7621-wdt + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + watchdog@100 { + compatible = "mediatek,mt7621-wdt"; + reg = <0x100 0x100>; + }; diff --git a/dts/Bindings/watchdog/mstar,msc313e-wdt.yaml b/dts/Bindings/watchdog/mstar,msc313e-wdt.yaml index e3e8b86dbf..33794711c5 100644 --- a/dts/Bindings/watchdog/mstar,msc313e-wdt.yaml +++ b/dts/Bindings/watchdog/mstar,msc313e-wdt.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/watchdog/mstar,msc313e-wdt.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: MStar Watchdog Device Tree Bindings +title: MStar Watchdog maintainers: - Daniel Palmer <daniel@0x0f.com> diff --git a/dts/Bindings/watchdog/mt7621-wdt.txt b/dts/Bindings/watchdog/mt7621-wdt.txt deleted file mode 100644 index c15ef0ef60..0000000000 --- a/dts/Bindings/watchdog/mt7621-wdt.txt +++ /dev/null @@ -1,12 +0,0 @@ -Ralink Watchdog Timers - -Required properties: -- compatible: must be "mediatek,mt7621-wdt" -- reg: physical base address of the controller and length of the register range - -Example: - - watchdog@100 { - compatible = "mediatek,mt7621-wdt"; - reg = <0x100 0x10>; - }; diff --git a/dts/Bindings/watchdog/of-xilinx-wdt.txt b/dts/Bindings/watchdog/of-xilinx-wdt.txt deleted file mode 100644 index c6ae9c9d5e..0000000000 --- a/dts/Bindings/watchdog/of-xilinx-wdt.txt +++ /dev/null @@ -1,26 +0,0 @@ -Xilinx AXI/PLB soft-core watchdog Device Tree Bindings ---------------------------------------------------------- - -Required properties: -- compatible : Should be "xlnx,xps-timebase-wdt-1.00.a" or - "xlnx,xps-timebase-wdt-1.01.a". -- reg : Physical base address and size - -Optional properties: -- clocks : Input clock specifier. Refer to common clock - bindings. -- clock-frequency : Frequency of clock in Hz -- xlnx,wdt-enable-once : 0 - Watchdog can be restarted - 1 - Watchdog can be enabled just once -- xlnx,wdt-interval : Watchdog timeout interval in 2^<val> clock cycles, - <val> is integer from 8 to 31. - -Example: -axi-timebase-wdt@40100000 { - clock-frequency = <50000000>; - compatible = "xlnx,xps-timebase-wdt-1.00.a"; - clocks = <&clkc 15>; - reg = <0x40100000 0x10000>; - xlnx,wdt-enable-once = <0x0>; - xlnx,wdt-interval = <0x1b>; -} ; diff --git a/dts/Bindings/watchdog/renesas,wdt.yaml b/dts/Bindings/watchdog/renesas,wdt.yaml index a8d7dde527..26b1815a67 100644 --- a/dts/Bindings/watchdog/renesas,wdt.yaml +++ b/dts/Bindings/watchdog/renesas,wdt.yaml @@ -33,6 +33,11 @@ properties: - items: - enum: + - renesas,r9a09g011-wdt # RZ/V2M + - const: renesas,rzv2m-wdt # RZ/V2M + + - items: + - enum: - renesas,r8a7742-wdt # RZ/G1H - renesas,r8a7743-wdt # RZ/G1M - renesas,r8a7744-wdt # RZ/G1N @@ -65,18 +70,35 @@ properties: - enum: - renesas,r8a779a0-wdt # R-Car V3U - renesas,r8a779f0-wdt # R-Car S4-8 + - renesas,r8a779g0-wdt # R-Car V4H - const: renesas,rcar-gen4-wdt # R-Car Gen4 reg: maxItems: 1 - interrupts: true - - interrupt-names: true - - clocks: true - - clock-names: true + interrupts: + minItems: 1 + items: + - description: Timeout + - description: Parity error + + interrupt-names: + minItems: 1 + items: + - const: wdt + - const: perrout + + clocks: + minItems: 1 + items: + - description: Register access clock + - description: Main clock + + clock-names: + minItems: 1 + items: + - const: pclk + - const: oscclk power-domains: maxItems: 1 @@ -89,6 +111,7 @@ properties: required: - compatible - reg + - interrupts - clocks allOf: @@ -113,31 +136,38 @@ allOf: contains: enum: - renesas,rzg2l-wdt + - renesas,rzv2m-wdt then: properties: - interrupts: - maxItems: 2 - interrupt-names: - items: - - const: wdt - - const: perrout clocks: - items: - - description: Register access clock - - description: Main clock + minItems: 2 clock-names: - items: - - const: pclk - - const: oscclk + minItems: 2 required: - clock-names + else: + properties: + clocks: + maxItems: 1 + + - if: + properties: + compatible: + contains: + enum: + - renesas,rzg2l-wdt + then: + properties: + interrupts: + minItems: 2 + interrupt-names: + minItems: 2 + required: - interrupt-names else: properties: interrupts: maxItems: 1 - clocks: - maxItems: 1 additionalProperties: false @@ -145,9 +175,11 @@ examples: - | #include <dt-bindings/clock/r8a7795-cpg-mssr.h> #include <dt-bindings/power/r8a7795-sysc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> wdt0: watchdog@e6020000 { compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; reg = <0xe6020000 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/dts/Bindings/watchdog/samsung-wdt.yaml b/dts/Bindings/watchdog/samsung-wdt.yaml index b08373336b..8fb6656ba0 100644 --- a/dts/Bindings/watchdog/samsung-wdt.yaml +++ b/dts/Bindings/watchdog/samsung-wdt.yaml @@ -23,6 +23,7 @@ properties: - samsung,exynos5420-wdt # for Exynos5420 - samsung,exynos7-wdt # for Exynos7 - samsung,exynos850-wdt # for Exynos850 + - samsung,exynosautov9-wdt # for Exynosautov9 reg: maxItems: 1 @@ -67,6 +68,7 @@ allOf: - samsung,exynos5420-wdt - samsung,exynos7-wdt - samsung,exynos850-wdt + - samsung,exynosautov9-wdt then: required: - samsung,syscon-phandle @@ -76,6 +78,7 @@ allOf: contains: enum: - samsung,exynos850-wdt + - samsung,exynosautov9-wdt then: properties: clocks: diff --git a/dts/Bindings/watchdog/snps,dw-wdt.yaml b/dts/Bindings/watchdog/snps,dw-wdt.yaml index 6461eb4f4a..92df6e453f 100644 --- a/dts/Bindings/watchdog/snps,dw-wdt.yaml +++ b/dts/Bindings/watchdog/snps,dw-wdt.yaml @@ -20,6 +20,7 @@ properties: - enum: - rockchip,px30-wdt - rockchip,rk3066-wdt + - rockchip,rk3128-wdt - rockchip,rk3188-wdt - rockchip,rk3228-wdt - rockchip,rk3288-wdt diff --git a/dts/Bindings/watchdog/toshiba,visconti-wdt.yaml b/dts/Bindings/watchdog/toshiba,visconti-wdt.yaml index 690e19ce4b..eba083822d 100644 --- a/dts/Bindings/watchdog/toshiba,visconti-wdt.yaml +++ b/dts/Bindings/watchdog/toshiba,visconti-wdt.yaml @@ -35,20 +35,16 @@ additionalProperties: false examples: - | + #include <dt-bindings/clock/toshiba,tmpv770x.h> + soc { #address-cells = <2>; #size-cells = <2>; - wdt_clk: wdt-clk { - compatible = "fixed-clock"; - clock-frequency = <150000000>; - #clock-cells = <0>; - }; - - watchdog@28330000 { + wdt: watchdog@28330000 { compatible = "toshiba,visconti-wdt"; reg = <0 0x28330000 0 0x1000>; - clocks = <&wdt_clk>; timeout-sec = <20>; + clocks = <&pismu TMPV770X_CLK_WDTCLK>; }; }; diff --git a/dts/Bindings/watchdog/xlnx,xps-timebase-wdt.yaml b/dts/Bindings/watchdog/xlnx,xps-timebase-wdt.yaml new file mode 100644 index 0000000000..493a1c9547 --- /dev/null +++ b/dts/Bindings/watchdog/xlnx,xps-timebase-wdt.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/xlnx,xps-timebase-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx AXI/PLB softcore and window Watchdog Timer + +maintainers: + - Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> + - Srinivas Neeli <srinivas.neeli@xilinx.com> + +description: + The Timebase watchdog timer(WDT) is a free-running 32 bit counter. + WDT uses a dual-expiration architecture. After one expiration of + the timeout interval, an interrupt is generated and the WDT state + bit is set to one in the status register. If the state bit is not + cleared (by writing a one to the state bit) before the next + expiration of the timeout interval, a WDT reset is generated. + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + enum: + - xlnx,xps-timebase-wdt-1.01.a + - xlnx,xps-timebase-wdt-1.00.a + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: + description: Frequency of clock in Hz + + xlnx,wdt-interval: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Watchdog timeout interval + minimum: 8 + maximum: 32 + + xlnx,wdt-enable-once: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: If watchdog is configured as enable once, + then the watchdog cannot be disabled after + it has been enabled. + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + watchdog@40100000 { + compatible = "xlnx,xps-timebase-wdt-1.00.a"; + reg = <0x40100000 0x1000>; + clock-frequency = <50000000>; + clocks = <&clkc 15>; + xlnx,wdt-enable-once = <0x0>; + xlnx,wdt-interval = <0x1b>; + }; +... |