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-rw-r--r--dts/Bindings/i2c/i2c-iop3xx.txt (renamed from dts/Bindings/i2c/i2c-xscale.txt)0
-rw-r--r--dts/Bindings/i2c/i2c-mt65xx.txt (renamed from dts/Bindings/i2c/i2c-mtk.txt)0
-rw-r--r--dts/Bindings/i2c/i2c-stu300.txt (renamed from dts/Bindings/i2c/i2c-st-ddci2c.txt)0
-rw-r--r--dts/Bindings/i2c/i2c-sun6i-p2wi.txt (renamed from dts/Bindings/i2c/i2c-sunxi-p2wi.txt)0
-rw-r--r--dts/Bindings/i2c/i2c-wmt.txt (renamed from dts/Bindings/i2c/i2c-vt8500.txt)0
-rw-r--r--dts/Bindings/net/dsa/qca8k.txt73
-rw-r--r--dts/Bindings/serial/mtk-uart.txt1
7 files changed, 67 insertions, 7 deletions
diff --git a/dts/Bindings/i2c/i2c-xscale.txt b/dts/Bindings/i2c/i2c-iop3xx.txt
index dcc8390..dcc8390 100644
--- a/dts/Bindings/i2c/i2c-xscale.txt
+++ b/dts/Bindings/i2c/i2c-iop3xx.txt
diff --git a/dts/Bindings/i2c/i2c-mtk.txt b/dts/Bindings/i2c/i2c-mt65xx.txt
index ee4c324..ee4c324 100644
--- a/dts/Bindings/i2c/i2c-mtk.txt
+++ b/dts/Bindings/i2c/i2c-mt65xx.txt
diff --git a/dts/Bindings/i2c/i2c-st-ddci2c.txt b/dts/Bindings/i2c/i2c-stu300.txt
index bd81a48..bd81a48 100644
--- a/dts/Bindings/i2c/i2c-st-ddci2c.txt
+++ b/dts/Bindings/i2c/i2c-stu300.txt
diff --git a/dts/Bindings/i2c/i2c-sunxi-p2wi.txt b/dts/Bindings/i2c/i2c-sun6i-p2wi.txt
index 49df005..49df005 100644
--- a/dts/Bindings/i2c/i2c-sunxi-p2wi.txt
+++ b/dts/Bindings/i2c/i2c-sun6i-p2wi.txt
diff --git a/dts/Bindings/i2c/i2c-vt8500.txt b/dts/Bindings/i2c/i2c-wmt.txt
index 94a425e..94a425e 100644
--- a/dts/Bindings/i2c/i2c-vt8500.txt
+++ b/dts/Bindings/i2c/i2c-wmt.txt
diff --git a/dts/Bindings/net/dsa/qca8k.txt b/dts/Bindings/net/dsa/qca8k.txt
index bbcb255..93a7469 100644
--- a/dts/Bindings/net/dsa/qca8k.txt
+++ b/dts/Bindings/net/dsa/qca8k.txt
@@ -12,10 +12,15 @@ Required properties:
Subnodes:
The integrated switch subnode should be specified according to the binding
-described in dsa/dsa.txt. As the QCA8K switches do not have a N:N mapping of
-port and PHY id, each subnode describing a port needs to have a valid phandle
-referencing the internal PHY connected to it. The CPU port of this switch is
-always port 0.
+described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external
+mdio-bus each subnode describing a port needs to have a valid phandle
+referencing the internal PHY it is connected to. This is because there's no
+N:N mapping of port and PHY id.
+
+Don't use mixed external and internal mdio-bus configurations, as this is
+not supported by the hardware.
+
+The CPU port of this switch is always port 0.
A CPU port node has the following optional node:
@@ -31,8 +36,9 @@ For QCA8K the 'fixed-link' sub-node supports only the following properties:
- 'full-duplex' (boolean, optional), to indicate that full duplex is
used. When absent, half duplex is assumed.
-Example:
+Examples:
+for the external mdio-bus configuration:
&mdio0 {
phy_port1: phy@0 {
@@ -55,12 +61,12 @@ Example:
reg = <4>;
};
- switch0@0 {
+ switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
- reg = <0>;
+ reg = <0x10>;
ports {
#address-cells = <1>;
@@ -108,3 +114,56 @@ Example:
};
};
};
+
+for the internal master mdio-bus configuration:
+
+ &mdio0 {
+ switch@10 {
+ compatible = "qca,qca8337";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0x10>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "cpu";
+ ethernet = <&gmac1>;
+ phy-mode = "rgmii";
+ fixed-link {
+ speed = 1000;
+ full-duplex;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan1";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan3";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan4";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "wan";
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/serial/mtk-uart.txt b/dts/Bindings/serial/mtk-uart.txt
index 742cb47..bcfb131 100644
--- a/dts/Bindings/serial/mtk-uart.txt
+++ b/dts/Bindings/serial/mtk-uart.txt
@@ -16,6 +16,7 @@ Required properties:
* "mediatek,mt8127-uart" for MT8127 compatible UARTS
* "mediatek,mt8135-uart" for MT8135 compatible UARTS
* "mediatek,mt8173-uart" for MT8173 compatible UARTS
+ * "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS
* "mediatek,mt6577-uart" for MT6577 and all of the above
- reg: The base address of the UART register bank.