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-rw-r--r--dts/Bindings/.gitignore1
-rw-r--r--dts/Bindings/Makefile52
-rw-r--r--dts/Bindings/arm/actions.yaml13
-rw-r--r--dts/Bindings/arm/altera.yaml2
-rw-r--r--dts/Bindings/arm/amlogic.yaml2
-rw-r--r--dts/Bindings/arm/atmel-at91.yaml1
-rw-r--r--dts/Bindings/arm/axxia.yaml2
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm4708.yaml2
-rw-r--r--dts/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml23
-rw-r--r--dts/Bindings/arm/bitmain.yaml2
-rw-r--r--dts/Bindings/arm/coresight-cti.yaml2
-rw-r--r--dts/Bindings/arm/cpus.yaml2
-rw-r--r--dts/Bindings/arm/digicolor.yaml2
-rw-r--r--dts/Bindings/arm/freescale/fsl,imx7ulp-pm.txt23
-rw-r--r--dts/Bindings/arm/freescale/fsl,imx7ulp-pm.yaml42
-rw-r--r--dts/Bindings/arm/freescale/fsl,imx7ulp-sim.txt16
-rw-r--r--dts/Bindings/arm/freescale/fsl,imx7ulp-sim.yaml38
-rw-r--r--dts/Bindings/arm/fsl.yaml95
-rw-r--r--dts/Bindings/arm/hisilicon/controller/cpuctrl.yaml54
-rw-r--r--dts/Bindings/arm/hisilicon/controller/hi3798cv200-perictrl.yaml64
-rw-r--r--dts/Bindings/arm/hisilicon/controller/hi6220-domain-ctrl.yaml68
-rw-r--r--dts/Bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml34
-rw-r--r--dts/Bindings/arm/hisilicon/controller/hip04-fabric.yaml27
-rw-r--r--dts/Bindings/arm/hisilicon/controller/pctrl.yaml34
-rw-r--r--dts/Bindings/arm/hisilicon/controller/sysctrl.yaml132
-rw-r--r--dts/Bindings/arm/hisilicon/hi3519-sysctrl.txt14
-rw-r--r--dts/Bindings/arm/hisilicon/hisilicon-low-pin-count.txt33
-rw-r--r--dts/Bindings/arm/hisilicon/hisilicon.txt319
-rw-r--r--dts/Bindings/arm/hisilicon/hisilicon.yaml67
-rw-r--r--dts/Bindings/arm/hisilicon/low-pin-count.yaml61
-rw-r--r--dts/Bindings/arm/intel-ixp4xx.yaml2
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt1
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,audsys.txt1
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,imgsys.txt1
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,infracfg.txt1
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,mfgcfg.txt1
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,pericfg.yaml2
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,topckgen.txt1
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,vdecsys.txt1
-rw-r--r--dts/Bindings/arm/nvidia,tegra194-ccplex.yaml2
-rw-r--r--dts/Bindings/arm/omap/prm-inst.txt2
-rw-r--r--dts/Bindings/arm/pmu.yaml2
-rw-r--r--dts/Bindings/arm/primecell.yaml3
-rw-r--r--dts/Bindings/arm/qcom.yaml13
-rw-r--r--dts/Bindings/arm/rda.yaml2
-rw-r--r--dts/Bindings/arm/renesas.yaml12
-rw-r--r--dts/Bindings/arm/rockchip.yaml16
-rw-r--r--dts/Bindings/arm/samsung/pmu.yaml27
-rw-r--r--dts/Bindings/arm/samsung/sysreg.yaml45
-rw-r--r--dts/Bindings/arm/stm32/st,mlahb.yaml2
-rw-r--r--dts/Bindings/arm/stm32/stm32.yaml8
-rw-r--r--dts/Bindings/arm/sunxi.yaml10
-rw-r--r--dts/Bindings/arm/tegra.yaml6
-rw-r--r--dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt3
-rw-r--r--dts/Bindings/arm/tegra/nvidia,tegra20-pmc.yaml2
-rw-r--r--dts/Bindings/arm/ti/k3.txt26
-rw-r--r--dts/Bindings/arm/ti/k3.yaml35
-rw-r--r--dts/Bindings/arm/toshiba.yaml22
-rw-r--r--dts/Bindings/ata/faraday,ftide010.yaml2
-rw-r--r--dts/Bindings/ata/imx-sata.txt37
-rw-r--r--dts/Bindings/ata/imx-sata.yaml83
-rw-r--r--dts/Bindings/ata/pata-common.yaml2
-rw-r--r--dts/Bindings/ata/sata-common.yaml2
-rw-r--r--dts/Bindings/bus/brcm,gisb-arb.txt3
-rw-r--r--dts/Bindings/bus/mti,mips-cdmm.yaml2
-rw-r--r--dts/Bindings/bus/renesas,bsc.yaml2
-rw-r--r--dts/Bindings/bus/simple-pm-bus.yaml2
-rw-r--r--dts/Bindings/bus/socionext,uniphier-system-bus.yaml7
-rw-r--r--dts/Bindings/chrome/google,cros-ec-typec.yaml2
-rw-r--r--dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml7
-rw-r--r--dts/Bindings/clock/arm,syscon-icst.yaml2
-rw-r--r--dts/Bindings/clock/baikal,bt1-ccu-div.yaml6
-rw-r--r--dts/Bindings/clock/baikal,bt1-ccu-pll.yaml2
-rw-r--r--dts/Bindings/clock/idt,versaclock5.yaml20
-rw-r--r--dts/Bindings/clock/imx23-clock.yaml4
-rw-r--r--dts/Bindings/clock/imx28-clock.yaml6
-rw-r--r--dts/Bindings/clock/imx6q-clock.yaml2
-rw-r--r--dts/Bindings/clock/imx6sl-clock.yaml2
-rw-r--r--dts/Bindings/clock/imx6sll-clock.yaml2
-rw-r--r--dts/Bindings/clock/imx6sx-clock.yaml2
-rw-r--r--dts/Bindings/clock/imx6ul-clock.yaml2
-rw-r--r--dts/Bindings/clock/imx8m-clock.yaml125
-rw-r--r--dts/Bindings/clock/imx8mm-clock.yaml68
-rw-r--r--dts/Bindings/clock/imx8mn-clock.yaml70
-rw-r--r--dts/Bindings/clock/imx8mp-clock.yaml70
-rw-r--r--dts/Bindings/clock/imx8mq-clock.yaml72
-rw-r--r--dts/Bindings/clock/imx8qxp-lpcg.yaml2
-rw-r--r--dts/Bindings/clock/intel,cgu-lgm.yaml2
-rw-r--r--dts/Bindings/clock/qcom,dispcc-sm8x50.yaml93
-rw-r--r--dts/Bindings/clock/qcom,gcc-sm8250.yaml2
-rw-r--r--dts/Bindings/clock/qcom,sc7180-videocc.yaml65
-rw-r--r--dts/Bindings/clock/qcom,videocc.yaml (renamed from dts/Bindings/clock/qcom,sdm845-videocc.yaml)18
-rw-r--r--dts/Bindings/clock/renesas,cpg-mssr.yaml1
-rw-r--r--dts/Bindings/clock/sifive/fu540-prci.txt46
-rw-r--r--dts/Bindings/clock/sifive/fu540-prci.yaml60
-rw-r--r--dts/Bindings/clock/sprd,sc9863a-clk.yaml2
-rw-r--r--dts/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml2
-rw-r--r--dts/Bindings/connector/samsung,usb-connector-11pin.txt49
-rw-r--r--dts/Bindings/connector/usb-connector.yaml76
-rw-r--r--dts/Bindings/cpufreq/cpufreq-qcom-hw.txt2
-rw-r--r--dts/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml6
-rw-r--r--dts/Bindings/crypto/fsl-dcp.txt18
-rw-r--r--dts/Bindings/crypto/fsl-dcp.yaml51
-rw-r--r--dts/Bindings/crypto/fsl-imx-sahara.txt15
-rw-r--r--dts/Bindings/crypto/fsl-imx-sahara.yaml37
-rw-r--r--dts/Bindings/crypto/fsl-imx-scc.txt21
-rw-r--r--dts/Bindings/crypto/fsl-imx-scc.yaml54
-rw-r--r--dts/Bindings/crypto/samsung-slimsss.yaml2
-rw-r--r--dts/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml11
-rw-r--r--dts/Bindings/display/brcm,bcm2711-hdmi.yaml117
-rw-r--r--dts/Bindings/display/brcm,bcm2835-dsi0.yaml3
-rw-r--r--dts/Bindings/display/brcm,bcm2835-hvs.yaml18
-rw-r--r--dts/Bindings/display/brcm,bcm2835-pixelvalve0.yaml5
-rw-r--r--dts/Bindings/display/brcm,bcm2835-vc4.yaml1
-rw-r--r--dts/Bindings/display/bridge/cdns,mhdp8546.yaml169
-rw-r--r--dts/Bindings/display/bridge/ite,it6505.yaml5
-rw-r--r--dts/Bindings/display/bridge/lontium,lt9611.yaml176
-rw-r--r--dts/Bindings/display/bridge/lvds-codec.yaml6
-rw-r--r--dts/Bindings/display/bridge/nwl-dsi.yaml15
-rw-r--r--dts/Bindings/display/bridge/renesas,dw-hdmi.txt4
-rw-r--r--dts/Bindings/display/bridge/renesas,lvds.yaml2
-rw-r--r--dts/Bindings/display/bridge/snps,dw-mipi-dsi.yaml2
-rw-r--r--dts/Bindings/display/bridge/toshiba,tc358762.yaml127
-rw-r--r--dts/Bindings/display/bridge/toshiba,tc358775.yaml215
-rw-r--r--dts/Bindings/display/dsi-controller.yaml2
-rw-r--r--dts/Bindings/display/imx/nxp,imx8mq-dcss.yaml108
-rw-r--r--dts/Bindings/display/mediatek/mediatek,disp.txt2
-rw-r--r--dts/Bindings/display/mediatek/mediatek,dpi.txt2
-rw-r--r--dts/Bindings/display/mediatek/mediatek,dsi.txt4
-rw-r--r--dts/Bindings/display/mediatek/mediatek,hdmi.txt4
-rw-r--r--dts/Bindings/display/msm/dsi.txt6
-rw-r--r--dts/Bindings/display/msm/gmu.yaml2
-rw-r--r--dts/Bindings/display/panel/ilitek,ili9881c.yaml4
-rw-r--r--dts/Bindings/display/panel/lvds.yaml2
-rw-r--r--dts/Bindings/display/panel/mantix,mlaf057we51-x.yaml70
-rw-r--r--dts/Bindings/display/panel/panel-common.yaml2
-rw-r--r--dts/Bindings/display/panel/panel-simple.yaml8
-rw-r--r--dts/Bindings/display/panel/rocktech,jh057n00900.yaml40
-rw-r--r--dts/Bindings/display/panel/samsung,amoled-mipi-dsi.yaml12
-rw-r--r--dts/Bindings/display/panel/tpo,tpg110.yaml2
-rw-r--r--dts/Bindings/display/renesas,du.txt6
-rw-r--r--dts/Bindings/display/ssd1307fb.txt1
-rw-r--r--dts/Bindings/display/st,stm32-dsi.yaml23
-rw-r--r--dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt92
-rw-r--r--dts/Bindings/display/tilcdc/tilcdc.txt2
-rw-r--r--dts/Bindings/dma/allwinner,sun50i-a64-dma.yaml9
-rw-r--r--dts/Bindings/dma/dma-common.yaml2
-rw-r--r--dts/Bindings/dma/dma-controller.yaml2
-rw-r--r--dts/Bindings/dma/dma-router.yaml2
-rw-r--r--dts/Bindings/dma/ingenic,dma.yaml2
-rw-r--r--dts/Bindings/dma/renesas,rcar-dmac.yaml1
-rw-r--r--dts/Bindings/dma/snps,dma-spear1340.yaml7
-rw-r--r--dts/Bindings/dma/st,stm32-dma.yaml2
-rw-r--r--dts/Bindings/dma/st,stm32-dmamux.yaml2
-rw-r--r--dts/Bindings/dma/st,stm32-mdma.yaml2
-rw-r--r--dts/Bindings/dma/ti/k3-udma.yaml2
-rw-r--r--dts/Bindings/edac/amazon,al-mc-edac.yaml67
-rw-r--r--dts/Bindings/edac/dmc-520.yaml2
-rw-r--r--dts/Bindings/eeprom/at24.yaml3
-rw-r--r--dts/Bindings/eeprom/at25.txt45
-rw-r--r--dts/Bindings/eeprom/at25.yaml129
-rw-r--r--dts/Bindings/example-schema.yaml33
-rw-r--r--dts/Bindings/extcon/extcon-ptn5150.txt27
-rw-r--r--dts/Bindings/extcon/extcon-ptn5150.yaml60
-rw-r--r--dts/Bindings/extcon/wlf,arizona.yaml2
-rw-r--r--dts/Bindings/fsi/fsi-master-aspeed.txt12
-rw-r--r--dts/Bindings/fsi/ibm,fsi2spi.yaml3
-rw-r--r--dts/Bindings/fuse/nvidia,tegra20-fuse.txt1
-rw-r--r--dts/Bindings/gpio/fsl-imx-gpio.yaml55
-rw-r--r--dts/Bindings/gpio/gpio-max732x.txt58
-rw-r--r--dts/Bindings/gpio/gpio-pca953x.txt90
-rw-r--r--dts/Bindings/gpio/gpio-pca95xx.yaml232
-rw-r--r--dts/Bindings/gpio/gpio-vf610.txt63
-rw-r--r--dts/Bindings/gpio/gpio-vf610.yaml83
-rw-r--r--dts/Bindings/gpio/kontron,sl28cpld-gpio.yaml54
-rw-r--r--dts/Bindings/gpio/pl061-gpio.yaml3
-rw-r--r--dts/Bindings/gpio/renesas,rcar-gpio.yaml1
-rw-r--r--dts/Bindings/gpio/snps,dw-apb-gpio.yaml6
-rw-r--r--dts/Bindings/gpio/socionext,uniphier-gpio.yaml2
-rw-r--r--dts/Bindings/gpu/arm,mali-midgard.yaml1
-rw-r--r--dts/Bindings/gpu/arm,mali-utgard.yaml6
-rw-r--r--dts/Bindings/gpu/samsung-rotator.yaml6
-rw-r--r--dts/Bindings/gpu/vivante,gc.yaml9
-rw-r--r--dts/Bindings/hwlock/omap-hwspinlock.txt41
-rw-r--r--dts/Bindings/hwlock/ti,omap-hwspinlock.yaml76
-rw-r--r--dts/Bindings/hwmon/adi,adm1266.yaml51
-rw-r--r--dts/Bindings/hwmon/adi,axi-fan-control.yaml2
-rw-r--r--dts/Bindings/hwmon/adt7475.yaml2
-rw-r--r--dts/Bindings/hwmon/baikal,bt1-pvt.yaml4
-rw-r--r--dts/Bindings/hwmon/kontron,sl28cpld-hwmon.yaml27
-rw-r--r--dts/Bindings/hwmon/lm75.txt39
-rw-r--r--dts/Bindings/hwmon/lm75.yaml66
-rw-r--r--dts/Bindings/hwmon/maxim,max20730.yaml65
-rw-r--r--dts/Bindings/hwmon/moortec,mr75203.yaml71
-rw-r--r--dts/Bindings/hwmon/sensirion,shtc1.yaml61
-rw-r--r--dts/Bindings/i2c/amlogic,meson6-i2c.yaml2
-rw-r--r--dts/Bindings/i2c/cdns,i2c-r1p10.yaml2
-rw-r--r--dts/Bindings/i2c/i2c-gpio.yaml2
-rw-r--r--dts/Bindings/i2c/i2c-imx-lpi2c.yaml29
-rw-r--r--dts/Bindings/i2c/i2c-imx.yaml8
-rw-r--r--dts/Bindings/i2c/i2c-rk3x.yaml2
-rw-r--r--dts/Bindings/i2c/i2c.txt5
-rw-r--r--dts/Bindings/i2c/ingenic,i2c.yaml12
-rw-r--r--dts/Bindings/i2c/mellanox,i2c-mlxbf.txt42
-rw-r--r--dts/Bindings/i2c/socionext,uniphier-fi2c.yaml2
-rw-r--r--dts/Bindings/i2c/socionext,uniphier-i2c.yaml2
-rw-r--r--dts/Bindings/i2c/st,stm32-i2c.yaml2
-rw-r--r--dts/Bindings/i2c/xlnx,xps-iic-2.00.a.yaml2
-rw-r--r--dts/Bindings/iio/accel/adi,adis16240.yaml4
-rw-r--r--dts/Bindings/iio/accel/adi,adxl345.yaml4
-rw-r--r--dts/Bindings/iio/accel/adi,adxl372.yaml4
-rw-r--r--dts/Bindings/iio/accel/kionix,kxsd9.yaml4
-rw-r--r--dts/Bindings/iio/adc/ad7949.txt16
-rw-r--r--dts/Bindings/iio/adc/adi,ad7124.yaml4
-rw-r--r--dts/Bindings/iio/adc/adi,ad7192.yaml4
-rw-r--r--dts/Bindings/iio/adc/adi,ad7291.yaml46
-rw-r--r--dts/Bindings/iio/adc/adi,ad7292.yaml4
-rw-r--r--dts/Bindings/iio/adc/adi,ad7606.yaml6
-rw-r--r--dts/Bindings/iio/adc/adi,ad7768-1.txt41
-rw-r--r--dts/Bindings/iio/adc/adi,ad7768-1.yaml89
-rw-r--r--dts/Bindings/iio/adc/adi,ad7923.yaml4
-rw-r--r--dts/Bindings/iio/adc/adi,ad7949.yaml57
-rw-r--r--dts/Bindings/iio/adc/adi,ad9467.yaml15
-rw-r--r--dts/Bindings/iio/adc/ads1015.txt73
-rw-r--r--dts/Bindings/iio/adc/amlogic,meson-saradc.txt48
-rw-r--r--dts/Bindings/iio/adc/amlogic,meson-saradc.yaml149
-rw-r--r--dts/Bindings/iio/adc/aspeed,ast2400-adc.yaml55
-rw-r--r--dts/Bindings/iio/adc/aspeed_adc.txt22
-rw-r--r--dts/Bindings/iio/adc/berlin2_adc.txt19
-rw-r--r--dts/Bindings/iio/adc/cc10001_adc.txt22
-rw-r--r--dts/Bindings/iio/adc/cosmic,10001-adc.yaml59
-rw-r--r--dts/Bindings/iio/adc/cpcap-adc.txt17
-rw-r--r--dts/Bindings/iio/adc/da9150-gpadc.txt16
-rw-r--r--dts/Bindings/iio/adc/dlg,da9150-gpadc.yaml35
-rw-r--r--dts/Bindings/iio/adc/fsl,imx25-gcq.txt57
-rw-r--r--dts/Bindings/iio/adc/fsl,imx25-gcq.yaml131
-rw-r--r--dts/Bindings/iio/adc/fsl,imx7d-adc.yaml62
-rw-r--r--dts/Bindings/iio/adc/fsl,vf610-adc.yaml81
-rw-r--r--dts/Bindings/iio/adc/hi8435.txt21
-rw-r--r--dts/Bindings/iio/adc/holt,hi8435.yaml50
-rw-r--r--dts/Bindings/iio/adc/imx7d-adc.txt24
-rw-r--r--dts/Bindings/iio/adc/lltc,ltc2497.yaml44
-rw-r--r--dts/Bindings/iio/adc/lpc1850-adc.txt20
-rw-r--r--dts/Bindings/iio/adc/lpc32xx-adc.txt21
-rw-r--r--dts/Bindings/iio/adc/ltc2497.txt13
-rw-r--r--dts/Bindings/iio/adc/marvell,berlin2-adc.yaml50
-rw-r--r--dts/Bindings/iio/adc/max11100.txt18
-rw-r--r--dts/Bindings/iio/adc/max1118.txt21
-rw-r--r--dts/Bindings/iio/adc/max9611.txt27
-rw-r--r--dts/Bindings/iio/adc/maxim,max11100.yaml49
-rw-r--r--dts/Bindings/iio/adc/maxim,max1118.yaml62
-rw-r--r--dts/Bindings/iio/adc/maxim,max1238.yaml2
-rw-r--r--dts/Bindings/iio/adc/maxim,max1241.yaml4
-rw-r--r--dts/Bindings/iio/adc/maxim,max1363.yaml2
-rw-r--r--dts/Bindings/iio/adc/maxim,max9611.yaml51
-rw-r--r--dts/Bindings/iio/adc/mcp320x.txt57
-rw-r--r--dts/Bindings/iio/adc/mcp3422.txt19
-rw-r--r--dts/Bindings/iio/adc/microchip,mcp3201.yaml77
-rw-r--r--dts/Bindings/iio/adc/motorola,cpcap-adc.yaml53
-rw-r--r--dts/Bindings/iio/adc/nuvoton,nau7802.yaml50
-rw-r--r--dts/Bindings/iio/adc/nuvoton,npcm-adc.txt26
-rw-r--r--dts/Bindings/iio/adc/nuvoton,npcm750-adc.yaml64
-rw-r--r--dts/Bindings/iio/adc/nuvoton-nau7802.txt18
-rw-r--r--dts/Bindings/iio/adc/nxp,lpc1850-adc.yaml61
-rw-r--r--dts/Bindings/iio/adc/nxp,lpc3220-adc.yaml50
-rw-r--r--dts/Bindings/iio/adc/qcom,spmi-vadc.yaml4
-rw-r--r--dts/Bindings/iio/adc/samsung,exynos-adc.yaml20
-rw-r--r--dts/Bindings/iio/adc/sprd,sc2720-adc.yaml72
-rw-r--r--dts/Bindings/iio/adc/sprd,sc27xx-adc.txt40
-rw-r--r--dts/Bindings/iio/adc/st,stmpe-adc.yaml45
-rw-r--r--dts/Bindings/iio/adc/stmpe-adc.txt21
-rw-r--r--dts/Bindings/iio/adc/ti,adc0832.yaml56
-rw-r--r--dts/Bindings/iio/adc/ti,adc108s102.yaml47
-rw-r--r--dts/Bindings/iio/adc/ti,adc12138.yaml86
-rw-r--r--dts/Bindings/iio/adc/ti,adc128s052.yaml59
-rw-r--r--dts/Bindings/iio/adc/ti,adc161s626.yaml51
-rw-r--r--dts/Bindings/iio/adc/ti,ads1015.yaml112
-rw-r--r--dts/Bindings/iio/adc/ti,ads7950.yaml65
-rw-r--r--dts/Bindings/iio/adc/ti,ads8344.yaml51
-rw-r--r--dts/Bindings/iio/adc/ti,ads8688.yaml4
-rw-r--r--dts/Bindings/iio/adc/ti,tlc4541.yaml52
-rw-r--r--dts/Bindings/iio/adc/ti,twl4030-madc.yaml48
-rw-r--r--dts/Bindings/iio/adc/ti-adc0832.txt19
-rw-r--r--dts/Bindings/iio/adc/ti-adc108s102.txt18
-rw-r--r--dts/Bindings/iio/adc/ti-adc12138.txt37
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-rw-r--r--dts/Bindings/power/supply/summit,smb347-charger.yaml152
-rw-r--r--dts/Bindings/powerpc/sleep.yaml47
-rw-r--r--dts/Bindings/ptp/ptp-qoriq.txt2
-rw-r--r--dts/Bindings/pwm/google,cros-ec-pwm.yaml2
-rw-r--r--dts/Bindings/pwm/imx-pwm.yaml25
-rw-r--r--dts/Bindings/pwm/kontron,sl28cpld-pwm.yaml35
-rw-r--r--dts/Bindings/pwm/pwm-sifive.txt33
-rw-r--r--dts/Bindings/pwm/pwm-sifive.yaml69
-rw-r--r--dts/Bindings/pwm/pwm.yaml2
-rw-r--r--dts/Bindings/pwm/renesas,pwm-rcar.yaml2
-rw-r--r--dts/Bindings/pwm/renesas,tpu-pwm.yaml1
-rw-r--r--dts/Bindings/regulator/fixed-regulator.yaml2
-rw-r--r--dts/Bindings/regulator/google,cros-ec-regulator.yaml2
-rw-r--r--dts/Bindings/regulator/gpio-regulator.yaml2
-rw-r--r--dts/Bindings/regulator/mp886x.txt27
-rw-r--r--dts/Bindings/regulator/mps,mp886x.yaml61
-rw-r--r--dts/Bindings/regulator/mt6360-regulator.yaml113
-rw-r--r--dts/Bindings/regulator/pfuze100.txt394
-rw-r--r--dts/Bindings/regulator/pfuze100.yaml186
-rw-r--r--dts/Bindings/regulator/qcom,smd-rpm-regulator.yaml12
-rw-r--r--dts/Bindings/regulator/qcom,spmi-regulator.txt31
-rw-r--r--dts/Bindings/regulator/qcom-labibb-regulator.yaml2
-rw-r--r--dts/Bindings/regulator/raspberrypi,7inch-touchscreen-panel-regulator.yaml44
-rw-r--r--dts/Bindings/regulator/regulator.yaml2
-rw-r--r--dts/Bindings/regulator/richtek,rt4801-regulator.yaml79
-rw-r--r--dts/Bindings/regulator/richtek,rtmv20-regulator.yaml159
-rw-r--r--dts/Bindings/regulator/rohm,bd71837-regulator.yaml11
-rw-r--r--dts/Bindings/regulator/rohm,bd71847-regulator.yaml11
-rw-r--r--dts/Bindings/regulator/rohm,bd9576-regulator.yaml34
-rw-r--r--dts/Bindings/regulator/silergy,sy8824x.yaml45
-rw-r--r--dts/Bindings/regulator/silergy,sy8827n.yaml2
-rw-r--r--dts/Bindings/regulator/st,stm32-booster.yaml2
-rw-r--r--dts/Bindings/regulator/st,stm32-vrefbuf.yaml2
-rw-r--r--dts/Bindings/regulator/sy8824x.txt24
-rw-r--r--dts/Bindings/regulator/vqmmc-ipq4019-regulator.yaml2
-rw-r--r--dts/Bindings/regulator/wlf,arizona.yaml2
-rw-r--r--dts/Bindings/remoteproc/qcom,pil-info.yaml2
-rw-r--r--dts/Bindings/remoteproc/ti,k3-r5f-rproc.yaml281
-rw-r--r--dts/Bindings/reserved-memory/reserved-memory.txt3
-rw-r--r--dts/Bindings/reset/fsl,imx7-src.yaml19
-rw-r--r--dts/Bindings/reset/nuvoton,npcm-reset.txt2
-rw-r--r--dts/Bindings/reset/renesas,rst.yaml1
-rw-r--r--dts/Bindings/reset/xlnx,zynqmp-reset.txt11
-rw-r--r--dts/Bindings/riscv/cpus.yaml2
-rw-r--r--dts/Bindings/riscv/sifive-l2-cache.txt51
-rw-r--r--dts/Bindings/riscv/sifive-l2-cache.yaml98
-rw-r--r--dts/Bindings/rng/imx-rng.txt23
-rw-r--r--dts/Bindings/rng/imx-rng.yaml52
-rw-r--r--dts/Bindings/rng/ingenic,trng.yaml43
-rw-r--r--dts/Bindings/rng/xiphera,xip8001b-trng.yaml33
-rw-r--r--dts/Bindings/rtc/ingenic,rtc.yaml2
-rw-r--r--dts/Bindings/rtc/microcrystal,rv3032.yaml64
-rw-r--r--dts/Bindings/rtc/rtc-ds1307.txt9
-rw-r--r--dts/Bindings/rtc/rtc.yaml18
-rw-r--r--dts/Bindings/rtc/s3c-rtc.yaml2
-rw-r--r--dts/Bindings/serial/fsl-imx-uart.txt40
-rw-r--r--dts/Bindings/serial/fsl-imx-uart.yaml100
-rw-r--r--dts/Bindings/serial/fsl-lpuart.txt43
-rw-r--r--dts/Bindings/serial/fsl-lpuart.yaml82
-rw-r--r--dts/Bindings/serial/fsl-mxs-auart.txt53
-rw-r--r--dts/Bindings/serial/fsl-mxs-auart.yaml91
-rw-r--r--dts/Bindings/serial/ingenic,uart.yaml5
-rw-r--r--dts/Bindings/serial/mtk-uart.txt1
-rw-r--r--dts/Bindings/serial/renesas,hscif.yaml3
-rw-r--r--dts/Bindings/serial/renesas,sci.yaml2
-rw-r--r--dts/Bindings/serial/renesas,scif.yaml3
-rw-r--r--dts/Bindings/serial/renesas,scifa.yaml2
-rw-r--r--dts/Bindings/serial/renesas,scifb.yaml2
-rw-r--r--dts/Bindings/serial/rs485.yaml3
-rw-r--r--dts/Bindings/serial/samsung_uart.yaml2
-rw-r--r--dts/Bindings/serial/serial.yaml2
-rw-r--r--dts/Bindings/serial/snps-dw-apb-uart.yaml2
-rw-r--r--dts/Bindings/serial/socionext,uniphier-uart.yaml2
-rw-r--r--dts/Bindings/serial/sprd-uart.yaml2
-rw-r--r--dts/Bindings/soc/imx/fsl,aips-bus.yaml2
-rw-r--r--dts/Bindings/soc/qcom/qcom,geni-se.yaml1
-rw-r--r--dts/Bindings/soc/qcom/qcom,smd-rpm.yaml2
-rw-r--r--dts/Bindings/soc/ti/k3-ringacc.yaml6
-rw-r--r--dts/Bindings/soc/ti/ti,pruss.yaml439
-rw-r--r--dts/Bindings/sound/ak4458.txt5
-rw-r--r--dts/Bindings/sound/ak5558.txt2
-rw-r--r--dts/Bindings/sound/allwinner,sun8i-a33-codec.yaml6
-rw-r--r--dts/Bindings/sound/amlogic,aiu.yaml2
-rw-r--r--dts/Bindings/sound/amlogic,g12a-toacodec.yaml2
-rw-r--r--dts/Bindings/sound/amlogic,gx-sound-card.yaml2
-rw-r--r--dts/Bindings/sound/amlogic,t9015.yaml2
-rw-r--r--dts/Bindings/sound/cirrus,cs4234.yaml74
-rw-r--r--dts/Bindings/sound/cirrus,cs42l51.yaml2
-rw-r--r--dts/Bindings/sound/cirrus,madera.yaml2
-rw-r--r--dts/Bindings/sound/fsl,easrc.yaml2
-rw-r--r--dts/Bindings/sound/fsl,spdif.txt68
-rw-r--r--dts/Bindings/sound/fsl,spdif.yaml110
-rw-r--r--dts/Bindings/sound/fsl-asoc-card.txt2
-rw-r--r--dts/Bindings/sound/google,cros-ec-codec.yaml2
-rw-r--r--dts/Bindings/sound/hdmi.txt16
-rw-r--r--dts/Bindings/sound/intel,keembay-i2s.yaml3
-rw-r--r--dts/Bindings/sound/max98090.txt2
-rw-r--r--dts/Bindings/sound/mchp,spdifrx.yaml73
-rw-r--r--dts/Bindings/sound/mchp,spdiftx.yaml75
-rw-r--r--dts/Bindings/sound/mt6359.yaml61
-rw-r--r--dts/Bindings/sound/mt8183-da7219-max98357.txt1
-rw-r--r--dts/Bindings/sound/nvidia,tegra186-dspk.yaml2
-rw-r--r--dts/Bindings/sound/nvidia,tegra210-admaif.yaml2
-rw-r--r--dts/Bindings/sound/nvidia,tegra210-ahub.yaml3
-rw-r--r--dts/Bindings/sound/nvidia,tegra210-dmic.yaml2
-rw-r--r--dts/Bindings/sound/nvidia,tegra210-i2s.yaml2
-rw-r--r--dts/Bindings/sound/qcom,apq8016-sbc.txt7
-rw-r--r--dts/Bindings/sound/qcom,apq8096.txt8
-rw-r--r--dts/Bindings/sound/qcom,lpass-cpu.txt79
-rw-r--r--dts/Bindings/sound/qcom,lpass-cpu.yaml219
-rw-r--r--dts/Bindings/sound/qcom,q6afe.txt23
-rw-r--r--dts/Bindings/sound/qcom,sdm845.txt8
-rw-r--r--dts/Bindings/sound/realtek,rt1015p.yaml36
-rw-r--r--dts/Bindings/sound/rockchip,rk3328-codec.yaml2
-rw-r--r--dts/Bindings/sound/rockchip-spdif.yaml1
-rw-r--r--dts/Bindings/sound/rt5640.txt2
-rw-r--r--dts/Bindings/sound/rt5659.txt2
-rw-r--r--dts/Bindings/sound/rt5665.txt2
-rw-r--r--dts/Bindings/sound/rt5668.txt2
-rw-r--r--dts/Bindings/sound/rt5677.txt2
-rw-r--r--dts/Bindings/sound/rt5682.txt2
-rw-r--r--dts/Bindings/sound/samsung,aries-wm8994.yaml11
-rw-r--r--dts/Bindings/sound/samsung,midas-audio.yaml6
-rw-r--r--dts/Bindings/sound/samsung,odroid.yaml5
-rw-r--r--dts/Bindings/sound/samsung-i2s.yaml15
-rw-r--r--dts/Bindings/sound/sgtl5000.yaml4
-rw-r--r--dts/Bindings/sound/tas2562.txt37
-rw-r--r--dts/Bindings/sound/tas2562.yaml8
-rw-r--r--dts/Bindings/sound/tas2764.yaml76
-rw-r--r--dts/Bindings/sound/tas2770.yaml11
-rw-r--r--dts/Bindings/sound/ti,j721e-cpb-audio.yaml92
-rw-r--r--dts/Bindings/sound/tlv320adcx140.yaml52
-rw-r--r--dts/Bindings/sound/wlf,arizona.yaml2
-rw-r--r--dts/Bindings/soundwire/qcom,sdw.txt1
-rw-r--r--dts/Bindings/soundwire/soundwire-controller.yaml2
-rw-r--r--dts/Bindings/spi/amlogic,meson-gx-spicc.yaml2
-rw-r--r--dts/Bindings/spi/amlogic,meson6-spifc.yaml2
-rw-r--r--dts/Bindings/spi/brcm,spi-bcm-qspi.txt2
-rw-r--r--dts/Bindings/spi/mediatek,spi-mtk-nor.yaml86
-rw-r--r--dts/Bindings/spi/mikrotik,rb4xx-spi.yaml2
-rw-r--r--dts/Bindings/spi/qca,ar934x-spi.yaml2
-rw-r--r--dts/Bindings/spi/qcom,spi-qcom-qspi.yaml2
-rw-r--r--dts/Bindings/spi/renesas,hspi.yaml2
-rw-r--r--dts/Bindings/spi/renesas,rspi.yaml3
-rw-r--r--dts/Bindings/spi/renesas,sh-msiof.yaml3
-rw-r--r--dts/Bindings/spi/snps,dw-apb-ssi.yaml54
-rw-r--r--dts/Bindings/spi/socionext,uniphier-spi.yaml2
-rw-r--r--dts/Bindings/spi/spi-controller.yaml22
-rw-r--r--dts/Bindings/spi/spi-gpio.yaml2
-rw-r--r--dts/Bindings/spi/spi-mtk-nor.txt47
-rw-r--r--dts/Bindings/spi/spi-mux.yaml2
-rw-r--r--dts/Bindings/spi/spi-pl022.yaml2
-rw-r--r--dts/Bindings/spi/spi-rockchip.yaml2
-rw-r--r--dts/Bindings/spi/spi-sifive.yaml2
-rw-r--r--dts/Bindings/spi/st,stm32-qspi.yaml2
-rw-r--r--dts/Bindings/spi/st,stm32-spi.yaml2
-rw-r--r--dts/Bindings/spmi/qcom,spmi-pmic-arb.txt4
-rw-r--r--dts/Bindings/spmi/spmi.txt41
-rw-r--r--dts/Bindings/spmi/spmi.yaml77
-rw-r--r--dts/Bindings/sram/allwinner,sun4i-a10-system-control.yaml6
-rw-r--r--dts/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml6
-rw-r--r--dts/Bindings/thermal/imx8mm-thermal.yaml10
-rw-r--r--dts/Bindings/thermal/rcar-gen3-thermal.yaml1
-rw-r--r--dts/Bindings/thermal/rcar-thermal.yaml5
-rw-r--r--dts/Bindings/thermal/sprd-thermal.yaml4
-rw-r--r--dts/Bindings/thermal/thermal-cooling-devices.yaml2
-rw-r--r--dts/Bindings/thermal/thermal-idle.yaml2
-rw-r--r--dts/Bindings/thermal/thermal-sensor.yaml2
-rw-r--r--dts/Bindings/thermal/thermal-zones.yaml2
-rw-r--r--dts/Bindings/timer/arm,sp804.txt29
-rw-r--r--dts/Bindings/timer/arm,sp804.yaml97
-rw-r--r--dts/Bindings/timer/cdns,ttc.yaml2
-rw-r--r--dts/Bindings/timer/mediatek,mtk-timer.txt1
-rw-r--r--dts/Bindings/timer/renesas,cmt.yaml4
-rw-r--r--dts/Bindings/timer/samsung,exynos4210-mct.yaml25
-rw-r--r--dts/Bindings/timer/snps,dw-apb-timer.yaml2
-rw-r--r--dts/Bindings/trivial-devices.yaml28
-rw-r--r--dts/Bindings/ufs/ufs-mediatek.txt4
-rw-r--r--dts/Bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml22
-rw-r--r--dts/Bindings/usb/atmel-usb.txt1
-rw-r--r--dts/Bindings/usb/cdns,usb3.yaml96
-rw-r--r--dts/Bindings/usb/cdns-usb3.txt45
-rw-r--r--dts/Bindings/usb/ci-hdrc-usb2.txt9
-rw-r--r--dts/Bindings/usb/dwc2.yaml5
-rw-r--r--dts/Bindings/usb/dwc3.txt3
-rw-r--r--dts/Bindings/usb/intel,keembay-dwc3.yaml77
-rw-r--r--dts/Bindings/usb/mediatek,mt6360-tcpc.yaml95
-rw-r--r--dts/Bindings/usb/nvidia,tegra-xudc.yaml2
-rw-r--r--dts/Bindings/usb/qcom,dwc3.yaml2
-rw-r--r--dts/Bindings/usb/renesas,usb-xhci.yaml1
-rw-r--r--dts/Bindings/usb/renesas,usb3-peri.yaml35
-rw-r--r--dts/Bindings/usb/renesas,usbhs.yaml1
-rw-r--r--dts/Bindings/usb/ti,hd3ss3220.txt38
-rw-r--r--dts/Bindings/usb/ti,hd3ss3220.yaml82
-rw-r--r--dts/Bindings/usb/ti,j721e-usb.yaml18
-rw-r--r--dts/Bindings/usb/ti,tps6598x.yaml2
-rw-r--r--dts/Bindings/usb/usb-hcd.yaml2
-rw-r--r--dts/Bindings/vendor-prefixes.yaml34
-rw-r--r--dts/Bindings/w1/fsl-imx-owire.txt18
-rw-r--r--dts/Bindings/w1/fsl-imx-owire.yaml44
-rw-r--r--dts/Bindings/watchdog/amlogic,meson-gxbb-wdt.yaml2
-rw-r--r--dts/Bindings/watchdog/arm,sp805.txt32
-rw-r--r--dts/Bindings/watchdog/arm,sp805.yaml71
-rw-r--r--dts/Bindings/watchdog/arm-smc-wdt.yaml2
-rw-r--r--dts/Bindings/watchdog/aspeed-wdt.txt2
-rw-r--r--dts/Bindings/watchdog/fsl-imx-wdt.yaml11
-rw-r--r--dts/Bindings/watchdog/kontron,sl28cpld-wdt.yaml35
-rw-r--r--dts/Bindings/watchdog/qcom-wdt.yaml2
-rw-r--r--dts/Bindings/watchdog/samsung-wdt.yaml2
-rw-r--r--dts/Bindings/watchdog/st,stm32-iwdg.yaml2
-rw-r--r--dts/Bindings/watchdog/ti,rti-wdt.yaml2
-rw-r--r--dts/Bindings/watchdog/toshiba,visconti-wdt.yaml54
-rw-r--r--dts/Bindings/watchdog/watchdog.yaml2
784 files changed, 17090 insertions, 5378 deletions
diff --git a/dts/Bindings/.gitignore b/dts/Bindings/.gitignore
index 5c6d8ea1a0..3a05b99bfa 100644
--- a/dts/Bindings/.gitignore
+++ b/dts/Bindings/.gitignore
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
*.example.dts
processed-schema*.yaml
+processed-schema*.json
diff --git a/dts/Bindings/Makefile b/dts/Bindings/Makefile
index 91c4d00e96..f50420099a 100644
--- a/dts/Bindings/Makefile
+++ b/dts/Bindings/Makefile
@@ -3,7 +3,9 @@ DT_DOC_CHECKER ?= dt-doc-validate
DT_EXTRACT_EX ?= dt-extract-example
DT_MK_SCHEMA ?= dt-mk-schema
-DT_SCHEMA_MIN_VERSION = 2020.5
+DT_SCHEMA_LINT = $(shell which yamllint)
+
+DT_SCHEMA_MIN_VERSION = 2020.8.1
PHONY += check_dtschema_version
check_dtschema_version:
@@ -11,26 +13,40 @@ check_dtschema_version:
$(DT_DOC_CHECKER) --version 2>/dev/null || echo 0; } | sort -VC || \
{ echo "ERROR: dtschema minimum version is v$(DT_SCHEMA_MIN_VERSION)" >&2; false; }
-quiet_cmd_chk_binding = CHKDT $(patsubst $(srctree)/%,%,$<)
- cmd_chk_binding = $(DT_DOC_CHECKER) -u $(srctree)/$(src) $< ; \
- $(DT_EXTRACT_EX) $< > $@
+quiet_cmd_extract_ex = DTEX $@
+ cmd_extract_ex = $(DT_EXTRACT_EX) $< > $@
$(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE
- $(call if_changed,chk_binding)
+ $(call if_changed,extract_ex)
# Use full schemas when checking %.example.dts
-DT_TMP_SCHEMA := $(obj)/processed-schema-examples.yaml
+DT_TMP_SCHEMA := $(obj)/processed-schema-examples.json
find_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
-name 'processed-schema*' ! \
-name '*.example.dt.yaml' \)
+quiet_cmd_yamllint = LINT $(src)
+ cmd_yamllint = $(find_cmd) | \
+ xargs $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint
+
+quiet_cmd_chk_bindings = CHKDT $@
+ cmd_chk_bindings = $(find_cmd) | \
+ xargs -n200 -P$$(nproc) $(DT_DOC_CHECKER) -u $(srctree)/$(src)
+
quiet_cmd_mk_schema = SCHEMA $@
- cmd_mk_schema = rm -f $@ ; \
+ cmd_mk_schema = f=$$(mktemp) ; \
$(if $(DT_MK_SCHEMA_FLAGS), \
echo $(real-prereqs), \
- $(find_cmd)) | \
- xargs $(DT_MK_SCHEMA) $(DT_MK_SCHEMA_FLAGS) >> $@
+ $(find_cmd)) > $$f ; \
+ $(DT_MK_SCHEMA) -j $(DT_MK_SCHEMA_FLAGS) @$$f > $@ ; \
+ rm -f $$f
+
+define rule_chkdt
+ $(if $(DT_SCHEMA_LINT),$(call cmd,yamllint),)
+ $(call cmd,chk_bindings)
+ $(call cmd,mk_schema)
+endef
DT_DOCS = $(shell $(find_cmd) | sed -e 's|^$(srctree)/||')
@@ -39,33 +55,33 @@ override DTC_FLAGS := \
-Wno-graph_child_address \
-Wno-interrupt_provider
-$(obj)/processed-schema-examples.yaml: $(DT_DOCS) check_dtschema_version FORCE
- $(call if_changed,mk_schema)
+$(obj)/processed-schema-examples.json: $(DT_DOCS) $(src)/.yamllint check_dtschema_version FORCE
+ $(call if_changed_rule,chkdt)
ifeq ($(DT_SCHEMA_FILES),)
# Unless DT_SCHEMA_FILES is specified, use the full schema for dtbs_check too.
-# Just copy processed-schema-examples.yaml
+# Just copy processed-schema-examples.json
-$(obj)/processed-schema.yaml: $(obj)/processed-schema-examples.yaml FORCE
+$(obj)/processed-schema.json: $(obj)/processed-schema-examples.json FORCE
$(call if_changed,copy)
DT_SCHEMA_FILES = $(DT_DOCS)
else
-# If DT_SCHEMA_FILES is specified, use it for processed-schema.yaml
+# If DT_SCHEMA_FILES is specified, use it for processed-schema.json
-$(obj)/processed-schema.yaml: DT_MK_SCHEMA_FLAGS := -u
-$(obj)/processed-schema.yaml: $(DT_SCHEMA_FILES) check_dtschema_version FORCE
+$(obj)/processed-schema.json: DT_MK_SCHEMA_FLAGS := -u
+$(obj)/processed-schema.json: $(DT_SCHEMA_FILES) check_dtschema_version FORCE
$(call if_changed,mk_schema)
endif
+extra-$(CHECK_DT_BINDING) += processed-schema-examples.json
+extra-$(CHECK_DTBS) += processed-schema.json
extra-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dts, $(DT_SCHEMA_FILES))
extra-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dt.yaml, $(DT_SCHEMA_FILES))
-extra-$(CHECK_DT_BINDING) += processed-schema-examples.yaml
-extra-$(CHECK_DTBS) += processed-schema.yaml
# Hack: avoid 'Argument list too long' error for 'make clean'. Remove most of
# build artifacts here before they are processed by scripts/Makefile.clean
diff --git a/dts/Bindings/arm/actions.yaml b/dts/Bindings/arm/actions.yaml
index ace3fdaa83..fe22c66e9c 100644
--- a/dts/Bindings/arm/actions.yaml
+++ b/dts/Bindings/arm/actions.yaml
@@ -11,6 +11,8 @@ maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
properties:
+ $nodename:
+ const: "/"
compatible:
oneOf:
# The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC.
@@ -18,6 +20,12 @@ properties:
- enum:
- allo,sparky # Allo.com Sparky
- cubietech,cubieboard6 # Cubietech CubieBoard6
+ - roseapplepi,roseapplepi # RoseapplePi.org RoseapplePi
+ - const: actions,s500
+ - items:
+ - enum:
+ - caninos,labrador-base-m # Labrador Base Board M v1
+ - const: caninos,labrador-v2 # Labrador Core v2
- const: actions,s500
- items:
- enum:
@@ -28,6 +36,11 @@ properties:
# The Actions Semi S700 is a quad-core ARM Cortex-A53 SoC.
- items:
- enum:
+ - caninos,labrador-base-m2 # Labrador Base Board M v2
+ - const: caninos,labrador-v3 # Labrador Core v3
+ - const: actions,s700
+ - items:
+ - enum:
- cubietech,cubieboard7 # Cubietech CubieBoard7
- const: actions,s700
diff --git a/dts/Bindings/arm/altera.yaml b/dts/Bindings/arm/altera.yaml
index b388c5aa79..0bc5020b75 100644
--- a/dts/Bindings/arm/altera.yaml
+++ b/dts/Bindings/arm/altera.yaml
@@ -10,6 +10,8 @@ maintainers:
- Dinh Nguyen <dinguyen@kernel.org>
properties:
+ $nodename:
+ const: "/"
compatible:
items:
- enum:
diff --git a/dts/Bindings/arm/amlogic.yaml b/dts/Bindings/arm/amlogic.yaml
index 5eba9f4882..0ee7c5b7b3 100644
--- a/dts/Bindings/arm/amlogic.yaml
+++ b/dts/Bindings/arm/amlogic.yaml
@@ -96,6 +96,7 @@ properties:
- hwacom,amazetv
- khadas,vim
- libretech,aml-s905x-cc
+ - libretech,aml-s905x-cc-v2
- nexbox,a95x
- const: amlogic,s905x
- const: amlogic,meson-gxl
@@ -153,6 +154,7 @@ properties:
- azw,gtking
- azw,gtking-pro
- hardkernel,odroid-n2
+ - hardkernel,odroid-n2-plus
- khadas,vim3
- ugoos,am6
- const: amlogic,s922x
diff --git a/dts/Bindings/arm/atmel-at91.yaml b/dts/Bindings/arm/atmel-at91.yaml
index 31b0c54fa2..614c919567 100644
--- a/dts/Bindings/arm/atmel-at91.yaml
+++ b/dts/Bindings/arm/atmel-at91.yaml
@@ -41,6 +41,7 @@ properties:
- overkiz,kizboxmini-mb # Overkiz kizbox Mini Mother Board
- overkiz,kizboxmini-rd # Overkiz kizbox Mini RailDIN
- overkiz,smartkiz # Overkiz SmartKiz Board
+ - gardena,smart-gateway-at91sam # GARDENA smart Gateway (Article No. 19000)
- const: atmel,at91sam9g25
- const: atmel,at91sam9x5
- const: atmel,at91sam9
diff --git a/dts/Bindings/arm/axxia.yaml b/dts/Bindings/arm/axxia.yaml
index 98780a569f..3ea5f2fdcd 100644
--- a/dts/Bindings/arm/axxia.yaml
+++ b/dts/Bindings/arm/axxia.yaml
@@ -10,6 +10,8 @@ maintainers:
- Anders Berg <anders.berg@lsi.com>
properties:
+ $nodename:
+ const: "/"
compatible:
description: LSI AXM5516 Validation board (Amarillo)
items:
diff --git a/dts/Bindings/arm/bcm/brcm,bcm4708.yaml b/dts/Bindings/arm/bcm/brcm,bcm4708.yaml
index d48313c7ae..988e0bbb2a 100644
--- a/dts/Bindings/arm/bcm/brcm,bcm4708.yaml
+++ b/dts/Bindings/arm/bcm/brcm,bcm4708.yaml
@@ -83,6 +83,8 @@ properties:
- brcm,bcm953012er
- brcm,bcm953012hr
- brcm,bcm953012k
+ - meraki,mr32
- const: brcm,brcm53012
+ - const: brcm,brcm53016
- const: brcm,bcm4708
...
diff --git a/dts/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml b/dts/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
index 6834f5e8df..a2c63c8b1d 100644
--- a/dts/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
+++ b/dts/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
@@ -48,12 +48,30 @@ properties:
- compatible
- "#clock-cells"
+ reset:
+ type: object
+
+ properties:
+ compatible:
+ const: raspberrypi,firmware-reset
+
+ "#reset-cells":
+ const: 1
+ description: >
+ The argument is the ID of the firmware reset line to affect.
+
+ required:
+ - compatible
+ - "#reset-cells"
+
additionalProperties: false
required:
- compatible
- mboxes
+additionalProperties: false
+
examples:
- |
firmware {
@@ -64,5 +82,10 @@ examples:
compatible = "raspberrypi,firmware-clocks";
#clock-cells = <1>;
};
+
+ reset: reset {
+ compatible = "raspberrypi,firmware-reset";
+ #reset-cells = <1>;
+ };
};
...
diff --git a/dts/Bindings/arm/bitmain.yaml b/dts/Bindings/arm/bitmain.yaml
index 5cd5b36cff..5880083ab8 100644
--- a/dts/Bindings/arm/bitmain.yaml
+++ b/dts/Bindings/arm/bitmain.yaml
@@ -10,6 +10,8 @@ maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
properties:
+ $nodename:
+ const: "/"
compatible:
items:
- enum:
diff --git a/dts/Bindings/arm/coresight-cti.yaml b/dts/Bindings/arm/coresight-cti.yaml
index e42ff69d8b..21e3515491 100644
--- a/dts/Bindings/arm/coresight-cti.yaml
+++ b/dts/Bindings/arm/coresight-cti.yaml
@@ -220,6 +220,8 @@ then:
required:
- cpu
+unevaluatedProperties: false
+
examples:
# minimum CTI definition. DEVID register used to set number of triggers.
- |
diff --git a/dts/Bindings/arm/cpus.yaml b/dts/Bindings/arm/cpus.yaml
index 1222bf1831..14cd727d3c 100644
--- a/dts/Bindings/arm/cpus.yaml
+++ b/dts/Bindings/arm/cpus.yaml
@@ -341,6 +341,8 @@ required:
dependencies:
rockchip,pmu: [enable-method]
+additionalProperties: true
+
examples:
- |
cpus {
diff --git a/dts/Bindings/arm/digicolor.yaml b/dts/Bindings/arm/digicolor.yaml
index d9c80b827e..849e205183 100644
--- a/dts/Bindings/arm/digicolor.yaml
+++ b/dts/Bindings/arm/digicolor.yaml
@@ -10,6 +10,8 @@ maintainers:
- Baruch Siach <baruch@tkos.co.il>
properties:
+ $nodename:
+ const: "/"
compatible:
const: cnxt,cx92755
diff --git a/dts/Bindings/arm/freescale/fsl,imx7ulp-pm.txt b/dts/Bindings/arm/freescale/fsl,imx7ulp-pm.txt
deleted file mode 100644
index 75195bee11..0000000000
--- a/dts/Bindings/arm/freescale/fsl,imx7ulp-pm.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-Freescale i.MX7ULP Power Management Components
-----------------------------------------------
-
-The Multi-System Mode Controller (MSMC) is responsible for sequencing
-the MCU into and out of all stop and run power modes. Specifically, it
-monitors events to trigger transitions between power modes while
-controlling the power, clocks, and memories of the MCU to achieve the
-power consumption and functionality of that mode.
-
-The WFI or WFE instruction is used to invoke a Sleep, Deep Sleep or
-Standby modes for either Cortex family. Run, Wait, and Stop are the
-common terms used for the primary operating modes of Kinetis
-microcontrollers.
-
-Required properties:
-- compatible: Should be "fsl,imx7ulp-smc1".
-- reg: Specifies base physical address and size of the register sets.
-
-Example:
-smc1: smc1@40410000 {
- compatible = "fsl,imx7ulp-smc1";
- reg = <0x40410000 0x1000>;
-};
diff --git a/dts/Bindings/arm/freescale/fsl,imx7ulp-pm.yaml b/dts/Bindings/arm/freescale/fsl,imx7ulp-pm.yaml
new file mode 100644
index 0000000000..3b26040f8f
--- /dev/null
+++ b/dts/Bindings/arm/freescale/fsl,imx7ulp-pm.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/freescale/fsl,imx7ulp-pm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX7ULP Power Management Components
+
+maintainers:
+ - A.s. Dong <aisheng.dong@nxp.com>
+
+description: |
+ The Multi-System Mode Controller (MSMC) is responsible for sequencing
+ the MCU into and out of all stop and run power modes. Specifically, it
+ monitors events to trigger transitions between power modes while
+ controlling the power, clocks, and memories of the MCU to achieve the
+ power consumption and functionality of that mode.
+
+ The WFI or WFE instruction is used to invoke a Sleep, Deep Sleep or
+ Standby modes for either Cortex family. Run, Wait, and Stop are the
+ common terms used for the primary operating modes of Kinetis
+ microcontrollers.
+
+properties:
+ compatible:
+ const: fsl,imx7ulp-smc1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ smc1@40410000 {
+ compatible = "fsl,imx7ulp-smc1";
+ reg = <0x40410000 0x1000>;
+ };
diff --git a/dts/Bindings/arm/freescale/fsl,imx7ulp-sim.txt b/dts/Bindings/arm/freescale/fsl,imx7ulp-sim.txt
deleted file mode 100644
index 7d0c7f0024..0000000000
--- a/dts/Bindings/arm/freescale/fsl,imx7ulp-sim.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-Freescale i.MX7ULP System Integration Module
-----------------------------------------------
-The system integration module (SIM) provides system control and chip configuration
-registers. In this module, chip revision information is located in JTAG ID register,
-and a set of registers have been made available in DGO domain for SW use, with the
-objective to maintain its value between system resets.
-
-Required properties:
-- compatible: Should be "fsl,imx7ulp-sim".
-- reg: Specifies base physical address and size of the register sets.
-
-Example:
-sim: sim@410a3000 {
- compatible = "fsl,imx7ulp-sim", "syscon";
- reg = <0x410a3000 0x1000>;
-};
diff --git a/dts/Bindings/arm/freescale/fsl,imx7ulp-sim.yaml b/dts/Bindings/arm/freescale/fsl,imx7ulp-sim.yaml
new file mode 100644
index 0000000000..526f508cb9
--- /dev/null
+++ b/dts/Bindings/arm/freescale/fsl,imx7ulp-sim.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/freescale/fsl,imx7ulp-sim.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX7ULP System Integration Module
+
+maintainers:
+ - Anson Huang <anson.huang@nxp.com>
+
+description: |
+ The system integration module (SIM) provides system control and chip configuration
+ registers. In this module, chip revision information is located in JTAG ID register,
+ and a set of registers have been made available in DGO domain for SW use, with the
+ objective to maintain its value between system resets.
+
+properties:
+ compatible:
+ items:
+ - const: fsl,imx7ulp-sim
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ sim@410a3000 {
+ compatible = "fsl,imx7ulp-sim", "syscon";
+ reg = <0x410a3000 0x1000>;
+ };
diff --git a/dts/Bindings/arm/fsl.yaml b/dts/Bindings/arm/fsl.yaml
index 6da9d734cd..1ca9dfa8ce 100644
--- a/dts/Bindings/arm/fsl.yaml
+++ b/dts/Bindings/arm/fsl.yaml
@@ -120,6 +120,7 @@ properties:
- fsl,imx6q-sabrelite
- fsl,imx6q-sabresd
- kontron,imx6q-samx6i # Kontron i.MX6 Dual/Quad SMARC Module
+ - logicpd,imx6q-logicpd
- prt,prti6q # Protonic PRTI6Q board
- prt,prtwd2 # Protonic WD2 board
- technexion,imx6q-pico-dwarf # TechNexion i.MX6Q Pico-Dwarf
@@ -156,6 +157,21 @@ properties:
- const: gw,ventana
- const: fsl,imx6q
+ - description: i.MX6Q PHYTEC phyBOARD-Mira
+ items:
+ - enum:
+ - phytec,imx6q-pbac06-emmc # PHYTEC phyBOARD-Mira eMMC RDK
+ - phytec,imx6q-pbac06-nand # PHYTEC phyBOARD-Mira NAND RDK
+ - const: phytec,imx6q-pbac06 # PHYTEC phyBOARD-Mira
+ - const: phytec,imx6qdl-pcm058 # PHYTEC phyCORE-i.MX6
+ - const: fsl,imx6q
+
+ - description: i.MX6Q PHYTEC phyFLEX-i.MX6
+ items:
+ - const: phytec,imx6q-pbab01 # PHYTEC phyFLEX carrier board
+ - const: phytec,imx6q-pfla02 # PHYTEC phyFLEX-i.MX6 Quad
+ - const: fsl,imx6q
+
- description: i.MX6QP based Boards
items:
- enum:
@@ -163,6 +179,13 @@ properties:
- fsl,imx6qp-sabresd # i.MX6 Quad Plus SABRE Smart Device Board
- const: fsl,imx6qp
+ - description: i.MX6QP PHYTEC phyBOARD-Mira
+ items:
+ - const: phytec,imx6qp-pbac06-nand
+ - const: phytec,imx6qp-pbac06 # PHYTEC phyBOARD-Mira
+ - const: phytec,imx6qdl-pcm058 # PHYTEC phyCORE-i.MX6
+ - const: fsl,imx6qp
+
- description: i.MX6DL based Boards
items:
- enum:
@@ -188,6 +211,7 @@ properties:
- toradex,colibri_imx6dl-v1_1-eval-v3 # Colibri iMX6 Module V1.1 on Colibri Evaluation Board V3
- ysoft,imx6dl-yapp4-draco # i.MX6 DualLite Y Soft IOTA Draco board
- ysoft,imx6dl-yapp4-hydra # i.MX6 DualLite Y Soft IOTA Hydra board
+ - ysoft,imx6dl-yapp4-orion # i.MX6 DualLite Y Soft IOTA Orion board
- ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board
- const: fsl,imx6dl
@@ -211,10 +235,26 @@ properties:
- const: gw,ventana
- const: fsl,imx6dl
+ - description: i.MX6DL PHYTEC phyBOARD-Mira
+ items:
+ - enum:
+ - phytec,imx6dl-pbac06-emmc # PHYTEC phyBOARD-Mira eMMC RDK
+ - phytec,imx6dl-pbac06-nand # PHYTEC phyBOARD-Mira NAND RDK
+ - const: phytec,imx6dl-pbac06 # PHYTEC phyBOARD-Mira
+ - const: phytec,imx6qdl-pcm058 # PHYTEC phyCORE-i.MX6
+ - const: fsl,imx6dl
+
+ - description: i.MX6DL PHYTEC phyFLEX-i.MX6
+ items:
+ - const: phytec,imx6dl-pbab01 # PHYTEC phyFLEX carrier board
+ - const: phytec,imx6dl-pfla02 # PHYTEC phyFLEX-i.MX6 Quad
+ - const: fsl,imx6dl
+
- description: i.MX6SL based Boards
items:
- enum:
- fsl,imx6sl-evk # i.MX6 SoloLite EVK Board
+ - kobo,tolino-shine2hd
- kobo,tolino-shine3
- const: fsl,imx6sl
@@ -246,6 +286,15 @@ properties:
- technexion,imx6ul-pico-pi # TechNexion i.MX6UL Pico-Pi
- const: fsl,imx6ul
+ - description: i.MX6UL PHYTEC phyBOARD-Segin
+ items:
+ - enum:
+ - phytec,imx6ul-pbacd10-emmc
+ - phytec,imx6ul-pbacd10-nand
+ - const: phytec,imx6ul-pbacd10 # PHYTEC phyBOARD-Segin with i.MX6 UL
+ - const: phytec,imx6ul-pcl063 # PHYTEC phyCORE-i.MX 6UL
+ - const: fsl,imx6ul
+
- description: Kontron N6310 S Board
items:
- const: kontron,imx6ul-n6310-s
@@ -277,6 +326,15 @@ properties:
- toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT Module on Colibri Eval Board
- const: fsl,imx6ull
+ - description: i.MX6ULL PHYTEC phyBOARD-Segin
+ items:
+ - enum:
+ - phytec,imx6ull-pbacd10-emmc
+ - phytec,imx6ull-pbacd10-nand
+ - const: phytec,imx6ull-pbacd10 # PHYTEC phyBOARD-Segin with i.MX6 ULL
+ - const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL
+ - const: fsl,imx6ull
+
- description: Kontron N6411 S Board
items:
- const: kontron,imx6ull-n6411-s
@@ -344,7 +402,16 @@ properties:
- description: i.MX8MM based Boards
items:
- enum:
+ - beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit
+ - fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
- fsl,imx8mm-evk # i.MX8MM EVK Board
+ - variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module
+ - const: fsl,imx8mm
+
+ - description: Variscite VAR-SOM-MX8MM based boards
+ items:
+ - const: variscite,var-som-mx8mm-symphony
+ - const: variscite,var-som-mx8mm
- const: fsl,imx8mm
- description: i.MX8MN based Boards
@@ -354,6 +421,12 @@ properties:
- fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board
- const: fsl,imx8mn
+ - description: Variscite VAR-SOM-MX8MN based boards
+ items:
+ - const: variscite,var-som-mx8mn-symphony
+ - const: variscite,var-som-mx8mn
+ - const: fsl,imx8mn
+
- description: i.MX8MP based Boards
items:
- enum:
@@ -372,13 +445,35 @@ properties:
- technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk
- const: fsl,imx8mq
+ - description: Purism Librem5 phones
+ items:
+ - enum:
+ - purism,librem5r2 # Purism Librem5 phone "Chestnut"
+ - purism,librem5r3 # Purism Librem5 phone "Dogwood"
+ - const: purism,librem5
+ - const: fsl,imx8mq
+
+ - description: Zodiac Inflight Innovations Ultra Boards
+ items:
+ - enum:
+ - zii,imx8mq-ultra-rmb3
+ - zii,imx8mq-ultra-zest
+ - const: zii,imx8mq-ultra
+ - const: fsl,imx8mq
+
- description: i.MX8QXP based Boards
items:
- enum:
- einfochips,imx8qxp-ai_ml # i.MX8QXP AI_ML Board
- fsl,imx8qxp-mek # i.MX8QXP MEK Board
- toradex,colibri-imx8x # Colibri iMX8X Module
+ - const: fsl,imx8qxp
+
+ - description: Toradex Colibri i.MX8 Evaluation Board
+ items:
+ - enum:
- toradex,colibri-imx8x-eval-v3 # Colibri iMX8X Module on Colibri Evaluation Board V3
+ - const: toradex,colibri-imx8x
- const: fsl,imx8qxp
- description:
diff --git a/dts/Bindings/arm/hisilicon/controller/cpuctrl.yaml b/dts/Bindings/arm/hisilicon/controller/cpuctrl.yaml
new file mode 100644
index 0000000000..528dad4cde
--- /dev/null
+++ b/dts/Bindings/arm/hisilicon/controller/cpuctrl.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/controller/cpuctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon CPU controller
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: |
+ The clock registers and power registers of secondary cores are defined
+ in CPU controller, especially in HIX5HD2 SoC.
+
+properties:
+ compatible:
+ items:
+ - const: hisilicon,cpuctrl
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties:
+ type: object
+
+examples:
+ - |
+ cpuctrl@a22000 {
+ compatible = "hisilicon,cpuctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x00a22000 0x2000>;
+ ranges = <0 0x00a22000 0x2000>;
+
+ clock: clock@0 {
+ compatible = "hisilicon,hix5hd2-clock";
+ reg = <0 0x2000>;
+ #clock-cells = <1>;
+ };
+ };
+...
diff --git a/dts/Bindings/arm/hisilicon/controller/hi3798cv200-perictrl.yaml b/dts/Bindings/arm/hisilicon/controller/hi3798cv200-perictrl.yaml
new file mode 100644
index 0000000000..cba1937aad
--- /dev/null
+++ b/dts/Bindings/arm/hisilicon/controller/hi3798cv200-perictrl.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/controller/hi3798cv200-perictrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon Hi3798CV200 Peripheral Controller
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: |
+ The Hi3798CV200 Peripheral Controller controls peripherals, queries
+ their status, and configures some functions of peripherals.
+
+properties:
+ compatible:
+ items:
+ - const: hisilicon,hi3798cv200-perictrl
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+additionalProperties:
+ type: object
+
+examples:
+ - |
+ peripheral-controller@8a20000 {
+ compatible = "hisilicon,hi3798cv200-perictrl", "syscon", "simple-mfd";
+ reg = <0x8a20000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8a20000 0x1000>;
+
+ phy@850 {
+ compatible = "hisilicon,hi3798cv200-combphy";
+ reg = <0x850 0x8>;
+ #phy-cells = <1>;
+ clocks = <&crg 42>;
+ resets = <&crg 0x188 4>;
+ assigned-clocks = <&crg 42>;
+ assigned-clock-rates = <100000000>;
+ hisilicon,fixed-mode = <4>;
+ };
+ };
+...
diff --git a/dts/Bindings/arm/hisilicon/controller/hi6220-domain-ctrl.yaml b/dts/Bindings/arm/hisilicon/controller/hi6220-domain-ctrl.yaml
new file mode 100644
index 0000000000..6ea6d7ee7a
--- /dev/null
+++ b/dts/Bindings/arm/hisilicon/controller/hi6220-domain-ctrl.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/controller/hi6220-domain-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon Hi6220 domain controller
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: |
+ Hisilicon designs some special domain controllers for mobile platform,
+ such as: the power Always On domain controller, the Media domain
+ controller(e.g. codec, G3D ...) and the Power Management domain
+ controller.
+
+ The compatible names of each domain controller are as follows:
+ Power Always ON domain controller --> hisilicon,hi6220-aoctrl
+ Media domain controller --> hisilicon,hi6220-mediactrl
+ Power Management domain controller --> hisilicon,hi6220-pmctrl
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - hisilicon,hi6220-aoctrl
+ - hisilicon,hi6220-mediactrl
+ - hisilicon,hi6220-pmctrl
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ ao_ctrl@f7800000 {
+ compatible = "hisilicon,hi6220-aoctrl", "syscon";
+ reg = <0xf7800000 0x2000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ media_ctrl@f4410000 {
+ compatible = "hisilicon,hi6220-mediactrl", "syscon";
+ reg = <0xf4410000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pm_ctrl@f7032000 {
+ compatible = "hisilicon,hi6220-pmctrl", "syscon";
+ reg = <0xf7032000 0x1000>;
+ #clock-cells = <1>;
+ };
+...
diff --git a/dts/Bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml b/dts/Bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml
new file mode 100644
index 0000000000..7378159e61
--- /dev/null
+++ b/dts/Bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/controller/hip04-bootwrapper.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bootwrapper boot method
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: Bootwrapper boot method (software protocol on SMP)
+
+properties:
+ compatible:
+ items:
+ - const: hisilicon,hip04-bootwrapper
+
+ boot-method:
+ description: |
+ Address and size of boot method.
+ [0]: bootwrapper physical address
+ [1]: bootwrapper size
+ [2]: relocation physical address
+ [3]: relocation size
+ minItems: 1
+ maxItems: 2
+
+required:
+ - compatible
+ - boot-method
+
+additionalProperties: false
+...
diff --git a/dts/Bindings/arm/hisilicon/controller/hip04-fabric.yaml b/dts/Bindings/arm/hisilicon/controller/hip04-fabric.yaml
new file mode 100644
index 0000000000..60c516a04a
--- /dev/null
+++ b/dts/Bindings/arm/hisilicon/controller/hip04-fabric.yaml
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/controller/hip04-fabric.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon Fabric controller
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: Hisilicon Fabric controller
+
+properties:
+ compatible:
+ items:
+ - const: hisilicon,hip04-fabric
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+...
diff --git a/dts/Bindings/arm/hisilicon/controller/pctrl.yaml b/dts/Bindings/arm/hisilicon/controller/pctrl.yaml
new file mode 100644
index 0000000000..6d50658728
--- /dev/null
+++ b/dts/Bindings/arm/hisilicon/controller/pctrl.yaml
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/controller/pctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Peripheral misc control register
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: Peripheral misc control register
+
+properties:
+ compatible:
+ items:
+ - const: hisilicon,pctrl
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ pctrl@fca09000 {
+ compatible = "hisilicon,pctrl";
+ reg = <0xfca09000 0x1000>;
+ };
+...
diff --git a/dts/Bindings/arm/hisilicon/controller/sysctrl.yaml b/dts/Bindings/arm/hisilicon/controller/sysctrl.yaml
new file mode 100644
index 0000000000..5a53d433b6
--- /dev/null
+++ b/dts/Bindings/arm/hisilicon/controller/sysctrl.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/controller/sysctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon system controller
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: |
+ The Hisilicon system controller is used on many Hisilicon boards, it can be
+ used to assist the slave core startup, reboot the system, etc.
+
+ There are some variants of the Hisilicon system controller, such as HiP01,
+ Hi3519, Hi6220 system controller, each of them is mostly compatible with the
+ Hisilicon system controller, but some same registers located at different
+ offset. In addition, the HiP01 system controller has some specific control
+ registers for HIP01 SoC family, such as slave core boot.
+
+ The compatible names of each system controller are as follows:
+ Hisilicon system controller --> hisilicon,sysctrl
+ HiP01 system controller --> hisilicon,hip01-sysctrl
+ Hi6220 system controller --> hisilicon,hi6220-sysctrl
+ Hi3519 system controller --> hisilicon,hi3519-sysctrl
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: hisilicon,hi6220-sysctrl
+ then:
+ required:
+ - '#clock-cells'
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - hisilicon,sysctrl
+ - hisilicon,hi6220-sysctrl
+ - hisilicon,hi3519-sysctrl
+ - const: syscon
+ - items:
+ - const: hisilicon,hip01-sysctrl
+ - const: hisilicon,sysctrl
+
+ reg:
+ maxItems: 1
+
+ smp-offset:
+ description: |
+ offset in sysctrl for notifying slave cpu booting
+ cpu 1, reg;
+ cpu 2, reg + 0x4;
+ cpu 3, reg + 0x8;
+ If reg value is not zero, cpun exit wfi and go
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ resume-offset:
+ description: offset in sysctrl for notifying cpu0 when resume
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ reboot-offset:
+ description: offset in sysctrl for system reboot
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+ ranges: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties:
+ type: object
+
+examples:
+ - |
+ /* Hisilicon system controller */
+ system-controller@802000 {
+ compatible = "hisilicon,sysctrl", "syscon";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x802000 0x1000>;
+ reg = <0x802000 0x1000>;
+
+ smp-offset = <0x31c>;
+ resume-offset = <0x308>;
+ reboot-offset = <0x4>;
+
+ clock: clock@0 {
+ compatible = "hisilicon,hi3620-clock";
+ reg = <0 0x10000>;
+ #clock-cells = <1>;
+ };
+ };
+
+ /* HiP01 system controller */
+ system-controller@10000000 {
+ compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
+ reg = <0x10000000 0x1000>;
+ reboot-offset = <0x4>;
+ };
+
+ /* Hi6220 system controller */
+ system-controller@f7030000 {
+ compatible = "hisilicon,hi6220-sysctrl", "syscon";
+ reg = <0xf7030000 0x2000>;
+ #clock-cells = <1>;
+ };
+
+ /* Hi3519 system controller */
+ system-controller@12010000 {
+ compatible = "hisilicon,hi3519-sysctrl", "syscon";
+ reg = <0x12010000 0x1000>;
+ };
+...
diff --git a/dts/Bindings/arm/hisilicon/hi3519-sysctrl.txt b/dts/Bindings/arm/hisilicon/hi3519-sysctrl.txt
deleted file mode 100644
index 8defacc44d..0000000000
--- a/dts/Bindings/arm/hisilicon/hi3519-sysctrl.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* Hisilicon Hi3519 System Controller Block
-
-This bindings use the following binding:
-Documentation/devicetree/bindings/mfd/syscon.yaml
-
-Required properties:
-- compatible: "hisilicon,hi3519-sysctrl".
-- reg: the register region of this block
-
-Examples:
-sysctrl: system-controller@12010000 {
- compatible = "hisilicon,hi3519-sysctrl", "syscon";
- reg = <0x12010000 0x1000>;
-};
diff --git a/dts/Bindings/arm/hisilicon/hisilicon-low-pin-count.txt b/dts/Bindings/arm/hisilicon/hisilicon-low-pin-count.txt
deleted file mode 100644
index 10bd35f920..0000000000
--- a/dts/Bindings/arm/hisilicon/hisilicon-low-pin-count.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-Hisilicon Hip06 Low Pin Count device
- Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which
- provides I/O access to some legacy ISA devices.
- Hip06 is based on arm64 architecture where there is no I/O space. So, the
- I/O ports here are not CPU addresses, and there is no 'ranges' property in
- LPC device node.
-
-Required properties:
-- compatible: value should be as follows:
- (a) "hisilicon,hip06-lpc"
- (b) "hisilicon,hip07-lpc"
-- #address-cells: must be 2 which stick to the ISA/EISA binding doc.
-- #size-cells: must be 1 which stick to the ISA/EISA binding doc.
-- reg: base memory range where the LPC register set is mapped.
-
-Note:
- The node name before '@' must be "isa" to represent the binding stick to the
- ISA/EISA binding specification.
-
-Example:
-
-isa@a01b0000 {
- compatible = "hisilicon,hip06-lpc";
- #address-cells = <2>;
- #size-cells = <1>;
- reg = <0x0 0xa01b0000 0x0 0x1000>;
-
- ipmi0: bt@e4 {
- compatible = "ipmi-bt";
- device_type = "ipmi";
- reg = <0x01 0xe4 0x04>;
- };
-};
diff --git a/dts/Bindings/arm/hisilicon/hisilicon.txt b/dts/Bindings/arm/hisilicon/hisilicon.txt
deleted file mode 100644
index a97f643e7d..0000000000
--- a/dts/Bindings/arm/hisilicon/hisilicon.txt
+++ /dev/null
@@ -1,319 +0,0 @@
-Hisilicon Platforms Device Tree Bindings
-----------------------------------------------------
-Hi3660 SoC
-Required root node properties:
- - compatible = "hisilicon,hi3660";
-
-HiKey960 Board
-Required root node properties:
- - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
-
-Hi3670 SoC
-Required root node properties:
- - compatible = "hisilicon,hi3670";
-
-HiKey970 Board
-Required root node properties:
- - compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
-
-Hi3798cv200 SoC
-Required root node properties:
- - compatible = "hisilicon,hi3798cv200";
-
-Hi3798cv200 Poplar Board
-Required root node properties:
- - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
-
-Hi4511 Board
-Required root node properties:
- - compatible = "hisilicon,hi3620-hi4511";
-
-Hi6220 SoC
-Required root node properties:
- - compatible = "hisilicon,hi6220";
-
-HiKey Board
-Required root node properties:
- - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
-
-HiP01 ca9x2 Board
-Required root node properties:
- - compatible = "hisilicon,hip01-ca9x2";
-
-HiP04 D01 Board
-Required root node properties:
- - compatible = "hisilicon,hip04-d01";
-
-HiP05 D02 Board
-Required root node properties:
- - compatible = "hisilicon,hip05-d02";
-
-HiP06 D03 Board
-Required root node properties:
- - compatible = "hisilicon,hip06-d03";
-
-HiP07 D05 Board
-Required root node properties:
- - compatible = "hisilicon,hip07-d05";
-
-Hisilicon system controller
-
-Required properties:
-- compatible : "hisilicon,sysctrl"
-- reg : Register address and size
-
-Optional properties:
-- smp-offset : offset in sysctrl for notifying slave cpu booting
- cpu 1, reg;
- cpu 2, reg + 0x4;
- cpu 3, reg + 0x8;
- If reg value is not zero, cpun exit wfi and go
-- resume-offset : offset in sysctrl for notifying cpu0 when resume
-- reboot-offset : offset in sysctrl for system reboot
-
-Example:
-
- /* for Hi3620 */
- sysctrl: system-controller@fc802000 {
- compatible = "hisilicon,sysctrl";
- reg = <0xfc802000 0x1000>;
- smp-offset = <0x31c>;
- resume-offset = <0x308>;
- reboot-offset = <0x4>;
- };
-
------------------------------------------------------------------------
-Hisilicon Hi3798CV200 Peripheral Controller
-
-The Hi3798CV200 Peripheral Controller controls peripherals, queries
-their status, and configures some functions of peripherals.
-
-Required properties:
-- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon"
- and "simple-mfd".
-- reg: Register address and size of Peripheral Controller.
-- #address-cells: Should be 1.
-- #size-cells: Should be 1.
-
-Examples:
-
- perictrl: peripheral-controller@8a20000 {
- compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
- "simple-mfd";
- reg = <0x8a20000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
------------------------------------------------------------------------
-Hisilicon Hi6220 system controller
-
-Required properties:
-- compatible : "hisilicon,hi6220-sysctrl"
-- reg : Register address and size
-- #clock-cells: should be set to 1, many clock registers are defined
- under this controller and this property must be present.
-
-Hisilicon designs this controller as one of the system controllers,
-its main functions are the same as Hisilicon system controller, but
-the register offset of some core modules are different.
-
-Example:
- /*for Hi6220*/
- sys_ctrl: sys_ctrl@f7030000 {
- compatible = "hisilicon,hi6220-sysctrl", "syscon";
- reg = <0x0 0xf7030000 0x0 0x2000>;
- #clock-cells = <1>;
- };
-
-
-Hisilicon Hi6220 Power Always ON domain controller
-
-Required properties:
-- compatible : "hisilicon,hi6220-aoctrl"
-- reg : Register address and size
-- #clock-cells: should be set to 1, many clock registers are defined
- under this controller and this property must be present.
-
-Hisilicon designs this system controller to control the power always
-on domain for mobile platform.
-
-Example:
- /*for Hi6220*/
- ao_ctrl: ao_ctrl@f7800000 {
- compatible = "hisilicon,hi6220-aoctrl", "syscon";
- reg = <0x0 0xf7800000 0x0 0x2000>;
- #clock-cells = <1>;
- };
-
-
-Hisilicon Hi6220 Media domain controller
-
-Required properties:
-- compatible : "hisilicon,hi6220-mediactrl"
-- reg : Register address and size
-- #clock-cells: should be set to 1, many clock registers are defined
- under this controller and this property must be present.
-
-Hisilicon designs this system controller to control the multimedia
-domain(e.g. codec, G3D ...) for mobile platform.
-
-Example:
- /*for Hi6220*/
- media_ctrl: media_ctrl@f4410000 {
- compatible = "hisilicon,hi6220-mediactrl", "syscon";
- reg = <0x0 0xf4410000 0x0 0x1000>;
- #clock-cells = <1>;
- };
-
-
-Hisilicon Hi6220 Power Management domain controller
-
-Required properties:
-- compatible : "hisilicon,hi6220-pmctrl"
-- reg : Register address and size
-- #clock-cells: should be set to 1, some clock registers are define
- under this controller and this property must be present.
-
-Hisilicon designs this system controller to control the power management
-domain for mobile platform.
-
-Example:
- /*for Hi6220*/
- pm_ctrl: pm_ctrl@f7032000 {
- compatible = "hisilicon,hi6220-pmctrl", "syscon";
- reg = <0x0 0xf7032000 0x0 0x1000>;
- #clock-cells = <1>;
- };
-
-
-Hisilicon Hi6220 SRAM controller
-
-Required properties:
-- compatible : "hisilicon,hi6220-sramctrl", "syscon"
-- reg : Register address and size
-
-Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several
-SRAM banks for power management, modem, security, etc. Further, use "syscon"
-managing the common sram which can be shared by multiple modules.
-
-Example:
- /*for Hi6220*/
- sram: sram@fff80000 {
- compatible = "hisilicon,hi6220-sramctrl", "syscon";
- reg = <0x0 0xfff80000 0x0 0x12000>;
- };
-
------------------------------------------------------------------------
-Hisilicon HiP01 system controller
-
-Required properties:
-- compatible : "hisilicon,hip01-sysctrl"
-- reg : Register address and size
-
-The HiP01 system controller is mostly compatible with hisilicon
-system controller,but it has some specific control registers for
-HIP01 SoC family, such as slave core boot, and also some same
-registers located at different offset.
-
-Example:
-
- /* for hip01-ca9x2 */
- sysctrl: system-controller@10000000 {
- compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
- reg = <0x10000000 0x1000>;
- reboot-offset = <0x4>;
- };
-
------------------------------------------------------------------------
-Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
-
-Required properties:
-- compatible : "hisilicon,pcie-sas-subctrl", "syscon";
-- reg : Register address and size
-
-The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
-HiP05 or HiP06 Soc to implement some basic configurations.
-
-Example:
- /* for HiP05 PCIe-SAS sub system */
- pcie_sas: system_controller@b0000000 {
- compatible = "hisilicon,pcie-sas-subctrl", "syscon";
- reg = <0xb0000000 0x10000>;
- };
-
-Hisilicon HiP05/HiP06 PERI sub system controller
-
-Required properties:
-- compatible : "hisilicon,peri-subctrl", "syscon";
-- reg : Register address and size
-
-The PERI sub system controller is shared by peripheral controllers in
-HiP05 or HiP06 Soc to implement some basic configurations. The peripheral
-controllers include mdio, ddr, iic, uart, timer and so on.
-
-Example:
- /* for HiP05 sub peri system */
- peri_c_subctrl: syscon@80000000 {
- compatible = "hisilicon,peri-subctrl", "syscon";
- reg = <0x0 0x80000000 0x0 0x10000>;
- };
-
-Hisilicon HiP05/HiP06 DSA sub system controller
-
-Required properties:
-- compatible : "hisilicon,dsa-subctrl", "syscon";
-- reg : Register address and size
-
-The DSA sub system controller is shared by peripheral controllers in
-HiP05 or HiP06 Soc to implement some basic configurations.
-
-Example:
- /* for HiP05 dsa sub system */
- pcie_sas: system_controller@a0000000 {
- compatible = "hisilicon,dsa-subctrl", "syscon";
- reg = <0xa0000000 0x10000>;
- };
-
------------------------------------------------------------------------
-Hisilicon CPU controller
-
-Required properties:
-- compatible : "hisilicon,cpuctrl"
-- reg : Register address and size
-
-The clock registers and power registers of secondary cores are defined
-in CPU controller, especially in HIX5HD2 SoC.
-
------------------------------------------------------------------------
-PCTRL: Peripheral misc control register
-
-Required Properties:
-- compatible: "hisilicon,pctrl"
-- reg: Address and size of pctrl.
-
-Example:
-
- /* for Hi3620 */
- pctrl: pctrl@fca09000 {
- compatible = "hisilicon,pctrl";
- reg = <0xfca09000 0x1000>;
- };
-
------------------------------------------------------------------------
-Fabric:
-
-Required Properties:
-- compatible: "hisilicon,hip04-fabric";
-- reg: Address and size of Fabric
-
------------------------------------------------------------------------
-Bootwrapper boot method (software protocol on SMP):
-
-Required Properties:
-- compatible: "hisilicon,hip04-bootwrapper";
-- boot-method: Address and size of boot method.
- [0]: bootwrapper physical address
- [1]: bootwrapper size
- [2]: relocation physical address
- [3]: relocation size
diff --git a/dts/Bindings/arm/hisilicon/hisilicon.yaml b/dts/Bindings/arm/hisilicon/hisilicon.yaml
new file mode 100644
index 0000000000..43b8ce2227
--- /dev/null
+++ b/dts/Bindings/arm/hisilicon/hisilicon.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/hisilicon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon Platforms Device Tree Bindings
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+properties:
+ $nodename:
+ const: '/'
+
+ compatible:
+ oneOf:
+ - description: Hi3660 based boards.
+ items:
+ - const: hisilicon,hi3660-hikey960
+ - const: hisilicon,hi3660
+
+ - description: Hi3670 based boards.
+ items:
+ - const: hisilicon,hi3670-hikey970
+ - const: hisilicon,hi3670
+
+ - description: Hi3798cv200 based boards.
+ items:
+ - const: hisilicon,hi3798cv200-poplar
+ - const: hisilicon,hi3798cv200
+
+ - description: Hi4511 Board
+ items:
+ - const: hisilicon,hi3620-hi4511
+
+ - description: Hi6220 based boards.
+ items:
+ - const: hisilicon,hi6220-hikey
+ - const: hisilicon,hi6220
+
+ - description: HiP01 based boards.
+ items:
+ - const: hisilicon,hip01-ca9x2
+ - const: hisilicon,hip01
+
+ - description: HiP04 D01 Board
+ items:
+ - const: hisilicon,hip04-d01
+
+ - description: HiP05 D02 Board
+ items:
+ - const: hisilicon,hip05-d02
+
+ - description: HiP06 D03 Board
+ items:
+ - const: hisilicon,hip06-d03
+
+ - description: HiP07 D05 Board
+ items:
+ - const: hisilicon,hip07-d05
+
+ - description: SD5203 based boards
+ items:
+ - const: H836ASDJ
+ - const: hisilicon,sd5203
+...
diff --git a/dts/Bindings/arm/hisilicon/low-pin-count.yaml b/dts/Bindings/arm/hisilicon/low-pin-count.yaml
new file mode 100644
index 0000000000..3b36e683bb
--- /dev/null
+++ b/dts/Bindings/arm/hisilicon/low-pin-count.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/low-pin-count.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon HiP06 Low Pin Count device
+
+maintainers:
+ - Wei Xu <xuwei5@hisilicon.com>
+
+description: |
+ Hisilicon HiP06 SoCs implement a Low Pin Count (LPC) controller, which
+ provides I/O access to some legacy ISA devices.
+ HiP06 is based on arm64 architecture where there is no I/O space. So, the
+ I/O ports here are not CPU addresses, and there is no 'ranges' property in
+ LPC device node.
+
+properties:
+ $nodename:
+ pattern: '^isa@[0-9a-f]+$'
+ description: |
+ The node name before '@' must be "isa" to represent the binding stick
+ to the ISA/EISA binding specification.
+
+ compatible:
+ enum:
+ - hisilicon,hip06-lpc
+ - hisilicon,hip07-lpc
+
+ reg:
+ maxItems: 1
+
+ '#address-cells':
+ const: 2
+
+ '#size-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties:
+ type: object
+
+examples:
+ - |
+ isa@a01b0000 {
+ compatible = "hisilicon,hip06-lpc";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ reg = <0xa01b0000 0x1000>;
+
+ ipmi0: bt@e4 {
+ compatible = "ipmi-bt";
+ device_type = "ipmi";
+ reg = <0x01 0xe4 0x04>;
+ };
+ };
+...
diff --git a/dts/Bindings/arm/intel-ixp4xx.yaml b/dts/Bindings/arm/intel-ixp4xx.yaml
index f4f7451e5e..f18302efb9 100644
--- a/dts/Bindings/arm/intel-ixp4xx.yaml
+++ b/dts/Bindings/arm/intel-ixp4xx.yaml
@@ -10,6 +10,8 @@ maintainers:
- Linus Walleij <linus.walleij@linaro.org>
properties:
+ $nodename:
+ const: "/"
compatible:
oneOf:
- items:
diff --git a/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt b/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt
index bd7a0fa580..ea827e8763 100644
--- a/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,apmixedsys.txt
@@ -15,6 +15,7 @@ Required Properties:
- "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
- "mediatek,mt7629-apmixedsys"
- "mediatek,mt8135-apmixedsys"
+ - "mediatek,mt8167-apmixedsys", "syscon"
- "mediatek,mt8173-apmixedsys"
- "mediatek,mt8183-apmixedsys", "syscon"
- "mediatek,mt8516-apmixedsys"
diff --git a/dts/Bindings/arm/mediatek/mediatek,audsys.txt b/dts/Bindings/arm/mediatek/mediatek,audsys.txt
index 38309db115..b32d374193 100644
--- a/dts/Bindings/arm/mediatek/mediatek,audsys.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,audsys.txt
@@ -11,6 +11,7 @@ Required Properties:
- "mediatek,mt6779-audio", "syscon"
- "mediatek,mt7622-audsys", "syscon"
- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
+ - "mediatek,mt8167-audiosys", "syscon"
- "mediatek,mt8183-audiosys", "syscon"
- "mediatek,mt8516-audsys", "syscon"
- #clock-cells: Must be 1
diff --git a/dts/Bindings/arm/mediatek/mediatek,imgsys.txt b/dts/Bindings/arm/mediatek/mediatek,imgsys.txt
index 1e1f00718a..dce4c92419 100644
--- a/dts/Bindings/arm/mediatek/mediatek,imgsys.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,imgsys.txt
@@ -12,6 +12,7 @@ Required Properties:
- "mediatek,mt6779-imgsys", "syscon"
- "mediatek,mt6797-imgsys", "syscon"
- "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
+ - "mediatek,mt8167-imgsys", "syscon"
- "mediatek,mt8173-imgsys", "syscon"
- "mediatek,mt8183-imgsys", "syscon"
- #clock-cells: Must be 1
diff --git a/dts/Bindings/arm/mediatek/mediatek,infracfg.txt b/dts/Bindings/arm/mediatek/mediatek,infracfg.txt
index 49a968be1a..eb3523c7a7 100644
--- a/dts/Bindings/arm/mediatek/mediatek,infracfg.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,infracfg.txt
@@ -16,6 +16,7 @@ Required Properties:
- "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
- "mediatek,mt7629-infracfg", "syscon"
- "mediatek,mt8135-infracfg", "syscon"
+ - "mediatek,mt8167-infracfg", "syscon"
- "mediatek,mt8173-infracfg", "syscon"
- "mediatek,mt8183-infracfg", "syscon"
- "mediatek,mt8516-infracfg", "syscon"
diff --git a/dts/Bindings/arm/mediatek/mediatek,mfgcfg.txt b/dts/Bindings/arm/mediatek/mediatek,mfgcfg.txt
index ad5f9d2f68..054424fb64 100644
--- a/dts/Bindings/arm/mediatek/mediatek,mfgcfg.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,mfgcfg.txt
@@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be one of:
- "mediatek,mt2712-mfgcfg", "syscon"
- "mediatek,mt6779-mfgcfg", "syscon"
+ - "mediatek,mt8167-mfgcfg", "syscon"
- "mediatek,mt8183-mfgcfg", "syscon"
- #clock-cells: Must be 1
diff --git a/dts/Bindings/arm/mediatek/mediatek,pericfg.yaml b/dts/Bindings/arm/mediatek/mediatek,pericfg.yaml
index 1af30174b2..8723dfe34b 100644
--- a/dts/Bindings/arm/mediatek/mediatek,pericfg.yaml
+++ b/dts/Bindings/arm/mediatek/mediatek,pericfg.yaml
@@ -47,6 +47,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
pericfg@10003000 {
diff --git a/dts/Bindings/arm/mediatek/mediatek,topckgen.txt b/dts/Bindings/arm/mediatek/mediatek,topckgen.txt
index 9b0394cbbd..5ce7578cf2 100644
--- a/dts/Bindings/arm/mediatek/mediatek,topckgen.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,topckgen.txt
@@ -15,6 +15,7 @@ Required Properties:
- "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
- "mediatek,mt7629-topckgen"
- "mediatek,mt8135-topckgen"
+ - "mediatek,mt8167-topckgen", "syscon"
- "mediatek,mt8173-topckgen"
- "mediatek,mt8183-topckgen", "syscon"
- "mediatek,mt8516-topckgen"
diff --git a/dts/Bindings/arm/mediatek/mediatek,vdecsys.txt b/dts/Bindings/arm/mediatek/mediatek,vdecsys.txt
index 7894558b7a..9819516917 100644
--- a/dts/Bindings/arm/mediatek/mediatek,vdecsys.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,vdecsys.txt
@@ -11,6 +11,7 @@ Required Properties:
- "mediatek,mt6779-vdecsys", "syscon"
- "mediatek,mt6797-vdecsys", "syscon"
- "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
+ - "mediatek,mt8167-vdecsys", "syscon"
- "mediatek,mt8173-vdecsys", "syscon"
- "mediatek,mt8183-vdecsys", "syscon"
- #clock-cells: Must be 1
diff --git a/dts/Bindings/arm/nvidia,tegra194-ccplex.yaml b/dts/Bindings/arm/nvidia,tegra194-ccplex.yaml
index 1043e4be4f..c9675c4cdc 100644
--- a/dts/Bindings/arm/nvidia,tegra194-ccplex.yaml
+++ b/dts/Bindings/arm/nvidia,tegra194-ccplex.yaml
@@ -30,6 +30,8 @@ properties:
Specifies the bpmp node that needs to be queried to get
operating point data for all CPUs.
+additionalProperties: true
+
examples:
- |
cpus {
diff --git a/dts/Bindings/arm/omap/prm-inst.txt b/dts/Bindings/arm/omap/prm-inst.txt
index fcd3456afb..42db138e09 100644
--- a/dts/Bindings/arm/omap/prm-inst.txt
+++ b/dts/Bindings/arm/omap/prm-inst.txt
@@ -18,6 +18,7 @@ Required properties:
(base address and length)
Optional properties:
+- #power-domain-cells: Should be 0 if the instance is a power domain provider.
- #reset-cells: Should be 1 if the PRM instance in question supports resets.
Example:
@@ -25,5 +26,6 @@ Example:
prm_dsp2: prm@1b00 {
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
reg = <0x1b00 0x40>;
+ #power-domain-cells = <0>;
#reset-cells = <1>;
};
diff --git a/dts/Bindings/arm/pmu.yaml b/dts/Bindings/arm/pmu.yaml
index 97df36d301..693ef3f185 100644
--- a/dts/Bindings/arm/pmu.yaml
+++ b/dts/Bindings/arm/pmu.yaml
@@ -93,4 +93,6 @@ properties:
required:
- compatible
+additionalProperties: false
+
...
diff --git a/dts/Bindings/arm/primecell.yaml b/dts/Bindings/arm/primecell.yaml
index 5aae37f1c5..e15fe00aaf 100644
--- a/dts/Bindings/arm/primecell.yaml
+++ b/dts/Bindings/arm/primecell.yaml
@@ -33,4 +33,7 @@ properties:
contains:
const: apb_pclk
additionalItems: true
+
+additionalProperties: true
+
...
diff --git a/dts/Bindings/arm/qcom.yaml b/dts/Bindings/arm/qcom.yaml
index 6031aee0f5..ad25deba4d 100644
--- a/dts/Bindings/arm/qcom.yaml
+++ b/dts/Bindings/arm/qcom.yaml
@@ -40,6 +40,7 @@ description: |
sdm630
sdm660
sdm845
+ sm8250
The 'board' element must be one of the following strings:
@@ -47,6 +48,8 @@ description: |
cp01-c1
dragonboard
hk01
+ hk10-c1
+ hk10-c2
idp
liquid
mtp
@@ -73,6 +76,8 @@ description: |
foundry 2.
properties:
+ $nodename:
+ const: "/"
compatible:
oneOf:
- items:
@@ -148,6 +153,8 @@ properties:
- items:
- enum:
- qcom,ipq8074-hk01
+ - qcom,ipq8074-hk10-c1
+ - qcom,ipq8074-hk10-c2
- const: qcom,ipq8074
- items:
@@ -165,4 +172,10 @@ properties:
- qcom,ipq6018-cp01-c1
- const: qcom,ipq6018
+ - items:
+ - enum:
+ - qcom,qrb5165-rb5
+ - qcom,sm8250-mtp
+ - const: qcom,sm8250
+
...
diff --git a/dts/Bindings/arm/rda.yaml b/dts/Bindings/arm/rda.yaml
index 51cec2b63b..9672aa0c76 100644
--- a/dts/Bindings/arm/rda.yaml
+++ b/dts/Bindings/arm/rda.yaml
@@ -10,6 +10,8 @@ maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
properties:
+ $nodename:
+ const: "/"
compatible:
items:
- enum:
diff --git a/dts/Bindings/arm/renesas.yaml b/dts/Bindings/arm/renesas.yaml
index 0d4dabb4a1..01a6d0c571 100644
--- a/dts/Bindings/arm/renesas.yaml
+++ b/dts/Bindings/arm/renesas.yaml
@@ -281,6 +281,18 @@ properties:
- renesas,draak # Draak (RTP0RC77995SEB0010S)
- const: renesas,r8a77995
+ - description: R-Car V3U (R8A779A0)
+ items:
+ - enum:
+ - renesas,falcon-cpu # Falcon CPU board (RTP0RC779A0CPB0010S)
+ - const: renesas,r8a779a0
+
+ - items:
+ - enum:
+ - renesas,falcon-breakout # Falcon BreakOut board (RTP0RC779A0BOB0010S)
+ - const: renesas,falcon-cpu
+ - const: renesas,r8a779a0
+
- description: RZ/N1D (R9A06G032)
items:
- enum:
diff --git a/dts/Bindings/arm/rockchip.yaml b/dts/Bindings/arm/rockchip.yaml
index db2e357967..65b4cc2c63 100644
--- a/dts/Bindings/arm/rockchip.yaml
+++ b/dts/Bindings/arm/rockchip.yaml
@@ -104,6 +104,11 @@ properties:
- firefly,roc-rk3399-pc-mezzanine
- const: rockchip,rk3399
+ - description: FriendlyElec NanoPi R2S
+ items:
+ - const: friendlyarm,nanopi-r2s
+ - const: rockchip,rk3328
+
- description: FriendlyElec NanoPi4 series boards
items:
- enum:
@@ -430,8 +435,12 @@ properties:
- const: radxa,rock
- const: rockchip,rk3188
- - description: Radxa ROCK Pi 4
+ - description: Radxa ROCK Pi 4A/B/C
items:
+ - enum:
+ - radxa,rockpi4a
+ - radxa,rockpi4b
+ - radxa,rockpi4c
- const: radxa,rockpi4
- const: rockchip,rk3399
@@ -555,4 +564,9 @@ properties:
items:
- const: tronsmart,orion-r68-meta
- const: rockchip,rk3368
+
+ - description: Zkmagic A95X Z2
+ items:
+ - const: zkmagic,a95x-z2
+ - const: rockchip,rk3318
...
diff --git a/dts/Bindings/arm/samsung/pmu.yaml b/dts/Bindings/arm/samsung/pmu.yaml
index c965189271..17678d9686 100644
--- a/dts/Bindings/arm/samsung/pmu.yaml
+++ b/dts/Bindings/arm/samsung/pmu.yaml
@@ -24,6 +24,7 @@ select:
- samsung,exynos5420-pmu
- samsung,exynos5433-pmu
- samsung,exynos7-pmu
+ - samsung-s5pv210-pmu
required:
- compatible
@@ -40,11 +41,15 @@ properties:
- samsung,exynos5420-pmu
- samsung,exynos5433-pmu
- samsung,exynos7-pmu
+ - samsung-s5pv210-pmu
- const: syscon
reg:
maxItems: 1
+ assigned-clock-parents: true
+ assigned-clocks: true
+
'#clock-cells':
const: 1
@@ -85,12 +90,28 @@ properties:
required:
- compatible
- reg
- - '#clock-cells'
- - clock-names
- - clocks
additionalProperties: false
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,exynos3250-pmu
+ - samsung,exynos4210-pmu
+ - samsung,exynos4412-pmu
+ - samsung,exynos5250-pmu
+ - samsung,exynos5410-pmu
+ - samsung,exynos5420-pmu
+ - samsung,exynos5433-pmu
+ then:
+ required:
+ - '#clock-cells'
+ - clock-names
+ - clocks
+
examples:
- |
#include <dt-bindings/clock/exynos5250.h>
diff --git a/dts/Bindings/arm/samsung/sysreg.yaml b/dts/Bindings/arm/samsung/sysreg.yaml
deleted file mode 100644
index 3b7811804c..0000000000
--- a/dts/Bindings/arm/samsung/sysreg.yaml
+++ /dev/null
@@ -1,45 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/arm/samsung/sysreg.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Samsung S5P/Exynos SoC series System Registers (SYSREG)
-
-maintainers:
- - Krzysztof Kozlowski <krzk@kernel.org>
-
-# Custom select to avoid matching all nodes with 'syscon'
-select:
- properties:
- compatible:
- contains:
- enum:
- - samsung,exynos4-sysreg
- - samsung,exynos5-sysreg
- required:
- - compatible
-
-properties:
- compatible:
- allOf:
- - items:
- - enum:
- - samsung,exynos4-sysreg
- - samsung,exynos5-sysreg
- - const: syscon
-
- reg:
- maxItems: 1
-
-examples:
- - |
- syscon@10010000 {
- compatible = "samsung,exynos4-sysreg", "syscon";
- reg = <0x10010000 0x400>;
- };
-
- syscon@10050000 {
- compatible = "samsung,exynos5-sysreg", "syscon";
- reg = <0x10050000 0x5000>;
- };
diff --git a/dts/Bindings/arm/stm32/st,mlahb.yaml b/dts/Bindings/arm/stm32/st,mlahb.yaml
index 9f276bc9ef..8e711bd202 100644
--- a/dts/Bindings/arm/stm32/st,mlahb.yaml
+++ b/dts/Bindings/arm/stm32/st,mlahb.yaml
@@ -50,6 +50,8 @@ required:
- '#size-cells'
- dma-ranges
+unevaluatedProperties: false
+
examples:
- |
mlahb: ahb@38000000 {
diff --git a/dts/Bindings/arm/stm32/stm32.yaml b/dts/Bindings/arm/stm32/stm32.yaml
index 790e6dd48e..deacb4e686 100644
--- a/dts/Bindings/arm/stm32/stm32.yaml
+++ b/dts/Bindings/arm/stm32/stm32.yaml
@@ -10,6 +10,8 @@ maintainers:
- Alexandre Torgue <alexandre.torgue@st.com>
properties:
+ $nodename:
+ const: "/"
compatible:
oneOf:
- items:
@@ -50,4 +52,10 @@ properties:
- const: st,stm32mp157c-ev1
- const: st,stm32mp157c-ed1
- const: st,stm32mp157
+ - description: Odyssey STM32MP1 SoM based Boards
+ items:
+ - enum:
+ - seeed,stm32mp157c-odyssey
+ - const: seeed,stm32mp157c-odyssey-som
+ - const: st,stm32mp157
...
diff --git a/dts/Bindings/arm/sunxi.yaml b/dts/Bindings/arm/sunxi.yaml
index efc9118233..afa00268c7 100644
--- a/dts/Bindings/arm/sunxi.yaml
+++ b/dts/Bindings/arm/sunxi.yaml
@@ -16,6 +16,11 @@ properties:
compatible:
oneOf:
+ - description: Allwinner A100 Perf1 Board
+ items:
+ - const: allwinner,a100-perf1
+ - const: allwinner,sun50i-a100
+
- description: Allwinner A23 Evaluation Board
items:
- const: allwinner,sun8i-a23-evb
@@ -626,6 +631,11 @@ properties:
- const: pine64,pine64-plus
- const: allwinner,sun50i-a64
+ - description: Pine64 PineCube
+ items:
+ - const: pine64,pinecube
+ - const: allwinner,sun8i-s3
+
- description: Pine64 PineH64 model A
items:
- const: pine64,pine-h64
diff --git a/dts/Bindings/arm/tegra.yaml b/dts/Bindings/arm/tegra.yaml
index e0b3debaee..8ae44948e8 100644
--- a/dts/Bindings/arm/tegra.yaml
+++ b/dts/Bindings/arm/tegra.yaml
@@ -11,6 +11,8 @@ maintainers:
- Jonathan Hunter <jonathanh@nvidia.com>
properties:
+ $nodename:
+ const: "/"
compatible:
oneOf:
- items:
@@ -119,3 +121,7 @@ properties:
items:
- const: nvidia,p3509-0000+p3668-0000
- const: nvidia,tegra194
+ - items:
+ - enum:
+ - nvidia,tegra234-vdk
+ - const: nvidia,tegra234
diff --git a/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt b/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt
index 2d89cdc39e..576462fae2 100644
--- a/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt
+++ b/dts/Bindings/arm/tegra/nvidia,tegra186-pmc.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible: Should contain one of the following:
- "nvidia,tegra186-pmc": for Tegra186
- "nvidia,tegra194-pmc": for Tegra194
+ - "nvidia,tegra234-pmc": for Tegra234
- reg: Must contain an (offset, length) pair of the register set for each
entry in reg-names.
- reg-names: Must include the following entries:
@@ -11,7 +12,7 @@ Required properties:
- "wake"
- "aotag"
- "scratch"
- - "misc" (Only for Tegra194)
+ - "misc" (Only for Tegra194 and later)
Optional properties:
- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal.
diff --git a/dts/Bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/dts/Bindings/arm/tegra/nvidia,tegra20-pmc.yaml
index b71a20af5f..43fd2f8927 100644
--- a/dts/Bindings/arm/tegra/nvidia,tegra20-pmc.yaml
+++ b/dts/Bindings/arm/tegra/nvidia,tegra20-pmc.yaml
@@ -308,6 +308,8 @@ required:
- clocks
- '#clock-cells'
+additionalProperties: false
+
dependencies:
"nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"]
"nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"]
diff --git a/dts/Bindings/arm/ti/k3.txt b/dts/Bindings/arm/ti/k3.txt
deleted file mode 100644
index 333e725612..0000000000
--- a/dts/Bindings/arm/ti/k3.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-Texas Instruments K3 Multicore SoC architecture device tree bindings
---------------------------------------------------------------------
-
-Platforms based on Texas Instruments K3 Multicore SoC architecture
-shall follow the following scheme:
-
-SoCs
-----
-
-Each device tree root node must specify which exact SoC in K3 Multicore SoC
-architecture it uses, using one of the following compatible values:
-
-- AM654
- compatible = "ti,am654";
-
-- J721E
- compatible = "ti,j721e";
-
-Boards
-------
-
-In addition, each device tree root node must specify which one or more
-of the following board-specific compatible values:
-
-- AM654 EVM
- compatible = "ti,am654-evm", "ti,am654";
diff --git a/dts/Bindings/arm/ti/k3.yaml b/dts/Bindings/arm/ti/k3.yaml
new file mode 100644
index 0000000000..8297512095
--- /dev/null
+++ b/dts/Bindings/arm/ti/k3.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/ti/k3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments K3 Multicore SoC architecture device tree bindings
+
+maintainers:
+ - Nishanth Menon <nm@ti.com>
+
+description: |
+ Platforms based on Texas Instruments K3 Multicore SoC architecture
+ shall have the following properties.
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+
+ - description: K3 AM654 SoC
+ items:
+ - enum:
+ - ti,am654-evm
+ - const: ti,am654
+
+ - description: K3 J721E SoC
+ items:
+ - const: ti,j721e
+
+ - description: K3 J7200 SoC
+ items:
+ - const: ti,j7200
+...
diff --git a/dts/Bindings/arm/toshiba.yaml b/dts/Bindings/arm/toshiba.yaml
new file mode 100644
index 0000000000..0e06629023
--- /dev/null
+++ b/dts/Bindings/arm/toshiba.yaml
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/toshiba.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Toshiba Visconti Platform Device Tree Bindings
+
+maintainers:
+ - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: Visconti5 TMPV7708
+ items:
+ - enum:
+ - toshiba,tmpv7708-rm-mbrc # TMPV7708 RM main board
+ - const: toshiba,tmpv7708
+...
diff --git a/dts/Bindings/ata/faraday,ftide010.yaml b/dts/Bindings/ata/faraday,ftide010.yaml
index 6451928dd2..fa16f3767c 100644
--- a/dts/Bindings/ata/faraday,ftide010.yaml
+++ b/dts/Bindings/ata/faraday,ftide010.yaml
@@ -64,6 +64,8 @@ allOf:
required:
- sata
+unevaluatedProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
diff --git a/dts/Bindings/ata/imx-sata.txt b/dts/Bindings/ata/imx-sata.txt
deleted file mode 100644
index 781f887517..0000000000
--- a/dts/Bindings/ata/imx-sata.txt
+++ /dev/null
@@ -1,37 +0,0 @@
-* Freescale i.MX AHCI SATA Controller
-
-The Freescale i.MX SATA controller mostly conforms to the AHCI interface
-with some special extensions at integration level.
-
-Required properties:
-- compatible : should be one of the following:
- - "fsl,imx53-ahci" for i.MX53 SATA controller
- - "fsl,imx6q-ahci" for i.MX6Q SATA controller
- - "fsl,imx6qp-ahci" for i.MX6QP SATA controller
-- interrupts : interrupt mapping for SATA IRQ
-- reg : registers mapping
-- clocks : list of clock specifiers, must contain an entry for each
- required entry in clock-names
-- clock-names : should include "sata", "sata_ref" and "ahb" entries
-
-Optional properties:
-- fsl,transmit-level-mV : transmit voltage level, in millivolts.
-- fsl,transmit-boost-mdB : transmit boost level, in milli-decibels
-- fsl,transmit-atten-16ths : transmit attenuation, in 16ths
-- fsl,receive-eq-mdB : receive equalisation, in milli-decibels
- Please refer to the technical documentation or the driver source code
- for the list of legal values for these options.
-- fsl,no-spread-spectrum : disable spread-spectrum clocking on the SATA
- link.
-
-Examples:
-
-sata@2200000 {
- compatible = "fsl,imx6q-ahci";
- reg = <0x02200000 0x4000>;
- interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_SATA>,
- <&clks IMX6QDL_CLK_SATA_REF_100M>,
- <&clks IMX6QDL_CLK_AHB>;
- clock-names = "sata", "sata_ref", "ahb";
-};
diff --git a/dts/Bindings/ata/imx-sata.yaml b/dts/Bindings/ata/imx-sata.yaml
new file mode 100644
index 0000000000..68ffb97ddc
--- /dev/null
+++ b/dts/Bindings/ata/imx-sata.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ata/imx-sata.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX AHCI SATA Controller
+
+maintainers:
+ - Shawn Guo <shawn.guo@linaro.org>
+
+description: |
+ The Freescale i.MX SATA controller mostly conforms to the AHCI interface
+ with some special extensions at integration level.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx53-ahci
+ - fsl,imx6q-ahci
+ - fsl,imx6qp-ahci
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: sata clock
+ - description: sata reference clock
+ - description: ahb clock
+
+ clock-names:
+ items:
+ - const: sata
+ - const: sata_ref
+ - const: ahb
+
+ fsl,transmit-level-mV:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: transmit voltage level, in millivolts.
+
+ fsl,transmit-boost-mdB:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: transmit boost level, in milli-decibels.
+
+ fsl,transmit-atten-16ths:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: transmit attenuation, in 16ths.
+
+ fsl,receive-eq-mdB:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: receive equalisation, in milli-decibels.
+
+ fsl,no-spread-spectrum:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: if present, disable spread-spectrum clocking on the SATA link.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx6qdl-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ sata@2200000 {
+ compatible = "fsl,imx6q-ahci";
+ reg = <0x02200000 0x4000>;
+ interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_SATA>,
+ <&clks IMX6QDL_CLK_SATA_REF_100M>,
+ <&clks IMX6QDL_CLK_AHB>;
+ clock-names = "sata", "sata_ref", "ahb";
+ };
diff --git a/dts/Bindings/ata/pata-common.yaml b/dts/Bindings/ata/pata-common.yaml
index fc5ebbe710..2412894a25 100644
--- a/dts/Bindings/ata/pata-common.yaml
+++ b/dts/Bindings/ata/pata-common.yaml
@@ -47,4 +47,6 @@ patternProperties:
The ID number of the drive port, 0 for the master port and 1 for the
slave port.
+additionalProperties: true
+
...
diff --git a/dts/Bindings/ata/sata-common.yaml b/dts/Bindings/ata/sata-common.yaml
index 6783a4dec6..7ac77b1c58 100644
--- a/dts/Bindings/ata/sata-common.yaml
+++ b/dts/Bindings/ata/sata-common.yaml
@@ -47,4 +47,6 @@ patternProperties:
multiplier making it possible to connect up to 15 disks to a single
SATA port.
+additionalProperties: true
+
...
diff --git a/dts/Bindings/bus/brcm,gisb-arb.txt b/dts/Bindings/bus/brcm,gisb-arb.txt
index 729def62f0..10f6d0a815 100644
--- a/dts/Bindings/bus/brcm,gisb-arb.txt
+++ b/dts/Bindings/bus/brcm,gisb-arb.txt
@@ -10,7 +10,8 @@ Required properties:
"brcm,bcm7038-gisb-arb" for 130nm chips
- reg: specifies the base physical address and size of the registers
- interrupts: specifies the two interrupts (timeout and TEA) to be used from
- the parent interrupt controller
+ the parent interrupt controller. A third optional interrupt may be specified
+ for breakpoints.
Optional properties:
diff --git a/dts/Bindings/bus/mti,mips-cdmm.yaml b/dts/Bindings/bus/mti,mips-cdmm.yaml
index 9cc2d5f1be..6a7b26b049 100644
--- a/dts/Bindings/bus/mti,mips-cdmm.yaml
+++ b/dts/Bindings/bus/mti,mips-cdmm.yaml
@@ -26,6 +26,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
cdmm@1bde8000 {
diff --git a/dts/Bindings/bus/renesas,bsc.yaml b/dts/Bindings/bus/renesas,bsc.yaml
index 7d10b62a52..f53a377854 100644
--- a/dts/Bindings/bus/renesas,bsc.yaml
+++ b/dts/Bindings/bus/renesas,bsc.yaml
@@ -44,6 +44,8 @@ properties:
required:
- reg
+unevaluatedProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
diff --git a/dts/Bindings/bus/simple-pm-bus.yaml b/dts/Bindings/bus/simple-pm-bus.yaml
index 33326ffdb2..182134d7a6 100644
--- a/dts/Bindings/bus/simple-pm-bus.yaml
+++ b/dts/Bindings/bus/simple-pm-bus.yaml
@@ -61,6 +61,8 @@ anyOf:
- required:
- power-domains
+additionalProperties: true
+
examples:
- |
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
diff --git a/dts/Bindings/bus/socionext,uniphier-system-bus.yaml b/dts/Bindings/bus/socionext,uniphier-system-bus.yaml
index a0c6c5d2b7..49df13fc2f 100644
--- a/dts/Bindings/bus/socionext,uniphier-system-bus.yaml
+++ b/dts/Bindings/bus/socionext,uniphier-system-bus.yaml
@@ -57,6 +57,11 @@ properties:
"ranges" property should provide a "reasonable" default that is known to
work. The software should initialize the bus controller according to it.
+patternProperties:
+ "^.*@[1-5],[1-9a-f][0-9a-f]+$":
+ description: Devices attached to chip selects
+ type: object
+
required:
- compatible
- reg
@@ -64,6 +69,8 @@ required:
- "#size-cells"
- ranges
+additionalProperties: false
+
examples:
- |
// In this example,
diff --git a/dts/Bindings/chrome/google,cros-ec-typec.yaml b/dts/Bindings/chrome/google,cros-ec-typec.yaml
index 6d7396ab8b..2d98f7c4d3 100644
--- a/dts/Bindings/chrome/google,cros-ec-typec.yaml
+++ b/dts/Bindings/chrome/google,cros-ec-typec.yaml
@@ -26,6 +26,8 @@ properties:
required:
- compatible
+additionalProperties: true #fixme
+
examples:
- |+
spi0 {
diff --git a/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml b/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml
index 4d382128b7..3b45344ed7 100644
--- a/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml
+++ b/dts/Bindings/clock/allwinner,sun4i-a10-ccu.yaml
@@ -36,6 +36,8 @@ properties:
- allwinner,sun9i-a80-ccu
- allwinner,sun50i-a64-ccu
- allwinner,sun50i-a64-r-ccu
+ - allwinner,sun50i-a100-ccu
+ - allwinner,sun50i-a100-r-ccu
- allwinner,sun50i-h5-ccu
- allwinner,sun50i-h6-ccu
- allwinner,sun50i-h6-r-ccu
@@ -78,6 +80,7 @@ if:
- allwinner,sun8i-a83t-r-ccu
- allwinner,sun8i-h3-r-ccu
- allwinner,sun50i-a64-r-ccu
+ - allwinner,sun50i-a100-r-ccu
- allwinner,sun50i-h6-r-ccu
then:
@@ -94,7 +97,9 @@ else:
if:
properties:
compatible:
- const: allwinner,sun50i-h6-ccu
+ enum:
+ - allwinner,sun50i-a100-ccu
+ - allwinner,sun50i-h6-ccu
then:
properties:
diff --git a/dts/Bindings/clock/arm,syscon-icst.yaml b/dts/Bindings/clock/arm,syscon-icst.yaml
index 444aeea27d..eb241587ef 100644
--- a/dts/Bindings/clock/arm,syscon-icst.yaml
+++ b/dts/Bindings/clock/arm,syscon-icst.yaml
@@ -89,6 +89,8 @@ required:
- compatible
- clocks
+additionalProperties: false
+
examples:
- |
vco1: clock {
diff --git a/dts/Bindings/clock/baikal,bt1-ccu-div.yaml b/dts/Bindings/clock/baikal,bt1-ccu-div.yaml
index 2821425ee4..bd4cefbb12 100644
--- a/dts/Bindings/clock/baikal,bt1-ccu-div.yaml
+++ b/dts/Bindings/clock/baikal,bt1-ccu-div.yaml
@@ -134,7 +134,11 @@ properties:
"#reset-cells":
const: 1
-unevaluatedProperties: false
+ clocks: true
+
+ clock-names: true
+
+additionalProperties: false
required:
- compatible
diff --git a/dts/Bindings/clock/baikal,bt1-ccu-pll.yaml b/dts/Bindings/clock/baikal,bt1-ccu-pll.yaml
index 97131bfa6f..624984d51c 100644
--- a/dts/Bindings/clock/baikal,bt1-ccu-pll.yaml
+++ b/dts/Bindings/clock/baikal,bt1-ccu-pll.yaml
@@ -101,7 +101,7 @@ properties:
clock-names:
const: ref_clk
-unevaluatedProperties: false
+additionalProperties: false
required:
- compatible
diff --git a/dts/Bindings/clock/idt,versaclock5.yaml b/dts/Bindings/clock/idt,versaclock5.yaml
index 28c6461b9a..2ac1131fd9 100644
--- a/dts/Bindings/clock/idt,versaclock5.yaml
+++ b/dts/Bindings/clock/idt,versaclock5.yaml
@@ -50,6 +50,15 @@ properties:
'#clock-cells':
const: 1
+ clock-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ enum: [ xin, clkin ]
+ clocks:
+ minItems: 1
+ maxItems: 2
+
patternProperties:
"^OUT[1-4]$":
type: object
@@ -93,19 +102,12 @@ allOf:
maxItems: 1
else:
# Devices without builtin crystal
- properties:
- clock-names:
- minItems: 1
- maxItems: 2
- items:
- enum: [ xin, clkin ]
- clocks:
- minItems: 1
- maxItems: 2
required:
- clock-names
- clocks
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clk/versaclock.h>
diff --git a/dts/Bindings/clock/imx23-clock.yaml b/dts/Bindings/clock/imx23-clock.yaml
index ad21899981..5e296a00e1 100644
--- a/dts/Bindings/clock/imx23-clock.yaml
+++ b/dts/Bindings/clock/imx23-clock.yaml
@@ -87,6 +87,8 @@ examples:
serial@8006c000 {
compatible = "fsl,imx23-auart";
reg = <0x8006c000 0x2000>;
- interrupts = <24 25 23>;
+ interrupts = <24>;
clocks = <&clks 32>;
+ dmas = <&dma_apbx 6>, <&dma_apbx 7>;
+ dma-names = "rx", "tx";
};
diff --git a/dts/Bindings/clock/imx28-clock.yaml b/dts/Bindings/clock/imx28-clock.yaml
index f1af110812..f831b780f9 100644
--- a/dts/Bindings/clock/imx28-clock.yaml
+++ b/dts/Bindings/clock/imx28-clock.yaml
@@ -108,8 +108,10 @@ examples:
};
serial@8006a000 {
- compatible = "fsl,imx28-auart", "fsl,imx23-auart";
+ compatible = "fsl,imx28-auart";
reg = <0x8006a000 0x2000>;
- interrupts = <112 70 71>;
+ interrupts = <112>;
+ dmas = <&dma_apbx 8>, <&dma_apbx 9>;
+ dma-names = "rx", "tx";
clocks = <&clks 45>;
};
diff --git a/dts/Bindings/clock/imx6q-clock.yaml b/dts/Bindings/clock/imx6q-clock.yaml
index 92a8e545e2..4f4637eddb 100644
--- a/dts/Bindings/clock/imx6q-clock.yaml
+++ b/dts/Bindings/clock/imx6q-clock.yaml
@@ -57,6 +57,8 @@ required:
- interrupts
- '#clock-cells'
+additionalProperties: false
+
examples:
# Clock Control Module node:
- |
diff --git a/dts/Bindings/clock/imx6sl-clock.yaml b/dts/Bindings/clock/imx6sl-clock.yaml
index c97bf95b41..b83c8f43d6 100644
--- a/dts/Bindings/clock/imx6sl-clock.yaml
+++ b/dts/Bindings/clock/imx6sl-clock.yaml
@@ -33,6 +33,8 @@ required:
- interrupts
- '#clock-cells'
+additionalProperties: false
+
examples:
# Clock Control Module node:
- |
diff --git a/dts/Bindings/clock/imx6sll-clock.yaml b/dts/Bindings/clock/imx6sll-clock.yaml
index de48924be1..484894a4b2 100644
--- a/dts/Bindings/clock/imx6sll-clock.yaml
+++ b/dts/Bindings/clock/imx6sll-clock.yaml
@@ -49,6 +49,8 @@ required:
- clocks
- clock-names
+additionalProperties: false
+
examples:
# Clock Control Module node:
- |
diff --git a/dts/Bindings/clock/imx6sx-clock.yaml b/dts/Bindings/clock/imx6sx-clock.yaml
index e50cddee43..e6c795657c 100644
--- a/dts/Bindings/clock/imx6sx-clock.yaml
+++ b/dts/Bindings/clock/imx6sx-clock.yaml
@@ -53,6 +53,8 @@ required:
- clocks
- clock-names
+additionalProperties: false
+
examples:
# Clock Control Module node:
- |
diff --git a/dts/Bindings/clock/imx6ul-clock.yaml b/dts/Bindings/clock/imx6ul-clock.yaml
index 36ce7667c9..6a51a3f51c 100644
--- a/dts/Bindings/clock/imx6ul-clock.yaml
+++ b/dts/Bindings/clock/imx6ul-clock.yaml
@@ -49,6 +49,8 @@ required:
- clocks
- clock-names
+additionalProperties: false
+
examples:
# Clock Control Module node:
- |
diff --git a/dts/Bindings/clock/imx8m-clock.yaml b/dts/Bindings/clock/imx8m-clock.yaml
new file mode 100644
index 0000000000..625f573a7b
--- /dev/null
+++ b/dts/Bindings/clock/imx8m-clock.yaml
@@ -0,0 +1,125 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/imx8m-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8M Family Clock Control Module Binding
+
+maintainers:
+ - Anson Huang <Anson.Huang@nxp.com>
+
+description: |
+ NXP i.MX8M Mini/Nano/Plus/Quad clock control module is an integrated clock
+ controller, which generates and supplies to all modules.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8mm-ccm
+ - fsl,imx8mn-ccm
+ - fsl,imx8mp-ccm
+ - fsl,imx8mq-ccm
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 6
+ maxItems: 7
+
+ clock-names:
+ minItems: 6
+ maxItems: 7
+
+ '#clock-cells':
+ const: 1
+ description:
+ The clock consumer should specify the desired clock by having the clock
+ ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m-clock.h
+ for the full list of i.MX8M clock IDs.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8mq-ccm
+ then:
+ properties:
+ clocks:
+ minItems: 7
+ maxItems: 7
+ items:
+ - description: 32k osc
+ - description: 25m osc
+ - description: 27m osc
+ - description: ext1 clock input
+ - description: ext2 clock input
+ - description: ext3 clock input
+ - description: ext4 clock input
+ clock-names:
+ minItems: 7
+ maxItems: 7
+ items:
+ - const: ckil
+ - const: osc_25m
+ - const: osc_27m
+ - const: clk_ext1
+ - const: clk_ext2
+ - const: clk_ext3
+ - const: clk_ext4
+ else:
+ properties:
+ clocks:
+ items:
+ - description: 32k osc
+ - description: 24m osc
+ - description: ext1 clock input
+ - description: ext2 clock input
+ - description: ext3 clock input
+ - description: ext4 clock input
+
+ clock-names:
+ items:
+ - const: osc_32k
+ - const: osc_24m
+ - const: clk_ext1
+ - const: clk_ext2
+ - const: clk_ext3
+ - const: clk_ext4
+
+additionalProperties: false
+
+examples:
+ # Clock Control Module node:
+ - |
+ clock-controller@30380000 {
+ compatible = "fsl,imx8mm-ccm";
+ reg = <0x30380000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
+ <&clk_ext3>, <&clk_ext4>;
+ clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
+ "clk_ext3", "clk_ext4";
+ };
+
+ - |
+ clock-controller@30390000 {
+ compatible = "fsl,imx8mq-ccm";
+ reg = <0x30380000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&ckil>, <&osc_25m>, <&osc_27m>, <&clk_ext1>,
+ <&clk_ext2>, <&clk_ext3>, <&clk_ext4>;
+ clock-names = "ckil", "osc_25m", "osc_27m", "clk_ext1",
+ "clk_ext2", "clk_ext3", "clk_ext4";
+ };
+
+...
diff --git a/dts/Bindings/clock/imx8mm-clock.yaml b/dts/Bindings/clock/imx8mm-clock.yaml
deleted file mode 100644
index ec830db136..0000000000
--- a/dts/Bindings/clock/imx8mm-clock.yaml
+++ /dev/null
@@ -1,68 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/imx8mm-clock.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: NXP i.MX8M Mini Clock Control Module Binding
-
-maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
-
-description: |
- NXP i.MX8M Mini clock control module is an integrated clock controller, which
- generates and supplies to all modules.
-
-properties:
- compatible:
- const: fsl,imx8mm-ccm
-
- reg:
- maxItems: 1
-
- clocks:
- items:
- - description: 32k osc
- - description: 24m osc
- - description: ext1 clock input
- - description: ext2 clock input
- - description: ext3 clock input
- - description: ext4 clock input
-
- clock-names:
- items:
- - const: osc_32k
- - const: osc_24m
- - const: clk_ext1
- - const: clk_ext2
- - const: clk_ext3
- - const: clk_ext4
-
- '#clock-cells':
- const: 1
- description:
- The clock consumer should specify the desired clock by having the clock
- ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mm-clock.h
- for the full list of i.MX8M Mini clock IDs.
-
-required:
- - compatible
- - reg
- - clocks
- - clock-names
- - '#clock-cells'
-
-examples:
- # Clock Control Module node:
- - |
- clk: clock-controller@30380000 {
- compatible = "fsl,imx8mm-ccm";
- reg = <0x30380000 0x10000>;
- #clock-cells = <1>;
- clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
- <&clk_ext3>, <&clk_ext4>;
- clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
- "clk_ext3", "clk_ext4";
- };
-
-...
diff --git a/dts/Bindings/clock/imx8mn-clock.yaml b/dts/Bindings/clock/imx8mn-clock.yaml
deleted file mode 100644
index bdaa29616a..0000000000
--- a/dts/Bindings/clock/imx8mn-clock.yaml
+++ /dev/null
@@ -1,70 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/imx8mn-clock.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: NXP i.MX8M Nano Clock Control Module Binding
-
-maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
-
-description: |
- NXP i.MX8M Nano clock control module is an integrated clock controller, which
- generates and supplies to all modules.
-
-properties:
- compatible:
- const: fsl,imx8mn-ccm
-
- reg:
- maxItems: 1
-
- clocks:
- items:
- - description: 32k osc
- - description: 24m osc
- - description: ext1 clock input
- - description: ext2 clock input
- - description: ext3 clock input
- - description: ext4 clock input
-
- clock-names:
- items:
- - const: osc_32k
- - const: osc_24m
- - const: clk_ext1
- - const: clk_ext2
- - const: clk_ext3
- - const: clk_ext4
-
- '#clock-cells':
- const: 1
- description:
- The clock consumer should specify the desired clock by having the clock
- ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mn-clock.h
- for the full list of i.MX8M Nano clock IDs.
-
-required:
- - compatible
- - reg
- - clocks
- - clock-names
- - '#clock-cells'
-
-additionalProperties: false
-
-examples:
- # Clock Control Module node:
- - |
- clk: clock-controller@30380000 {
- compatible = "fsl,imx8mn-ccm";
- reg = <0x30380000 0x10000>;
- #clock-cells = <1>;
- clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>,
- <&clk_ext2>, <&clk_ext3>, <&clk_ext4>;
- clock-names = "osc_32k", "osc_24m", "clk_ext1",
- "clk_ext2", "clk_ext3", "clk_ext4";
- };
-
-...
diff --git a/dts/Bindings/clock/imx8mp-clock.yaml b/dts/Bindings/clock/imx8mp-clock.yaml
deleted file mode 100644
index 4351a1dbb4..0000000000
--- a/dts/Bindings/clock/imx8mp-clock.yaml
+++ /dev/null
@@ -1,70 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/imx8mp-clock.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: NXP i.MX8M Plus Clock Control Module Binding
-
-maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
-
-description:
- NXP i.MX8M Plus clock control module is an integrated clock controller, which
- generates and supplies to all modules.
-
-properties:
- compatible:
- const: fsl,imx8mp-ccm
-
- reg:
- maxItems: 1
-
- clocks:
- items:
- - description: 32k osc
- - description: 24m osc
- - description: ext1 clock input
- - description: ext2 clock input
- - description: ext3 clock input
- - description: ext4 clock input
-
- clock-names:
- items:
- - const: osc_32k
- - const: osc_24m
- - const: clk_ext1
- - const: clk_ext2
- - const: clk_ext3
- - const: clk_ext4
-
- '#clock-cells':
- const: 1
- description:
- The clock consumer should specify the desired clock by having the clock
- ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mp-clock.h
- for the full list of i.MX8M Plus clock IDs.
-
-required:
- - compatible
- - reg
- - clocks
- - clock-names
- - '#clock-cells'
-
-additionalProperties: false
-
-examples:
- # Clock Control Module node:
- - |
- clk: clock-controller@30380000 {
- compatible = "fsl,imx8mp-ccm";
- reg = <0x30380000 0x10000>;
- #clock-cells = <1>;
- clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>,
- <&clk_ext2>, <&clk_ext3>, <&clk_ext4>;
- clock-names = "osc_32k", "osc_24m", "clk_ext1",
- "clk_ext2", "clk_ext3", "clk_ext4";
- };
-
-...
diff --git a/dts/Bindings/clock/imx8mq-clock.yaml b/dts/Bindings/clock/imx8mq-clock.yaml
deleted file mode 100644
index 05d7d1471e..0000000000
--- a/dts/Bindings/clock/imx8mq-clock.yaml
+++ /dev/null
@@ -1,72 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/imx8mq-clock.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: NXP i.MX8M Quad Clock Control Module Binding
-
-maintainers:
- - Anson Huang <Anson.Huang@nxp.com>
-
-description: |
- NXP i.MX8M Quad clock control module is an integrated clock controller, which
- generates and supplies to all modules.
-
-properties:
- compatible:
- const: fsl,imx8mq-ccm
-
- reg:
- maxItems: 1
-
- clocks:
- items:
- - description: 32k osc
- - description: 25m osc
- - description: 27m osc
- - description: ext1 clock input
- - description: ext2 clock input
- - description: ext3 clock input
- - description: ext4 clock input
-
- clock-names:
- items:
- - const: ckil
- - const: osc_25m
- - const: osc_27m
- - const: clk_ext1
- - const: clk_ext2
- - const: clk_ext3
- - const: clk_ext4
-
- '#clock-cells':
- const: 1
- description:
- The clock consumer should specify the desired clock by having the clock
- ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h
- for the full list of i.MX8M Quad clock IDs.
-
-required:
- - compatible
- - reg
- - clocks
- - clock-names
- - '#clock-cells'
-
-examples:
- # Clock Control Module node:
- - |
- clk: clock-controller@30380000 {
- compatible = "fsl,imx8mq-ccm";
- reg = <0x30380000 0x10000>;
- #clock-cells = <1>;
- clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
- <&clk_ext1>, <&clk_ext2>,
- <&clk_ext3>, <&clk_ext4>;
- clock-names = "ckil", "osc_25m", "osc_27m",
- "clk_ext1", "clk_ext2",
- "clk_ext3", "clk_ext4";
- };
-
-...
diff --git a/dts/Bindings/clock/imx8qxp-lpcg.yaml b/dts/Bindings/clock/imx8qxp-lpcg.yaml
index 1d5e9bcce4..33f3010f48 100644
--- a/dts/Bindings/clock/imx8qxp-lpcg.yaml
+++ b/dts/Bindings/clock/imx8qxp-lpcg.yaml
@@ -62,7 +62,7 @@ examples:
};
mmc@5b010000 {
- compatible = "fsl,imx8qxp-usdhc";
+ compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
diff --git a/dts/Bindings/clock/intel,cgu-lgm.yaml b/dts/Bindings/clock/intel,cgu-lgm.yaml
index 6dc1414bfb..f3e1a700a2 100644
--- a/dts/Bindings/clock/intel,cgu-lgm.yaml
+++ b/dts/Bindings/clock/intel,cgu-lgm.yaml
@@ -33,6 +33,8 @@ required:
- reg
- '#clock-cells'
+additionalProperties: false
+
examples:
- |
cgu: clock-controller@e0200000 {
diff --git a/dts/Bindings/clock/qcom,dispcc-sm8x50.yaml b/dts/Bindings/clock/qcom,dispcc-sm8x50.yaml
new file mode 100644
index 0000000000..0cdf53f41f
--- /dev/null
+++ b/dts/Bindings/clock/qcom,dispcc-sm8x50.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
+
+maintainers:
+ - Jonathan Marek <jonathan@marek.ca>
+
+description: |
+ Qualcomm display clock control module which supports the clocks, resets and
+ power domains on SM8150 and SM8250.
+
+ See also:
+ dt-bindings/clock/qcom,dispcc-sm8150.h
+ dt-bindings/clock/qcom,dispcc-sm8250.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,sm8150-dispcc
+ - qcom,sm8250-dispcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Byte clock from DSI PHY0
+ - description: Pixel clock from DSI PHY0
+ - description: Byte clock from DSI PHY1
+ - description: Pixel clock from DSI PHY1
+ - description: Link clock from DP PHY
+ - description: VCO DIV clock from DP PHY
+
+ clock-names:
+ items:
+ - const: bi_tcxo
+ - const: dsi0_phy_pll_out_byteclk
+ - const: dsi0_phy_pll_out_dsiclk
+ - const: dsi1_phy_pll_out_byteclk
+ - const: dsi1_phy_pll_out_dsiclk
+ - const: dp_phy_pll_link_clk
+ - const: dp_phy_pll_vco_div_clk
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@af00000 {
+ compatible = "qcom,sm8250-dispcc";
+ reg = <0x0af00000 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&dsi0_phy 0>,
+ <&dsi0_phy 1>,
+ <&dsi1_phy 0>,
+ <&dsi1_phy 1>,
+ <&dp_phy 0>,
+ <&dp_phy 1>;
+ clock-names = "bi_tcxo",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk",
+ "dsi1_phy_pll_out_byteclk",
+ "dsi1_phy_pll_out_dsiclk",
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/dts/Bindings/clock/qcom,gcc-sm8250.yaml b/dts/Bindings/clock/qcom,gcc-sm8250.yaml
index a5766ff890..80bd6caf5b 100644
--- a/dts/Bindings/clock/qcom,gcc-sm8250.yaml
+++ b/dts/Bindings/clock/qcom,gcc-sm8250.yaml
@@ -56,6 +56,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
diff --git a/dts/Bindings/clock/qcom,sc7180-videocc.yaml b/dts/Bindings/clock/qcom,sc7180-videocc.yaml
deleted file mode 100644
index 2feea2b91a..0000000000
--- a/dts/Bindings/clock/qcom,sc7180-videocc.yaml
+++ /dev/null
@@ -1,65 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/qcom,sc7180-videocc.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Video Clock & Reset Controller Binding for SC7180
-
-maintainers:
- - Taniya Das <tdas@codeaurora.org>
-
-description: |
- Qualcomm video clock control module which supports the clocks, resets and
- power domains on SC7180.
-
- See also dt-bindings/clock/qcom,videocc-sc7180.h.
-
-properties:
- compatible:
- const: qcom,sc7180-videocc
-
- clocks:
- items:
- - description: Board XO source
-
- clock-names:
- items:
- - const: bi_tcxo
-
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
- reg:
- maxItems: 1
-
-required:
- - compatible
- - reg
- - clocks
- - clock-names
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-
-additionalProperties: false
-
-examples:
- - |
- #include <dt-bindings/clock/qcom,rpmh.h>
- clock-controller@ab00000 {
- compatible = "qcom,sc7180-videocc";
- reg = <0x0ab00000 0x10000>;
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "bi_tcxo";
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- };
-...
diff --git a/dts/Bindings/clock/qcom,sdm845-videocc.yaml b/dts/Bindings/clock/qcom,videocc.yaml
index f7a0cf53d5..567202942b 100644
--- a/dts/Bindings/clock/qcom,sdm845-videocc.yaml
+++ b/dts/Bindings/clock/qcom,videocc.yaml
@@ -1,23 +1,31 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
-$id: http://devicetree.org/schemas/clock/qcom,sdm845-videocc.yaml#
+$id: http://devicetree.org/schemas/clock/qcom,videocc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Video Clock & Reset Controller Binding for SDM845
+title: Qualcomm Video Clock & Reset Controller Binding
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm video clock control module which supports the clocks, resets and
- power domains on SDM845.
+ power domains on SDM845/SC7180/SM8150/SM8250.
- See also dt-bindings/clock/qcom,videocc-sdm845.h.
+ See also:
+ dt-bindings/clock/qcom,videocc-sc7180.h
+ dt-bindings/clock/qcom,videocc-sdm845.h
+ dt-bindings/clock/qcom,videocc-sm8150.h
+ dt-bindings/clock/qcom,videocc-sm8250.h
properties:
compatible:
- const: qcom,sdm845-videocc
+ enum:
+ - qcom,sc7180-videocc
+ - qcom,sdm845-videocc
+ - qcom,sm8150-videocc
+ - qcom,sm8250-videocc
clocks:
items:
diff --git a/dts/Bindings/clock/renesas,cpg-mssr.yaml b/dts/Bindings/clock/renesas,cpg-mssr.yaml
index e13aee8ab6..9b414fbde6 100644
--- a/dts/Bindings/clock/renesas,cpg-mssr.yaml
+++ b/dts/Bindings/clock/renesas,cpg-mssr.yaml
@@ -47,6 +47,7 @@ properties:
- renesas,r8a77980-cpg-mssr # R-Car V3H
- renesas,r8a77990-cpg-mssr # R-Car E3
- renesas,r8a77995-cpg-mssr # R-Car D3
+ - renesas,r8a779a0-cpg-mssr # R-Car V3U
reg:
maxItems: 1
diff --git a/dts/Bindings/clock/sifive/fu540-prci.txt b/dts/Bindings/clock/sifive/fu540-prci.txt
deleted file mode 100644
index 349808f4fb..0000000000
--- a/dts/Bindings/clock/sifive/fu540-prci.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-SiFive FU540 PRCI bindings
-
-On the FU540 family of SoCs, most system-wide clock and reset integration
-is via the PRCI IP block.
-
-Required properties:
-- compatible: Should be "sifive,<chip>-prci". Only one value is
- supported: "sifive,fu540-c000-prci"
-- reg: Should describe the PRCI's register target physical address region
-- clocks: Should point to the hfclk device tree node and the rtcclk
- device tree node. The RTC clock here is not a time-of-day clock,
- but is instead a high-stability clock source for system timers
- and cycle counters.
-- #clock-cells: Should be <1>
-
-The clock consumer should specify the desired clock via the clock ID
-macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
-These macros begin with PRCI_CLK_.
-
-The hfclk and rtcclk nodes are required, and represent physical
-crystals or resonators located on the PCB. These nodes should be present
-underneath /, rather than /soc.
-
-Examples:
-
-/* under /, in PCB-specific DT data */
-hfclk: hfclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <33333333>;
- clock-output-names = "hfclk";
-};
-rtcclk: rtcclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <1000000>;
- clock-output-names = "rtcclk";
-};
-
-/* under /soc, in SoC-specific DT data */
-prci: clock-controller@10000000 {
- compatible = "sifive,fu540-c000-prci";
- reg = <0x0 0x10000000 0x0 0x1000>;
- clocks = <&hfclk>, <&rtcclk>;
- #clock-cells = <1>;
-};
diff --git a/dts/Bindings/clock/sifive/fu540-prci.yaml b/dts/Bindings/clock/sifive/fu540-prci.yaml
new file mode 100644
index 0000000000..c3be1b6000
--- /dev/null
+++ b/dts/Bindings/clock/sifive/fu540-prci.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 SiFive, Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
+
+maintainers:
+ - Sagar Kadam <sagar.kadam@sifive.com>
+ - Paul Walmsley <paul.walmsley@sifive.com>
+
+description:
+ On the FU540 family of SoCs, most system-wide clock and reset integration
+ is via the PRCI IP block.
+ The clock consumer should specify the desired clock via the clock ID
+ macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
+ These macros begin with PRCI_CLK_.
+
+ The hfclk and rtcclk nodes are required, and represent physical
+ crystals or resonators located on the PCB. These nodes should be present
+ underneath /, rather than /soc.
+
+properties:
+ compatible:
+ const: sifive,fu540-c000-prci
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: high frequency clock.
+ - description: RTL clock.
+
+ clock-names:
+ items:
+ - const: hfclk
+ - const: rtcclk
+
+ "#clock-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ prci: clock-controller@10000000 {
+ compatible = "sifive,fu540-c000-prci";
+ reg = <0x10000000 0x1000>;
+ clocks = <&hfclk>, <&rtcclk>;
+ #clock-cells = <1>;
+ };
diff --git a/dts/Bindings/clock/sprd,sc9863a-clk.yaml b/dts/Bindings/clock/sprd,sc9863a-clk.yaml
index c6d0915186..4069e09cb6 100644
--- a/dts/Bindings/clock/sprd,sc9863a-clk.yaml
+++ b/dts/Bindings/clock/sprd,sc9863a-clk.yaml
@@ -73,6 +73,8 @@ else:
The 'reg' property for the clock node is also required if there is a sub
range of registers for the clocks.
+additionalProperties: false
+
examples:
- |
ap_clk: clock-controller@21500000 {
diff --git a/dts/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml b/dts/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml
index 869b18ac88..6b419a9878 100644
--- a/dts/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml
+++ b/dts/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml
@@ -26,6 +26,8 @@ required:
- "#clock-cells"
- reg
+additionalProperties: false
+
examples:
- |
ehrpwm_tbclk: syscon@4140 {
diff --git a/dts/Bindings/connector/samsung,usb-connector-11pin.txt b/dts/Bindings/connector/samsung,usb-connector-11pin.txt
deleted file mode 100644
index 3dd8961154..0000000000
--- a/dts/Bindings/connector/samsung,usb-connector-11pin.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-Samsung micro-USB 11-pin connector
-==================================
-
-Samsung micro-USB 11-pin connector is an extension of micro-USB connector.
-It is present in multiple Samsung mobile devices.
-It has additional pins to route MHL traffic simultanously with USB.
-
-The bindings are superset of usb-connector bindings for micro-USB connector[1].
-
-Required properties:
-- compatible: must be: "samsung,usb-connector-11pin", "usb-b-connector",
-- type: must be "micro".
-
-Required nodes:
-- any data bus to the connector should be modeled using the OF graph bindings
- specified in bindings/graph.txt, unless the bus is between parent node and
- the connector. Since single connector can have multpile data buses every bus
- has assigned OF graph port number as follows:
- 0: High Speed (HS),
- 3: Mobile High-Definition Link (MHL), specific to 11-pin Samsung micro-USB.
-
-[1]: bindings/connector/usb-connector.yaml
-
-Example
--------
-
-Micro-USB connector with HS lines routed via controller (MUIC) and MHL lines
-connected to HDMI-MHL bridge (sii8620):
-
-muic-max77843@66 {
- ...
- usb_con: connector {
- compatible = "samsung,usb-connector-11pin", "usb-b-connector";
- label = "micro-USB";
- type = "micro";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@3 {
- reg = <3>;
- usb_con_mhl: endpoint {
- remote-endpoint = <&sii8620_mhl>;
- };
- };
- };
- };
-};
diff --git a/dts/Bindings/connector/usb-connector.yaml b/dts/Bindings/connector/usb-connector.yaml
index 9bd52e63c9..728f82db07 100644
--- a/dts/Bindings/connector/usb-connector.yaml
+++ b/dts/Bindings/connector/usb-connector.yaml
@@ -11,7 +11,8 @@ maintainers:
description:
A USB connector node represents a physical USB connector. It should be a child
- of a USB interface controller.
+ of a USB interface controller or a separate node when it is attached to both
+ MUX and USB interface controller.
properties:
compatible:
@@ -25,6 +26,10 @@ properties:
- const: gpio-usb-b-connector
- const: usb-b-connector
+ - items:
+ - const: samsung,usb-connector-11pin
+ - const: usb-b-connector
+
label:
description: Symbolic name for the connector.
@@ -158,6 +163,18 @@ allOf:
- required:
- id-gpios
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,usb-connector-11pin
+ then:
+ properties:
+ type:
+ const: micro
+
+additionalProperties: true
+
examples:
# Micro-USB connector with HS lines routed via controller (MUIC).
- |
@@ -221,6 +238,33 @@ examples:
};
};
+ # USB-C connector attached to SoC and USB3 typec port controller(hd3ss3220)
+ # with SS 2:1 MUX. HS lines routed to SoC, SS lines routed to the MUX and
+ # the output of MUX is connected to the SoC.
+ - |
+ connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ hs_ep: endpoint {
+ remote-endpoint = <&usb3_hs_ep>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ ss_ep: endpoint {
+ remote-endpoint = <&hd3ss3220_in_ep>;
+ };
+ };
+ };
+ };
+
# USB connector with GPIO control lines
- |
#include <dt-bindings/gpio/gpio.h>
@@ -233,3 +277,33 @@ examples:
vbus-supply = <&usb_p0_vbus>;
};
};
+
+ # Micro-USB connector with HS lines routed via controller (MUIC) and MHL
+ # lines connected to HDMI-MHL bridge (sii8620) on Samsung Exynos5433-based
+ # mobile phone
+ - |
+ muic-max77843 {
+ usb_con4: connector {
+ compatible = "samsung,usb-connector-11pin", "usb-b-connector";
+ label = "micro-USB";
+ type = "micro";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ muic_to_usb: endpoint {
+ remote-endpoint = <&usb_to_muic>;
+ };
+ };
+ port@3 {
+ reg = <3>;
+ usb_con_mhl: endpoint {
+ remote-endpoint = <&sii8620_mhl>;
+ };
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/cpufreq/cpufreq-qcom-hw.txt b/dts/Bindings/cpufreq/cpufreq-qcom-hw.txt
index 33856947c5..9299028ee7 100644
--- a/dts/Bindings/cpufreq/cpufreq-qcom-hw.txt
+++ b/dts/Bindings/cpufreq/cpufreq-qcom-hw.txt
@@ -8,7 +8,7 @@ Properties:
- compatible
Usage: required
Value type: <string>
- Definition: must be "qcom,cpufreq-hw".
+ Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".
- clocks
Usage: required
diff --git a/dts/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml b/dts/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml
index fc823572bc..0429fb774f 100644
--- a/dts/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml
+++ b/dts/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml
@@ -23,7 +23,9 @@ properties:
- items:
- const: allwinner,sun7i-a20-crypto
- const: allwinner,sun4i-a10-crypto
+ - const: allwinner,sun8i-a33-crypto
- items:
+ - const: allwinner,sun8i-v3s-crypto
- const: allwinner,sun8i-a33-crypto
reg:
@@ -59,7 +61,9 @@ if:
properties:
compatible:
contains:
- const: allwinner,sun6i-a31-crypto
+ enum:
+ - allwinner,sun6i-a31-crypto
+ - allwinner,sun8i-a33-crypto
then:
required:
diff --git a/dts/Bindings/crypto/fsl-dcp.txt b/dts/Bindings/crypto/fsl-dcp.txt
deleted file mode 100644
index 513499fcdb..0000000000
--- a/dts/Bindings/crypto/fsl-dcp.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-Freescale DCP (Data Co-Processor) found on i.MX23/i.MX28 .
-
-Required properties:
-- compatible : Should be "fsl,<soc>-dcp"
-- reg : Should contain MXS DCP registers location and length
-- interrupts : Should contain MXS DCP interrupt numbers, VMI IRQ and DCP IRQ
- must be supplied, optionally Secure IRQ can be present, but
- is currently not implemented and not used.
-- clocks : Clock reference (only required on some SOCs: 6ull and 6sll).
-- clock-names : Must be "dcp".
-
-Example:
-
-dcp: crypto@80028000 {
- compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
- reg = <0x80028000 0x2000>;
- interrupts = <52 53>;
-};
diff --git a/dts/Bindings/crypto/fsl-dcp.yaml b/dts/Bindings/crypto/fsl-dcp.yaml
new file mode 100644
index 0000000000..a30bf38a4a
--- /dev/null
+++ b/dts/Bindings/crypto/fsl-dcp.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/fsl-dcp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale DCP (Data Co-Processor) found on i.MX23/i.MX28
+
+maintainers:
+ - Marek Vasut <marex@denx.de>
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx23-dcp
+ - fsl,imx28-dcp
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: Should contain MXS DCP interrupt numbers, VMI IRQ and DCP IRQ
+ must be supplied, optionally Secure IRQ can be present, but is currently
+ not implemented and not used.
+ items:
+ - description: MXS DCP VMI interrupt
+ - description: MXS DCP DCP interrupt
+ - description: MXS DCP secure interrupt
+ minItems: 2
+ maxItems: 3
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: dcp
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ crypto@80028000 {
+ compatible = "fsl,imx23-dcp";
+ reg = <0x80028000 0x2000>;
+ interrupts = <53>, <54>;
+ };
diff --git a/dts/Bindings/crypto/fsl-imx-sahara.txt b/dts/Bindings/crypto/fsl-imx-sahara.txt
deleted file mode 100644
index db690b10e5..0000000000
--- a/dts/Bindings/crypto/fsl-imx-sahara.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-Freescale SAHARA Cryptographic Accelerator included in some i.MX chips.
-Currently only i.MX27 and i.MX53 are supported.
-
-Required properties:
-- compatible : Should be "fsl,<soc>-sahara"
-- reg : Should contain SAHARA registers location and length
-- interrupts : Should contain SAHARA interrupt number
-
-Example:
-
-sah: crypto@10025000 {
- compatible = "fsl,imx27-sahara";
- reg = < 0x10025000 0x800>;
- interrupts = <75>;
-};
diff --git a/dts/Bindings/crypto/fsl-imx-sahara.yaml b/dts/Bindings/crypto/fsl-imx-sahara.yaml
new file mode 100644
index 0000000000..d531f3af3e
--- /dev/null
+++ b/dts/Bindings/crypto/fsl-imx-sahara.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/fsl-imx-sahara.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale SAHARA Cryptographic Accelerator included in some i.MX chips
+
+maintainers:
+ - Steffen Trumtrar <s.trumtrar@pengutronix.de>
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx27-sahara
+ - fsl,imx53-sahara
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ crypto@10025000 {
+ compatible = "fsl,imx27-sahara";
+ reg = < 0x10025000 0x800>;
+ interrupts = <75>;
+ };
diff --git a/dts/Bindings/crypto/fsl-imx-scc.txt b/dts/Bindings/crypto/fsl-imx-scc.txt
deleted file mode 100644
index 7aad448e8a..0000000000
--- a/dts/Bindings/crypto/fsl-imx-scc.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Freescale Security Controller (SCC)
-
-Required properties:
-- compatible : Should be "fsl,imx25-scc".
-- reg : Should contain register location and length.
-- interrupts : Should contain interrupt numbers for SCM IRQ and SMN IRQ.
-- interrupt-names : Should specify the names "scm" and "smn" for the
- SCM IRQ and SMN IRQ.
-- clocks: Should contain the clock driving the SCC core.
-- clock-names: Should be set to "ipg".
-
-Example:
-
- scc: crypto@53fac000 {
- compatible = "fsl,imx25-scc";
- reg = <0x53fac000 0x4000>;
- clocks = <&clks 111>;
- clock-names = "ipg";
- interrupts = <49>, <50>;
- interrupt-names = "scm", "smn";
- };
diff --git a/dts/Bindings/crypto/fsl-imx-scc.yaml b/dts/Bindings/crypto/fsl-imx-scc.yaml
new file mode 100644
index 0000000000..563a31605d
--- /dev/null
+++ b/dts/Bindings/crypto/fsl-imx-scc.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/fsl-imx-scc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Security Controller (SCC)
+
+maintainers:
+ - Steffen Trumtrar <s.trumtrar@pengutronix.de>
+
+properties:
+ compatible:
+ const: fsl,imx25-scc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: SCC SCM interrupt
+ - description: SCC SMN interrupt
+
+ interrupt-names:
+ items:
+ - const: scm
+ - const: smn
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: ipg
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ crypto@53fac000 {
+ compatible = "fsl,imx25-scc";
+ reg = <0x53fac000 0x4000>;
+ clocks = <&clks 111>;
+ clock-names = "ipg";
+ interrupts = <49>, <50>;
+ interrupt-names = "scm", "smn";
+ };
diff --git a/dts/Bindings/crypto/samsung-slimsss.yaml b/dts/Bindings/crypto/samsung-slimsss.yaml
index 04fe5dfa79..7743eae049 100644
--- a/dts/Bindings/crypto/samsung-slimsss.yaml
+++ b/dts/Bindings/crypto/samsung-slimsss.yaml
@@ -19,7 +19,7 @@ description: |+
properties:
compatible:
items:
- - const: samsung,exynos5433-slim-ss
+ - const: samsung,exynos5433-slim-sss
reg:
maxItems: 1
diff --git a/dts/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml b/dts/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
index 63f9481752..7aa330dabc 100644
--- a/dts/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
+++ b/dts/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
@@ -11,9 +11,6 @@ maintainers:
- Maxime Ripard <mripard@kernel.org>
properties:
- "#address-cells": true
- "#size-cells": true
-
compatible:
enum:
- allwinner,sun6i-a31-mipi-dsi
@@ -57,12 +54,7 @@ properties:
port should be the input endpoint, usually coming from the
associated TCON.
-patternProperties:
- "^panel@[0-9]+$": true
-
required:
- - "#address-cells"
- - "#size-cells"
- compatible
- reg
- interrupts
@@ -74,6 +66,7 @@ required:
- port
allOf:
+ - $ref: dsi-controller.yaml#
- if:
properties:
compatible:
@@ -99,7 +92,7 @@ allOf:
clocks:
minItems: 1
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/Bindings/display/brcm,bcm2711-hdmi.yaml b/dts/Bindings/display/brcm,bcm2711-hdmi.yaml
new file mode 100644
index 0000000000..03a76729d2
--- /dev/null
+++ b/dts/Bindings/display/brcm,bcm2711-hdmi.yaml
@@ -0,0 +1,117 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/brcm,bcm2711-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM2711 HDMI Controller Device Tree Bindings
+
+maintainers:
+ - Eric Anholt <eric@anholt.net>
+
+properties:
+ compatible:
+ enum:
+ - brcm,bcm2711-hdmi0
+ - brcm,bcm2711-hdmi1
+
+ reg:
+ items:
+ - description: HDMI controller register range
+ - description: DVP register range
+ - description: HDMI PHY register range
+ - description: Rate Manager register range
+ - description: Packet RAM register range
+ - description: Metadata RAM register range
+ - description: CSC register range
+ - description: CEC register range
+ - description: HD register range
+
+ reg-names:
+ items:
+ - const: hdmi
+ - const: dvp
+ - const: phy
+ - const: rm
+ - const: packet
+ - const: metadata
+ - const: csc
+ - const: cec
+ - const: hd
+
+ clocks:
+ items:
+ - description: The HDMI state machine clock
+ - description: The Pixel BVB clock
+ - description: The HDMI Audio parent clock
+ - description: The HDMI CEC parent clock
+
+ clock-names:
+ items:
+ - const: hdmi
+ - const: bvb
+ - const: audio
+ - const: cec
+
+ ddc:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/phandle
+ description: >
+ Phandle of the I2C controller used for DDC EDID probing
+
+ hpd-gpios:
+ description: >
+ The GPIO pin for the HDMI hotplug detect (if it doesn't appear
+ as an interrupt/status bit in the HDMI controller itself)
+
+ dmas:
+ maxItems: 1
+ description: >
+ Should contain one entry pointing to the DMA channel used to
+ transfer audio data.
+
+ dma-names:
+ const: audio-rx
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - resets
+ - ddc
+
+additionalProperties: false
+
+examples:
+ - |
+ hdmi0: hdmi@7ef00700 {
+ compatible = "brcm,bcm2711-hdmi0";
+ reg = <0x7ef00700 0x300>,
+ <0x7ef00300 0x200>,
+ <0x7ef00f00 0x80>,
+ <0x7ef00f80 0x80>,
+ <0x7ef01b00 0x200>,
+ <0x7ef01f00 0x400>,
+ <0x7ef00200 0x80>,
+ <0x7ef04300 0x100>,
+ <0x7ef20000 0x100>;
+ reg-names = "hdmi",
+ "dvp",
+ "phy",
+ "rm",
+ "packet",
+ "metadata",
+ "csc",
+ "cec",
+ "hd";
+ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
+ clock-names = "hdmi", "bvb", "audio", "cec";
+ resets = <&dvp 0>;
+ ddc = <&ddc0>;
+ };
+
+...
diff --git a/dts/Bindings/display/brcm,bcm2835-dsi0.yaml b/dts/Bindings/display/brcm,bcm2835-dsi0.yaml
index 3c643b227a..eb44e072b6 100644
--- a/dts/Bindings/display/brcm,bcm2835-dsi0.yaml
+++ b/dts/Bindings/display/brcm,bcm2835-dsi0.yaml
@@ -9,6 +9,9 @@ title: Broadcom VC4 (VideoCore4) DSI Controller
maintainers:
- Eric Anholt <eric@anholt.net>
+allOf:
+ - $ref: dsi-controller.yaml#
+
properties:
"#clock-cells":
const: 1
diff --git a/dts/Bindings/display/brcm,bcm2835-hvs.yaml b/dts/Bindings/display/brcm,bcm2835-hvs.yaml
index 02410f8d6d..e826ab0adb 100644
--- a/dts/Bindings/display/brcm,bcm2835-hvs.yaml
+++ b/dts/Bindings/display/brcm,bcm2835-hvs.yaml
@@ -11,7 +11,9 @@ maintainers:
properties:
compatible:
- const: brcm,bcm2835-hvs
+ enum:
+ - brcm,bcm2711-hvs
+ - brcm,bcm2835-hvs
reg:
maxItems: 1
@@ -19,6 +21,10 @@ properties:
interrupts:
maxItems: 1
+ clocks:
+ maxItems: 1
+ description: Core Clock
+
required:
- compatible
- reg
@@ -26,6 +32,16 @@ required:
additionalProperties: false
+if:
+ properties:
+ compatible:
+ contains:
+ const: brcm,bcm2711-hvs"
+
+then:
+ required:
+ - clocks
+
examples:
- |
hvs@7e400000 {
diff --git a/dts/Bindings/display/brcm,bcm2835-pixelvalve0.yaml b/dts/Bindings/display/brcm,bcm2835-pixelvalve0.yaml
index e60791db1f..4e1ba03f64 100644
--- a/dts/Bindings/display/brcm,bcm2835-pixelvalve0.yaml
+++ b/dts/Bindings/display/brcm,bcm2835-pixelvalve0.yaml
@@ -15,6 +15,11 @@ properties:
- brcm,bcm2835-pixelvalve0
- brcm,bcm2835-pixelvalve1
- brcm,bcm2835-pixelvalve2
+ - brcm,bcm2711-pixelvalve0
+ - brcm,bcm2711-pixelvalve1
+ - brcm,bcm2711-pixelvalve2
+ - brcm,bcm2711-pixelvalve3
+ - brcm,bcm2711-pixelvalve4
reg:
maxItems: 1
diff --git a/dts/Bindings/display/brcm,bcm2835-vc4.yaml b/dts/Bindings/display/brcm,bcm2835-vc4.yaml
index 0dcf0c3973..49a5e041aa 100644
--- a/dts/Bindings/display/brcm,bcm2835-vc4.yaml
+++ b/dts/Bindings/display/brcm,bcm2835-vc4.yaml
@@ -17,6 +17,7 @@ description: >
properties:
compatible:
enum:
+ - brcm,bcm2711-vc5
- brcm,bcm2835-vc4
- brcm,cygnus-vc4
diff --git a/dts/Bindings/display/bridge/cdns,mhdp8546.yaml b/dts/Bindings/display/bridge/cdns,mhdp8546.yaml
new file mode 100644
index 0000000000..74d675fc6e
--- /dev/null
+++ b/dts/Bindings/display/bridge/cdns,mhdp8546.yaml
@@ -0,0 +1,169 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Cadence MHDP8546 bridge
+
+maintainers:
+ - Swapnil Jakhade <sjakhade@cadence.com>
+ - Yuti Amonkar <yamonkar@cadence.com>
+
+properties:
+ compatible:
+ enum:
+ - cdns,mhdp8546
+ - ti,j721e-mhdp8546
+
+ reg:
+ minItems: 1
+ maxItems: 2
+ items:
+ - description:
+ Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
+ The AUX and PMA registers are not part of this range, they are instead
+ included in the associated PHY.
+ - description:
+ Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs.
+
+ reg-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: mhdptx
+ - const: j721e-intg
+
+ clocks:
+ maxItems: 1
+ description:
+ DP bridge clock, used by the IP to know how to translate a number of
+ clock cycles into a time (which is used to comply with DP standard timings
+ and delays).
+
+ phys:
+ maxItems: 1
+ description:
+ phandle to the DisplayPort PHY.
+
+ phy-names:
+ items:
+ - const: dpphy
+
+ power-domains:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ ports:
+ type: object
+ description:
+ Ports as described in Documentation/devicetree/bindings/graph.txt.
+
+ properties:
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ port@0:
+ type: object
+ description:
+ First input port representing the DP bridge input.
+
+ port@1:
+ type: object
+ description:
+ Second input port representing the DP bridge input.
+
+ port@2:
+ type: object
+ description:
+ Third input port representing the DP bridge input.
+
+ port@3:
+ type: object
+ description:
+ Fourth input port representing the DP bridge input.
+
+ port@4:
+ type: object
+ description:
+ Output port representing the DP bridge output.
+
+ required:
+ - port@0
+ - port@4
+ - '#address-cells'
+ - '#size-cells'
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,j721e-mhdp8546
+ then:
+ properties:
+ reg:
+ minItems: 2
+ reg-names:
+ minItems: 2
+ else:
+ properties:
+ reg:
+ maxItems: 1
+ reg-names:
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - reg
+ - reg-names
+ - phys
+ - phy-names
+ - interrupts
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ mhdp: dp-bridge@f0fb000000 {
+ compatible = "cdns,mhdp8546";
+ reg = <0xf0 0xfb000000 0x0 0x1000000>;
+ reg-names = "mhdptx";
+ clocks = <&mhdp_clock>;
+ phys = <&dp_phy>;
+ phy-names = "dpphy";
+ interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp_bridge_input: endpoint {
+ remote-endpoint = <&xxx_dpi_output>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ dp_bridge_output: endpoint {
+ remote-endpoint = <&xxx_dp_connector_input>;
+ };
+ };
+ };
+ };
+ };
+...
diff --git a/dts/Bindings/display/bridge/ite,it6505.yaml b/dts/Bindings/display/bridge/ite,it6505.yaml
index 2c500166c6..efbb3d0117 100644
--- a/dts/Bindings/display/bridge/ite,it6505.yaml
+++ b/dts/Bindings/display/bridge/ite,it6505.yaml
@@ -31,6 +31,9 @@ properties:
compatible:
const: ite,it6505
+ reg:
+ maxItems: 1
+
ovdd-supply:
maxItems: 1
description: I/O voltage
@@ -63,6 +66,8 @@ required:
- reset-gpios
- extcon
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
diff --git a/dts/Bindings/display/bridge/lontium,lt9611.yaml b/dts/Bindings/display/bridge/lontium,lt9611.yaml
new file mode 100644
index 0000000000..d602083592
--- /dev/null
+++ b/dts/Bindings/display/bridge/lontium,lt9611.yaml
@@ -0,0 +1,176 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/lontium,lt9611.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Lontium LT9611 2 Port MIPI to HDMI Bridge
+
+maintainers:
+ - Vinod Koul <vkoul@kernel.org>
+
+description: |
+ The LT9611 is a bridge device which converts DSI to HDMI
+
+properties:
+ compatible:
+ enum:
+ - lontium,lt9611
+
+ reg:
+ maxItems: 1
+
+ "#sound-dai-cells":
+ const: 1
+
+ interrupts:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+ description: GPIO connected to active high RESET pin.
+
+ vdd-supply:
+ description: Regulator for 1.8V MIPI phy power.
+
+ vcc-supply:
+ description: Regulator for 3.3V IO power.
+
+ ports:
+ type: object
+
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ port@0:
+ type: object
+ description: |
+ Primary MIPI port-1 for MIPI input
+
+ properties:
+ reg:
+ const: 0
+
+ patternProperties:
+ "^endpoint(@[0-9])$":
+ type: object
+ additionalProperties: false
+
+ properties:
+ remote-endpoint:
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ required:
+ - reg
+
+ port@1:
+ type: object
+ description: |
+ Additional MIPI port-2 for MIPI input, used in combination
+ with primary MIPI port-1 to drive higher resolution displays
+
+ properties:
+ reg:
+ const: 1
+
+ patternProperties:
+ "^endpoint(@[0-9])$":
+ type: object
+ additionalProperties: false
+
+ properties:
+ remote-endpoint:
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ required:
+ - reg
+
+ port@2:
+ type: object
+ description: |
+ HDMI port for HDMI output
+
+ properties:
+ reg:
+ const: 2
+
+ patternProperties:
+ "^endpoint(@[0-9])$":
+ type: object
+ additionalProperties: false
+
+ properties:
+ remote-endpoint:
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ required:
+ - reg
+
+ required:
+ - "#address-cells"
+ - "#size-cells"
+ - port@0
+ - port@2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - vdd-supply
+ - vcc-supply
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c10 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi-bridge@3b {
+ compatible = "lontium,lt9611";
+ reg = <0x3b>;
+
+ reset-gpios = <&tlmm 128 GPIO_ACTIVE_HIGH>;
+ interrupts-extended = <&tlmm 84 IRQ_TYPE_EDGE_FALLING>;
+
+ vdd-supply = <&lt9611_1v8>;
+ vcc-supply = <&lt9611_3v3>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lt9611_a: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ lt9611_b: endpoint {
+ remote-endpoint = <&dsi1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ lt9611_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/display/bridge/lvds-codec.yaml b/dts/Bindings/display/bridge/lvds-codec.yaml
index 68951d56eb..e5e3c72630 100644
--- a/dts/Bindings/display/bridge/lvds-codec.yaml
+++ b/dts/Bindings/display/bridge/lvds-codec.yaml
@@ -79,10 +79,16 @@ properties:
The GPIO used to control the power down line of this device.
maxItems: 1
+ power-supply:
+ maxItems: 1
+
required:
- compatible
- ports
+additionalProperties: false
+
+
examples:
- |
lvds-encoder {
diff --git a/dts/Bindings/display/bridge/nwl-dsi.yaml b/dts/Bindings/display/bridge/nwl-dsi.yaml
index 04099f5bea..a125b2dd3a 100644
--- a/dts/Bindings/display/bridge/nwl-dsi.yaml
+++ b/dts/Bindings/display/bridge/nwl-dsi.yaml
@@ -14,6 +14,9 @@ description: |
NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
the SOCs NWL MIPI-DSI host controller.
+allOf:
+ - $ref: ../dsi-controller.yaml#
+
properties:
compatible:
const: fsl,imx8mq-nwl-dsi
@@ -30,6 +33,10 @@ properties:
'#size-cells':
const: 0
+ assigned-clock-parents: true
+ assigned-clock-rates: true
+ assigned-clocks: true
+
clocks:
items:
- description: DSI core clock
@@ -140,10 +147,6 @@ properties:
additionalProperties: false
-patternProperties:
- "^panel@[0-9]+$":
- type: object
-
required:
- '#address-cells'
- '#size-cells'
@@ -159,7 +162,7 @@ required:
- reset-names
- resets
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
@@ -168,7 +171,7 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/imx8mq-reset.h>
- mipi_dsi: mipi_dsi@30a00000 {
+ dsi@30a00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mq-nwl-dsi";
diff --git a/dts/Bindings/display/bridge/renesas,dw-hdmi.txt b/dts/Bindings/display/bridge/renesas,dw-hdmi.txt
index 819f3e3101..3f60726511 100644
--- a/dts/Bindings/display/bridge/renesas,dw-hdmi.txt
+++ b/dts/Bindings/display/bridge/renesas,dw-hdmi.txt
@@ -14,8 +14,10 @@ Required properties:
- compatible : Shall contain one or more of
- "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX
- "renesas,r8a774b1-hdmi" for R8A774B1 (RZ/G2N) compatible HDMI TX
+ - "renesas,r8a774e1-hdmi" for R8A774E1 (RZ/G2H) compatible HDMI TX
- "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
- "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
+ - "renesas,r8a77961-hdmi" for R8A77961 (R-Car M3-W+) compatible HDMI TX
- "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
- "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 and RZ/G2 compatible
HDMI TX
@@ -42,7 +44,7 @@ Optional properties:
Example:
hdmi0: hdmi@fead0000 {
- compatible = "renesas,r8a7795-dw-hdmi";
+ compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
reg = <0 0xfead0000 0 0x10000>;
interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
diff --git a/dts/Bindings/display/bridge/renesas,lvds.yaml b/dts/Bindings/display/bridge/renesas,lvds.yaml
index baaf2a2a6f..e5b163951b 100644
--- a/dts/Bindings/display/bridge/renesas,lvds.yaml
+++ b/dts/Bindings/display/bridge/renesas,lvds.yaml
@@ -16,11 +16,13 @@ description: |
properties:
compatible:
enum:
+ - renesas,r8a7742-lvds # for RZ/G1H compatible LVDS encoders
- renesas,r8a7743-lvds # for RZ/G1M compatible LVDS encoders
- renesas,r8a7744-lvds # for RZ/G1N compatible LVDS encoders
- renesas,r8a774a1-lvds # for RZ/G2M compatible LVDS encoders
- renesas,r8a774b1-lvds # for RZ/G2N compatible LVDS encoders
- renesas,r8a774c0-lvds # for RZ/G2E compatible LVDS encoders
+ - renesas,r8a774e1-lvds # for RZ/G2H compatible LVDS encoders
- renesas,r8a7790-lvds # for R-Car H2 compatible LVDS encoders
- renesas,r8a7791-lvds # for R-Car M2-W compatible LVDS encoders
- renesas,r8a7793-lvds # for R-Car M2-N compatible LVDS encoders
diff --git a/dts/Bindings/display/bridge/snps,dw-mipi-dsi.yaml b/dts/Bindings/display/bridge/snps,dw-mipi-dsi.yaml
index 012aa8e7cb..e42cb610f5 100644
--- a/dts/Bindings/display/bridge/snps,dw-mipi-dsi.yaml
+++ b/dts/Bindings/display/bridge/snps,dw-mipi-dsi.yaml
@@ -66,3 +66,5 @@ required:
- clocks
- ports
- reg
+
+additionalProperties: true
diff --git a/dts/Bindings/display/bridge/toshiba,tc358762.yaml b/dts/Bindings/display/bridge/toshiba,tc358762.yaml
new file mode 100644
index 0000000000..195025e680
--- /dev/null
+++ b/dts/Bindings/display/bridge/toshiba,tc358762.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/toshiba,tc358762.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Toshiba TC358762 MIPI DSI to MIPI DPI bridge
+
+maintainers:
+ - Marek Vasut <marex@denx.de>
+
+description: |
+ The TC358762 is bridge device which converts MIPI DSI to MIPI DPI.
+
+properties:
+ compatible:
+ enum:
+ - toshiba,tc358762
+
+ reg:
+ maxItems: 1
+ description: virtual channel number of a DSI peripheral
+
+ vddc-supply:
+ description: Regulator for 1.2V internal core power.
+
+ ports:
+ type: object
+
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ port@0:
+ type: object
+ additionalProperties: false
+
+ description: |
+ Video port for MIPI DSI input
+
+ properties:
+ reg:
+ const: 0
+
+ patternProperties:
+ endpoint:
+ type: object
+ additionalProperties: false
+
+ properties:
+ remote-endpoint: true
+
+ required:
+ - reg
+
+ port@1:
+ type: object
+ additionalProperties: false
+
+ description: |
+ Video port for MIPI DPI output (panel or connector).
+
+ properties:
+ reg:
+ const: 1
+
+ patternProperties:
+ endpoint:
+ type: object
+ additionalProperties: false
+
+ properties:
+ remote-endpoint: true
+
+ required:
+ - reg
+
+ required:
+ - "#address-cells"
+ - "#size-cells"
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - vddc-supply
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bridge@0 {
+ reg = <0>;
+ compatible = "toshiba,tc358762";
+ vddc-supply = <&vcc_1v2_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ bridge_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ bridge_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/display/bridge/toshiba,tc358775.yaml b/dts/Bindings/display/bridge/toshiba,tc358775.yaml
new file mode 100644
index 0000000000..31f085d8ab
--- /dev/null
+++ b/dts/Bindings/display/bridge/toshiba,tc358775.yaml
@@ -0,0 +1,215 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/toshiba,tc358775.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Toshiba TC358775 DSI to LVDS bridge bindings
+
+maintainers:
+ - Vinay Simha BN <simhavcs@gmail.com>
+
+description: |
+ This binding supports DSI to LVDS bridge TC358775
+
+ MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
+ Video frame size:
+ Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
+ limited by 135 MHz LVDS speed
+ Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
+ panel, limited by 270 MHz LVDS speed.
+
+properties:
+ compatible:
+ const: toshiba,tc358775
+
+ reg:
+ maxItems: 1
+ description: i2c address of the bridge, 0x0f
+
+ vdd-supply:
+ maxItems: 1
+ description: 1.2V LVDS Power Supply
+
+ vddio-supply:
+ maxItems: 1
+ description: 1.8V IO Power Supply
+
+ stby-gpios:
+ maxItems: 1
+ description: Standby pin, Low active
+
+ reset-gpios:
+ maxItems: 1
+ description: Hardware reset, Low active
+
+ ports:
+ type: object
+ description:
+ A node containing input and output port nodes with endpoint definitions
+ as documented in
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ port@0:
+ type: object
+ description: |
+ DSI Input. The remote endpoint phandle should be a
+ reference to a valid mipi_dsi_host device node.
+
+ port@1:
+ type: object
+ description: |
+ Video port for LVDS output (panel or connector).
+
+ port@2:
+ type: object
+ description: |
+ Video port for Dual link LVDS output (panel or connector).
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - vdd-supply
+ - vddio-supply
+ - stby-gpios
+ - reset-gpios
+ - ports
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ /* For single-link LVDS display panel */
+
+ i2c@78b8000 {
+ /* On High speed expansion */
+ label = "HS-I2C2";
+ reg = <0x078b8000 0x500>;
+ clock-frequency = <400000>; /* fastmode operation */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tc_bridge: bridge@f {
+ compatible = "toshiba,tc358775";
+ reg = <0x0f>;
+
+ vdd-supply = <&pm8916_l2>;
+ vddio-supply = <&pm8916_l6>;
+
+ stby-gpios = <&msmgpio 99 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&msmgpio 72 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ d2l_in_test: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ lvds_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
+ };
+
+ dsi@1a98000 {
+ reg = <0x1a98000 0x25c>;
+ reg-names = "dsi_ctrl";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ remote-endpoint = <&d2l_in_test>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
+ };
+
+ - |
+ /* For dual-link LVDS display panel */
+
+ i2c@78b8000 {
+ /* On High speed expansion */
+ label = "HS-I2C2";
+ reg = <0x078b8000 0x500>;
+ clock-frequency = <400000>; /* fastmode operation */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tc_bridge_dual: bridge@f {
+ compatible = "toshiba,tc358775";
+ reg = <0x0f>;
+
+ vdd-supply = <&pm8916_l2>;
+ vddio-supply = <&pm8916_l6>;
+
+ stby-gpios = <&msmgpio 99 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&msmgpio 72 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ d2l_in_dual: endpoint {
+ remote-endpoint = <&dsi0_out_dual>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in0>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ lvds1_out: endpoint {
+ remote-endpoint = <&panel_in1>;
+ };
+ };
+ };
+ };
+ };
+
+ dsi@1a98000 {
+ reg = <0x1a98000 0x25c>;
+ reg-names = "dsi_ctrl";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@1 {
+ reg = <1>;
+ dsi0_out_dual: endpoint {
+ remote-endpoint = <&d2l_in_dual>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
+ };
+...
diff --git a/dts/Bindings/display/dsi-controller.yaml b/dts/Bindings/display/dsi-controller.yaml
index a02039e3ac..ca21671f6b 100644
--- a/dts/Bindings/display/dsi-controller.yaml
+++ b/dts/Bindings/display/dsi-controller.yaml
@@ -73,6 +73,8 @@ patternProperties:
required:
- reg
+additionalProperties: true
+
examples:
- |
#include <dt-bindings/gpio/gpio.h>
diff --git a/dts/Bindings/display/imx/nxp,imx8mq-dcss.yaml b/dts/Bindings/display/imx/nxp,imx8mq-dcss.yaml
new file mode 100644
index 0000000000..f1f25aa794
--- /dev/null
+++ b/dts/Bindings/display/imx/nxp,imx8mq-dcss.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 NXP
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: iMX8MQ Display Controller Subsystem (DCSS)
+
+maintainers:
+ - Laurentiu Palcu <laurentiu.palcu@nxp.com>
+
+description:
+
+ The DCSS (display controller sub system) is used to source up to three
+ display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP
+ 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
+ image processing capabilities are included to provide a solution capable of
+ driving next generation high dynamic range displays.
+
+properties:
+ compatible:
+ const: nxp,imx8mq-dcss
+
+ reg:
+ items:
+ - description: DCSS base address and size, up to IRQ steer start
+ - description: DCSS BLKCTL base address and size
+
+ interrupts:
+ items:
+ - description: Context loader completion and error interrupt
+ - description: DTG interrupt used to signal context loader trigger time
+ - description: DTG interrupt for Vblank
+
+ interrupt-names:
+ items:
+ - const: ctxld
+ - const: ctxld_kick
+ - const: vblank
+
+ clocks:
+ items:
+ - description: Display APB clock for all peripheral PIO access interfaces
+ - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
+ - description: RTRAM clock
+ - description: Pixel clock, can be driven either by HDMI phy clock or MIPI
+ - description: DTRC clock, needed by video decompressor
+
+ clock-names:
+ items:
+ - const: apb
+ - const: axi
+ - const: rtrm
+ - const: pix
+ - const: dtrc
+
+ assigned-clocks:
+ items:
+ - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_AXI_ROOT
+ - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_RTRM
+ - description: Phandle and clock specifier of either IMX8MQ_VIDEO2_PLL1_REF_SEL or
+ IMX8MQ_VIDEO_PLL1_REF_SEL
+
+ assigned-clock-parents:
+ items:
+ - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
+ - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
+ - description: Phandle and clock specifier of IMX8MQ_CLK_27M
+
+ assigned-clock-rates:
+ items:
+ - description: Must be 800 MHz
+ - description: Must be 400 MHz
+
+ port:
+ type: object
+ description:
+ A port node pointing to the input port of a HDMI/DP or MIPI display bridge.
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8mq-clock.h>
+ dcss: display-controller@32e00000 {
+ compatible = "nxp,imx8mq-dcss";
+ reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
+ interrupts = <6>, <8>, <9>;
+ interrupt-names = "ctxld", "ctxld_kick", "vblank";
+ interrupt-parent = <&irqsteer>;
+ clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, <&clk IMX8MQ_VIDEO2_PLL_OUT>,
+ <&clk IMX8MQ_CLK_DISP_DTRC>;
+ clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
+ assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, <&clk IMX8MQ_CLK_DISP_RTRM>,
+ <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>,
+ <&clk IMX8MQ_CLK_27M>;
+ assigned-clock-rates = <800000000>,
+ <400000000>;
+ port {
+ dcss_out: endpoint {
+ remote-endpoint = <&hdmi_in>;
+ };
+ };
+ };
+
diff --git a/dts/Bindings/display/mediatek/mediatek,disp.txt b/dts/Bindings/display/mediatek/mediatek,disp.txt
index b91e709db7..121220745d 100644
--- a/dts/Bindings/display/mediatek/mediatek,disp.txt
+++ b/dts/Bindings/display/mediatek/mediatek,disp.txt
@@ -43,7 +43,7 @@ Required properties (all function blocks):
"mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
"mediatek,<chip>-disp-mutex" - display mutex
"mediatek,<chip>-disp-od" - overdrive
- the supported chips are mt2701, mt2712 and mt8173.
+ the supported chips are mt2701, mt7623, mt2712 and mt8173.
- reg: Physical base address and length of the function block register space
- interrupts: The interrupt signal from the function block (required, except for
merge and split function blocks).
diff --git a/dts/Bindings/display/mediatek/mediatek,dpi.txt b/dts/Bindings/display/mediatek/mediatek,dpi.txt
index 77def44567..dc1ebd13cc 100644
--- a/dts/Bindings/display/mediatek/mediatek,dpi.txt
+++ b/dts/Bindings/display/mediatek/mediatek,dpi.txt
@@ -7,7 +7,7 @@ output bus.
Required properties:
- compatible: "mediatek,<chip>-dpi"
- the supported chips are mt2701 , mt8173 and mt8183.
+ the supported chips are mt2701, mt7623, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
diff --git a/dts/Bindings/display/mediatek/mediatek,dsi.txt b/dts/Bindings/display/mediatek/mediatek,dsi.txt
index 8e4729de8c..f06f24d405 100644
--- a/dts/Bindings/display/mediatek/mediatek,dsi.txt
+++ b/dts/Bindings/display/mediatek/mediatek,dsi.txt
@@ -7,7 +7,7 @@ channel output.
Required properties:
- compatible: "mediatek,<chip>-dsi"
- the supported chips are mt2701, mt8173 and mt8183.
+- the supported chips are mt2701, mt7623, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
@@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
Required properties:
- compatible: "mediatek,<chip>-mipi-tx"
- the supported chips are mt2701, mt8173 and mt8183.
+- the supported chips are mt2701, 7623, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- clocks: PLL reference clock
- clock-output-names: name of the output clock line to the DSI encoder
diff --git a/dts/Bindings/display/mediatek/mediatek,hdmi.txt b/dts/Bindings/display/mediatek/mediatek,hdmi.txt
index 7b124242b0..6b1c586403 100644
--- a/dts/Bindings/display/mediatek/mediatek,hdmi.txt
+++ b/dts/Bindings/display/mediatek/mediatek,hdmi.txt
@@ -6,6 +6,7 @@ its parallel input.
Required properties:
- compatible: Should be "mediatek,<chip>-hdmi".
+- the supported chips are mt2701, mt7623 and mt8173
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
@@ -32,6 +33,7 @@ The HDMI CEC controller handles hotplug detection and CEC communication.
Required properties:
- compatible: Should be "mediatek,<chip>-cec"
+- the supported chips are mt7623 and mt8173
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clock
@@ -44,6 +46,7 @@ The Mediatek's I2C controller is used to interface with I2C devices.
Required properties:
- compatible: Should be "mediatek,<chip>-hdmi-ddc"
+- the supported chips are mt7623 and mt8173
- reg: Physical base address and length of the controller's registers
- clocks: device clock
- clock-names: Should be "ddc-i2c".
@@ -56,6 +59,7 @@ output and drives the HDMI pads.
Required properties:
- compatible: "mediatek,<chip>-hdmi-phy"
+- the supported chips are mt2701, mt7623 and mt8173
- reg: Physical base address and length of the module's registers
- clocks: PLL reference clock
- clock-names: must contain "pll_ref"
diff --git a/dts/Bindings/display/msm/dsi.txt b/dts/Bindings/display/msm/dsi.txt
index 7884fd7a85..b9a64d3ff1 100644
--- a/dts/Bindings/display/msm/dsi.txt
+++ b/dts/Bindings/display/msm/dsi.txt
@@ -90,6 +90,8 @@ Required properties:
* "qcom,dsi-phy-14nm-660"
* "qcom,dsi-phy-10nm"
* "qcom,dsi-phy-10nm-8998"
+ * "qcom,dsi-phy-7nm"
+ * "qcom,dsi-phy-7nm-8150"
- reg: Physical base address and length of the registers of PLL, PHY. Some
revisions require the PHY regulator base address, whereas others require the
PHY lane base address. See below for each PHY revision.
@@ -98,7 +100,7 @@ Required properties:
* "dsi_pll"
* "dsi_phy"
* "dsi_phy_regulator"
- For DSI 14nm and 10nm PHYs:
+ For DSI 14nm, 10nm and 7nm PHYs:
* "dsi_pll"
* "dsi_phy"
* "dsi_phy_lane"
@@ -116,7 +118,7 @@ Required properties:
- vcca-supply: phandle to vcca regulator device node
For 14nm PHY:
- vcca-supply: phandle to vcca regulator device node
- For 10nm PHY:
+ For 10nm and 7nm PHY:
- vdds-supply: phandle to vdds regulator device node
Optional properties:
diff --git a/dts/Bindings/display/msm/gmu.yaml b/dts/Bindings/display/msm/gmu.yaml
index 53056dd025..fe55611d26 100644
--- a/dts/Bindings/display/msm/gmu.yaml
+++ b/dts/Bindings/display/msm/gmu.yaml
@@ -89,6 +89,8 @@ required:
- iommus
- operating-points-v2
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
diff --git a/dts/Bindings/display/panel/ilitek,ili9881c.yaml b/dts/Bindings/display/panel/ilitek,ili9881c.yaml
index 76a9068a85..c60b3bd743 100644
--- a/dts/Bindings/display/panel/ilitek,ili9881c.yaml
+++ b/dts/Bindings/display/panel/ilitek,ili9881c.yaml
@@ -13,7 +13,9 @@ properties:
compatible:
items:
- enum:
- - bananapi,lhr050h41
+ - bananapi,lhr050h41
+ - feixin,k101-im2byl02
+
- const: ilitek,ili9881c
backlight: true
diff --git a/dts/Bindings/display/panel/lvds.yaml b/dts/Bindings/display/panel/lvds.yaml
index 946dd35425..31164608ba 100644
--- a/dts/Bindings/display/panel/lvds.yaml
+++ b/dts/Bindings/display/panel/lvds.yaml
@@ -112,4 +112,6 @@ oneOf:
- required:
- ports
+additionalProperties: true
+
...
diff --git a/dts/Bindings/display/panel/mantix,mlaf057we51-x.yaml b/dts/Bindings/display/panel/mantix,mlaf057we51-x.yaml
new file mode 100644
index 0000000000..937323cc9a
--- /dev/null
+++ b/dts/Bindings/display/panel/mantix,mlaf057we51-x.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/mantix,mlaf057we51-x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mantix MLAF057WE51-X 5.7" 720x1440 TFT LCD panel
+
+maintainers:
+ - Guido Günther <agx@sigxcpu.org>
+
+description:
+ Mantix MLAF057WE51 X is a 720x1440 TFT LCD panel connected using
+ a MIPI-DSI video interface.
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - mantix,mlaf057we51-x
+
+ port: true
+ reg:
+ maxItems: 1
+ description: DSI virtual channel
+
+ avdd-supply:
+ description: Positive analog power supply
+
+ avee-supply:
+ description: Negative analog power supply
+
+ vddi-supply:
+ description: 1.8V I/O voltage supply
+
+ reset-gpios: true
+
+ backlight: true
+
+required:
+ - compatible
+ - reg
+ - avdd-supply
+ - avee-supply
+ - vddi-supply
+ - reset-gpios
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ panel@0 {
+ compatible = "mantix,mlaf057we51-x";
+ reg = <0>;
+ avdd-supply = <&reg_avdd>;
+ avee-supply = <&reg_avee>;
+ vddi-supply = <&reg_1v8_p>;
+ reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
+ backlight = <&backlight>;
+ };
+ };
+
+...
diff --git a/dts/Bindings/display/panel/panel-common.yaml b/dts/Bindings/display/panel/panel-common.yaml
index 45fe8fe5fa..cd6dc54617 100644
--- a/dts/Bindings/display/panel/panel-common.yaml
+++ b/dts/Bindings/display/panel/panel-common.yaml
@@ -163,4 +163,6 @@ dependencies:
width-mm: [ height-mm ]
height-mm: [ width-mm ]
+additionalProperties: true
+
...
diff --git a/dts/Bindings/display/panel/panel-simple.yaml b/dts/Bindings/display/panel/panel-simple.yaml
index 6deeeed59e..edb53ab0d9 100644
--- a/dts/Bindings/display/panel/panel-simple.yaml
+++ b/dts/Bindings/display/panel/panel-simple.yaml
@@ -29,6 +29,8 @@ properties:
# compatible must be listed in alphabetical order, ordered by compatible.
# The description in the comment is mandatory for each compatible.
+ # Ampire AM-1280800N3TZQW-T00H 10.1" WQVGA TFT LCD panel
+ - ampire,am-1280800n3tzqw-t00h
# Ampire AM-480272H3TMQW-T01H 4.3" WQVGA TFT LCD panel
- ampire,am-480272h3tmqw-t01h
# Ampire AM-800480R3TMQW-A1H 7.0" WVGA TFT LCD panel
@@ -87,6 +89,8 @@ properties:
- cdtech,s070swv29hg-dc44
# CDTech(H.K.) Electronics Limited 7" 800x480 color TFT-LCD panel
- cdtech,s070wv95-ct16
+ # Chefree CH101OLHLWH-002 10.1" (1280x800) color TFT LCD panel
+ - chefree,ch101olhlwh-002
# Chunghwa Picture Tubes Ltd. 7" WXGA TFT LCD panel
- chunghwa,claa070wp03xg
# Chunghwa Picture Tubes Ltd. 10.1" WXGA TFT LCD panel
@@ -159,6 +163,8 @@ properties:
- innolux,n156bge-l21
# Innolux Corporation 7.0" WSVGA (1024x600) TFT LCD panel
- innolux,zj070na-01p
+ # King & Display KD116N21-30NV-A010 eDP TFT LCD panel
+ - kingdisplay,kd116n21-30nv-a010
# Kaohsiung Opto-Electronics Inc. 5.7" QVGA (320 x 240) TFT LCD panel
- koe,tx14d24vm1bpa
# Kaohsiung Opto-Electronics Inc. 10.1" WUXGA (1920 x 1200) LVDS TFT LCD panel
@@ -219,6 +225,8 @@ properties:
- osddisplays,osd070t1718-19ts
# One Stop Displays OSD101T2045-53TS 10.1" 1920x1200 panel
- osddisplays,osd101t2045-53ts
+ # POWERTIP PH800480T013-IDF2 7.0" WVGA TFT LCD panel
+ - powertip,ph800480t013-idf02
# QiaoDian XianShi Corporation 4"3 TFT LCD panel
- qiaodian,qd43003c0-40
# Rocktech Displays Ltd. RK101II01D-CT 10.1" TFT 1280x800
diff --git a/dts/Bindings/display/panel/rocktech,jh057n00900.yaml b/dts/Bindings/display/panel/rocktech,jh057n00900.yaml
index d5733ef309..09b5eb7542 100644
--- a/dts/Bindings/display/panel/rocktech,jh057n00900.yaml
+++ b/dts/Bindings/display/panel/rocktech,jh057n00900.yaml
@@ -8,10 +8,11 @@ title: Rocktech JH057N00900 5.5" 720x1440 TFT LCD panel
maintainers:
- Ondrej Jirman <megi@xff.cz>
+ - Guido Gŭnther <agx@sigxcpu.org>
-description: |
- Rocktech JH057N00900 is a 720x1440 TFT LCD panel
- connected using a MIPI-DSI video interface.
+description:
+ Rocktech JH057N00900 is a 720x1440 TFT LCD panel
+ connected using a MIPI-DSI video interface.
allOf:
- $ref: panel-common.yaml#
@@ -19,9 +20,9 @@ allOf:
properties:
compatible:
enum:
- # Rocktech JH057N00900 5.5" 720x1440 TFT LCD panel
+ # Rocktech JH057N00900 5.5" 720x1440 TFT LCD panel
- rocktech,jh057n00900
- # Xingbangda XBD599 5.99" 720x1440 TFT LCD panel
+ # Xingbangda XBD599 5.99" 720x1440 TFT LCD panel
- xingbangda,xbd599
port: true
@@ -35,13 +36,9 @@ properties:
iovcc-supply:
description: I/O voltage supply
- reset-gpios:
- description: GPIO used for the reset pin
- maxItems: 1
+ reset-gpios: true
- backlight:
- description: Backlight used by the panel
- $ref: "/schemas/types.yaml#/definitions/phandle"
+ backlight: true
required:
- compatible
@@ -57,15 +54,16 @@ examples:
#include <dt-bindings/gpio/gpio.h>
dsi {
- #address-cells = <1>;
- #size-cells = <0>;
- panel@0 {
- compatible = "rocktech,jh057n00900";
- reg = <0>;
- vcc-supply = <&reg_2v8_p>;
- iovcc-supply = <&reg_1v8_p>;
- reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
- backlight = <&backlight>;
- };
+ #address-cells = <1>;
+ #size-cells = <0>;
+ panel@0 {
+ compatible = "rocktech,jh057n00900";
+ reg = <0>;
+ vcc-supply = <&reg_2v8_p>;
+ iovcc-supply = <&reg_1v8_p>;
+ reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
+ backlight = <&backlight>;
+ };
};
+
...
diff --git a/dts/Bindings/display/panel/samsung,amoled-mipi-dsi.yaml b/dts/Bindings/display/panel/samsung,amoled-mipi-dsi.yaml
index 96bdde9298..ccc482570d 100644
--- a/dts/Bindings/display/panel/samsung,amoled-mipi-dsi.yaml
+++ b/dts/Bindings/display/panel/samsung,amoled-mipi-dsi.yaml
@@ -12,6 +12,17 @@ maintainers:
allOf:
- $ref: panel-common.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,s6e3ha2
+ - samsung,s6e3hf2
+ then:
+ required:
+ - enable-gpios
+
properties:
compatible:
enum:
@@ -39,7 +50,6 @@ required:
- vdd3-supply
- vci-supply
- reset-gpios
- - enable-gpios
additionalProperties: false
diff --git a/dts/Bindings/display/panel/tpo,tpg110.yaml b/dts/Bindings/display/panel/tpo,tpg110.yaml
index a51660b73f..6f1f02044b 100644
--- a/dts/Bindings/display/panel/tpo,tpg110.yaml
+++ b/dts/Bindings/display/panel/tpo,tpg110.yaml
@@ -72,6 +72,8 @@ required:
- spi-max-frequency
- port
+unevaluatedProperties: false
+
examples:
- |+
spi {
diff --git a/dts/Bindings/display/renesas,du.txt b/dts/Bindings/display/renesas,du.txt
index 51cd4d1627..7d65c24fcd 100644
--- a/dts/Bindings/display/renesas,du.txt
+++ b/dts/Bindings/display/renesas,du.txt
@@ -3,6 +3,7 @@
Required Properties:
- compatible: must be one of the following.
+ - "renesas,du-r8a7742" for R8A7742 (RZ/G1H) compatible DU
- "renesas,du-r8a7743" for R8A7743 (RZ/G1M) compatible DU
- "renesas,du-r8a7744" for R8A7744 (RZ/G1N) compatible DU
- "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU
@@ -10,6 +11,7 @@ Required Properties:
- "renesas,du-r8a774a1" for R8A774A1 (RZ/G2M) compatible DU
- "renesas,du-r8a774b1" for R8A774B1 (RZ/G2N) compatible DU
- "renesas,du-r8a774c0" for R8A774C0 (RZ/G2E) compatible DU
+ - "renesas,du-r8a774e1" for R8A774E1 (RZ/G2H) compatible DU
- "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
- "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
- "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU
@@ -18,6 +20,7 @@ Required Properties:
- "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
- "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
- "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU
+ - "renesas,du-r8a77961" for R8A77961 (R-Car M3-W+) compatible DU
- "renesas,du-r8a77965" for R8A77965 (R-Car M3-N) compatible DU
- "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU
- "renesas,du-r8a77980" for R8A77980 (R-Car V3H) compatible DU
@@ -68,6 +71,7 @@ corresponding to each DU output.
Port0 Port1 Port2 Port3
-----------------------------------------------------------------------------
+ R8A7742 (RZ/G1H) DPAD 0 LVDS 0 LVDS 1 -
R8A7743 (RZ/G1M) DPAD 0 LVDS 0 - -
R8A7744 (RZ/G1N) DPAD 0 LVDS 0 - -
R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - -
@@ -75,6 +79,7 @@ corresponding to each DU output.
R8A774A1 (RZ/G2M) DPAD 0 HDMI 0 LVDS 0 -
R8A774B1 (RZ/G2N) DPAD 0 HDMI 0 LVDS 0 -
R8A774C0 (RZ/G2E) DPAD 0 LVDS 0 LVDS 1 -
+ R8A774E1 (RZ/G2H) DPAD 0 HDMI 0 LVDS 0 -
R8A7779 (R-Car H1) DPAD 0 DPAD 1 - -
R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 -
R8A7791 (R-Car M2-W) DPAD 0 LVDS 0 - -
@@ -83,6 +88,7 @@ corresponding to each DU output.
R8A7794 (R-Car E2) DPAD 0 DPAD 1 - -
R8A7795 (R-Car H3) DPAD 0 HDMI 0 HDMI 1 LVDS 0
R8A7796 (R-Car M3-W) DPAD 0 HDMI 0 LVDS 0 -
+ R8A77961 (R-Car M3-W+) DPAD 0 HDMI 0 LVDS 0 -
R8A77965 (R-Car M3-N) DPAD 0 HDMI 0 LVDS 0 -
R8A77970 (R-Car V3M) DPAD 0 LVDS 0 - -
R8A77980 (R-Car V3H) DPAD 0 LVDS 0 - -
diff --git a/dts/Bindings/display/ssd1307fb.txt b/dts/Bindings/display/ssd1307fb.txt
index 27333b9551..2dcb6d12d1 100644
--- a/dts/Bindings/display/ssd1307fb.txt
+++ b/dts/Bindings/display/ssd1307fb.txt
@@ -19,6 +19,7 @@ Optional properties:
- vbat-supply: The supply for VBAT
- solomon,segment-no-remap: Display needs normal (non-inverted) data column
to segment mapping
+ - solomon,col-offset: Offset of columns (COL/SEG) that the screen is mapped to.
- solomon,com-seq: Display uses sequential COM pin configuration
- solomon,com-lrremap: Display uses left-right COM pin remap
- solomon,com-invdir: Display uses inverted COM pin scan direction
diff --git a/dts/Bindings/display/st,stm32-dsi.yaml b/dts/Bindings/display/st,stm32-dsi.yaml
index 69cc7e8bf1..327a14d85d 100644
--- a/dts/Bindings/display/st,stm32-dsi.yaml
+++ b/dts/Bindings/display/st,stm32-dsi.yaml
@@ -13,6 +13,9 @@ maintainers:
description:
The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.
+allOf:
+ - $ref: dsi-controller.yaml#
+
properties:
compatible:
const: st,stm32-dsi
@@ -65,24 +68,6 @@ properties:
description:
DSI output port node, connected to a panel or a bridge input port"
-patternProperties:
- "^(panel|panel-dsi)@[0-9]$":
- type: object
- description:
- A node containing the panel or bridge description as documented in
- Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
- properties:
- port:
- type: object
- description:
- Panel or bridge port node, connected to the DSI output port (port@1)
-
- "#address-cells":
- const: 1
-
- "#size-cells":
- const: 0
-
required:
- "#address-cells"
- "#size-cells"
@@ -92,7 +77,7 @@ required:
- clock-names
- ports
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt b/dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt
index 47319214b5..ac63ae4a38 100644
--- a/dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt
+++ b/dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt
@@ -51,8 +51,16 @@ of the following host1x client modules:
- vi
- Tegra210:
- power-domains: Must include venc powergate node as vi is in VE partition.
- - Tegra210 has CSI part of VI sharing same host interface and register space.
- So, VI device node should have CSI child node.
+
+ ports (optional node)
+ vi can have optional ports node and max 6 ports are supported. Each port
+ should have single 'endpoint' child node. All port nodes are grouped under
+ ports node. Please refer to the bindings defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+
+ csi (required node)
+ Tegra210 has CSI part of VI sharing same host interface and register space.
+ So, VI device node should have CSI child node.
- csi: mipi csi interface to vi
@@ -65,6 +73,46 @@ of the following host1x client modules:
- power-domains: Must include sor powergate node as csicil is in
SOR partition.
+ channel (optional nodes)
+ Maximum 6 channels are supported with each csi brick as either x4 or x2
+ based on hw connectivity to sensor.
+
+ Required properties:
+ - reg: csi port number. Valid port numbers are 0 through 5.
+ - nvidia,mipi-calibrate: Should contain a phandle and a specifier
+ specifying which pads are used by this CSI port and need to be
+ calibrated. See also ../display/tegra/nvidia,tegra114-mipi.txt.
+
+ Each channel node must contain 2 port nodes which can be grouped
+ under 'ports' node and each port should have a single child 'endpoint'
+ node.
+
+ ports node
+ Please refer to the bindings defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+
+ ports node must contain below 2 port nodes.
+ port@0 with single child 'endpoint' node always a sink.
+ port@1 with single child 'endpoint' node always a source.
+
+ port@0 (required node)
+ Required properties:
+ - reg: 0
+
+ endpoint (required node)
+ Required properties:
+ - data-lanes: an array of data lane from 1 to 4. Valid array
+ lengths are 1/2/4.
+ - remote-endpoint: phandle to sensor 'endpoint' node.
+
+ port@1 (required node)
+ Required properties:
+ - reg: 1
+
+ endpoint (required node)
+ Required properties:
+ - remote-endpoint: phandle to vi port 'endpoint' node.
+
- epp: encoder pre-processor
Required properties:
@@ -340,6 +388,18 @@ Example:
ranges = <0x0 0x0 0x54080000 0x2000>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ imx219_vi_in0: endpoint {
+ remote-endpoint = <&imx219_csi_out0>;
+ };
+ };
+ };
+
csi@838 {
compatible = "nvidia,tegra210-csi";
reg = <0x838 0x1300>;
@@ -362,6 +422,34 @@ Example:
<&tegra_car TEGRA210_CLK_CSI_TPG>;
clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
power-domains = <&pd_sor>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ nvidia,mipi-calibrate = <&mipi 0x001>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ imx219_csi_in0: endpoint {
+ data-lanes = <1 2>;
+ remote-endpoint = <&imx219_out0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ imx219_csi_out0: endpoint {
+ remote-endpoint = <&imx219_vi_in0>;
+ };
+ };
+ };
+ };
};
};
diff --git a/dts/Bindings/display/tilcdc/tilcdc.txt b/dts/Bindings/display/tilcdc/tilcdc.txt
index 8b2a713956..3e64075ac7 100644
--- a/dts/Bindings/display/tilcdc/tilcdc.txt
+++ b/dts/Bindings/display/tilcdc/tilcdc.txt
@@ -37,7 +37,7 @@ Optional nodes:
supports a single port with a single endpoint.
- See also Documentation/devicetree/bindings/display/tilcdc/panel.txt and
- Documentation/devicetree/bindings/display/bridge/ti,tfp410.txt for connecting
+ Documentation/devicetree/bindings/display/bridge/ti,tfp410.yaml for connecting
tfp410 DVI encoder or lcd panel to lcdc
[1] There is an errata about AM335x color wiring. For 16-bit color mode
diff --git a/dts/Bindings/dma/allwinner,sun50i-a64-dma.yaml b/dts/Bindings/dma/allwinner,sun50i-a64-dma.yaml
index 9e53472be1..372679dbd2 100644
--- a/dts/Bindings/dma/allwinner,sun50i-a64-dma.yaml
+++ b/dts/Bindings/dma/allwinner,sun50i-a64-dma.yaml
@@ -19,9 +19,12 @@ properties:
description: The cell is the request line number.
compatible:
- enum:
- - allwinner,sun50i-a64-dma
- - allwinner,sun50i-h6-dma
+ oneOf:
+ - const: allwinner,sun50i-a64-dma
+ - const: allwinner,sun50i-h6-dma
+ - items:
+ - const: allwinner,sun8i-r40-dma
+ - const: allwinner,sun50i-a64-dma
reg:
maxItems: 1
diff --git a/dts/Bindings/dma/dma-common.yaml b/dts/Bindings/dma/dma-common.yaml
index c365926833..307b499e89 100644
--- a/dts/Bindings/dma/dma-common.yaml
+++ b/dts/Bindings/dma/dma-common.yaml
@@ -49,3 +49,5 @@ properties:
required:
- "#dma-cells"
+
+additionalProperties: true
diff --git a/dts/Bindings/dma/dma-controller.yaml b/dts/Bindings/dma/dma-controller.yaml
index c39f6de766..0043b91da9 100644
--- a/dts/Bindings/dma/dma-controller.yaml
+++ b/dts/Bindings/dma/dma-controller.yaml
@@ -17,6 +17,8 @@ properties:
$nodename:
pattern: "^dma-controller(@.*)?$"
+additionalProperties: true
+
examples:
- |
dma: dma-controller@48000000 {
diff --git a/dts/Bindings/dma/dma-router.yaml b/dts/Bindings/dma/dma-router.yaml
index 5b5f073931..4cee5667b8 100644
--- a/dts/Bindings/dma/dma-router.yaml
+++ b/dts/Bindings/dma/dma-router.yaml
@@ -36,6 +36,8 @@ required:
- "#dma-cells"
- dma-masters
+additionalProperties: true
+
examples:
- |
sdma_xbar: dma-router@4a002b78 {
diff --git a/dts/Bindings/dma/ingenic,dma.yaml b/dts/Bindings/dma/ingenic,dma.yaml
index 92794c5005..00f19b3cac 100644
--- a/dts/Bindings/dma/ingenic,dma.yaml
+++ b/dts/Bindings/dma/ingenic,dma.yaml
@@ -62,6 +62,8 @@ required:
- interrupts
- clocks
+unevaluatedProperties: false
+
examples:
- |
#include <dt-bindings/clock/jz4780-cgu.h>
diff --git a/dts/Bindings/dma/renesas,rcar-dmac.yaml b/dts/Bindings/dma/renesas,rcar-dmac.yaml
index 13f1a46be4..b548e47239 100644
--- a/dts/Bindings/dma/renesas,rcar-dmac.yaml
+++ b/dts/Bindings/dma/renesas,rcar-dmac.yaml
@@ -16,6 +16,7 @@ properties:
compatible:
items:
- enum:
+ - renesas,dmac-r8a7742 # RZ/G1H
- renesas,dmac-r8a7743 # RZ/G1M
- renesas,dmac-r8a7744 # RZ/G1N
- renesas,dmac-r8a7745 # RZ/G1E
diff --git a/dts/Bindings/dma/snps,dma-spear1340.yaml b/dts/Bindings/dma/snps,dma-spear1340.yaml
index 20870f5c14..ef1d6879c1 100644
--- a/dts/Bindings/dma/snps,dma-spear1340.yaml
+++ b/dts/Bindings/dma/snps,dma-spear1340.yaml
@@ -18,12 +18,15 @@ properties:
const: snps,dma-spear1340
"#dma-cells":
- const: 3
+ minimum: 3
+ maximum: 4
description: |
First cell is a phandle pointing to the DMA controller. Second one is
the DMA request line number. Third cell is the memory master identifier
for transfers on dynamically allocated channel. Fourth cell is the
- peripheral master identifier for transfers on an allocated channel.
+ peripheral master identifier for transfers on an allocated channel. Fifth
+ cell is an optional mask of the DMA channels permitted to be allocated
+ for the corresponding client device.
reg:
maxItems: 1
diff --git a/dts/Bindings/dma/st,stm32-dma.yaml b/dts/Bindings/dma/st,stm32-dma.yaml
index 71987878e4..2a5325f480 100644
--- a/dts/Bindings/dma/st,stm32-dma.yaml
+++ b/dts/Bindings/dma/st,stm32-dma.yaml
@@ -81,6 +81,8 @@ required:
- clocks
- interrupts
+unevaluatedProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/Bindings/dma/st,stm32-dmamux.yaml b/dts/Bindings/dma/st,stm32-dmamux.yaml
index 915bc4af95..c8d2b51d84 100644
--- a/dts/Bindings/dma/st,stm32-dmamux.yaml
+++ b/dts/Bindings/dma/st,stm32-dmamux.yaml
@@ -33,6 +33,8 @@ required:
- reg
- dma-masters
+unevaluatedProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/Bindings/dma/st,stm32-mdma.yaml b/dts/Bindings/dma/st,stm32-mdma.yaml
index c66543d0c2..c30be840be 100644
--- a/dts/Bindings/dma/st,stm32-mdma.yaml
+++ b/dts/Bindings/dma/st,stm32-mdma.yaml
@@ -84,6 +84,8 @@ required:
- clocks
- interrupts
+unevaluatedProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/Bindings/dma/ti/k3-udma.yaml b/dts/Bindings/dma/ti/k3-udma.yaml
index dd70ddab4f..9a87fd9041 100644
--- a/dts/Bindings/dma/ti/k3-udma.yaml
+++ b/dts/Bindings/dma/ti/k3-udma.yaml
@@ -141,6 +141,8 @@ then:
required:
- ti,udma-atype
+unevaluatedProperties: false
+
examples:
- |+
cbass_main {
diff --git a/dts/Bindings/edac/amazon,al-mc-edac.yaml b/dts/Bindings/edac/amazon,al-mc-edac.yaml
new file mode 100644
index 0000000000..a25387df08
--- /dev/null
+++ b/dts/Bindings/edac/amazon,al-mc-edac.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/edac/amazon,al-mc-edac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amazon's Annapurna Labs Memory Controller EDAC
+
+maintainers:
+ - Talel Shenhar <talel@amazon.com>
+ - Talel Shenhar <talelshenhar@gmail.com>
+
+description: |
+ EDAC node is defined to describe on-chip error detection and correction for
+ Amazon's Annapurna Labs Memory Controller.
+
+properties:
+
+ compatible:
+ const: amazon,al-mc-edac
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: uncorrectable error interrupt
+ - description: correctable error interrupt
+
+ interrupt-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: ue
+ - const: ce
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ edac@f0080000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "amazon,al-mc-edac";
+ reg = <0x0 0xf0080000 0x0 0x00010000>;
+ interrupt-parent = <&amazon_al_system_fabric>;
+ interrupt-names = "ue";
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
diff --git a/dts/Bindings/edac/dmc-520.yaml b/dts/Bindings/edac/dmc-520.yaml
index 9272d2bd86..3b6842e92d 100644
--- a/dts/Bindings/edac/dmc-520.yaml
+++ b/dts/Bindings/edac/dmc-520.yaml
@@ -49,6 +49,8 @@ required:
- interrupts
- interrupt-names
+additionalProperties: false
+
examples:
- |
dmc0: dmc@200000 {
diff --git a/dts/Bindings/eeprom/at24.yaml b/dts/Bindings/eeprom/at24.yaml
index 4cee72d533..6edfa705b4 100644
--- a/dts/Bindings/eeprom/at24.yaml
+++ b/dts/Bindings/eeprom/at24.yaml
@@ -114,6 +114,9 @@ properties:
- const: renesas,r1ex24128
- const: atmel,24c128
+ label:
+ description: Descriptive name of the EEPROM.
+
reg:
maxItems: 1
diff --git a/dts/Bindings/eeprom/at25.txt b/dts/Bindings/eeprom/at25.txt
deleted file mode 100644
index fcacd97abd..0000000000
--- a/dts/Bindings/eeprom/at25.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-EEPROMs (SPI) compatible with Atmel at25.
-
-Required properties:
-- compatible : Should be "<vendor>,<type>", and generic value "atmel,at25".
- Example "<vendor>,<type>" values:
- "anvo,anv32e61w"
- "microchip,25lc040"
- "st,m95m02"
- "st,m95256"
-
-- reg : chip select number
-- spi-max-frequency : max spi frequency to use
-- pagesize : size of the eeprom page
-- size : total eeprom size in bytes
-- address-width : number of address bits (one of 8, 9, 16, or 24).
- For 9 bits, the MSB of the address is sent as bit 3 of the instruction
- byte, before the address byte.
-
-Optional properties:
-- spi-cpha : SPI shifted clock phase, as per spi-bus bindings.
-- spi-cpol : SPI inverse clock polarity, as per spi-bus bindings.
-- read-only : this parameter-less property disables writes to the eeprom
-- wp-gpios : GPIO to which the write-protect pin of the chip is connected
-
-Obsolete legacy properties can be used in place of "size", "pagesize",
-"address-width", and "read-only":
-- at25,byte-len : total eeprom size in bytes
-- at25,addr-mode : addr-mode flags, as defined in include/linux/spi/eeprom.h
-- at25,page-size : size of the eeprom page
-
-Additional compatible properties are also allowed.
-
-Example:
- eeprom@0 {
- compatible = "st,m95256", "atmel,at25";
- reg = <0>
- spi-max-frequency = <5000000>;
- spi-cpha;
- spi-cpol;
- wp-gpios = <&gpio1 3 0>;
-
- pagesize = <64>;
- size = <32768>;
- address-width = <16>;
- };
diff --git a/dts/Bindings/eeprom/at25.yaml b/dts/Bindings/eeprom/at25.yaml
new file mode 100644
index 0000000000..9810619a2b
--- /dev/null
+++ b/dts/Bindings/eeprom/at25.yaml
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/eeprom/at25.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: SPI EEPROMs compatible with Atmel's AT25
+
+maintainers:
+ - Christian Eggers <ceggers@arri.de>
+
+properties:
+ $nodename:
+ pattern: "^eeprom@[0-9a-f]{1,2}$"
+
+ # There are multiple known vendors who manufacture EEPROM chips compatible
+ # with Atmel's AT25. The compatible string requires two items where the
+ # 'vendor' and 'model' parts of the first are the actual chip and the second
+ # item is fixed to "atmel,at25". Some existing bindings only have the
+ # "atmel,at25" part and should be fixed by somebody who knows vendor and
+ # product.
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - anvo,anv32e61w
+ - atmel,at25256B
+ - fujitsu,mb85rs1mt
+ - fujitsu,mb85rs64
+ - microchip,at25160bn
+ - microchip,25lc040
+ - st,m95m02
+ - st,m95256
+
+ - const: atmel,at25
+
+ # Please don't use this alternative for new bindings.
+ - items:
+ - const: atmel,at25
+
+ reg:
+ description:
+ Chip select number.
+
+ spi-max-frequency: true
+
+ pagesize:
+ $ref: /schemas/types.yaml#definitions/uint32
+ enum: [1, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, 131072]
+ description:
+ Size of the eeprom page.
+
+ size:
+ $ref: /schemas/types.yaml#definitions/uint32
+ description:
+ Total eeprom size in bytes.
+
+ address-width:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 8, 9, 16, 24 ]
+ description:
+ Number of address bits.
+ For 9 bits, the MSB of the address is sent as bit 3 of the instruction
+ byte, before the address byte.
+
+ spi-cpha: true
+
+ spi-cpol: true
+
+ read-only:
+ description:
+ Disable writes to the eeprom.
+ type: boolean
+
+ wp-gpios:
+ maxItems: 1
+ description:
+ GPIO to which the write-protect pin of the chip is connected.
+
+ # Deprecated: at25,byte-len, at25,addr-mode, at25,page-size
+ at25,byte-len:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Total eeprom size in bytes. Deprecated, use "size" property instead.
+ deprecated: true
+
+ at25,addr-mode:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Addr-mode flags, as defined in include/linux/spi/eeprom.h.
+ Deprecated, use "address-width" property instead.
+ deprecated: true
+
+ at25,page-size:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Size of the eeprom page. Deprecated, use "pagesize" property instead.
+ deprecated: true
+
+required:
+ - compatible
+ - reg
+ - spi-max-frequency
+ - pagesize
+ - size
+ - address-width
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ spi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ compatible = "st,m95256", "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <5000000>;
+ spi-cpha;
+ spi-cpol;
+ wp-gpios = <&gpio1 3 0>;
+
+ pagesize = <64>;
+ size = <32768>;
+ address-width = <16>;
+ };
+ };
diff --git a/dts/Bindings/example-schema.yaml b/dts/Bindings/example-schema.yaml
index 822975dbea..a97f39109f 100644
--- a/dts/Bindings/example-schema.yaml
+++ b/dts/Bindings/example-schema.yaml
@@ -81,6 +81,8 @@ properties:
maxItems: 1
description: bus clock. A description is only needed for a single item if
there's something unique to add.
+ The items should have a fixed order, so pattern matching names are
+ discouraged.
clock-names:
items:
@@ -97,6 +99,8 @@ properties:
A variable number of interrupts warrants a description of what conditions
affect the number of interrupts. Otherwise, descriptions on standard
properties are not necessary.
+ The items should have a fixed order, so pattern matching names are
+ discouraged.
interrupt-names:
# minItems must be specified here because the default would be 2
@@ -196,14 +200,24 @@ required:
#
# If the conditionals become too unweldy, then it may be better to just split
# the binding into separate schema documents.
-if:
- properties:
- compatible:
- contains:
- const: vendor,soc2-ip
-then:
- required:
- - foo-supply
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: vendor,soc2-ip
+ then:
+ required:
+ - foo-supply
+ # Altering schema depending on presence of properties is usually done by
+ # dependencies (see above), however some adjustments might require if:
+ - if:
+ required:
+ - vendor,bool-property
+ then:
+ properties:
+ vendor,int-property:
+ enum: [2, 4, 6]
# Ideally, the schema should have this line otherwise any other properties
# present are allowed. There's a few common properties such as 'status' and
@@ -211,6 +225,9 @@ then:
#
# This can't be used in cases where another schema is referenced
# (i.e. allOf: [{$ref: ...}]).
+# If and only if another schema is referenced and arbitrary children nodes can
+# appear, "unevaluatedProperties: false" could be used. A typical example is
+# an I2C controller where no name pattern matching for children can be added.
additionalProperties: false
examples:
diff --git a/dts/Bindings/extcon/extcon-ptn5150.txt b/dts/Bindings/extcon/extcon-ptn5150.txt
deleted file mode 100644
index 936fbdf128..0000000000
--- a/dts/Bindings/extcon/extcon-ptn5150.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-* PTN5150 CC (Configuration Channel) Logic device
-
-PTN5150 is a small thin low power CC logic chip supporting the USB Type-C
-connector application with CC control logic detection and indication functions.
-It is interfaced to the host controller using an I2C interface.
-
-Required properties:
-- compatible: should be "nxp,ptn5150"
-- reg: specifies the I2C slave address of the device
-- int-gpio: should contain a phandle and GPIO specifier for the GPIO pin
- connected to the PTN5150's INTB pin.
-- vbus-gpio: should contain a phandle and GPIO specifier for the GPIO pin which
- is used to control VBUS.
-- pinctrl-names : a pinctrl state named "default" must be defined.
-- pinctrl-0 : phandle referencing pin configuration of interrupt and vbus
- control.
-
-Example:
- ptn5150@1d {
- compatible = "nxp,ptn5150";
- reg = <0x1d>;
- int-gpio = <&msmgpio 78 GPIO_ACTIVE_HIGH>;
- vbus-gpio = <&msmgpio 148 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&ptn5150_default>;
- status = "okay";
- };
diff --git a/dts/Bindings/extcon/extcon-ptn5150.yaml b/dts/Bindings/extcon/extcon-ptn5150.yaml
new file mode 100644
index 0000000000..4b0f414486
--- /dev/null
+++ b/dts/Bindings/extcon/extcon-ptn5150.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/extcon/extcon-ptn5150.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PTN5150 CC (Configuration Channel) Logic device
+
+maintainers:
+ - Krzysztof Kozlowski <krzk@kernel.org>
+
+description: |
+ PTN5150 is a small thin low power CC logic chip supporting the USB Type-C
+ connector application with CC control logic detection and indication
+ functions. It is interfaced to the host controller using an I2C interface.
+
+properties:
+ compatible:
+ const: nxp,ptn5150
+
+ int-gpios:
+ deprecated: true
+ description:
+ GPIO pin (input) connected to the PTN5150's INTB pin.
+ Use "interrupts" instead.
+
+ interrupts:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+ vbus-gpios:
+ description:
+ GPIO pin (output) used to control VBUS. If skipped, no such control
+ takes place.
+
+required:
+ - compatible
+ - interrupts
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ptn5150@1d {
+ compatible = "nxp,ptn5150";
+ reg = <0x1d>;
+ interrupt-parent = <&msmgpio>;
+ interrupts = <78 IRQ_TYPE_LEVEL_HIGH>;
+ vbus-gpios = <&msmgpio 148 GPIO_ACTIVE_HIGH>;
+ };
+ };
diff --git a/dts/Bindings/extcon/wlf,arizona.yaml b/dts/Bindings/extcon/wlf,arizona.yaml
index f9845dc2f5..5fe784f487 100644
--- a/dts/Bindings/extcon/wlf,arizona.yaml
+++ b/dts/Bindings/extcon/wlf,arizona.yaml
@@ -123,3 +123,5 @@ properties:
$ref: "/schemas/types.yaml#/definitions/uint32"
minimum: 0
maximum: 3
+
+additionalProperties: true
diff --git a/dts/Bindings/fsi/fsi-master-aspeed.txt b/dts/Bindings/fsi/fsi-master-aspeed.txt
index b758f91914..9853fefff5 100644
--- a/dts/Bindings/fsi/fsi-master-aspeed.txt
+++ b/dts/Bindings/fsi/fsi-master-aspeed.txt
@@ -12,6 +12,13 @@ Required properties:
- pinctrl-0: phandle to pinctrl node
- pinctrl-names: pinctrl state
+Optional properties:
+ - cfam-reset-gpios: GPIO for CFAM reset
+
+ - fsi-routing-gpios: GPIO for setting the FSI mux (internal or cabled)
+ - fsi-mux-gpios: GPIO for detecting the desired FSI mux state
+
+
Examples:
fsi-master {
@@ -21,4 +28,9 @@ Examples:
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fsi1_default>;
clocks = <&syscon ASPEED_CLK_GATE_FSICLK>;
+
+ fsi-routing-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>;
+ fsi-mux-gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_HIGH>;
+
+ cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
};
diff --git a/dts/Bindings/fsi/ibm,fsi2spi.yaml b/dts/Bindings/fsi/ibm,fsi2spi.yaml
index b26d4b4be7..e425278653 100644
--- a/dts/Bindings/fsi/ibm,fsi2spi.yaml
+++ b/dts/Bindings/fsi/ibm,fsi2spi.yaml
@@ -19,6 +19,7 @@ properties:
compatible:
enum:
- ibm,fsi2spi
+ - ibm,fsi2spi-restricted
reg:
items:
@@ -28,6 +29,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
fsi2spi@1c00 {
diff --git a/dts/Bindings/fuse/nvidia,tegra20-fuse.txt b/dts/Bindings/fuse/nvidia,tegra20-fuse.txt
index 2aaf661c04..b109911669 100644
--- a/dts/Bindings/fuse/nvidia,tegra20-fuse.txt
+++ b/dts/Bindings/fuse/nvidia,tegra20-fuse.txt
@@ -7,6 +7,7 @@ Required properties:
For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse".
For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain
"nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse".
+ For Tegra234 must contain "nvidia,tegra234-efuse".
Details:
nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
due to a hardware bug. Tegra20 also lacks certain information which is
diff --git a/dts/Bindings/gpio/fsl-imx-gpio.yaml b/dts/Bindings/gpio/fsl-imx-gpio.yaml
index 0b223abe8c..f57d22d1eb 100644
--- a/dts/Bindings/gpio/fsl-imx-gpio.yaml
+++ b/dts/Bindings/gpio/fsl-imx-gpio.yaml
@@ -11,12 +11,33 @@ maintainers:
properties:
compatible:
- enum:
- - fsl,imx1-gpio
- - fsl,imx21-gpio
- - fsl,imx31-gpio
- - fsl,imx35-gpio
- - fsl,imx7d-gpio
+ oneOf:
+ - enum:
+ - fsl,imx1-gpio
+ - fsl,imx21-gpio
+ - fsl,imx31-gpio
+ - fsl,imx35-gpio
+ - fsl,imx7d-gpio
+ - items:
+ - const: fsl,imx35-gpio
+ - const: fsl,imx31-gpio
+ - items:
+ - enum:
+ - fsl,imx50-gpio
+ - fsl,imx51-gpio
+ - fsl,imx53-gpio
+ - fsl,imx6q-gpio
+ - fsl,imx6sl-gpio
+ - fsl,imx6sll-gpio
+ - fsl,imx6sx-gpio
+ - fsl,imx6ul-gpio
+ - fsl,imx7d-gpio
+ - fsl,imx8mm-gpio
+ - fsl,imx8mn-gpio
+ - fsl,imx8mp-gpio
+ - fsl,imx8mq-gpio
+ - fsl,imx8qxp-gpio
+ - const: fsl,imx35-gpio
reg:
maxItems: 1
@@ -41,6 +62,28 @@ properties:
const: 2
gpio-controller: true
+ gpio-line-names: true
+ gpio-ranges: true
+
+ power-domains:
+ maxItems: 1
+
+patternProperties:
+ "^(hog-[0-9]+|.+-hog(-[0-9]+)?)$":
+ type: object
+ properties:
+ gpio-hog: true
+ gpios: true
+ input: true
+ output-high: true
+ output-low: true
+ line-name: true
+
+ required:
+ - gpio-hog
+ - gpios
+
+ additionalProperties: false
required:
- compatible
diff --git a/dts/Bindings/gpio/gpio-max732x.txt b/dts/Bindings/gpio/gpio-max732x.txt
deleted file mode 100644
index b3a9c0c328..0000000000
--- a/dts/Bindings/gpio/gpio-max732x.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-* MAX732x-compatible I/O expanders
-
-Required properties:
- - compatible: Should be one of the following:
- - "maxim,max7319": For the Maxim MAX7319
- - "maxim,max7320": For the Maxim MAX7320
- - "maxim,max7321": For the Maxim MAX7321
- - "maxim,max7322": For the Maxim MAX7322
- - "maxim,max7323": For the Maxim MAX7323
- - "maxim,max7324": For the Maxim MAX7324
- - "maxim,max7325": For the Maxim MAX7325
- - "maxim,max7326": For the Maxim MAX7326
- - "maxim,max7327": For the Maxim MAX7327
- - reg: I2C slave address for this device.
- - gpio-controller: Marks the device node as a GPIO controller.
- - #gpio-cells: Should be 2.
- - first cell is the GPIO number
- - second cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>.
- Only the GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
-
-Optional properties:
-
- The I/O expander can detect input state changes, and thus optionally act as
- an interrupt controller. When the expander interrupt line is connected all the
- following properties must be set. For more information please see the
- interrupt controller device tree bindings documentation available at
- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt.
-
- - interrupt-controller: Identifies the node as an interrupt controller.
- - #interrupt-cells: Number of cells to encode an interrupt source, shall be 2.
- - first cell is the pin number
- - second cell is used to specify flags
- - interrupts: Interrupt specifier for the controllers interrupt.
-
-Please refer to gpio.txt in this directory for details of the common GPIO
-bindings used by client devices.
-
-Example 1. MAX7325 with interrupt support enabled (CONFIG_GPIO_MAX732X_IRQ=y):
-
- expander: max7325@6d {
- compatible = "maxim,max7325";
- reg = <0x6d>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gpio4>;
- interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
- };
-
-Example 2. MAX7325 with interrupt support disabled (CONFIG_GPIO_MAX732X_IRQ=n):
-
- expander: max7325@6d {
- compatible = "maxim,max7325";
- reg = <0x6d>;
- gpio-controller;
- #gpio-cells = <2>;
- };
diff --git a/dts/Bindings/gpio/gpio-pca953x.txt b/dts/Bindings/gpio/gpio-pca953x.txt
deleted file mode 100644
index 3126c3817e..0000000000
--- a/dts/Bindings/gpio/gpio-pca953x.txt
+++ /dev/null
@@ -1,90 +0,0 @@
-* NXP PCA953x I2C GPIO multiplexer
-
-Required properties:
- - compatible: Has to contain one of the following:
- nxp,pca6416
- nxp,pca9505
- nxp,pca9534
- nxp,pca9535
- nxp,pca9536
- nxp,pca9537
- nxp,pca9538
- nxp,pca9539
- nxp,pca9554
- nxp,pca9555
- nxp,pca9556
- nxp,pca9557
- nxp,pca9574
- nxp,pca9575
- nxp,pca9698
- nxp,pcal6416
- nxp,pcal6524
- nxp,pcal9535
- nxp,pcal9555a
- maxim,max7310
- maxim,max7312
- maxim,max7313
- maxim,max7315
- ti,pca6107
- ti,pca9536
- ti,tca6408
- ti,tca6416
- ti,tca6424
- ti,tca9539
- ti,tca9554
- onnn,cat9554
- onnn,pca9654
- exar,xra1202
- - gpio-controller: if used as gpio expander.
- - #gpio-cells: if used as gpio expander.
- - interrupt-controller: if to be used as interrupt expander.
- - #interrupt-cells: if to be used as interrupt expander.
-
-Optional properties:
- - interrupts: interrupt specifier for the device's interrupt output.
- - reset-gpios: GPIO specification for the RESET input. This is an
- active low signal to the PCA953x.
- - vcc-supply: power supply regulator.
-
-Example:
-
-
- gpio@20 {
- compatible = "nxp,pca9505";
- reg = <0x20>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pca9505>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&gpio3>;
- interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
- };
-
-
-Example with Interrupts:
-
-
- gpio99: gpio@22 {
- compatible = "nxp,pcal6524";
- reg = <0x22>;
- interrupt-parent = <&gpio6>;
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>; /* gpio6_161 */
- interrupt-controller;
- #interrupt-cells = <2>;
- vcc-supply = <&vdds_1v8_main>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-line-names =
- "hdmi-ct-hpd", "hdmi.ls-oe", "p02", "p03", "vibra", "fault2", "p06", "p07",
- "en-usb", "en-host1", "en-host2", "chg-int", "p14", "p15", "mic-int", "en-modem",
- "shdn-hs-amp", "chg-status+red", "green", "blue", "en-esata", "fault1", "p26", "p27";
- };
-
- ts3a227@3b {
- compatible = "ti,ts3a227e";
- reg = <0x3b>;
- interrupt-parent = <&gpio99>;
- interrupts = <14 IRQ_TYPE_EDGE_RISING>;
- ti,micbias = <0>; /* 2.1V */
- };
-
diff --git a/dts/Bindings/gpio/gpio-pca95xx.yaml b/dts/Bindings/gpio/gpio-pca95xx.yaml
new file mode 100644
index 0000000000..183ec23eda
--- /dev/null
+++ b/dts/Bindings/gpio/gpio-pca95xx.yaml
@@ -0,0 +1,232 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/gpio-pca95xx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP PCA95xx I2C GPIO multiplexer
+
+maintainers:
+ - Krzysztof Kozlowski <krzk@kernel.org>
+
+description: |+
+ Bindings for the family of I2C GPIO multiplexers/expanders: NXP PCA95xx,
+ Maxim MAX73xx
+
+properties:
+ compatible:
+ enum:
+ - exar,xra1202
+ - maxim,max7310
+ - maxim,max7312
+ - maxim,max7313
+ - maxim,max7315
+ - maxim,max7319
+ - maxim,max7320
+ - maxim,max7321
+ - maxim,max7322
+ - maxim,max7323
+ - maxim,max7324
+ - maxim,max7325
+ - maxim,max7326
+ - maxim,max7327
+ - nxp,pca6416
+ - nxp,pca9505
+ - nxp,pca9534
+ - nxp,pca9535
+ - nxp,pca9536
+ - nxp,pca9537
+ - nxp,pca9538
+ - nxp,pca9539
+ - nxp,pca9554
+ - nxp,pca9555
+ - nxp,pca9556
+ - nxp,pca9557
+ - nxp,pca9574
+ - nxp,pca9575
+ - nxp,pca9698
+ - nxp,pcal6416
+ - nxp,pcal6524
+ - nxp,pcal9535
+ - nxp,pcal9555a
+ - onnn,cat9554
+ - onnn,pca9654
+ - ti,pca6107
+ - ti,pca9536
+ - ti,tca6408
+ - ti,tca6416
+ - ti,tca6424
+ - ti,tca9539
+ - ti,tca9554
+
+ reg:
+ maxItems: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-line-names:
+ minItems: 1
+ maxItems: 32
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ reset-gpios:
+ description:
+ GPIO specification for the RESET input. This is an active low signal to
+ the PCA953x. Not valid for Maxim MAX732x devices.
+
+ vcc-supply:
+ description:
+ Optional power supply. Not valid for Maxim MAX732x devices.
+
+ wakeup-source:
+ $ref: /schemas/types.yaml#/definitions/flag
+
+patternProperties:
+ "^(hog-[0-9]+|.+-hog(-[0-9]+)?)$":
+ type: object
+ properties:
+ gpio-hog: true
+ gpios: true
+ input: true
+ output-high: true
+ output-low: true
+ line-name: true
+
+ required:
+ - gpio-hog
+ - gpios
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - "#gpio-cells"
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - maxim,max7320
+ - maxim,max7321
+ - maxim,max7322
+ - maxim,max7323
+ - maxim,max7324
+ - maxim,max7325
+ - maxim,max7326
+ - maxim,max7327
+ then:
+ properties:
+ reset-gpios: false
+ vcc-supply: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@20 {
+ compatible = "nxp,pca9505";
+ reg = <0x20>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pca9505>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+
+ usb3-sata-sel-hog {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "usb3_sata_sel";
+ };
+ };
+ };
+
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio99: gpio@22 {
+ compatible = "nxp,pcal6524";
+ reg = <0x22>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>; /* gpio6_161 */
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ vcc-supply = <&vdds_1v8_main>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "hdmi-ct-hpd", "hdmi.ls-oe", "p02", "p03",
+ "vibra", "fault2", "p06", "p07", "en-usb",
+ "en-host1", "en-host2", "chg-int", "p14", "p15",
+ "mic-int", "en-modem", "shdn-hs-amp",
+ "chg-status+red", "green", "blue", "en-esata",
+ "fault1", "p26", "p27";
+ };
+
+ ts3a227@3b {
+ compatible = "ti,ts3a227e";
+ reg = <0x3b>;
+ interrupt-parent = <&gpio99>;
+ interrupts = <14 IRQ_TYPE_EDGE_RISING>;
+ ti,micbias = <0>; /* 2.1V */
+ };
+ };
+
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* MAX7325 with interrupt support enabled */
+ gpio@6d {
+ compatible = "maxim,max7325";
+ reg = <0x6d>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
+
+ - |
+ i2c3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* MAX7325 with interrupt support disabled */
+ gpio@6e {
+ compatible = "maxim,max7325";
+ reg = <0x6e>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
diff --git a/dts/Bindings/gpio/gpio-vf610.txt b/dts/Bindings/gpio/gpio-vf610.txt
deleted file mode 100644
index ae254aadee..0000000000
--- a/dts/Bindings/gpio/gpio-vf610.txt
+++ /dev/null
@@ -1,63 +0,0 @@
-* Freescale VF610 PORT/GPIO module
-
-The Freescale PORT/GPIO modules are two adjacent modules providing GPIO
-functionality. Each pair serves 32 GPIOs. The VF610 has 5 instances of
-each, and each PORT module has its own interrupt.
-
-Required properties for GPIO node:
-- compatible : Should be "fsl,<soc>-gpio", below is supported list:
- "fsl,vf610-gpio"
- "fsl,imx7ulp-gpio"
-- reg : The first reg tuple represents the PORT module, the second tuple
- the GPIO module.
-- interrupts : Should be the port interrupt shared by all 32 pins.
-- gpio-controller : Marks the device node as a gpio controller.
-- #gpio-cells : Should be two. The first cell is the pin number and
- the second cell is used to specify the gpio polarity:
- 0 = active high
- 1 = active low
-- interrupt-controller: Marks the device node as an interrupt controller.
-- #interrupt-cells : Should be 2. The first cell is the GPIO number.
- The second cell bits[3:0] is used to specify trigger type and level flags:
- 1 = low-to-high edge triggered.
- 2 = high-to-low edge triggered.
- 4 = active high level-sensitive.
- 8 = active low level-sensitive.
-
-Optional properties:
--clocks: Must contain an entry for each entry in clock-names.
- See common clock-bindings.txt for details.
--clock-names: A list of clock names. For imx7ulp, it must contain
- "gpio", "port".
-
-Note: Each GPIO port should have an alias correctly numbered in "aliases"
-node.
-
-Examples:
-
-aliases {
- gpio0 = &gpio1;
- gpio1 = &gpio2;
-};
-
-gpio1: gpio@40049000 {
- compatible = "fsl,vf610-gpio";
- reg = <0x40049000 0x1000 0x400ff000 0x40>;
- interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-ranges = <&iomuxc 0 0 32>;
-};
-
-gpio2: gpio@4004a000 {
- compatible = "fsl,vf610-gpio";
- reg = <0x4004a000 0x1000 0x400ff040 0x40>;
- interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-ranges = <&iomuxc 0 32 32>;
-};
diff --git a/dts/Bindings/gpio/gpio-vf610.yaml b/dts/Bindings/gpio/gpio-vf610.yaml
new file mode 100644
index 0000000000..19738a457a
--- /dev/null
+++ b/dts/Bindings/gpio/gpio-vf610.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/gpio-vf610.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale VF610 PORT/GPIO module
+
+maintainers:
+ - Stefan Agner <stefan@agner.ch>
+
+description: |
+ The Freescale PORT/GPIO modules are two adjacent modules providing GPIO
+ functionality. Each pair serves 32 GPIOs. The VF610 has 5 instances of
+ each, and each PORT module has its own interrupt.
+
+ Note: Each GPIO port should have an alias correctly numbered in "aliases"
+ node.
+
+properties:
+ compatible:
+ oneOf:
+ - const: fsl,vf610-gpio
+ - items:
+ - const: fsl,imx7ulp-gpio
+ - const: fsl,vf610-gpio
+
+ reg:
+ description: The first reg tuple represents the PORT module, the second tuple
+ represents the GPIO module.
+ maxItems: 2
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 2
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-controller: true
+
+ clocks:
+ items:
+ - description: SoC GPIO clock
+ - description: SoC PORT clock
+
+ clock-names:
+ items:
+ - const: gpio
+ - const: port
+
+ gpio-ranges:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - "#interrupt-cells"
+ - "#gpio-cells"
+ - gpio-controller
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ gpio1: gpio@40049000 {
+ compatible = "fsl,vf610-gpio";
+ reg = <0x40049000 0x1000>, <0x400ff000 0x40>;
+ interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 0 32>;
+ };
diff --git a/dts/Bindings/gpio/kontron,sl28cpld-gpio.yaml b/dts/Bindings/gpio/kontron,sl28cpld-gpio.yaml
new file mode 100644
index 0000000000..e2d2c10e53
--- /dev/null
+++ b/dts/Bindings/gpio/kontron,sl28cpld-gpio.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/kontron,sl28cpld-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: GPIO driver for the sl28cpld board management controller
+
+maintainers:
+ - Michael Walle <michael@walle.cc>
+
+description: |
+ This module is part of the sl28cpld multi-function device. For more
+ details see ../mfd/kontron,sl28cpld.yaml.
+
+ There are three flavors of the GPIO controller, one full featured
+ input/output with interrupt support (kontron,sl28cpld-gpio), one
+ output-only (kontron,sl28-gpo) and one input-only (kontron,sl28-gpi).
+
+ Each controller supports 8 GPIO lines.
+
+properties:
+ compatible:
+ enum:
+ - kontron,sl28cpld-gpio
+ - kontron,sl28cpld-gpi
+ - kontron,sl28cpld-gpo
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#interrupt-cells":
+ const: 2
+
+ interrupt-controller: true
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-controller: true
+
+ gpio-line-names:
+ minItems: 1
+ maxItems: 8
+
+required:
+ - compatible
+ - "#gpio-cells"
+ - gpio-controller
+
+additionalProperties: false
diff --git a/dts/Bindings/gpio/pl061-gpio.yaml b/dts/Bindings/gpio/pl061-gpio.yaml
index 313b172292..bd35cbf7fa 100644
--- a/dts/Bindings/gpio/pl061-gpio.yaml
+++ b/dts/Bindings/gpio/pl061-gpio.yaml
@@ -51,7 +51,10 @@ properties:
gpio-controller: true
+ gpio-line-names: true
+
gpio-ranges:
+ minItems: 1
maxItems: 8
required:
diff --git a/dts/Bindings/gpio/renesas,rcar-gpio.yaml b/dts/Bindings/gpio/renesas,rcar-gpio.yaml
index 3ad229307b..5026662e45 100644
--- a/dts/Bindings/gpio/renesas,rcar-gpio.yaml
+++ b/dts/Bindings/gpio/renesas,rcar-gpio.yaml
@@ -37,6 +37,7 @@ properties:
- renesas,gpio-r8a774a1 # RZ/G2M
- renesas,gpio-r8a774b1 # RZ/G2N
- renesas,gpio-r8a774c0 # RZ/G2E
+ - renesas,gpio-r8a774e1 # RZ/G2H
- renesas,gpio-r8a7795 # R-Car H3
- renesas,gpio-r8a7796 # R-Car M3-W
- renesas,gpio-r8a77961 # R-Car M3-W+
diff --git a/dts/Bindings/gpio/snps,dw-apb-gpio.yaml b/dts/Bindings/gpio/snps,dw-apb-gpio.yaml
index 1240f62892..b391cc1b45 100644
--- a/dts/Bindings/gpio/snps,dw-apb-gpio.yaml
+++ b/dts/Bindings/gpio/snps,dw-apb-gpio.yaml
@@ -61,8 +61,14 @@ patternProperties:
'#gpio-cells':
const: 2
+ ngpios:
+ default: 32
+ minimum: 1
+ maximum: 32
+
snps,nr-gpios:
description: The number of GPIO pins exported by the port.
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
default: 32
minimum: 1
diff --git a/dts/Bindings/gpio/socionext,uniphier-gpio.yaml b/dts/Bindings/gpio/socionext,uniphier-gpio.yaml
index c58ff9a94f..1a54db04f2 100644
--- a/dts/Bindings/gpio/socionext,uniphier-gpio.yaml
+++ b/dts/Bindings/gpio/socionext,uniphier-gpio.yaml
@@ -64,6 +64,8 @@ required:
- gpio-ranges
- socionext,interrupt-ranges
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/gpio/gpio.h>
diff --git a/dts/Bindings/gpu/arm,mali-midgard.yaml b/dts/Bindings/gpu/arm,mali-midgard.yaml
index 80d519a76d..e9c42b59f3 100644
--- a/dts/Bindings/gpu/arm,mali-midgard.yaml
+++ b/dts/Bindings/gpu/arm,mali-midgard.yaml
@@ -74,6 +74,7 @@ properties:
- const: bus
mali-supply: true
+ opp-table: true
power-domains:
maxItems: 1
diff --git a/dts/Bindings/gpu/arm,mali-utgard.yaml b/dts/Bindings/gpu/arm,mali-utgard.yaml
index 6226d31ec4..eceaa176bd 100644
--- a/dts/Bindings/gpu/arm,mali-utgard.yaml
+++ b/dts/Bindings/gpu/arm,mali-utgard.yaml
@@ -8,7 +8,7 @@ title: ARM Mali Utgard GPU
maintainers:
- Rob Herring <robh@kernel.org>
- - Maxime Ripard <maxime.ripard@free-electrons.com>
+ - Maxime Ripard <mripard@kernel.org>
- Heiko Stuebner <heiko@sntech.de>
properties:
@@ -25,6 +25,7 @@ properties:
- allwinner,sun4i-a10-mali
- allwinner,sun7i-a20-mali
- allwinner,sun8i-h3-mali
+ - allwinner,sun8i-r40-mali
- allwinner,sun50i-a64-mali
- rockchip,rk3036-mali
- rockchip,rk3066-mali
@@ -100,6 +101,8 @@ properties:
mali-supply: true
+ opp-table: true
+
power-domains:
maxItems: 1
@@ -129,6 +132,7 @@ allOf:
enum:
- allwinner,sun4i-a10-mali
- allwinner,sun7i-a20-mali
+ - allwinner,sun8i-r40-mali
- allwinner,sun50i-a64-mali
- allwinner,sun50i-h5-mali
- amlogic,meson8-mali
diff --git a/dts/Bindings/gpu/samsung-rotator.yaml b/dts/Bindings/gpu/samsung-rotator.yaml
index 665c6e3b31..62486f5517 100644
--- a/dts/Bindings/gpu/samsung-rotator.yaml
+++ b/dts/Bindings/gpu/samsung-rotator.yaml
@@ -22,6 +22,12 @@ properties:
interrupts:
maxItems: 1
+ iommus:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
clocks:
maxItems: 1
diff --git a/dts/Bindings/gpu/vivante,gc.yaml b/dts/Bindings/gpu/vivante,gc.yaml
index 4843df1ddb..3ed1726299 100644
--- a/dts/Bindings/gpu/vivante,gc.yaml
+++ b/dts/Bindings/gpu/vivante,gc.yaml
@@ -21,12 +21,19 @@ properties:
interrupts:
maxItems: 1
+ '#cooling-cells':
+ const: 2
+
+ assigned-clock-parents: true
+ assigned-clock-rates: true
+ assigned-clocks: true
+
clocks:
items:
- description: AXI/master interface clock
- description: GPU core clock
- description: Shader clock (only required if GPU has feature PIPE_3D)
- - description: AHB/slave interface clock (only required if GPU can gate
+ - description: AHB/slave interface clock (only required if GPU can gate
slave interface independently)
minItems: 1
maxItems: 4
diff --git a/dts/Bindings/hwlock/omap-hwspinlock.txt b/dts/Bindings/hwlock/omap-hwspinlock.txt
deleted file mode 100644
index 8d365f8969..0000000000
--- a/dts/Bindings/hwlock/omap-hwspinlock.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-TI HwSpinlock for OMAP and K3 based SoCs
-=========================================
-
-Required properties:
-- compatible: Should be one of the following,
- "ti,omap4-hwspinlock" for
- OMAP44xx, OMAP54xx, AM33xx, AM43xx, DRA7xx SoCs
- "ti,am654-hwspinlock" for
- K3 AM65x and J721E SoCs
-- reg: Contains the hwspinlock module register address space
- (base address and length)
-- ti,hwmods: Name of the hwmod associated with the hwspinlock device
- (for OMAP architecture based SoCs only)
-- #hwlock-cells: Should be 1. The OMAP hwspinlock users will use a
- 0-indexed relative hwlock number as the argument
- specifier value for requesting a specific hwspinlock
- within a hwspinlock bank.
-
-Please look at the generic hwlock binding for usage information for consumers,
-"Documentation/devicetree/bindings/hwlock/hwlock.txt"
-
-Example:
-
-1. OMAP4 SoCs
-hwspinlock: spinlock@4a0f6000 {
- compatible = "ti,omap4-hwspinlock";
- reg = <0x4a0f6000 0x1000>;
- ti,hwmods = "spinlock";
- #hwlock-cells = <1>;
-};
-
-2. AM65x SoCs and J721E SoCs
-&cbass_main {
- cbass_main_navss: interconnect0 {
- hwspinlock: spinlock@30e00000 {
- compatible = "ti,am654-hwspinlock";
- reg = <0x00 0x30e00000 0x00 0x1000>;
- #hwlock-cells = <1>;
- };
- };
-};
diff --git a/dts/Bindings/hwlock/ti,omap-hwspinlock.yaml b/dts/Bindings/hwlock/ti,omap-hwspinlock.yaml
new file mode 100644
index 0000000000..ac35491a6f
--- /dev/null
+++ b/dts/Bindings/hwlock/ti,omap-hwspinlock.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwlock/ti,omap-hwspinlock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI HwSpinlock for OMAP and K3 based SoCs
+
+maintainers:
+ - Suman Anna <s-anna@ti.com>
+
+properties:
+ compatible:
+ enum:
+ - ti,omap4-hwspinlock # for OMAP44xx, OMAP54xx, AM33xx, AM43xx, DRA7xx SoCs
+ - ti,am654-hwspinlock # for K3 AM65x, J721E and J7200 SoCs
+
+ reg:
+ maxItems: 1
+
+ "#hwlock-cells":
+ const: 1
+ description: |
+ The OMAP hwspinlock users will use a 0-indexed relative hwlock number as
+ the argument specifier value for requesting a specific hwspinlock within
+ a hwspinlock bank.
+
+ Please look at the generic hwlock binding for usage information for
+ consumers, "Documentation/devicetree/bindings/hwlock/hwlock.txt"
+
+required:
+ - compatible
+ - reg
+ - "#hwlock-cells"
+
+additionalProperties: false
+
+examples:
+
+ - |
+ /* OMAP4 SoCs */
+ hwspinlock: spinlock@4a0f6000 {
+ compatible = "ti,omap4-hwspinlock";
+ reg = <0x4a0f6000 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ - |
+ / {
+ /* K3 AM65x SoCs */
+ model = "Texas Instruments K3 AM654 SoC";
+ compatible = "ti,am654-evm", "ti,am654";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ bus@100000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
+ <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>; /* Main NavSS */
+
+ bus@30800000 {
+ compatible = "simple-mfd";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>;
+
+ spinlock@30e00000 {
+ compatible = "ti,am654-hwspinlock";
+ reg = <0x00 0x30e00000 0x00 0x1000>;
+ #hwlock-cells = <1>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/hwmon/adi,adm1266.yaml b/dts/Bindings/hwmon/adi,adm1266.yaml
new file mode 100644
index 0000000000..43b4f4f57b
--- /dev/null
+++ b/dts/Bindings/hwmon/adi,adm1266.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/adi,adm1266.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices ADM1266 Cascadable Super Sequencer with Margin
+ Control and Fault Recording
+
+maintainers:
+ - Alexandru Tachici <alexandru.tachici@analog.com>
+
+description: |
+ Analog Devices ADM1266 Cascadable Super Sequencer with Margin
+ Control and Fault Recording.
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ADM1266.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,adm1266
+
+ reg:
+ description: |
+ I2C address of slave device.
+ items:
+ minimum: 0x40
+ maximum: 0x4F
+
+ avcc-supply:
+ description: |
+ Phandle to the Avcc power supply.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adm1266@40 {
+ compatible = "adi,adm1266";
+ reg = <0x40>;
+ };
+ };
+...
diff --git a/dts/Bindings/hwmon/adi,axi-fan-control.yaml b/dts/Bindings/hwmon/adi,axi-fan-control.yaml
index 7898b9dba5..6747b870f2 100644
--- a/dts/Bindings/hwmon/adi,axi-fan-control.yaml
+++ b/dts/Bindings/hwmon/adi,axi-fan-control.yaml
@@ -44,6 +44,8 @@ required:
- interrupts
- pulses-per-revolution
+additionalProperties: false
+
examples:
- |
fpga_axi: fpga-axi {
diff --git a/dts/Bindings/hwmon/adt7475.yaml b/dts/Bindings/hwmon/adt7475.yaml
index dfa821c0aa..ad0ec9f35b 100644
--- a/dts/Bindings/hwmon/adt7475.yaml
+++ b/dts/Bindings/hwmon/adt7475.yaml
@@ -65,6 +65,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
i2c {
diff --git a/dts/Bindings/hwmon/baikal,bt1-pvt.yaml b/dts/Bindings/hwmon/baikal,bt1-pvt.yaml
index 84ae4cdd08..00a6511354 100644
--- a/dts/Bindings/hwmon/baikal,bt1-pvt.yaml
+++ b/dts/Bindings/hwmon/baikal,bt1-pvt.yaml
@@ -79,7 +79,7 @@ properties:
minimum: 0
maximum: 7130
-unevaluatedProperties: false
+additionalProperties: false
required:
- compatible
@@ -99,7 +99,7 @@ examples:
interrupts = <GIC_SHARED 31 IRQ_TYPE_LEVEL_HIGH>;
- baikal,pvt-temp-trim-millicelsius = <1000>;
+ baikal,pvt-temp-offset-millicelsius = <1000>;
clocks = <&ccu_sys>, <&ccu_sys>;
clock-names = "ref", "pclk";
diff --git a/dts/Bindings/hwmon/kontron,sl28cpld-hwmon.yaml b/dts/Bindings/hwmon/kontron,sl28cpld-hwmon.yaml
new file mode 100644
index 0000000000..010333cb25
--- /dev/null
+++ b/dts/Bindings/hwmon/kontron,sl28cpld-hwmon.yaml
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/kontron,sl28cpld-hwmon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hardware monitoring driver for the sl28cpld board management controller
+
+maintainers:
+ - Michael Walle <michael@walle.cc>
+
+description: |
+ This module is part of the sl28cpld multi-function device. For more
+ details see ../mfd/kontron,sl28cpld.yaml.
+
+properties:
+ compatible:
+ enum:
+ - kontron,sl28cpld-fan
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+
+additionalProperties: false
diff --git a/dts/Bindings/hwmon/lm75.txt b/dts/Bindings/hwmon/lm75.txt
deleted file mode 100644
index 273616702c..0000000000
--- a/dts/Bindings/hwmon/lm75.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-*LM75 hwmon sensor.
-
-Required properties:
-- compatible: manufacturer and chip name, one of
- "adi,adt75",
- "dallas,ds1775",
- "dallas,ds75",
- "dallas,ds7505",
- "gmt,g751",
- "national,lm75",
- "national,lm75a",
- "national,lm75b",
- "maxim,max6625",
- "maxim,max6626",
- "maxim,max31725",
- "maxim,max31726",
- "maxim,mcp980x",
- "nxp,pct2075",
- "st,stds75",
- "st,stlm75",
- "microchip,tcn75",
- "ti,tmp100",
- "ti,tmp101",
- "ti,tmp105",
- "ti,tmp112",
- "ti,tmp175",
- "ti,tmp275",
- "ti,tmp75",
- "ti,tmp75b",
- "ti,tmp75c",
-
-- reg: I2C bus address of the device
-
-Example:
-
-sensor@48 {
- compatible = "st,stlm75";
- reg = <0x48>;
-};
diff --git a/dts/Bindings/hwmon/lm75.yaml b/dts/Bindings/hwmon/lm75.yaml
new file mode 100644
index 0000000000..96eed5cc78
--- /dev/null
+++ b/dts/Bindings/hwmon/lm75.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/lm75.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LM75 hwmon sensor
+
+maintainers:
+ - Jean Delvare <jdelvare@suse.com>
+ - Guenter Roeck <linux@roeck-us.net>
+
+properties:
+ compatible:
+ enum:
+ - adi,adt75
+ - dallas,ds1775
+ - dallas,ds75
+ - dallas,ds7505
+ - gmt,g751
+ - national,lm75
+ - national,lm75a
+ - national,lm75b
+ - maxim,max6625
+ - maxim,max6626
+ - maxim,max31725
+ - maxim,max31726
+ - maxim,mcp980x
+ - nxp,pct2075
+ - st,stds75
+ - st,stlm75
+ - microchip,tcn75
+ - ti,tmp100
+ - ti,tmp101
+ - ti,tmp105
+ - ti,tmp112
+ - ti,tmp175
+ - ti,tmp275
+ - ti,tmp75
+ - ti,tmp75b
+ - ti,tmp75c
+
+ reg:
+ maxItems: 1
+
+ vs-supply:
+ description: phandle to the regulator that provides the +VS supply
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sensor@48 {
+ compatible = "st,stlm75";
+ reg = <0x48>;
+ vs-supply = <&vs>;
+ };
+ };
diff --git a/dts/Bindings/hwmon/maxim,max20730.yaml b/dts/Bindings/hwmon/maxim,max20730.yaml
new file mode 100644
index 0000000000..93e86e3b46
--- /dev/null
+++ b/dts/Bindings/hwmon/maxim,max20730.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+
+$id: http://devicetree.org/schemas/hwmon/maxim,max20730.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim max20730
+
+maintainers:
+ - Jean Delvare <jdelvare@suse.com>
+ - Guenter Roeck <linux@roeck-us.net>
+
+description: |
+ The MAX20730 is a fully integrated, highly efficient switching regulator
+ with PMBus for applications operating from 4.5V to 16V and requiring
+ up to 25A (max) load. This single-chip regulator provides extremely
+ compact, high efficiency power-delivery solutions with high-precision
+ output voltages and excellent transient response.
+
+ Datasheets:
+ https://datasheets.maximintegrated.com/en/ds/MAX20730.pdf
+ https://datasheets.maximintegrated.com/en/ds/MAX20734.pdf
+ https://datasheets.maximintegrated.com/en/ds/MAX20743.pdf
+
+properties:
+ compatible:
+ enum:
+ - maxim,max20730
+ - maxim,max20734
+ - maxim,max20743
+
+ reg:
+ maxItems: 1
+
+ vout-voltage-divider:
+ description: |
+ If voltage divider present at vout, the voltage at voltage sensor pin
+ will be scaled. The properties will convert the raw reading to a more
+ meaningful number if voltage divider present. It has two numbers,
+ the first number is the output resistor, the second number is the total
+ resistance. Therefore, the adjusted vout is equal to
+ Vout = Vout * output_resistance / total resistance.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 2
+ maxItems: 2
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ max20730@10 {
+ compatible = "maxim,max20730";
+ reg = <0x10>;
+ vout-voltage-divider = <1000 2000>; // vout would be scaled to 0.5
+ };
+ };
diff --git a/dts/Bindings/hwmon/moortec,mr75203.yaml b/dts/Bindings/hwmon/moortec,mr75203.yaml
new file mode 100644
index 0000000000..6f3e3c01f7
--- /dev/null
+++ b/dts/Bindings/hwmon/moortec,mr75203.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/moortec,mr75203.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Moortec Semiconductor MR75203 PVT Controller bindings
+
+maintainers:
+ - Rahul Tanwar <rtanwar@maxlinear.com>
+
+properties:
+ compatible:
+ const: moortec,mr75203
+
+ reg:
+ items:
+ - description: PVT common registers
+ - description: PVT temprature sensor registers
+ - description: PVT process detector registers
+ - description: PVT voltage monitor registers
+
+ reg-names:
+ items:
+ - const: common
+ - const: ts
+ - const: pd
+ - const: vm
+
+ intel,vm-map:
+ description:
+ PVT controller has 5 VM (voltage monitor) sensors.
+ vm-map defines CPU core to VM instance mapping. A
+ value of 0xff means that VM sensor is unused.
+ $ref: /schemas/types.yaml#definitions/uint8-array
+ maxItems: 5
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ "#thermal-sensor-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - intel,vm-map
+ - clocks
+ - resets
+ - "#thermal-sensor-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ pvt: pvt@e0680000 {
+ compatible = "moortec,mr75203";
+ reg = <0xe0680000 0x80>,
+ <0xe0680080 0x180>,
+ <0xe0680200 0x200>,
+ <0xe0680400 0xc00>;
+ reg-names = "common", "ts", "pd", "vm";
+ intel,vm-map = [03 01 04 ff ff];
+ clocks = <&osc0>;
+ resets = <&rcu0 0x40 7>;
+ #thermal-sensor-cells = <1>;
+ };
diff --git a/dts/Bindings/hwmon/sensirion,shtc1.yaml b/dts/Bindings/hwmon/sensirion,shtc1.yaml
new file mode 100644
index 0000000000..c523a1beb2
--- /dev/null
+++ b/dts/Bindings/hwmon/sensirion,shtc1.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/sensirion,shtc1.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sensirion SHTC1 Humidity and Temperature Sensor IC
+
+maintainers:
+ - Christopher Ruehl chris.ruehl@gtsys.com.hk
+
+description: |
+ The SHTC1, SHTW1 and SHTC3 are digital humidity and temperature sensor
+ designed especially for battery-driven high-volume consumer electronics
+ applications.
+ For further information refere to Documentation/hwmon/shtc1.rst
+
+ This binding document describes the binding for the hardware monitor
+ portion of the driver.
+
+properties:
+ compatible:
+ enum:
+ - sensirion,shtc1
+ - sensirion,shtw1
+ - sensirion,shtc3
+
+ reg:
+ const: 0x70
+
+ sensirion,blocking-io:
+ $ref: /schemas/types.yaml#definitions/flag
+ description:
+ If set, the driver hold the i2c bus until measurement is finished.
+
+ sensirion,low-precision:
+ $ref: /schemas/types.yaml#definitions/flag
+ description:
+ If set, the sensor aquire data with low precision (not recommended).
+ The driver aquire data with high precision by default.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+
+ shtc3@70 {
+ compatible = "sensirion,shtc3";
+ reg = <0x70>;
+ sensirion,blocking-io;
+ };
+ };
+...
diff --git a/dts/Bindings/i2c/amlogic,meson6-i2c.yaml b/dts/Bindings/i2c/amlogic,meson6-i2c.yaml
index 49cad273c8..6ecb0270d8 100644
--- a/dts/Bindings/i2c/amlogic,meson6-i2c.yaml
+++ b/dts/Bindings/i2c/amlogic,meson6-i2c.yaml
@@ -36,6 +36,8 @@ required:
- interrupts
- clocks
+unevaluatedProperties: false
+
examples:
- |
i2c@c8100500 {
diff --git a/dts/Bindings/i2c/cdns,i2c-r1p10.yaml b/dts/Bindings/i2c/cdns,i2c-r1p10.yaml
index dc0952f378..1ca1cd19bd 100644
--- a/dts/Bindings/i2c/cdns,i2c-r1p10.yaml
+++ b/dts/Bindings/i2c/cdns,i2c-r1p10.yaml
@@ -44,6 +44,8 @@ required:
- clocks
- interrupts
+unevaluatedProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/Bindings/i2c/i2c-gpio.yaml b/dts/Bindings/i2c/i2c-gpio.yaml
index 78ffcab242..cc3aa2a5e7 100644
--- a/dts/Bindings/i2c/i2c-gpio.yaml
+++ b/dts/Bindings/i2c/i2c-gpio.yaml
@@ -70,4 +70,6 @@ required:
- sda-gpios
- scl-gpios
+unevaluatedProperties: false
+
...
diff --git a/dts/Bindings/i2c/i2c-imx-lpi2c.yaml b/dts/Bindings/i2c/i2c-imx-lpi2c.yaml
index ac0bc5dd64..29b9447f3b 100644
--- a/dts/Bindings/i2c/i2c-imx-lpi2c.yaml
+++ b/dts/Bindings/i2c/i2c-imx-lpi2c.yaml
@@ -9,12 +9,18 @@ title: Freescale Low Power Inter IC (LPI2C) for i.MX
maintainers:
- Anson Huang <Anson.Huang@nxp.com>
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
properties:
compatible:
- enum:
- - fsl,imx7ulp-lpi2c
- - fsl,imx8qxp-lpi2c
- - fsl,imx8qm-lpi2c
+ oneOf:
+ - enum:
+ - fsl,imx7ulp-lpi2c
+ - fsl,imx8qm-lpi2c
+ - items:
+ - const: fsl,imx8qxp-lpi2c
+ - const: fsl,imx7ulp-lpi2c
reg:
maxItems: 1
@@ -22,23 +28,34 @@ properties:
interrupts:
maxItems: 1
+ assigned-clock-parents: true
+ assigned-clock-rates: true
+ assigned-clocks: true
+ clock-frequency: true
+
+ clock-names:
+ maxItems: 1
+
clocks:
maxItems: 1
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- reg
- interrupts
- clocks
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/imx7ulp-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
- lpi2c7@40a50000 {
+ i2c@40a50000 {
compatible = "fsl,imx7ulp-lpi2c";
reg = <0x40A50000 0x10000>;
interrupt-parent = <&intc>;
diff --git a/dts/Bindings/i2c/i2c-imx.yaml b/dts/Bindings/i2c/i2c-imx.yaml
index 8105369531..f23966b0d6 100644
--- a/dts/Bindings/i2c/i2c-imx.yaml
+++ b/dts/Bindings/i2c/i2c-imx.yaml
@@ -9,6 +9,9 @@ title: Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX
maintainers:
- Wolfram Sang <wolfram@the-dreams.de>
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
properties:
compatible:
oneOf:
@@ -19,6 +22,9 @@ properties:
- const: fsl,imx35-i2c
- const: fsl,imx1-i2c
- items:
+ - const: fsl,imx7d-i2c
+ - const: fsl,imx21-i2c
+ - items:
- enum:
- fsl,imx25-i2c
- fsl,imx27-i2c
@@ -75,7 +81,7 @@ required:
- interrupts
- clocks
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/Bindings/i2c/i2c-rk3x.yaml b/dts/Bindings/i2c/i2c-rk3x.yaml
index 790aa7218e..7f254d7955 100644
--- a/dts/Bindings/i2c/i2c-rk3x.yaml
+++ b/dts/Bindings/i2c/i2c-rk3x.yaml
@@ -117,6 +117,8 @@ then:
required:
- rockchip,grf
+unevaluatedProperties: false
+
examples:
- |
#include <dt-bindings/clock/rk3188-cru-common.h>
diff --git a/dts/Bindings/i2c/i2c.txt b/dts/Bindings/i2c/i2c.txt
index a21c359b9f..df41f72afc 100644
--- a/dts/Bindings/i2c/i2c.txt
+++ b/dts/Bindings/i2c/i2c.txt
@@ -87,6 +87,11 @@ wants to support one of the below features, it should adapt these bindings.
this information to detect a stalled bus more reliably, for example.
Can not be combined with 'multi-master'.
+- smbus
+ states that additional SMBus restrictions and features apply to this bus.
+ Examples of features are SMBusHostNotify and SMBusAlert. Examples of
+ restrictions are more reserved addresses and timeout definitions.
+
Required properties (per child device)
--------------------------------------
diff --git a/dts/Bindings/i2c/ingenic,i2c.yaml b/dts/Bindings/i2c/ingenic,i2c.yaml
index 682ed1bbf5..0e7b4b8a7e 100644
--- a/dts/Bindings/i2c/ingenic,i2c.yaml
+++ b/dts/Bindings/i2c/ingenic,i2c.yaml
@@ -17,9 +17,13 @@ properties:
pattern: "^i2c@[0-9a-f]+$"
compatible:
- enum:
- - ingenic,jz4780-i2c
- - ingenic,x1000-i2c
+ oneOf:
+ - enum:
+ - ingenic,jz4770-i2c
+ - ingenic,x1000-i2c
+ - items:
+ - const: ingenic,jz4780-i2c
+ - const: ingenic,jz4770-i2c
reg:
maxItems: 1
@@ -60,7 +64,7 @@ examples:
#include <dt-bindings/dma/jz4780-dma.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c@10054000 {
- compatible = "ingenic,jz4780-i2c";
+ compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10054000 0x1000>;
diff --git a/dts/Bindings/i2c/mellanox,i2c-mlxbf.txt b/dts/Bindings/i2c/mellanox,i2c-mlxbf.txt
new file mode 100644
index 0000000000..566ea861aa
--- /dev/null
+++ b/dts/Bindings/i2c/mellanox,i2c-mlxbf.txt
@@ -0,0 +1,42 @@
+Device tree configuration for the Mellanox I2C SMBus on BlueField SoCs
+
+Required Properties:
+
+- compatible : should be "mellanox,i2c-mlxbf1" or "mellanox,i2c-mlxbf2".
+
+- reg : address offset and length of the device registers. The
+ registers consist of the following set of resources:
+ 1) Smbus block registers.
+ 2) Cause master registers.
+ 3) Cause slave registers.
+ 4) Cause coalesce registers (if compatible isn't set
+ to "mellanox,i2c-mlxbf1").
+
+- interrupts : interrupt number.
+
+Optional Properties:
+
+- clock-frequency : bus frequency used to configure timing registers;
+ allowed values are 100000, 400000 and 1000000;
+ those are expressed in Hz. Default is 100000.
+
+Example:
+
+i2c@2804000 {
+ compatible = "mellanox,i2c-mlxbf1";
+ reg = <0x02804000 0x800>,
+ <0x02801200 0x020>,
+ <0x02801260 0x020>;
+ interrupts = <57>;
+ clock-frequency = <100000>;
+};
+
+i2c@2808800 {
+ compatible = "mellanox,i2c-mlxbf2";
+ reg = <0x02808800 0x600>,
+ <0x02808e00 0x020>,
+ <0x02808e20 0x020>,
+ <0x02808e40 0x010>;
+ interrupts = <57>;
+ clock-frequency = <400000>;
+};
diff --git a/dts/Bindings/i2c/socionext,uniphier-fi2c.yaml b/dts/Bindings/i2c/socionext,uniphier-fi2c.yaml
index 15abc02296..c76131902b 100644
--- a/dts/Bindings/i2c/socionext,uniphier-fi2c.yaml
+++ b/dts/Bindings/i2c/socionext,uniphier-fi2c.yaml
@@ -37,6 +37,8 @@ required:
- interrupts
- clocks
+unevaluatedProperties: false
+
examples:
- |
i2c0: i2c@58780000 {
diff --git a/dts/Bindings/i2c/socionext,uniphier-i2c.yaml b/dts/Bindings/i2c/socionext,uniphier-i2c.yaml
index ef998def55..ddde08636a 100644
--- a/dts/Bindings/i2c/socionext,uniphier-i2c.yaml
+++ b/dts/Bindings/i2c/socionext,uniphier-i2c.yaml
@@ -37,6 +37,8 @@ required:
- interrupts
- clocks
+unevaluatedProperties: false
+
examples:
- |
i2c0: i2c@58400000 {
diff --git a/dts/Bindings/i2c/st,stm32-i2c.yaml b/dts/Bindings/i2c/st,stm32-i2c.yaml
index f2fcbb3611..d747f4990a 100644
--- a/dts/Bindings/i2c/st,stm32-i2c.yaml
+++ b/dts/Bindings/i2c/st,stm32-i2c.yaml
@@ -94,6 +94,8 @@ required:
- resets
- clocks
+unevaluatedProperties: false
+
examples:
- |
#include <dt-bindings/mfd/stm32f7-rcc.h>
diff --git a/dts/Bindings/i2c/xlnx,xps-iic-2.00.a.yaml b/dts/Bindings/i2c/xlnx,xps-iic-2.00.a.yaml
index 67c1c84ba3..ffb2ed039a 100644
--- a/dts/Bindings/i2c/xlnx,xps-iic-2.00.a.yaml
+++ b/dts/Bindings/i2c/xlnx,xps-iic-2.00.a.yaml
@@ -36,6 +36,8 @@ required:
- interrupts
- clocks
+unevaluatedProperties: false
+
examples:
- |
axi_iic_0: i2c@40800000 {
diff --git a/dts/Bindings/iio/accel/adi,adis16240.yaml b/dts/Bindings/iio/accel/adi,adis16240.yaml
index 4147f02b5e..4fcbfd93e2 100644
--- a/dts/Bindings/iio/accel/adi,adis16240.yaml
+++ b/dts/Bindings/iio/accel/adi,adis16240.yaml
@@ -25,11 +25,15 @@ properties:
interrupts:
maxItems: 1
+ spi-max-frequency: true
+
required:
- compatible
- reg
- interrupts
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/gpio/gpio.h>
diff --git a/dts/Bindings/iio/accel/adi,adxl345.yaml b/dts/Bindings/iio/accel/adi,adxl345.yaml
index fd4eaa3d0a..11d32a2885 100644
--- a/dts/Bindings/iio/accel/adi,adxl345.yaml
+++ b/dts/Bindings/iio/accel/adi,adxl345.yaml
@@ -32,6 +32,8 @@ properties:
spi-cpol: true
+ spi-max-frequency: true
+
interrupts:
maxItems: 1
@@ -40,6 +42,8 @@ required:
- reg
- interrupts
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/gpio/gpio.h>
diff --git a/dts/Bindings/iio/accel/adi,adxl372.yaml b/dts/Bindings/iio/accel/adi,adxl372.yaml
index e7daffec88..38b59b6454 100644
--- a/dts/Bindings/iio/accel/adi,adxl372.yaml
+++ b/dts/Bindings/iio/accel/adi,adxl372.yaml
@@ -25,11 +25,15 @@ properties:
interrupts:
maxItems: 1
+ spi-max-frequency: true
+
required:
- compatible
- reg
- interrupts
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/gpio/gpio.h>
diff --git a/dts/Bindings/iio/accel/kionix,kxsd9.yaml b/dts/Bindings/iio/accel/kionix,kxsd9.yaml
index d61ab4fa3d..390b87242f 100644
--- a/dts/Bindings/iio/accel/kionix,kxsd9.yaml
+++ b/dts/Bindings/iio/accel/kionix,kxsd9.yaml
@@ -29,10 +29,14 @@ properties:
mount-matrix:
description: an optional 3x3 mounting rotation matrix.
+ spi-max-frequency: true
+
required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
# include <dt-bindings/interrupt-controller/irq.h>
diff --git a/dts/Bindings/iio/adc/ad7949.txt b/dts/Bindings/iio/adc/ad7949.txt
deleted file mode 100644
index c7f5057356..0000000000
--- a/dts/Bindings/iio/adc/ad7949.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-* Analog Devices AD7949/AD7682/AD7689
-
-Required properties:
- - compatible: Should be one of
- * "adi,ad7949"
- * "adi,ad7682"
- * "adi,ad7689"
- - reg: spi chip select number for the device
- - vref-supply: The regulator supply for ADC reference voltage
-
-Example:
-adc@0 {
- compatible = "adi,ad7949";
- reg = <0>;
- vref-supply = <&vdd_supply>;
-};
diff --git a/dts/Bindings/iio/adc/adi,ad7124.yaml b/dts/Bindings/iio/adc/adi,ad7124.yaml
index deb34deff0..f1c574c896 100644
--- a/dts/Bindings/iio/adc/adi,ad7124.yaml
+++ b/dts/Bindings/iio/adc/adi,ad7124.yaml
@@ -52,6 +52,8 @@ properties:
avdd-supply:
description: avdd supply can be used as reference for conversion.
+ spi-max-frequency: true
+
required:
- compatible
- reg
@@ -108,6 +110,8 @@ patternProperties:
- reg
- diff-channels
+additionalProperties: false
+
examples:
- |
spi {
diff --git a/dts/Bindings/iio/adc/adi,ad7192.yaml b/dts/Bindings/iio/adc/adi,ad7192.yaml
index d0913034b1..e0cc3b2e89 100644
--- a/dts/Bindings/iio/adc/adi,ad7192.yaml
+++ b/dts/Bindings/iio/adc/adi,ad7192.yaml
@@ -30,6 +30,8 @@ properties:
spi-cpha: true
+ spi-max-frequency: true
+
clocks:
maxItems: 1
description: phandle to the master clock (mclk)
@@ -92,6 +94,8 @@ required:
- spi-cpol
- spi-cpha
+additionalProperties: false
+
examples:
- |
spi0 {
diff --git a/dts/Bindings/iio/adc/adi,ad7291.yaml b/dts/Bindings/iio/adc/adi,ad7291.yaml
new file mode 100644
index 0000000000..6feafb7e53
--- /dev/null
+++ b/dts/Bindings/iio/adc/adi,ad7291.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad7291.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AD7291 8-Channel, I2C, 12-Bit SAR ADC with Temperature Sensor
+
+maintainers:
+ - Michael Auchter <michael.auchter@ni.com>
+
+description: |
+ Analog Devices AD7291 8-Channel I2C 12-Bit SAR ADC with Temperature Sensor
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad7291.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,ad7291
+
+ reg:
+ maxItems: 1
+
+ vref-supply:
+ description: |
+ The regulator supply for ADC reference voltage.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ad7291: adc@0 {
+ compatible = "adi,ad7291";
+ reg = <0>;
+ vref-supply = <&adc_vref>;
+ };
+ };
+... \ No newline at end of file
diff --git a/dts/Bindings/iio/adc/adi,ad7292.yaml b/dts/Bindings/iio/adc/adi,ad7292.yaml
index e1f6d64bdc..108d202b28 100644
--- a/dts/Bindings/iio/adc/adi,ad7292.yaml
+++ b/dts/Bindings/iio/adc/adi,ad7292.yaml
@@ -30,6 +30,8 @@ properties:
spi-cpha: true
+ spi-max-frequency: true
+
'#address-cells':
const: 1
@@ -63,6 +65,8 @@ patternProperties:
required:
- reg
+additionalProperties: false
+
examples:
- |
spi {
diff --git a/dts/Bindings/iio/adc/adi,ad7606.yaml b/dts/Bindings/iio/adc/adi,ad7606.yaml
index cbb8819d70..73775174cf 100644
--- a/dts/Bindings/iio/adc/adi,ad7606.yaml
+++ b/dts/Bindings/iio/adc/adi,ad7606.yaml
@@ -31,6 +31,10 @@ properties:
spi-cpha: true
+ spi-cpol: true
+
+ spi-max-frequency: true
+
avcc-supply: true
interrupts:
@@ -102,6 +106,8 @@ required:
- interrupts
- adi,conversion-start-gpios
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/gpio/gpio.h>
diff --git a/dts/Bindings/iio/adc/adi,ad7768-1.txt b/dts/Bindings/iio/adc/adi,ad7768-1.txt
deleted file mode 100644
index 9f5b88cf68..0000000000
--- a/dts/Bindings/iio/adc/adi,ad7768-1.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-Analog Devices AD7768-1 ADC device driver
-
-Required properties for the AD7768-1:
-
-- compatible: Must be "adi,ad7768-1"
-- reg: SPI chip select number for the device
-- spi-max-frequency: Max SPI frequency to use
- see: Documentation/devicetree/bindings/spi/spi-bus.txt
-- clocks: phandle to the master clock (mclk)
- see: Documentation/devicetree/bindings/clock/clock-bindings.txt
-- clock-names: Must be "mclk".
-- interrupts: IRQ line for the ADC
- see: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
-- vref-supply: vref supply can be used as reference for conversion
-- adi,sync-in-gpios: must be the device tree identifier of the SYNC-IN pin. Enables
- synchronization of multiple devices that require simultaneous sampling.
- A pulse is always required if the configuration is changed in any way, for example
- if the filter decimation rate changes. As the line is active low, it should
- be marked GPIO_ACTIVE_LOW.
-
-Optional properties:
-
- - reset-gpios : GPIO spec for the RESET pin. If specified, it will be asserted during
- driver probe. As the line is active low, it should be marked GPIO_ACTIVE_LOW.
-
-Example:
-
- adc@0 {
- compatible = "adi,ad7768-1";
- reg = <0>;
- spi-max-frequency = <2000000>;
- spi-cpol;
- spi-cpha;
- vref-supply = <&adc_vref>;
- interrupts = <25 IRQ_TYPE_EDGE_RISING>;
- interrupt-parent = <&gpio>;
- adi,sync-in-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
- reset-gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
- clocks = <&ad7768_mclk>;
- clock-names = "mclk";
- };
diff --git a/dts/Bindings/iio/adc/adi,ad7768-1.yaml b/dts/Bindings/iio/adc/adi,ad7768-1.yaml
new file mode 100644
index 0000000000..d3733ad878
--- /dev/null
+++ b/dts/Bindings/iio/adc/adi,ad7768-1.yaml
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad7768-1.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD7768-1 ADC device driver
+
+maintainers:
+ - Michael Hennerich <michael.hennerich@analog.com>
+
+description: |
+ Datasheet at:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad7768-1.pdf
+
+properties:
+ compatible:
+ const: adi,ad7768-1
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: mclk
+
+ interrupts:
+ maxItems: 1
+
+ vref-supply:
+ description:
+ ADC reference voltage supply
+
+ adi,sync-in-gpios:
+ description:
+ Enables synchronization of multiple devices that require simultaneous
+ sampling. A pulse is always required if the configuration is changed
+ in any way, for example if the filter decimation rate changes.
+ As the line is active low, it should be marked GPIO_ACTIVE_LOW.
+
+ reset-gpios:
+ maxItems: 1
+
+ spi-max-frequency: true
+
+ spi-cpol: true
+ spi-cpha : true
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - vref-supply
+ - spi-cpol
+ - spi-cpha
+ - adi,sync-in-gpios
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad7768-1";
+ reg = <0>;
+ spi-max-frequency = <2000000>;
+ spi-cpol;
+ spi-cpha;
+ vref-supply = <&adc_vref>;
+ interrupts = <25 IRQ_TYPE_EDGE_RISING>;
+ interrupt-parent = <&gpio>;
+ adi,sync-in-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+ clocks = <&ad7768_mclk>;
+ clock-names = "mclk";
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/adi,ad7923.yaml b/dts/Bindings/iio/adc/adi,ad7923.yaml
index a11b918e00..e82194974e 100644
--- a/dts/Bindings/iio/adc/adi,ad7923.yaml
+++ b/dts/Bindings/iio/adc/adi,ad7923.yaml
@@ -43,10 +43,14 @@ properties:
'#size-cells':
const: 0
+ spi-max-frequency: true
+
required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
spi {
diff --git a/dts/Bindings/iio/adc/adi,ad7949.yaml b/dts/Bindings/iio/adc/adi,ad7949.yaml
new file mode 100644
index 0000000000..9b56bd4d55
--- /dev/null
+++ b/dts/Bindings/iio/adc/adi,ad7949.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad7949.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD7949/AD7682/AD7689 analog to digital converters
+
+maintainers:
+ - Charles-Antoine Couret <charles-antoine.couret@essensium.com>
+
+description: |
+ Specifications on the converters can be found at:
+ AD7949:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD7949.pdf
+ AD7682/AD7698:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD7682_7689.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,ad7682
+ - adi,ad7689
+ - adi,ad7949
+
+ reg:
+ maxItems: 1
+
+ vref-supply:
+ description:
+ ADC reference voltage supply
+
+ spi-max-frequency: true
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad7949";
+ reg = <0>;
+ vref-supply = <&vdd_supply>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/adi,ad9467.yaml b/dts/Bindings/iio/adc/adi,ad9467.yaml
index c4f57fa6aa..b5aed40d8a 100644
--- a/dts/Bindings/iio/adc/adi,ad9467.yaml
+++ b/dts/Bindings/iio/adc/adi,ad9467.yaml
@@ -4,21 +4,30 @@
$id: http://devicetree.org/schemas/iio/adc/adi,ad9467.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Analog Devices AD9467 High-Speed ADC
+title: Analog Devices AD9467 and similar High-Speed ADCs
maintainers:
- Michael Hennerich <michael.hennerich@analog.com>
- Alexandru Ardelean <alexandru.ardelean@analog.com>
description: |
- The AD9467 is a 16-bit, monolithic, IF sampling analog-to-digital
- converter (ADC).
+ The AD9467 and the parts similar with it, are high-speed analog-to-digital
+ converters (ADCs), operating in the range of 100 to 500 mega samples
+ per second (MSPS). Some parts support higher MSPS and some
+ lower MSPS, suitable for the intended application of each part.
+ All the parts support the register map described by Application Note AN-877
+ https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf
+
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD9265.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD9434.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/AD9467.pdf
properties:
compatible:
enum:
+ - adi,ad9265
+ - adi,ad9434
- adi,ad9467
reg:
diff --git a/dts/Bindings/iio/adc/ads1015.txt b/dts/Bindings/iio/adc/ads1015.txt
deleted file mode 100644
index 918a507d11..0000000000
--- a/dts/Bindings/iio/adc/ads1015.txt
+++ /dev/null
@@ -1,73 +0,0 @@
-ADS1015 (I2C)
-
-This device is a 12-bit A-D converter with 4 inputs.
-
-The inputs can be used single ended or in certain differential combinations.
-
-For configuration all possible combinations are mapped to 8 channels:
- 0: Voltage over AIN0 and AIN1.
- 1: Voltage over AIN0 and AIN3.
- 2: Voltage over AIN1 and AIN3.
- 3: Voltage over AIN2 and AIN3.
- 4: Voltage over AIN0 and GND.
- 5: Voltage over AIN1 and GND.
- 6: Voltage over AIN2 and GND.
- 7: Voltage over AIN3 and GND.
-
-Each channel can be configured individually:
- - pga is the programmable gain amplifier (values are full scale)
- 0: +/- 6.144 V
- 1: +/- 4.096 V
- 2: +/- 2.048 V (default)
- 3: +/- 1.024 V
- 4: +/- 0.512 V
- 5: +/- 0.256 V
- - data_rate in samples per second
- 0: 128
- 1: 250
- 2: 490
- 3: 920
- 4: 1600 (default)
- 5: 2400
- 6: 3300
-
-1) The /ads1015 node
-
- Required properties:
-
- - compatible : must be "ti,ads1015"
- - reg : I2C bus address of the device
- - #address-cells : must be <1>
- - #size-cells : must be <0>
-
- The node contains child nodes for each channel that the platform uses.
-
- Example ADS1015 node:
-
- ads1015@49 {
- compatible = "ti,ads1015";
- reg = <0x49>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- [ child node definitions... ]
- }
-
-2) channel nodes
-
- Required properties:
-
- - reg : the channel number
-
- Optional properties:
-
- - ti,gain : the programmable gain amplifier setting
- - ti,datarate : the converter data rate
-
- Example ADS1015 channel node:
-
- channel@4 {
- reg = <4>;
- ti,gain = <3>;
- ti,datarate = <5>;
- };
diff --git a/dts/Bindings/iio/adc/amlogic,meson-saradc.txt b/dts/Bindings/iio/adc/amlogic,meson-saradc.txt
deleted file mode 100644
index d57e9df25f..0000000000
--- a/dts/Bindings/iio/adc/amlogic,meson-saradc.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-* Amlogic Meson SAR (Successive Approximation Register) A/D converter
-
-Required properties:
-- compatible: depending on the SoC this should be one of:
- - "amlogic,meson8-saradc" for Meson8
- - "amlogic,meson8b-saradc" for Meson8b
- - "amlogic,meson8m2-saradc" for Meson8m2
- - "amlogic,meson-gxbb-saradc" for GXBB
- - "amlogic,meson-gxl-saradc" for GXL
- - "amlogic,meson-gxm-saradc" for GXM
- - "amlogic,meson-axg-saradc" for AXG
- - "amlogic,meson-g12a-saradc" for AXG
- along with the generic "amlogic,meson-saradc"
-- reg: the physical base address and length of the registers
-- interrupts: the interrupt indicating end of sampling
-- clocks: phandle and clock identifier (see clock-names)
-- clock-names: mandatory clocks:
- - "clkin" for the reference clock (typically XTAL)
- - "core" for the SAR ADC core clock
- optional clocks:
- - "adc_clk" for the ADC (sampling) clock
- - "adc_sel" for the ADC (sampling) clock mux
-- vref-supply: the regulator supply for the ADC reference voltage
-- #io-channel-cells: must be 1, see ../iio-bindings.txt
-
-Optional properties:
-- amlogic,hhi-sysctrl: phandle to the syscon which contains the 5th bit
- of the TSC (temperature sensor coefficient) on
- Meson8b and Meson8m2 (which used to calibrate the
- temperature sensor)
-- nvmem-cells: phandle to the temperature_calib eFuse cells
-- nvmem-cell-names: if present (to enable the temperature sensor
- calibration) this must contain "temperature_calib"
-
-
-Example:
- saradc: adc@8680 {
- compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
- #io-channel-cells = <1>;
- reg = <0x0 0x8680 0x0 0x34>;
- interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>,
- <&clkc CLKID_SAR_ADC>,
- <&clkc CLKID_SANA>,
- <&clkc CLKID_SAR_ADC_CLK>,
- <&clkc CLKID_SAR_ADC_SEL>;
- clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
- };
diff --git a/dts/Bindings/iio/adc/amlogic,meson-saradc.yaml b/dts/Bindings/iio/adc/amlogic,meson-saradc.yaml
new file mode 100644
index 0000000000..3be8955587
--- /dev/null
+++ b/dts/Bindings/iio/adc/amlogic,meson-saradc.yaml
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/amlogic,meson-saradc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic Meson SAR (Successive Approximation Register) A/D converter
+
+maintainers:
+ - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+
+description:
+ Binding covers a range of ADCs found on Amlogic Meson SoCs.
+
+properties:
+ compatible:
+ oneOf:
+ - const: amlogic,meson-saradc
+ - items:
+ - enum:
+ - amlogic,meson8-saradc
+ - amlogic,meson8b-saradc
+ - amlogic,meson8m2-saradc
+ - amlogic,meson-gxbb-saradc
+ - amlogic,meson-gxl-saradc
+ - amlogic,meson-gxm-saradc
+ - amlogic,meson-axg-saradc
+ - amlogic,meson-g12a-saradc
+ - const: amlogic,meson-saradc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: Interrupt indicates end of sampling.
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 4
+
+ clock-names:
+ minItems: 2
+ maxItems: 4
+ items:
+ - const: clkin
+ - const: core
+ - const: adc_clk
+ - const: adc_sel
+
+ vref-supply: true
+
+ "#io-channel-cells":
+ const: 1
+
+ amlogic,hhi-sysctrl:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Syscon which contains the 5th bit of the TSC (temperature sensor
+ coefficient) on Meson8b and Meson8m2 (which used to calibrate the
+ temperature sensor)
+
+ nvmem-cells:
+ description: phandle to the temperature_calib eFuse cells
+ maxItems: 1
+
+ nvmem-cell-names:
+ const: temperature_calib
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - amlogic,meson8-saradc
+ - amlogic,meson8b-saradc
+ - amlogic,meson8m2-saradc
+ then:
+ properties:
+ clocks:
+ maxItems: 2
+ clock-names:
+ maxItems: 2
+ else:
+ properties:
+ nvmem-cells: false
+ mvmem-cel-names: false
+ clocks:
+ minItems: 4
+ clock-names:
+ minItems: 4
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - amlogic,meson8b-saradc
+ - amlogic,meson8m2-saradc
+ then:
+ properties:
+ amlogic,hhi-sysctrl: true
+ else:
+ properties:
+ amlogic,hhi-sysctrl: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/gxbb-clkc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ adc@8680 {
+ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ reg = <0x0 0x8680 0x0 0x34>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "adc_clk", "adc_sel";
+ };
+ adc@9680 {
+ compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ reg = <0x0 0x9680 0x0 0x34>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
+ clock-names = "clkin", "core";
+ nvmem-cells = <&tsens_caldata>;
+ nvmem-cell-names = "temperature_calib";
+ amlogic,hhi-sysctrl = <&hhi>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/aspeed,ast2400-adc.yaml b/dts/Bindings/iio/adc/aspeed,ast2400-adc.yaml
new file mode 100644
index 0000000000..7f534a933e
--- /dev/null
+++ b/dts/Bindings/iio/adc/aspeed,ast2400-adc.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/aspeed,ast2400-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ADC that forms part of an ASPEED server management processor.
+
+maintainers:
+ - Joel Stanley <joel@jms.id.au>
+
+description:
+ This device is a 10-bit converter for 16 voltage channels. All inputs are
+ single ended.
+
+properties:
+ compatible:
+ enum:
+ - aspeed,ast2400-adc
+ - aspeed,ast2500-adc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description:
+ Input clock used to derive the sample clock. Expected to be the
+ SoC's APB clock.
+
+ resets:
+ maxItems: 1
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/aspeed-clock.h>
+ adc@1e6e9000 {
+ compatible = "aspeed,ast2400-adc";
+ reg = <0x1e6e9000 0xb0>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_ADC>;
+ #io-channel-cells = <1>;
+ };
+...
diff --git a/dts/Bindings/iio/adc/aspeed_adc.txt b/dts/Bindings/iio/adc/aspeed_adc.txt
deleted file mode 100644
index 034fc2ba10..0000000000
--- a/dts/Bindings/iio/adc/aspeed_adc.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-Aspeed ADC
-
-This device is a 10-bit converter for 16 voltage channels. All inputs are
-single ended.
-
-Required properties:
-- compatible: Should be "aspeed,ast2400-adc" or "aspeed,ast2500-adc"
-- reg: memory window mapping address and length
-- clocks: Input clock used to derive the sample clock. Expected to be the
- SoC's APB clock.
-- resets: Reset controller phandle
-- #io-channel-cells: Must be set to <1> to indicate channels are selected
- by index.
-
-Example:
- adc@1e6e9000 {
- compatible = "aspeed,ast2400-adc";
- reg = <0x1e6e9000 0xb0>;
- clocks = <&syscon ASPEED_CLK_APB>;
- resets = <&syscon ASPEED_RESET_ADC>;
- #io-channel-cells = <1>;
- };
diff --git a/dts/Bindings/iio/adc/berlin2_adc.txt b/dts/Bindings/iio/adc/berlin2_adc.txt
deleted file mode 100644
index 908334c6b0..0000000000
--- a/dts/Bindings/iio/adc/berlin2_adc.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-* Berlin Analog to Digital Converter (ADC)
-
-The Berlin ADC has 8 channels, with one connected to a temperature sensor.
-It is part of the system controller register set. The ADC node should be a
-sub-node of the system controller node.
-
-Required properties:
-- compatible: must be "marvell,berlin2-adc"
-- interrupts: the interrupts for the ADC and the temperature sensor
-- interrupt-names: should be "adc" and "tsen"
-
-Example:
-
-adc: adc {
- compatible = "marvell,berlin2-adc";
- interrupt-parent = <&sic>;
- interrupts = <12>, <14>;
- interrupt-names = "adc", "tsen";
-};
diff --git a/dts/Bindings/iio/adc/cc10001_adc.txt b/dts/Bindings/iio/adc/cc10001_adc.txt
deleted file mode 100644
index 904f76de90..0000000000
--- a/dts/Bindings/iio/adc/cc10001_adc.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-* Cosmic Circuits - Analog to Digital Converter (CC-10001-ADC)
-
-Required properties:
- - compatible: Should be "cosmic,10001-adc"
- - reg: Should contain adc registers location and length.
- - clock-names: Should contain "adc".
- - clocks: Should contain a clock specifier for each entry in clock-names
- - vref-supply: The regulator supply ADC reference voltage.
-
-Optional properties:
- - adc-reserved-channels: Bitmask of reserved channels,
- i.e. channels that cannot be used by the OS.
-
-Example:
-adc: adc@18101600 {
- compatible = "cosmic,10001-adc";
- reg = <0x18101600 0x24>;
- adc-reserved-channels = <0x2>;
- clocks = <&adc_clk>;
- clock-names = "adc";
- vref-supply = <&reg_1v8>;
-};
diff --git a/dts/Bindings/iio/adc/cosmic,10001-adc.yaml b/dts/Bindings/iio/adc/cosmic,10001-adc.yaml
new file mode 100644
index 0000000000..5d92b477e2
--- /dev/null
+++ b/dts/Bindings/iio/adc/cosmic,10001-adc.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/cosmic,10001-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cosmic Circuits CC-10001 ADC
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+description:
+ Cosmic Circuits 10001 10-bit ADC device.
+
+properties:
+ compatible:
+ const: cosmic,10001-adc
+
+ reg:
+ maxItems: 1
+
+ adc-reserved-channels:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Bitmask of reserved channels, i.e. channels that cannot be
+ used by the OS.
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: adc
+
+ vref-supply: true
+
+ "#io-channel-cells":
+ const: 1
+
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - vref-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ adc@18101600 {
+ compatible = "cosmic,10001-adc";
+ reg = <0x18101600 0x24>;
+ adc-reserved-channels = <0x2>;
+ clocks = <&adc_clk>;
+ clock-names = "adc";
+ vref-supply = <&reg_1v8>;
+ };
+...
diff --git a/dts/Bindings/iio/adc/cpcap-adc.txt b/dts/Bindings/iio/adc/cpcap-adc.txt
deleted file mode 100644
index ec04008e8f..0000000000
--- a/dts/Bindings/iio/adc/cpcap-adc.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-Motorola CPCAP PMIC ADC binding
-
-Required properties:
-- compatible: Should be "motorola,cpcap-adc" or "motorola,mapphone-cpcap-adc"
-- interrupts: The interrupt number for the ADC device
-- interrupt-names: Should be "adcdone"
-- #io-channel-cells: Number of cells in an IIO specifier
-
-Example:
-
-cpcap_adc: adc {
- compatible = "motorola,mapphone-cpcap-adc";
- interrupt-parent = <&cpcap>;
- interrupts = <8 IRQ_TYPE_NONE>;
- interrupt-names = "adcdone";
- #io-channel-cells = <1>;
-};
diff --git a/dts/Bindings/iio/adc/da9150-gpadc.txt b/dts/Bindings/iio/adc/da9150-gpadc.txt
deleted file mode 100644
index c07228da92..0000000000
--- a/dts/Bindings/iio/adc/da9150-gpadc.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-Dialog Semiconductor DA9150 IIO GPADC bindings
-
-Required properties:
-- compatible: "dlg,da9150-gpadc" for DA9150 IIO GPADC
-- #io-channel-cells: Should be set to <1>
- (See Documentation/devicetree/bindings/iio/iio-bindings.txt for further info)
-
-For further information on GPADC channels, see device datasheet.
-
-
-Example:
-
- gpadc: da9150-gpadc {
- compatible = "dlg,da9150-gpadc";
- #io-channel-cells = <1>;
- };
diff --git a/dts/Bindings/iio/adc/dlg,da9150-gpadc.yaml b/dts/Bindings/iio/adc/dlg,da9150-gpadc.yaml
new file mode 100644
index 0000000000..cc29a2f211
--- /dev/null
+++ b/dts/Bindings/iio/adc/dlg,da9150-gpadc.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/dlg,da9150-gpadc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Dialog Semiconductor DA9150 IIO GPADC
+
+maintainers:
+ - Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
+
+description:
+ This patch adds support for general purpose ADC within the
+ DA9150 Charger & Fuel-Gauge IC.
+
+properties:
+ compatible:
+ const: dlg,da9150-gpadc
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ adc {
+ compatible = "dlg,da9150-gpadc";
+ #io-channel-cells = <1>;
+ };
+...
diff --git a/dts/Bindings/iio/adc/fsl,imx25-gcq.txt b/dts/Bindings/iio/adc/fsl,imx25-gcq.txt
deleted file mode 100644
index eebdcec3da..0000000000
--- a/dts/Bindings/iio/adc/fsl,imx25-gcq.txt
+++ /dev/null
@@ -1,57 +0,0 @@
-Freescale i.MX25 ADC GCQ device
-
-This is a generic conversion queue device that can convert any of the
-analog inputs using the ADC unit of the i.MX25.
-
-Required properties:
- - compatible: Should be "fsl,imx25-gcq".
- - reg: Should be the register range of the module.
- - interrupts: Should be the interrupt number of the module.
- Typically this is <1>.
- - #address-cells: Should be <1> (setting for the subnodes)
- - #size-cells: Should be <0> (setting for the subnodes)
-
-Optional properties:
- - vref-ext-supply: The regulator supplying the ADC reference voltage.
- Required when at least one subnode uses the this reference.
- - vref-xp-supply: The regulator supplying the ADC reference voltage on pin XP.
- Required when at least one subnode uses this reference.
- - vref-yp-supply: The regulator supplying the ADC reference voltage on pin YP.
- Required when at least one subnode uses this reference.
-
-Sub-nodes:
-Optionally you can define subnodes which define the reference voltage
-for the analog inputs.
-
-Required properties for subnodes:
- - reg: Should be the number of the analog input.
- 0: xp
- 1: yp
- 2: xn
- 3: yn
- 4: wiper
- 5: inaux0
- 6: inaux1
- 7: inaux2
-Optional properties for subnodes:
- - fsl,adc-refp: specifies the positive reference input as defined in
- <dt-bindings/iio/adc/fsl-imx25-gcq.h>
- - fsl,adc-refn: specifies the negative reference input as defined in
- <dt-bindings/iio/adc/fsl-imx25-gcq.h>
-
-Example:
-
- adc: adc@50030800 {
- compatible = "fsl,imx25-gcq";
- reg = <0x50030800 0x60>;
- interrupt-parent = <&tscadc>;
- interrupts = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- inaux@5 {
- reg = <5>;
- fsl,adc-refp = <MX25_ADC_REFP_INT>;
- fsl,adc-refn = <MX25_ADC_REFN_NGND>;
- };
- };
diff --git a/dts/Bindings/iio/adc/fsl,imx25-gcq.yaml b/dts/Bindings/iio/adc/fsl,imx25-gcq.yaml
new file mode 100644
index 0000000000..e9103497e3
--- /dev/null
+++ b/dts/Bindings/iio/adc/fsl,imx25-gcq.yaml
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/fsl,imx25-gcq.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale ADC GCQ device
+
+description:
+ This is a generic conversion queue device that can convert any of the
+ analog inputs using the ADC unit of the i.MX25.
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+properties:
+ compatible:
+ const: fsl,imx25-gcq
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ vref-ext-supply:
+ description:
+ The regulator supplying the ADC reference voltage.
+ Required when at least one subnode uses the this reference.
+
+ vref-xp-supply:
+ description:
+ The regulator supplying the ADC reference voltage on pin XP.
+ Required when at least one subnode uses this reference.
+
+ vref-yp-supply:
+ description:
+ The regulator supplying the ADC reference voltage on pin YP.
+ Required when at least one subnode uses this reference.
+
+ "#io-channel-cells":
+ const: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#address-cells"
+ - "#size-cells"
+
+patternProperties:
+ "[a-z][a-z0-9]+@[0-9a-f]+$":
+ type: object
+ description:
+ Child nodes used to define the reference voltages used for each channel
+
+ properties:
+ reg:
+ description: |
+ Number of the analog input.
+ 0: xp
+ 1: yp
+ 2: xn
+ 3: yn
+ 4: wiper
+ 5: inaux0
+ 6: inaux1
+ 7: inaux2
+ items:
+ - minimum: 0
+ maximum: 7
+
+ fsl,adc-refp:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Specifies the positive reference input as defined in
+ <dt-bindings/iio/adc/fsl-imx25-gcq.h>
+ 0: YP voltage reference
+ 1: XP voltage reference
+ 2: External voltage reference
+ 3: Internal voltage reference (default)
+ minimum: 0
+ maximum: 3
+
+ fsl,adc-refn:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Specifies the negative reference input as defined in
+ <dt-bindings/iio/adc/fsl-imx25-gcq.h>
+ 0: XN ground reference
+ 1: YN ground reference
+ 2: Internal ground reference
+ 3: External ground reference (default)
+ minimum: 0
+ maximum: 3
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/iio/adc/fsl-imx25-gcq.h>
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ adc@50030800 {
+ compatible = "fsl,imx25-gcq";
+ reg = <0x50030800 0x60>;
+ interrupt-parent = <&tscadc>;
+ interrupts = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ inaux@5 {
+ reg = <5>;
+ fsl,adc-refp = <MX25_ADC_REFP_INT>;
+ fsl,adc-refn = <MX25_ADC_REFN_NGND>;
+ };
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/fsl,imx7d-adc.yaml b/dts/Bindings/iio/adc/fsl,imx7d-adc.yaml
new file mode 100644
index 0000000000..afc5cc48a0
--- /dev/null
+++ b/dts/Bindings/iio/adc/fsl,imx7d-adc.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/fsl,imx7d-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale ADC found on the imx7d SoC
+
+maintainers:
+ - Haibo Chen <haibo.chen@nxp.com>
+
+properties:
+ compatible:
+ const: fsl,imx7d-adc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: adc
+
+ vref-supply: true
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - vref-supply
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/imx7d-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ adc@30610000 {
+ compatible = "fsl,imx7d-adc";
+ reg = <0x30610000 0x10000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_ADC_ROOT_CLK>;
+ clock-names = "adc";
+ vref-supply = <&reg_vcc_3v3_mcu>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/fsl,vf610-adc.yaml b/dts/Bindings/iio/adc/fsl,vf610-adc.yaml
new file mode 100644
index 0000000000..1ca571056e
--- /dev/null
+++ b/dts/Bindings/iio/adc/fsl,vf610-adc.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/fsl,vf610-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ADC found on Freescale vf610 and similar SoCs
+
+maintainers:
+ - Fugang Duan <fugang.duan@nxp.com>
+
+description:
+ ADCs found on vf610/i.MX6slx and upward SoCs from Freescale.
+
+properties:
+ compatible:
+ const: fsl,vf610-adc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ description: ADC source clock (ipg clock)
+ maxItems: 1
+
+ clock-names:
+ const: adc
+
+ vref-supply:
+ description: ADC reference voltage supply.
+
+ fsl,adck-max-frequency:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 3
+ maxItems: 3
+ description: |
+ Maximum frequencies from datasheet operating requirements.
+ Three values necessary to cover the 3 conversion modes.
+ * Frequency in normal mode (ADLPC=0, ADHSC=0)
+ * Frequency in high-speed mode (ADLPC=0, ADHSC=1)
+ * Frequency in low-power mode (ADLPC=1, ADHSC=0)
+
+ min-sample-time:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Minimum sampling time in nanoseconds. This value has
+ to be chosen according to the conversion mode and the connected analog
+ source resistance (R_as) and capacitance (C_as). Refer the datasheet's
+ operating requirements. A safe default across a wide range of R_as and
+ C_as as well as conversion modes is 1000ns.
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - vref-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/vf610-clock.h>
+ adc@4003b000 {
+ compatible = "fsl,vf610-adc";
+ reg = <0x4003b000 0x1000>;
+ interrupts = <0 53 0x04>;
+ clocks = <&clks VF610_CLK_ADC0>;
+ clock-names = "adc";
+ fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>;
+ vref-supply = <&reg_vcc_3v3_mcu>;
+ min-sample-time = <10000>;
+ };
+...
diff --git a/dts/Bindings/iio/adc/hi8435.txt b/dts/Bindings/iio/adc/hi8435.txt
deleted file mode 100644
index 3b0348c5e5..0000000000
--- a/dts/Bindings/iio/adc/hi8435.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Holt Integrated Circuits HI-8435 threshold detector bindings
-
-Required properties:
- - compatible: should be "holt,hi8435"
- - reg: spi chip select number for the device
-
-Recommended properties:
- - spi-max-frequency: definition as per
- Documentation/devicetree/bindings/spi/spi-bus.txt
-
-Optional properties:
- - gpios: GPIO used for controlling the reset pin
-
-Example:
-sensor@0 {
- compatible = "holt,hi8435";
- reg = <0>;
- gpios = <&gpio6 1 0>;
-
- spi-max-frequency = <1000000>;
-};
diff --git a/dts/Bindings/iio/adc/holt,hi8435.yaml b/dts/Bindings/iio/adc/holt,hi8435.yaml
new file mode 100644
index 0000000000..9514c3381c
--- /dev/null
+++ b/dts/Bindings/iio/adc/holt,hi8435.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/holt,hi8435.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Holt Integrated Circuits HI-8435 SPI threshold detector
+
+maintainers:
+ - Vladimir Barinov <vladimir.barinov@cogentembedded.com>
+
+description: |
+ Datasheet: http://www.holtic.com/documents/427-hi-8435_v-rev-lpdf.do
+
+properties:
+ compatible:
+ const: holt,hi8435
+
+ reg:
+ maxItems: 1
+
+ gpios:
+ description:
+ GPIO used for controlling the reset pin
+ maxItems: 1
+
+ spi-max-frequency: true
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ threshold-detector@0 {
+ compatible = "holt,hi8435";
+ reg = <0>;
+ gpios = <&gpio6 1 0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/imx7d-adc.txt b/dts/Bindings/iio/adc/imx7d-adc.txt
deleted file mode 100644
index f1f3a55245..0000000000
--- a/dts/Bindings/iio/adc/imx7d-adc.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-Freescale imx7d ADC bindings
-
-The devicetree bindings are for the ADC driver written for
-imx7d SoC.
-
-Required properties:
-- compatible: Should be "fsl,imx7d-adc"
-- reg: Offset and length of the register set for the ADC device
-- interrupts: The interrupt number for the ADC device
-- clocks: The root clock of the ADC controller
-- clock-names: Must contain "adc", matching entry in the clocks property
-- vref-supply: The regulator supply ADC reference voltage
-- #io-channel-cells: Must be 1 as per ../iio-bindings.txt
-
-Example:
-adc1: adc@30610000 {
- compatible = "fsl,imx7d-adc";
- reg = <0x30610000 0x10000>;
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_ADC_ROOT_CLK>;
- clock-names = "adc";
- vref-supply = <&reg_vcc_3v3_mcu>;
- #io-channel-cells = <1>;
-};
diff --git a/dts/Bindings/iio/adc/lltc,ltc2497.yaml b/dts/Bindings/iio/adc/lltc,ltc2497.yaml
new file mode 100644
index 0000000000..6a176f551d
--- /dev/null
+++ b/dts/Bindings/iio/adc/lltc,ltc2497.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/lltc,ltc2497.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Linear Technology / Analog Devices LTC2497 ADC
+
+maintainers:
+ - Michael Hennerich <michael.hennerich@analog.com>
+
+description: |
+ 16bit ADC supporting up to 16 single ended or 8 differential inputs.
+ I2C interface.
+
+properties:
+ compatible:
+ const:
+ lltc,ltc2497
+
+ reg: true
+ vref-supply: true
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@76 {
+ compatible = "lltc,ltc2497";
+ reg = <0x76>;
+ vref-supply = <&ltc2497_reg>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/lpc1850-adc.txt b/dts/Bindings/iio/adc/lpc1850-adc.txt
deleted file mode 100644
index 9ada5abd45..0000000000
--- a/dts/Bindings/iio/adc/lpc1850-adc.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-NXP LPC1850 ADC bindings
-
-Required properties:
-- compatible: Should be "nxp,lpc1850-adc"
-- reg: Offset and length of the register set for the ADC device
-- interrupts: The interrupt number for the ADC device
-- clocks: The root clock of the ADC controller
-- vref-supply: The regulator supply ADC reference voltage
-- resets: phandle to reset controller and line specifier
-
-Example:
-
-adc0: adc@400e3000 {
- compatible = "nxp,lpc1850-adc";
- reg = <0x400e3000 0x1000>;
- interrupts = <17>;
- clocks = <&ccu1 CLK_APB3_ADC0>;
- vref-supply = <&reg_vdda>;
- resets = <&rgu 40>;
-};
diff --git a/dts/Bindings/iio/adc/lpc32xx-adc.txt b/dts/Bindings/iio/adc/lpc32xx-adc.txt
deleted file mode 100644
index 3a1bc669bd..0000000000
--- a/dts/Bindings/iio/adc/lpc32xx-adc.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-* NXP LPC32xx SoC ADC controller
-
-Required properties:
-- compatible: must be "nxp,lpc3220-adc"
-- reg: physical base address of the controller and length of memory mapped
- region.
-- interrupts: The ADC interrupt
-
-Optional:
- - vref-supply: The regulator supply ADC reference voltage, optional
- for legacy reason, but highly encouraging to us in new device tree
-
-Example:
-
- adc@40048000 {
- compatible = "nxp,lpc3220-adc";
- reg = <0x40048000 0x1000>;
- interrupt-parent = <&mic>;
- interrupts = <39 0>;
- vref-supply = <&vcc>;
- };
diff --git a/dts/Bindings/iio/adc/ltc2497.txt b/dts/Bindings/iio/adc/ltc2497.txt
deleted file mode 100644
index a237ed99c0..0000000000
--- a/dts/Bindings/iio/adc/ltc2497.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-* Linear Technology / Analog Devices LTC2497 ADC
-
-Required properties:
- - compatible: Must be "lltc,ltc2497"
- - reg: Must contain the ADC I2C address
- - vref-supply: The regulator supply for ADC reference voltage
-
-Example:
- ltc2497: adc@76 {
- compatible = "lltc,ltc2497";
- reg = <0x76>;
- vref-supply = <&ltc2497_reg>;
- };
diff --git a/dts/Bindings/iio/adc/marvell,berlin2-adc.yaml b/dts/Bindings/iio/adc/marvell,berlin2-adc.yaml
new file mode 100644
index 0000000000..b3b292fb1c
--- /dev/null
+++ b/dts/Bindings/iio/adc/marvell,berlin2-adc.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/marvell,berlin2-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Berlin 2 Analog to Digital Converter (ADC)
+
+maintainers:
+ - Antoine Tenart <antoine.tenart@free-electrons.com>
+
+description:
+ The Berlin ADC has 8 channels, with one connected to a temperature sensor.
+ It is part of the system controller register set. The ADC node should be a
+ sub-node of the system controller node.
+
+properties:
+ compatible:
+ const: marvell,berlin2-adc
+
+ interrupts:
+ minItems: 2
+ maxItems: 2
+
+ interrupt-names:
+ items:
+ - const: adc
+ - const: tsen
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - interrupts
+ - interrupt-names
+
+additionalProperties: false
+
+examples:
+ - |
+ sysctrl {
+ adc {
+ compatible = "marvell,berlin2-adc";
+ interrupt-parent = <&sic>;
+ interrupts = <12>, <14>;
+ interrupt-names = "adc", "tsen";
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/max11100.txt b/dts/Bindings/iio/adc/max11100.txt
deleted file mode 100644
index b7f7177b8a..0000000000
--- a/dts/Bindings/iio/adc/max11100.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-* Maxim max11100 Analog to Digital Converter (ADC)
-
-Required properties:
- - compatible: Should be "maxim,max11100"
- - reg: the adc unit address
- - vref-supply: phandle to the regulator that provides reference voltage
-
-Optional properties:
- - spi-max-frequency: SPI maximum frequency
-
-Example:
-
-max11100: adc@0 {
- compatible = "maxim,max11100";
- reg = <0>;
- vref-supply = <&adc0_vref>;
- spi-max-frequency = <240000>;
-};
diff --git a/dts/Bindings/iio/adc/max1118.txt b/dts/Bindings/iio/adc/max1118.txt
deleted file mode 100644
index cf33d0b15a..0000000000
--- a/dts/Bindings/iio/adc/max1118.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-* MAX1117/MAX1118/MAX1119 8-bit, dual-channel ADCs
-
-Required properties:
- - compatible: Should be one of
- * "maxim,max1117"
- * "maxim,max1118"
- * "maxim,max1119"
- - reg: spi chip select number for the device
- - (max1118 only) vref-supply: The regulator supply for ADC reference voltage
-
-Recommended properties:
- - spi-max-frequency: Definition as per
- Documentation/devicetree/bindings/spi/spi-bus.txt
-
-Example:
-adc@0 {
- compatible = "maxim,max1118";
- reg = <0>;
- vref-supply = <&vdd_supply>;
- spi-max-frequency = <1000000>;
-};
diff --git a/dts/Bindings/iio/adc/max9611.txt b/dts/Bindings/iio/adc/max9611.txt
deleted file mode 100644
index ab4f43145a..0000000000
--- a/dts/Bindings/iio/adc/max9611.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-* Maxim max9611/max9612 current sense amplifier with 12-bits ADC interface
-
-Maxim max9611/max9612 is an high-side current sense amplifier with integrated
-12-bits ADC communicating over I2c bus.
-The device node for this driver shall be a child of a I2c controller.
-
-Required properties
- - compatible: Should be "maxim,max9611" or "maxim,max9612"
- - reg: The 7-bits long I2c address of the device
- - shunt-resistor-micro-ohms: Value, in micro Ohms, of the current sense shunt
- resistor
-
-Example:
-
-&i2c4 {
- csa: adc@7c {
- compatible = "maxim,max9611";
- reg = <0x7c>;
-
- shunt-resistor-micro-ohms = <5000>;
- };
-};
-
-This device node describes a current sense amplifier sitting on I2c4 bus
-with address 0x7c (read address is 0xf9, write address is 0xf8).
-A sense resistor of 0,005 Ohm is installed between RS+ and RS- current-sensing
-inputs.
diff --git a/dts/Bindings/iio/adc/maxim,max11100.yaml b/dts/Bindings/iio/adc/maxim,max11100.yaml
new file mode 100644
index 0000000000..0cf87556ef
--- /dev/null
+++ b/dts/Bindings/iio/adc/maxim,max11100.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/maxim,max11100.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX11100 ADC
+
+maintainers:
+ - Jacopo Mondi <jacopo@jmondi.org>
+
+description: |
+ Single channel 16 bit ADC with SPI interface.
+
+properties:
+ compatible:
+ const: maxim,max11100
+
+ reg:
+ maxItems: 1
+
+ vref-supply:
+ description: External reference, needed to establish input scaling.
+
+ spi-max-frequency:
+ minimum: 100000
+ maximum: 4800000
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "maxim,max11100";
+ reg = <0>;
+ vref-supply = <&adc_vref>;
+ spi-max-frequency = <240000>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/maxim,max1118.yaml b/dts/Bindings/iio/adc/maxim,max1118.yaml
new file mode 100644
index 0000000000..e948b3e37b
--- /dev/null
+++ b/dts/Bindings/iio/adc/maxim,max1118.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/maxim,max1118.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX1118 and similar ADCs
+
+maintainers:
+ - Akinobu Mita <akinobu.mita@gmail.com>
+
+description: |
+ Dual channel 8bit ADCs.
+
+properties:
+ compatible:
+ enum:
+ - maxim,max1117
+ - maxim,max1118
+ - maxim,max1119
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 5000000
+
+ vref-supply:
+ description: External reference, needed to establish input scaling
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: maxim,max1118
+then:
+ required:
+ - vref-supply
+else:
+ properties:
+ vref-supply: false
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "maxim,max1118";
+ reg = <0>;
+ vref-supply = <&adc_vref>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/maxim,max1238.yaml b/dts/Bindings/iio/adc/maxim,max1238.yaml
index cccd3033a5..50bcd72ac9 100644
--- a/dts/Bindings/iio/adc/maxim,max1238.yaml
+++ b/dts/Bindings/iio/adc/maxim,max1238.yaml
@@ -62,6 +62,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
i2c {
diff --git a/dts/Bindings/iio/adc/maxim,max1241.yaml b/dts/Bindings/iio/adc/maxim,max1241.yaml
index f562505f5e..4c7e0d94bf 100644
--- a/dts/Bindings/iio/adc/maxim,max1241.yaml
+++ b/dts/Bindings/iio/adc/maxim,max1241.yaml
@@ -39,12 +39,16 @@ properties:
thus enabling power-down mode.
maxItems: 1
+ spi-max-frequency: true
+
required:
- compatible
- reg
- vdd-supply
- vref-supply
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/gpio/gpio.h>
diff --git a/dts/Bindings/iio/adc/maxim,max1363.yaml b/dts/Bindings/iio/adc/maxim,max1363.yaml
index 48377549c3..e04f09f356 100644
--- a/dts/Bindings/iio/adc/maxim,max1363.yaml
+++ b/dts/Bindings/iio/adc/maxim,max1363.yaml
@@ -36,6 +36,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
i2c {
diff --git a/dts/Bindings/iio/adc/maxim,max9611.yaml b/dts/Bindings/iio/adc/maxim,max9611.yaml
new file mode 100644
index 0000000000..9475a9e6e9
--- /dev/null
+++ b/dts/Bindings/iio/adc/maxim,max9611.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/maxim,max9611.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX9611 and similar current sense amplifiers with integrated ADCs
+
+maintainers:
+ - Jacopo Mondi <jacopo@jmondi.org>
+
+description: |
+ These devices combine a high-side current sense amplifier with a 12 bit ADC.
+ They have an i2c interface.
+
+properties:
+ compatible:
+ enum:
+ - maxim,max9611
+ - maxim,max9612
+
+ reg:
+ maxItems: 1
+
+ shunt-resistor-micro-ohms:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Value in micro Ohms of the shunt resistor connected between the RS+ and
+ RS- inputs, across which the current is measured. Value needed to compute
+ the scaling of the measured current.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - shunt-resistor-micro-ohms
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@7c {
+ compatible = "maxim,max9611";
+ reg = <0x7c>;
+ shunt-resistor-micro-ohms = <5000>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/mcp320x.txt b/dts/Bindings/iio/adc/mcp320x.txt
deleted file mode 100644
index 56373d643f..0000000000
--- a/dts/Bindings/iio/adc/mcp320x.txt
+++ /dev/null
@@ -1,57 +0,0 @@
-* Microchip Analog to Digital Converter (ADC)
-
-The node for this driver must be a child node of a SPI controller, hence
-all mandatory properties described in
-
- Documentation/devicetree/bindings/spi/spi-bus.txt
-
-must be specified.
-
-Required properties:
- - compatible: Must be one of the following, depending on the
- model:
- "mcp3001" (DEPRECATED)
- "mcp3002" (DEPRECATED)
- "mcp3004" (DEPRECATED)
- "mcp3008" (DEPRECATED)
- "mcp3201" (DEPRECATED)
- "mcp3202" (DEPRECATED)
- "mcp3204" (DEPRECATED)
- "mcp3208" (DEPRECATED)
- "mcp3301" (DEPRECATED)
-
- "microchip,mcp3001"
- "microchip,mcp3002"
- "microchip,mcp3004"
- "microchip,mcp3008"
- "microchip,mcp3201"
- "microchip,mcp3202"
- "microchip,mcp3204"
- "microchip,mcp3208"
- "microchip,mcp3301"
- "microchip,mcp3550-50"
- "microchip,mcp3550-60"
- "microchip,mcp3551"
- "microchip,mcp3553"
-
- NOTE: The use of the compatibles with no vendor prefix
- is deprecated and only listed because old DT use them.
-
- - spi-cpha, spi-cpol (boolean):
- Either SPI mode (0,0) or (1,1) must be used, so specify
- none or both of spi-cpha, spi-cpol. The MCP3550/1/3
- is more efficient in mode (1,1) as only 3 instead of
- 4 bytes need to be read from the ADC, but not all SPI
- masters support it.
-
- - vref-supply: Phandle to the external reference voltage supply.
-
-Examples:
-spi_controller {
- mcp3x0x@0 {
- compatible = "microchip,mcp3002";
- reg = <0>;
- spi-max-frequency = <1000000>;
- vref-supply = <&vref_reg>;
- };
-};
diff --git a/dts/Bindings/iio/adc/mcp3422.txt b/dts/Bindings/iio/adc/mcp3422.txt
deleted file mode 100644
index 82bcce0725..0000000000
--- a/dts/Bindings/iio/adc/mcp3422.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-* Microchip mcp3421/2/3/4/6/7/8 chip family (ADC)
-
-Required properties:
- - compatible: Should be
- "microchip,mcp3421" or
- "microchip,mcp3422" or
- "microchip,mcp3423" or
- "microchip,mcp3424" or
- "microchip,mcp3425" or
- "microchip,mcp3426" or
- "microchip,mcp3427" or
- "microchip,mcp3428"
- - reg: I2C address for the device
-
-Example:
-adc@0 {
- compatible = "microchip,mcp3424";
- reg = <0x68>;
-};
diff --git a/dts/Bindings/iio/adc/microchip,mcp3201.yaml b/dts/Bindings/iio/adc/microchip,mcp3201.yaml
new file mode 100644
index 0000000000..cbbac4ce56
--- /dev/null
+++ b/dts/Bindings/iio/adc/microchip,mcp3201.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/microchip,mcp3201.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip mcp3201 and similar ADCs
+
+maintainers:
+ - Oskar Andero <oskar.andero@gmail.com>
+
+description: |
+ Family of simple ADCs with an I2C inteface.
+
+properties:
+ compatible:
+ enum:
+ - microchip,mcp3001
+ - microchip,mcp3002
+ - microchip,mcp3004
+ - microchip,mcp3008
+ - microchip,mcp3201
+ - microchip,mcp3202
+ - microchip,mcp3204
+ - microchip,mcp3208
+ - microchip,mcp3301
+ - microchip,mcp3550-50
+ - microchip,mcp3550-60
+ - microchip,mcp3551
+ - microchip,mcp3553
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency: true
+ spi-cpha: true
+ spi-cpol: true
+
+ vref-supply:
+ description: External reference.
+
+ "#io-channel-cells":
+ const: 1
+
+dependencies:
+ spi-cpol: [ spi-cpha ]
+ spi-cpha: [ spi-cpol ]
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "microchip,mcp3002";
+ reg = <0>;
+ vref-supply = <&vref_reg>;
+ spi-cpha;
+ spi-cpol;
+ #io-channel-cells = <1>;
+ };
+ adc@1 {
+ compatible = "microchip,mcp3002";
+ reg = <1>;
+ vref-supply = <&vref_reg>;
+ spi-max-frequency = <1500000>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/motorola,cpcap-adc.yaml b/dts/Bindings/iio/adc/motorola,cpcap-adc.yaml
new file mode 100644
index 0000000000..a6cb857a23
--- /dev/null
+++ b/dts/Bindings/iio/adc/motorola,cpcap-adc.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/motorola,cpcap-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Motorola CPCAP PMIC ADC binding
+
+maintainers:
+ - Tony Lindgren <tony@atomide.com>
+
+description:
+ On Motorola phones like droid 4 there is a custom CPCAP PMIC. This PMIC
+ has ADCs that are used for battery charging and USB PHY VBUS and ID pin
+ detection.
+
+properties:
+ compatible:
+ enum:
+ - motorola,cpcap-adc
+ - motorola,mapphone-cpcap-adc
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ const: adcdone
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - interrupts
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ pmic {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ adc {
+ compatible = "motorola,mapphone-cpcap-adc";
+ interrupt-parent = <&cpcap>;
+ interrupts = <8 IRQ_TYPE_NONE>;
+ interrupt-names = "adcdone";
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/nuvoton,nau7802.yaml b/dts/Bindings/iio/adc/nuvoton,nau7802.yaml
new file mode 100644
index 0000000000..04566ff02e
--- /dev/null
+++ b/dts/Bindings/iio/adc/nuvoton,nau7802.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/nuvoton,nau7802.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton NAU7802 I2c Analog to Digital Converter (ADC)
+
+maintainers:
+ - Alexandre Belloni <alexandre.belloni@bootlin.com>
+ - Maxime Ripard <mripard@kernel.org>
+
+properties:
+ compatible:
+ const: nuvoton,nau7802
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ nuvoton,vldo:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Internal reference voltage in millivolts to be configured.
+ minimum: 2400
+ maximum: 4500
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nau7802@2a {
+ compatible = "nuvoton,nau7802";
+ reg = <0x2a>;
+ nuvoton,vldo = <3000>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/nuvoton,npcm-adc.txt b/dts/Bindings/iio/adc/nuvoton,npcm-adc.txt
deleted file mode 100644
index ef8eeec1a9..0000000000
--- a/dts/Bindings/iio/adc/nuvoton,npcm-adc.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-Nuvoton NPCM Analog to Digital Converter (ADC)
-
-The NPCM ADC is a 10-bit converter for eight channel inputs.
-
-Required properties:
-- compatible: "nuvoton,npcm750-adc" for the NPCM7XX BMC.
-- reg: specifies physical base address and size of the registers.
-- interrupts: Contain the ADC interrupt with flags for falling edge.
-- resets : phandle to the reset control for this device.
-
-Optional properties:
-- clocks: phandle of ADC reference clock, in case the clock is not
- added the ADC will use the default ADC sample rate.
-- vref-supply: The regulator supply ADC reference voltage, in case the
- vref-supply is not added the ADC will use internal voltage
- reference.
-
-Example:
-
-adc: adc@f000c000 {
- compatible = "nuvoton,npcm750-adc";
- reg = <0xf000c000 0x8>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk NPCM7XX_CLK_ADC>;
- resets = <&rstc NPCM7XX_RESET_IPSRST1 NPCM7XX_RESET_ADC>;
-};
diff --git a/dts/Bindings/iio/adc/nuvoton,npcm750-adc.yaml b/dts/Bindings/iio/adc/nuvoton,npcm750-adc.yaml
new file mode 100644
index 0000000000..001cf263b7
--- /dev/null
+++ b/dts/Bindings/iio/adc/nuvoton,npcm750-adc.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/nuvoton,npcm750-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton NPCM BMC Analog to Digital Converter (ADC)
+
+maintainers:
+ - Tomer Maimon <tmaimon77@gmail.com>
+
+description:
+ The NPCM ADC is a 10-bit converter for eight channel inputs.
+
+properties:
+ compatible:
+ const: nuvoton,npcm750-adc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+ description: ADC interrupt, should be set for falling edge.
+
+ resets:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description: If not provided the defulat ADC sample rate will be used.
+
+ vref-supply:
+ description: If not supplied, the internal voltage reference will be used.
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
+ #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ adc@f000c000 {
+ compatible = "nuvoton,npcm750-adc";
+ reg = <0xf000c000 0x8>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk NPCM7XX_CLK_ADC>;
+ resets = <&rstc NPCM7XX_RESET_IPSRST1 NPCM7XX_RESET_ADC>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/nuvoton-nau7802.txt b/dts/Bindings/iio/adc/nuvoton-nau7802.txt
deleted file mode 100644
index e9582e6fe3..0000000000
--- a/dts/Bindings/iio/adc/nuvoton-nau7802.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-* Nuvoton NAU7802 Analog to Digital Converter (ADC)
-
-Required properties:
- - compatible: Should be "nuvoton,nau7802"
- - reg: Should contain the ADC I2C address
-
-Optional properties:
- - nuvoton,vldo: Internal reference voltage in millivolts to be
- configured valid values are between 2400 mV and 4500 mV.
- - interrupts: IRQ line for the ADC. If not used the driver will use
- polling.
-
-Example:
-adc2: nau7802@2a {
- compatible = "nuvoton,nau7802";
- reg = <0x2a>;
- nuvoton,vldo = <3000>;
-};
diff --git a/dts/Bindings/iio/adc/nxp,lpc1850-adc.yaml b/dts/Bindings/iio/adc/nxp,lpc1850-adc.yaml
new file mode 100644
index 0000000000..6404fb73f8
--- /dev/null
+++ b/dts/Bindings/iio/adc/nxp,lpc1850-adc.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/nxp,lpc1850-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP LPC1850 ADC bindings
+
+maintainers:
+ - Joachim Eastwood <manabian@gmail.com>
+
+description:
+ Supports the ADC found on the LPC1850 SoC.
+
+properties:
+ compatible:
+ const: nxp,lpc1850-adc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ vref-supply: true
+
+ resets:
+ maxItems: 1
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - vref-supply
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/lpc18xx-ccu.h>
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ adc@400e3000 {
+ compatible = "nxp,lpc1850-adc";
+ reg = <0x400e3000 0x1000>;
+ interrupts = <17>;
+ clocks = <&ccu1 CLK_APB3_ADC0>;
+ vref-supply = <&reg_vdda>;
+ resets = <&rgu 40>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/nxp,lpc3220-adc.yaml b/dts/Bindings/iio/adc/nxp,lpc3220-adc.yaml
new file mode 100644
index 0000000000..2c5032be83
--- /dev/null
+++ b/dts/Bindings/iio/adc/nxp,lpc3220-adc.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/nxp,lpc3220-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP LPC3220 SoC ADC controller
+
+maintainers:
+ - Gregory Clement <gregory.clement@bootlin.com>
+
+description:
+ This hardware block has been used on several LPC32XX SoCs.
+
+properties:
+ compatible:
+ const: nxp,lpc3220-adc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ vref-supply: true
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ adc@40048000 {
+ compatible = "nxp,lpc3220-adc";
+ reg = <0x40048000 0x1000>;
+ interrupt-parent = <&mic>;
+ interrupts = <39 0>;
+ vref-supply = <&vcc>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/qcom,spmi-vadc.yaml b/dts/Bindings/iio/adc/qcom,spmi-vadc.yaml
index 0ca992465a..7f4f827c57 100644
--- a/dts/Bindings/iio/adc/qcom,spmi-vadc.yaml
+++ b/dts/Bindings/iio/adc/qcom,spmi-vadc.yaml
@@ -48,6 +48,8 @@ properties:
description:
End of conversion interrupt.
+ io-channel-ranges: true
+
required:
- compatible
- reg
@@ -232,6 +234,8 @@ allOf:
enum: [ 1, 2, 4, 8, 16 ]
default: 1
+additionalProperties: false
+
examples:
- |
spmi_bus {
diff --git a/dts/Bindings/iio/adc/samsung,exynos-adc.yaml b/dts/Bindings/iio/adc/samsung,exynos-adc.yaml
index cc3c8ea6a8..5ebb0ab250 100644
--- a/dts/Bindings/iio/adc/samsung,exynos-adc.yaml
+++ b/dts/Bindings/iio/adc/samsung,exynos-adc.yaml
@@ -41,11 +41,16 @@ properties:
maxItems: 2
interrupts:
- maxItems: 1
+ description:
+ ADC interrupt followed by optional touchscreen interrupt.
+ minItems: 1
+ maxItems: 2
"#io-channel-cells":
const: 1
+ io-channel-ranges: true
+
vdd-supply: true
samsung,syscon-phandle:
@@ -68,6 +73,9 @@ required:
- "#io-channel-cells"
- vdd-supply
+additionalProperties:
+ type: object
+
allOf:
- if:
properties:
@@ -78,7 +86,6 @@ allOf:
- samsung,exynos-adc-v2
- samsung,exynos3250-adc
- samsung,exynos4212-adc
- - samsung,s5pv210-adc
then:
required:
- samsung,syscon-phandle
@@ -107,6 +114,15 @@ allOf:
items:
- const: adc
+ - if:
+ required:
+ - has-touchscreen
+ then:
+ properties:
+ interrupts:
+ minItems: 2
+ maxItems: 2
+
examples:
- |
adc: adc@12d10000 {
diff --git a/dts/Bindings/iio/adc/sprd,sc2720-adc.yaml b/dts/Bindings/iio/adc/sprd,sc2720-adc.yaml
new file mode 100644
index 0000000000..caa3ee0b4b
--- /dev/null
+++ b/dts/Bindings/iio/adc/sprd,sc2720-adc.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/sprd,sc2720-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Spreadtrum SC27XX series PMICs ADC binding
+
+maintainers:
+ - Baolin Wang <baolin.wang7@gmail.com>
+
+description:
+ Supports the ADC found on these PMICs.
+
+properties:
+ compatible:
+ enum:
+ - sprd,sc2720-adc
+ - sprd,sc2721-adc
+ - sprd,sc2723-adc
+ - sprd,sc2730-adc
+ - sprd,sc2731-adc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#io-channel-cells":
+ const: 1
+
+ hwlocks:
+ maxItems: 1
+
+ nvmem-cells:
+ maxItems: 2
+
+ nvmem-cell-names:
+ items:
+ - const: big_scale_calib
+ - const: small_scale_calib
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#io-channel-cells"
+ - hwlocks
+ - nvmem-cells
+ - nvmem-cell-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ pmic {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ adc@480 {
+ compatible = "sprd,sc2731-adc";
+ reg = <0x480>;
+ interrupt-parent = <&sc2731_pmic>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ hwlocks = <&hwlock 4>;
+ nvmem-cells = <&adc_big_scale>, <&adc_small_scale>;
+ nvmem-cell-names = "big_scale_calib", "small_scale_calib";
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/sprd,sc27xx-adc.txt b/dts/Bindings/iio/adc/sprd,sc27xx-adc.txt
deleted file mode 100644
index b4daa15dcf..0000000000
--- a/dts/Bindings/iio/adc/sprd,sc27xx-adc.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-Spreadtrum SC27XX series PMICs ADC binding
-
-Required properties:
-- compatible: Should be one of the following.
- "sprd,sc2720-adc"
- "sprd,sc2721-adc"
- "sprd,sc2723-adc"
- "sprd,sc2730-adc"
- "sprd,sc2731-adc"
-- reg: The address offset of ADC controller.
-- interrupt-parent: The interrupt controller.
-- interrupts: The interrupt number for the ADC device.
-- #io-channel-cells: Number of cells in an IIO specifier.
-- hwlocks: Reference to a phandle of a hwlock provider node.
-- nvmem-cells: A phandle to the calibration cells provided by eFuse device.
-- nvmem-cell-names: Should be "big_scale_calib", "small_scale_calib".
-
-Example:
-
- sc2731_pmic: pmic@0 {
- compatible = "sprd,sc2731";
- reg = <0>;
- spi-max-frequency = <26000000>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pmic_adc: adc@480 {
- compatible = "sprd,sc2731-adc";
- reg = <0x480>;
- interrupt-parent = <&sc2731_pmic>;
- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
- #io-channel-cells = <1>;
- hwlocks = <&hwlock 4>;
- nvmem-cells = <&adc_big_scale>, <&adc_small_scale>;
- nvmem-cell-names = "big_scale_calib", "small_scale_calib";
- };
- };
diff --git a/dts/Bindings/iio/adc/st,stmpe-adc.yaml b/dts/Bindings/iio/adc/st,stmpe-adc.yaml
new file mode 100644
index 0000000000..9049c69915
--- /dev/null
+++ b/dts/Bindings/iio/adc/st,stmpe-adc.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/st,stmpe-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ADC on an STMPE multifunction device.
+
+maintainers:
+ - Stefan Agner <stefan@agner.ch>
+
+description:
+ This ADC forms part of an ST microelectronics STMPE multifunction device .
+ The ADC is shared with the STMPE touchscreen. As a result some ADC related
+ settings are specified in the parent node.
+ The node name myst be stmpe_adc and should be a child node of the stmpe node
+ to which it belongs.
+
+properties:
+ compatible:
+ const: st,stmpe-adc
+
+ st,norequest-mask:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Bitmask specifying which ADC channels should _not_ be
+ requestable due to different usage (e.g. touch).
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ stmpe {
+ stmpe_adc {
+ compatible = "st,stmpe-adc";
+ st,norequest-mask = <0x0F>; /* dont use ADC CH3-0 */
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/stmpe-adc.txt b/dts/Bindings/iio/adc/stmpe-adc.txt
deleted file mode 100644
index 480e664226..0000000000
--- a/dts/Bindings/iio/adc/stmpe-adc.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-STMPE ADC driver
-----------------
-
-Required properties:
- - compatible: "st,stmpe-adc"
-
-Optional properties:
-Note that the ADC is shared with the STMPE touchscreen. ADC related settings
-have to be done in the mfd.
-- st,norequest-mask: bitmask specifying which ADC channels should _not_ be
- requestable due to different usage (e.g. touch)
-
-Node name must be stmpe_adc and should be child node of stmpe node to
-which it belongs.
-
-Example:
-
- stmpe_adc {
- compatible = "st,stmpe-adc";
- st,norequest-mask = <0x0F>; /* dont use ADC CH3-0 */
- };
diff --git a/dts/Bindings/iio/adc/ti,adc0832.yaml b/dts/Bindings/iio/adc/ti,adc0832.yaml
new file mode 100644
index 0000000000..f5a923cc84
--- /dev/null
+++ b/dts/Bindings/iio/adc/ti,adc0832.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,adc0832.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments ADC0832 and similar ADCs
+
+maintainers:
+ - Akinobu Mita <akinobu.mita@gmail.com>
+
+description: |
+ 8 bit ADCs with 1, 2, 4 or 8 inputs for single ended or differential
+ conversion.
+
+properties:
+ compatible:
+ enum:
+ - ti,adc0831
+ - ti,adc0832
+ - ti,adc0834
+ - ti,adc0838
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency: true
+
+ vref-supply:
+ description: External reference, needed to establish input scaling
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,adc0832";
+ reg = <0>;
+ vref-supply = <&vdd_supply>;
+ spi-max-frequency = <200000>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/ti,adc108s102.yaml b/dts/Bindings/iio/adc/ti,adc108s102.yaml
new file mode 100644
index 0000000000..54955f03df
--- /dev/null
+++ b/dts/Bindings/iio/adc/ti,adc108s102.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,adc108s102.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments ADC108S102 and ADC128S102
+
+maintainers:
+ - Bogdan Pricop <bogdan.pricop@emutex.com>
+
+description: |
+ Family of 8 channel, 10/12 bit, SPI, single ended ADCs.
+
+properties:
+ compatible:
+ const:
+ ti,adc108s102
+
+ reg: true
+ vref-supply: true
+ spi-max-frequency: true
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells= <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,adc108s102";
+ reg = <0>;
+ vref-supply = <&vdd_supply>;
+ spi-max-frequency = <1000000>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/ti,adc12138.yaml b/dts/Bindings/iio/adc/ti,adc12138.yaml
new file mode 100644
index 0000000000..ec3b2edf1f
--- /dev/null
+++ b/dts/Bindings/iio/adc/ti,adc12138.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,adc12138.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments ADC12138 and similar self-calibrating ADCs
+
+maintainers:
+ - Akinobu Mita <akinobu.mita@gmail.com>
+
+description: |
+ 13 bit ADCs with 1, 2 or 8 inputs and self calibrating circuitry to
+ correct for linearity, zero and full scale errors.
+
+properties:
+ compatible:
+ enum:
+ - ti,adc12130
+ - ti,adc12132
+ - ti,adc12138
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+ description: End of Conversion (EOC) interrupt
+
+ clocks:
+ maxItems: 1
+ description: Conversion clock input.
+
+ spi-max-frequency: true
+
+ vref-p-supply:
+ description: The regulator supply for positive analog voltage reference
+
+ vref-n-supply:
+ description: |
+ The regulator supply for negative analog voltage reference
+ (Note that this must not go below GND or exceed vref-p)
+ If not specified, this is assumed to be analog ground.
+
+ ti,acquisition-time:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 6, 10, 18, 34 ]
+ description: |
+ The number of conversion clock periods for the S/H's acquisition time.
+ For high source impedances, this value can be increased to 18 or 34.
+ For less ADC accuracy and/or slower CCLK frequencies this value may be
+ decreased to 6. See section 6.0 INPUT SOURCE RESISTANCE in the
+ datasheet for details.
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - vref-p-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,adc12138";
+ reg = <0>;
+ interrupts = <28 IRQ_TYPE_EDGE_RISING>;
+ interrupt-parent = <&gpio1>;
+ clocks = <&cclk>;
+ vref-p-supply = <&ldo4_reg>;
+ spi-max-frequency = <5000000>;
+ ti,acquisition-time = <6>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/ti,adc128s052.yaml b/dts/Bindings/iio/adc/ti,adc128s052.yaml
new file mode 100644
index 0000000000..d54a0183f0
--- /dev/null
+++ b/dts/Bindings/iio/adc/ti,adc128s052.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,adc128s052.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments ADC128S052 and similar ADCs
+
+maintainers:
+ - Angelo Compagnucci <angelo.compagnucci@gmail.com>
+
+description: |
+ Family of 12 bit SPI ADCs with 2 to 8 channels with a range of different
+ target sample rates.
+
+properties:
+ compatible:
+ enum:
+ - ti,adc122s021
+ - ti,adc122s051
+ - ti,adc122s101
+ - ti,adc124s021
+ - ti,adc124s051
+ - ti,adc124s101
+ - ti,adc128s052
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency: true
+
+ vref-supply: true
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,adc128s052";
+ reg = <0>;
+ vref-supply = <&vdd_supply>;
+ spi-max-frequency = <1000000>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/ti,adc161s626.yaml b/dts/Bindings/iio/adc/ti,adc161s626.yaml
new file mode 100644
index 0000000000..3f4f334d6f
--- /dev/null
+++ b/dts/Bindings/iio/adc/ti,adc161s626.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,adc161s626.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments ADC141S626 and ADC161S626 ADCs
+
+maintainers:
+ - Matt Ranostay <matt.ranostay@konsulko.com>
+
+description: |
+ Single channel 14/16bit differential ADCs
+
+properties:
+ compatible:
+ enum:
+ - ti,adc141s626
+ - ti,adc161s626
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency: true
+
+ vdda-supply: true
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,adc161s626";
+ vdda-supply = <&vdda_fixed>;
+ reg = <0>;
+ spi-max-frequency = <4300000>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/ti,ads1015.yaml b/dts/Bindings/iio/adc/ti,ads1015.yaml
new file mode 100644
index 0000000000..2c2d01bbc2
--- /dev/null
+++ b/dts/Bindings/iio/adc/ti,ads1015.yaml
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,ads1015.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI ADS1015 4 channel I2C analog to digital converter
+
+maintainers:
+ - Daniel Baluta <daniel.baluta@nxp.com>
+
+description: |
+ Datasheet at: https://www.ti.com/lit/gpn/ads1015
+ Supports both single ended and differential channels.
+
+properties:
+ compatible:
+ const: ti,ads1015
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
+
+patternProperties:
+ "^channel@[0-7]+$":
+ type: object
+ description:
+ Child nodes needed for each channel that the platform uses.
+
+ properties:
+ reg:
+ description: |
+ 0: Voltage over AIN0 and AIN1.
+ 1: Voltage over AIN0 and AIN3.
+ 2: Voltage over AIN1 and AIN3.
+ 3: Voltage over AIN2 and AIN3.
+ 4: Voltage over AIN0 and GND.
+ 5: Voltage over AIN1 and GND.
+ 6: Voltage over AIN2 and GND.
+ 7: Voltage over AIN3 and GND.
+ items:
+ - minimum: 0
+ maximum: 7
+
+ ti,gain:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 5
+ description: |
+ pga is the programmable gain amplifier (values are full scale)
+ 0: +/- 6.144 V
+ 1: +/- 4.096 V
+ 2: +/- 2.048 V (default)
+ 3: +/- 1.024 V
+ 4: +/- 0.512 V
+ 5: +/- 0.256 V
+
+ ti,datarate:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 6
+ description: |
+ Data acquisition rate in samples per second
+ 0: 128
+ 1: 250
+ 2: 490
+ 3: 920
+ 4: 1600 (default)
+ 5: 2400
+ 6: 3300
+
+ required:
+ - reg
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@49 {
+ compatible = "ti,ads1015";
+ reg = <0x49>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ channel@0 {
+ reg = <0>;
+ };
+ channel@4 {
+ reg = <4>;
+ ti,gain = <3>;
+ ti,datarate = <5>;
+ };
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/ti,ads7950.yaml b/dts/Bindings/iio/adc/ti,ads7950.yaml
new file mode 100644
index 0000000000..5ab5027be9
--- /dev/null
+++ b/dts/Bindings/iio/adc/ti,ads7950.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,ads7950.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments ADS7950 and similar ADCs
+
+maintainers:
+ - David Lechner <david@lechnology.com>
+
+description: |
+ Family of 4-16 channel, 8-12 bit ADCs with SPI interface.
+
+properties:
+ compatible:
+ enum:
+ - ti,ads7950
+ - ti,ads7951
+ - ti,ads7952
+ - ti,ads7953
+ - ti,ads7954
+ - ti,ads7955
+ - ti,ads7956
+ - ti,ads7957
+ - ti,ads7958
+ - ti,ads7959
+ - ti,ads7960
+ - ti,ads7961
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 20000000
+
+ vref-supply:
+ description: Supplies the 2.5V or 5V reference voltage
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,ads7957";
+ reg = <0>;
+ vref-supply = <&refin_supply>;
+ spi-max-frequency = <10000000>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/ti,ads8344.yaml b/dts/Bindings/iio/adc/ti,ads8344.yaml
new file mode 100644
index 0000000000..b8c398187d
--- /dev/null
+++ b/dts/Bindings/iio/adc/ti,ads8344.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,ads8344.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments ADS8344 ADC
+
+maintainers:
+ - Gregory Clement <gregory.clement@bootlin.com>
+
+description: |
+ 16bit 8-channel ADC with single ended inputs.
+
+properties:
+ compatible:
+ const: ti,ads8344
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency: true
+
+ vref-supply:
+ description: Supply the 2.5V or 5V reference voltage
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,ads8344";
+ reg = <0>;
+ vref-supply = <&refin_supply>;
+ spi-max-frequency = <10000000>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/ti,ads8688.yaml b/dts/Bindings/iio/adc/ti,ads8688.yaml
index 97fe6cbb2e..a0af4b2487 100644
--- a/dts/Bindings/iio/adc/ti,ads8688.yaml
+++ b/dts/Bindings/iio/adc/ti,ads8688.yaml
@@ -25,10 +25,14 @@ properties:
description: Optional external reference. If not supplied, assume
REFSEL input tied low to enable the internal reference.
+ spi-max-frequency: true
+
required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
spi {
diff --git a/dts/Bindings/iio/adc/ti,tlc4541.yaml b/dts/Bindings/iio/adc/ti,tlc4541.yaml
new file mode 100644
index 0000000000..6c2539b3d7
--- /dev/null
+++ b/dts/Bindings/iio/adc/ti,tlc4541.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,tlc4541.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments TLC4541 and similar ADCs
+
+maintainers:
+ - Phil Reid <preid@electromag.com.au>
+
+description: |
+ 14/16bit single channel ADC with SPI interface.
+
+properties:
+ compatible:
+ enum:
+ - ti,tlc3541
+ - ti,tlc4541
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency: true
+
+ vref-supply: true
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,tlc4541";
+ reg = <0>;
+ vref-supply = <&vdd_supply>;
+ spi-max-frequency = <200000>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/ti,twl4030-madc.yaml b/dts/Bindings/iio/adc/ti,twl4030-madc.yaml
new file mode 100644
index 0000000000..6781ad2f0f
--- /dev/null
+++ b/dts/Bindings/iio/adc/ti,twl4030-madc.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,twl4030-madc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MADC subsystem in the TWL4030 power module
+
+maintainers:
+ - Sebastian Reichel <sre@kernel.org>
+
+description:
+ The MADC subsystem in the TWL4030 consists of a 10-bit ADC
+ combined with a 16-input analog multiplexer.
+
+properties:
+ compatible:
+ const: ti,twl4030-madc
+
+ interrupts:
+ maxItems: 1
+
+ ti,system-uses-second-madc-irq:
+ type: boolean
+ description:
+ Set if the second madc irq register should be used, which is intended
+ to be used by Co-Processors (e.g. a modem).
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - interrupts
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ twl {
+ madc {
+ compatible = "ti,twl4030-madc";
+ interrupts = <3>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/ti-adc0832.txt b/dts/Bindings/iio/adc/ti-adc0832.txt
deleted file mode 100644
index d91130587d..0000000000
--- a/dts/Bindings/iio/adc/ti-adc0832.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-* Texas Instruments' ADC0831/ADC0832/ADC0832/ADC0838
-
-Required properties:
- - compatible: Should be one of
- * "ti,adc0831"
- * "ti,adc0832"
- * "ti,adc0834"
- * "ti,adc0838"
- - reg: spi chip select number for the device
- - vref-supply: The regulator supply for ADC reference voltage
- - spi-max-frequency: Max SPI frequency to use (< 400000)
-
-Example:
-adc@0 {
- compatible = "ti,adc0832";
- reg = <0>;
- vref-supply = <&vdd_supply>;
- spi-max-frequency = <200000>;
-};
diff --git a/dts/Bindings/iio/adc/ti-adc108s102.txt b/dts/Bindings/iio/adc/ti-adc108s102.txt
deleted file mode 100644
index bbbbb4a9f5..0000000000
--- a/dts/Bindings/iio/adc/ti-adc108s102.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-* Texas Instruments' ADC108S102 and ADC128S102 ADC chip
-
-Required properties:
- - compatible: Should be "ti,adc108s102"
- - reg: spi chip select number for the device
- - vref-supply: The regulator supply for ADC reference voltage
-
-Recommended properties:
- - spi-max-frequency: Definition as per
- Documentation/devicetree/bindings/spi/spi-bus.txt
-
-Example:
-adc@0 {
- compatible = "ti,adc108s102";
- reg = <0>;
- vref-supply = <&vdd_supply>;
- spi-max-frequency = <1000000>;
-};
diff --git a/dts/Bindings/iio/adc/ti-adc12138.txt b/dts/Bindings/iio/adc/ti-adc12138.txt
deleted file mode 100644
index 049a1d36f0..0000000000
--- a/dts/Bindings/iio/adc/ti-adc12138.txt
+++ /dev/null
@@ -1,37 +0,0 @@
-* Texas Instruments' ADC12130/ADC12132/ADC12138
-
-Required properties:
- - compatible: Should be one of
- * "ti,adc12130"
- * "ti,adc12132"
- * "ti,adc12138"
- - reg: SPI chip select number for the device
- - interrupts: Should contain interrupt for EOC (end of conversion)
- - clocks: phandle to conversion clock input
- - spi-max-frequency: Definision as per
- Documentation/devicetree/bindings/spi/spi-bus.txt
- - vref-p-supply: The regulator supply for positive analog voltage reference
-
-Optional properties:
- - vref-n-supply: The regulator supply for negative analog voltage reference
- (Note that this must not go below GND or exceed vref-p)
- If not specified, this is assumed to be analog ground.
- - ti,acquisition-time: The number of conversion clock periods for the S/H's
- acquisition time. Should be one of 6, 10, 18, 34. If not specified,
- default value of 10 is used.
- For high source impedances, this value can be increased to 18 or 34.
- For less ADC accuracy and/or slower CCLK frequencies this value may be
- decreased to 6. See section 6.0 INPUT SOURCE RESISTANCE in the
- datasheet for details.
-
-Example:
-adc@0 {
- compatible = "ti,adc12138";
- reg = <0>;
- interrupts = <28 IRQ_TYPE_EDGE_RISING>;
- interrupt-parent = <&gpio1>;
- clocks = <&cclk>;
- vref-p-supply = <&ldo4_reg>;
- spi-max-frequency = <5000000>;
- ti,acquisition-time = <6>;
-};
diff --git a/dts/Bindings/iio/adc/ti-adc128s052.txt b/dts/Bindings/iio/adc/ti-adc128s052.txt
deleted file mode 100644
index c07ce1a3f5..0000000000
--- a/dts/Bindings/iio/adc/ti-adc128s052.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-* Texas Instruments' ADC128S052, ADC122S021 and ADC124S021 ADC chip
-
-Required properties:
- - compatible: Should be one of:
- - "ti,adc128s052"
- - "ti,adc122s021"
- - "ti,adc122s051"
- - "ti,adc122s101"
- - "ti,adc124s021"
- - "ti,adc124s051"
- - "ti,adc124s101"
- - reg: spi chip select number for the device
- - vref-supply: The regulator supply for ADC reference voltage
-
-Recommended properties:
- - spi-max-frequency: Definition as per
- Documentation/devicetree/bindings/spi/spi-bus.txt
-
-Example:
-adc@0 {
- compatible = "ti,adc128s052";
- reg = <0>;
- vref-supply = <&vdd_supply>;
- spi-max-frequency = <1000000>;
-};
diff --git a/dts/Bindings/iio/adc/ti-adc161s626.txt b/dts/Bindings/iio/adc/ti-adc161s626.txt
deleted file mode 100644
index 3d25011f0c..0000000000
--- a/dts/Bindings/iio/adc/ti-adc161s626.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-* Texas Instruments ADC141S626 and ADC161S626 chips
-
-Required properties:
- - compatible: Should be "ti,adc141s626" or "ti,adc161s626"
- - reg: spi chip select number for the device
- - vdda-supply: supply voltage to VDDA pin
-
-Recommended properties:
- - spi-max-frequency: Definition as per
- Documentation/devicetree/bindings/spi/spi-bus.txt
-
-Example:
-adc@0 {
- compatible = "ti,adc161s626";
- vdda-supply = <&vdda_fixed>;
- reg = <0>;
- spi-max-frequency = <4300000>;
-};
diff --git a/dts/Bindings/iio/adc/ti-ads7950.txt b/dts/Bindings/iio/adc/ti-ads7950.txt
deleted file mode 100644
index e77a6f7e10..0000000000
--- a/dts/Bindings/iio/adc/ti-ads7950.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-* Texas Instruments ADS7950 family of A/DC chips
-
-Required properties:
- - compatible: Must be one of "ti,ads7950", "ti,ads7951", "ti,ads7952",
- "ti,ads7953", "ti,ads7954", "ti,ads7955", "ti,ads7956", "ti,ads7957",
- "ti,ads7958", "ti,ads7959", "ti,ads7960", or "ti,ads7961"
- - reg: SPI chip select number for the device
- - #io-channel-cells: Must be 1 as per ../iio-bindings.txt
- - vref-supply: phandle to a regulator node that supplies the 2.5V or 5V
- reference voltage
-
-Recommended properties:
- - spi-max-frequency: Definition as per
- Documentation/devicetree/bindings/spi/spi-bus.txt
-
-Example:
-adc@0 {
- compatible = "ti,ads7957";
- reg = <0>;
- #io-channel-cells = <1>;
- vref-supply = <&refin_supply>;
- spi-max-frequency = <10000000>;
-};
diff --git a/dts/Bindings/iio/adc/ti-ads8344.txt b/dts/Bindings/iio/adc/ti-ads8344.txt
deleted file mode 100644
index e47c3759a8..0000000000
--- a/dts/Bindings/iio/adc/ti-ads8344.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-* Texas Instruments ADS8344 A/DC chip
-
-Required properties:
- - compatible: Must be "ti,ads8344"
- - reg: SPI chip select number for the device
- - vref-supply: phandle to a regulator node that supplies the
- reference voltage
-
-Recommended properties:
- - spi-max-frequency: Definition as per
- Documentation/devicetree/bindings/spi/spi-bus.txt
-
-Example:
-adc@0 {
- compatible = "ti,ads8344";
- reg = <0>;
- vref-supply = <&refin_supply>;
- spi-max-frequency = <10000000>;
-};
diff --git a/dts/Bindings/iio/adc/twl4030-madc.txt b/dts/Bindings/iio/adc/twl4030-madc.txt
deleted file mode 100644
index 6bdd21404b..0000000000
--- a/dts/Bindings/iio/adc/twl4030-madc.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-* TWL4030 Monitoring Analog to Digital Converter (MADC)
-
-The MADC subsystem in the TWL4030 consists of a 10-bit ADC
-combined with a 16-input analog multiplexer.
-
-Required properties:
- - compatible: Should contain "ti,twl4030-madc".
- - interrupts: IRQ line for the MADC submodule.
- - #io-channel-cells: Should be set to <1>.
-
-Optional properties:
- - ti,system-uses-second-madc-irq: boolean, set if the second madc irq register
- should be used, which is intended to be used
- by Co-Processors (e.g. a modem).
-
-Example:
-
-&twl {
- madc {
- compatible = "ti,twl4030-madc";
- interrupts = <3>;
- #io-channel-cells = <1>;
- };
-};
diff --git a/dts/Bindings/iio/adc/vf610-adc.txt b/dts/Bindings/iio/adc/vf610-adc.txt
deleted file mode 100644
index 1aad0514e6..0000000000
--- a/dts/Bindings/iio/adc/vf610-adc.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-Freescale vf610 Analog to Digital Converter bindings
-
-The devicetree bindings are for the new ADC driver written for
-vf610/i.MX6slx and upward SoCs from Freescale.
-
-Required properties:
-- compatible: Should contain "fsl,vf610-adc"
-- reg: Offset and length of the register set for the device
-- interrupts: Should contain the interrupt for the device
-- clocks: The clock is needed by the ADC controller, ADC clock source is ipg clock.
-- clock-names: Must contain "adc", matching entry in the clocks property.
-- vref-supply: The regulator supply ADC reference voltage.
-
-Recommended properties:
-- fsl,adck-max-frequency: Maximum frequencies according to datasheets operating
- requirements. Three values are required, depending on conversion mode:
- - Frequency in normal mode (ADLPC=0, ADHSC=0)
- - Frequency in high-speed mode (ADLPC=0, ADHSC=1)
- - Frequency in low-power mode (ADLPC=1, ADHSC=0)
-- min-sample-time: Minimum sampling time in nanoseconds. This value has
- to be chosen according to the conversion mode and the connected analog
- source resistance (R_as) and capacitance (C_as). Refer the datasheet's
- operating requirements. A safe default across a wide range of R_as and
- C_as as well as conversion modes is 1000ns.
-
-Example:
-adc0: adc@4003b000 {
- compatible = "fsl,vf610-adc";
- reg = <0x4003b000 0x1000>;
- interrupts = <0 53 0x04>;
- clocks = <&clks VF610_CLK_ADC0>;
- clock-names = "adc";
- fsl,adck-max-frequency = <30000000>, <40000000>,
- <20000000>;
- vref-supply = <&reg_vcc_3v3_mcu>;
-};
diff --git a/dts/Bindings/iio/amplifiers/adi,hmc425a.yaml b/dts/Bindings/iio/amplifiers/adi,hmc425a.yaml
index 5342360e96..a557761d80 100644
--- a/dts/Bindings/iio/amplifiers/adi,hmc425a.yaml
+++ b/dts/Bindings/iio/amplifiers/adi,hmc425a.yaml
@@ -33,6 +33,8 @@ required:
- compatible
- ctrl-gpios
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/gpio/gpio.h>
diff --git a/dts/Bindings/iio/chemical/atlas,sensor.yaml b/dts/Bindings/iio/chemical/atlas,sensor.yaml
index 9a89b34bdd..4646deeb6f 100644
--- a/dts/Bindings/iio/chemical/atlas,sensor.yaml
+++ b/dts/Bindings/iio/chemical/atlas,sensor.yaml
@@ -19,6 +19,8 @@ description: |
http://www.atlas-scientific.com/_files/_datasheets/_oem/pH_oem_datasheet.pdf
http://www.atlas-scientific.com/_files/_datasheets/_oem/RTD_oem_datasheet.pdf
http://www.atlas-scientific.com/_files/_datasheets/_probe/EZO_CO2_Datasheet.pdf
+ https://www.atlas-scientific.com/files/EZO_O2_datasheet.pdf
+ https://www.atlas-scientific.com/files/EZO_HUM_Datasheet.pdf
properties:
compatible:
@@ -29,6 +31,8 @@ properties:
- atlas,ph-sm
- atlas,rtd-sm
- atlas,co2-ezo
+ - atlas,o2-ezo
+ - atlas,hum-ezo
reg:
maxItems: 1
diff --git a/dts/Bindings/iio/common.yaml b/dts/Bindings/iio/common.yaml
index 97ffcb7704..f845b41d74 100644
--- a/dts/Bindings/iio/common.yaml
+++ b/dts/Bindings/iio/common.yaml
@@ -32,4 +32,6 @@ properties:
considered 'near' to the device (an object is near to the
sensor).
+additionalProperties: true
+
...
diff --git a/dts/Bindings/iio/dac/adi,ad5770r.yaml b/dts/Bindings/iio/dac/adi,ad5770r.yaml
index 82424e06be..fb2c48fc7c 100644
--- a/dts/Bindings/iio/dac/adi,ad5770r.yaml
+++ b/dts/Bindings/iio/dac/adi,ad5770r.yaml
@@ -49,6 +49,14 @@ properties:
asserted during driver probe.
maxItems: 1
+ spi-max-frequency: true
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
channel@0:
description: Represents an external channel which are
connected to the DAC. Channel 0 can act both as a current
@@ -130,6 +138,8 @@ required:
- channel@4
- channel@5
+additionalProperties: false
+
examples:
- |
spi {
diff --git a/dts/Bindings/iio/dac/lltc,ltc2632.yaml b/dts/Bindings/iio/dac/lltc,ltc2632.yaml
new file mode 100644
index 0000000000..edf804d0ac
--- /dev/null
+++ b/dts/Bindings/iio/dac/lltc,ltc2632.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/iio/dac/lltc,ltc2632.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Linear Technology LTC263x 12-/10-/8-Bit Rail-to-Rail DAC
+
+maintainers:
+ - Michael Hennerich <michael.hennerich@analog.com>
+
+description: |
+ Bindings for the Linear Technology LTC2632/2634/2636 DAC
+ Datasheet can be found here: https://www.analog.com/media/en/technical-documentation/data-sheets/LTC263[246].pdf
+
+properties:
+ compatible:
+ enum:
+ - lltc,ltc2632-l12
+ - lltc,ltc2632-l10
+ - lltc,ltc2632-l8
+ - lltc,ltc2632-h12
+ - lltc,ltc2632-h10
+ - lltc,ltc2632-h8
+ - lltc,ltc2634-l12
+ - lltc,ltc2634-l10
+ - lltc,ltc2634-l8
+ - lltc,ltc2634-h12
+ - lltc,ltc2634-h10
+ - lltc,ltc2634-h8
+ - lltc,ltc2636-l12
+ - lltc,ltc2636-l10
+ - lltc,ltc2636-l8
+ - lltc,ltc2636-h12
+ - lltc,ltc2636-h10
+ - lltc,ltc2636-h8
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 2000000
+
+ vref-supply:
+ description:
+ Phandle to the external reference voltage supply. This should
+ only be set if there is an external reference voltage connected to the VREF
+ pin. If the property is not set the internal reference is used.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ vref: regulator-vref {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-ltc2632";
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dac@0 {
+ compatible = "lltc,ltc2632";
+ reg = <0>; /* CS0 */
+ spi-max-frequency = <1000000>;
+ vref-supply = <&vref>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/dac/ltc2632.txt b/dts/Bindings/iio/dac/ltc2632.txt
deleted file mode 100644
index 1ab9570cf2..0000000000
--- a/dts/Bindings/iio/dac/ltc2632.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-Linear Technology LTC2632/2634/2636 DAC
-
-Required properties:
- - compatible: Has to contain one of the following:
- lltc,ltc2632-l12
- lltc,ltc2632-l10
- lltc,ltc2632-l8
- lltc,ltc2632-h12
- lltc,ltc2632-h10
- lltc,ltc2632-h8
- lltc,ltc2634-l12
- lltc,ltc2634-l10
- lltc,ltc2634-l8
- lltc,ltc2634-h12
- ll