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-rw-r--r--dts/Bindings/Makefile10
-rw-r--r--dts/Bindings/arm/arm,scmi.txt34
-rw-r--r--dts/Bindings/arm/bcm/brcm,bcm4908.yaml38
-rw-r--r--dts/Bindings/arm/freescale/fsl,scu.txt12
-rw-r--r--dts/Bindings/arm/fsl.yaml360
-rw-r--r--dts/Bindings/arm/idle-states.yaml2
-rw-r--r--dts/Bindings/arm/mediatek.yaml4
-rw-r--r--dts/Bindings/arm/msm/qcom,llcc.yaml1
-rw-r--r--dts/Bindings/arm/mstar/mstar,smpctrl.yaml40
-rw-r--r--dts/Bindings/arm/mstar/mstar.yaml6
-rw-r--r--dts/Bindings/arm/picoxcell.txt24
-rw-r--r--dts/Bindings/arm/renesas.yaml1
-rw-r--r--dts/Bindings/arm/rockchip.yaml23
-rw-r--r--dts/Bindings/arm/samsung/samsung-boards.yaml21
-rw-r--r--dts/Bindings/arm/stm32/st,stm32-syscon.yaml5
-rw-r--r--dts/Bindings/arm/stm32/stm32.yaml23
-rw-r--r--dts/Bindings/arm/sunxi.yaml23
-rw-r--r--dts/Bindings/arm/tegra.yaml3
-rw-r--r--dts/Bindings/arm/tegra/nvidia,tegra30-actmon.txt25
-rw-r--r--dts/Bindings/arm/vt8500.yaml3
-rw-r--r--dts/Bindings/auxdisplay/modtronix,lcd2s.yaml58
-rw-r--r--dts/Bindings/bus/allwinner,sun50i-a64-de2.yaml2
-rw-r--r--dts/Bindings/bus/baikal,bt1-axi.yaml2
-rw-r--r--dts/Bindings/bus/nvidia,tegra210-aconnect.txt44
-rw-r--r--dts/Bindings/bus/nvidia,tegra210-aconnect.yaml82
-rw-r--r--dts/Bindings/clock/adi,axi-clkgen.yaml53
-rw-r--r--dts/Bindings/clock/axi-clkgen.txt25
-rw-r--r--dts/Bindings/clock/canaan,k210-clk.yaml54
-rw-r--r--dts/Bindings/clock/fsl,flexspi-clock.yaml55
-rw-r--r--dts/Bindings/clock/imx8qxp-lpcg.yaml79
-rw-r--r--dts/Bindings/clock/ingenic,cgu.yaml2
-rw-r--r--dts/Bindings/clock/qcom,aoncc-sm8250.yaml58
-rw-r--r--dts/Bindings/clock/qcom,audiocc-sm8250.yaml58
-rw-r--r--dts/Bindings/clock/qcom,gcc-sdx55.yaml77
-rw-r--r--dts/Bindings/clock/qcom,rpmhcc.yaml2
-rw-r--r--dts/Bindings/clock/qcom,sc7180-camcc.yaml73
-rw-r--r--dts/Bindings/clock/renesas,rcar-usb2-clock-sel.txt68
-rw-r--r--dts/Bindings/clock/renesas,rcar-usb2-clock-sel.yaml100
-rw-r--r--dts/Bindings/clock/sifive/fu740-prci.yaml60
-rw-r--r--dts/Bindings/connector/usb-connector.yaml51
-rw-r--r--dts/Bindings/crypto/intel,keembay-ocs-aes.yaml45
-rw-r--r--dts/Bindings/crypto/picochip-spacc.txt21
-rw-r--r--dts/Bindings/devfreq/exynos-bus.txt71
-rw-r--r--dts/Bindings/display/bridge/analogix,anx7625.yaml95
-rw-r--r--dts/Bindings/display/bridge/anx6345.yaml2
-rw-r--r--dts/Bindings/display/bridge/intel,keembay-dsi.yaml101
-rw-r--r--dts/Bindings/display/bridge/ite,it6505.yaml2
-rw-r--r--dts/Bindings/display/bridge/lontium,lt9611.yaml5
-rw-r--r--dts/Bindings/display/bridge/lvds-codec.yaml3
-rw-r--r--dts/Bindings/display/bridge/ps8640.yaml2
-rw-r--r--dts/Bindings/display/bridge/sii902x.txt4
-rw-r--r--dts/Bindings/display/bridge/simple-bridge.yaml1
-rw-r--r--dts/Bindings/display/bridge/thine,thc63lvd1024.yaml1
-rw-r--r--dts/Bindings/display/bridge/toshiba,tc358775.yaml2
-rw-r--r--dts/Bindings/display/imx/fsl-imx-drm.txt2
-rw-r--r--dts/Bindings/display/intel,keembay-display.yaml72
-rw-r--r--dts/Bindings/display/intel,keembay-msscam.yaml43
-rw-r--r--dts/Bindings/display/mediatek/mediatek,disp.txt4
-rw-r--r--dts/Bindings/display/mediatek/mediatek,dpi.txt42
-rw-r--r--dts/Bindings/display/mediatek/mediatek,dpi.yaml98
-rw-r--r--dts/Bindings/display/msm/gpu.txt7
-rw-r--r--dts/Bindings/display/panel/abt,y030xx067a.yaml62
-rw-r--r--dts/Bindings/display/panel/novatek,nt36672a.yaml87
-rw-r--r--dts/Bindings/display/panel/panel-simple-dsi.yaml7
-rw-r--r--dts/Bindings/display/panel/panel-simple.yaml4
-rw-r--r--dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt68
-rw-r--r--dts/Bindings/display/ti/ti,am65x-dss.yaml11
-rw-r--r--dts/Bindings/display/ti/ti,j721e-dss.yaml11
-rw-r--r--dts/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml1
-rw-r--r--dts/Bindings/dma/allwinner,sun50i-a64-dma.yaml5
-rw-r--r--dts/Bindings/dma/atmel-xdma.txt3
-rw-r--r--dts/Bindings/dma/dma-common.yaml4
-rw-r--r--dts/Bindings/dma/dma-router.yaml2
-rw-r--r--dts/Bindings/dma/ingenic,dma.yaml2
-rw-r--r--dts/Bindings/dma/mtk-uart-apdma.txt1
-rw-r--r--dts/Bindings/dma/nvidia,tegra210-adma.txt56
-rw-r--r--dts/Bindings/dma/nvidia,tegra210-adma.yaml99
-rw-r--r--dts/Bindings/dma/qcom,gpi.yaml88
-rw-r--r--dts/Bindings/dma/renesas,rcar-dmac.yaml1
-rw-r--r--dts/Bindings/dma/snps,dma-spear1340.yaml10
-rw-r--r--dts/Bindings/dma/ti/k3-bcdma.yaml164
-rw-r--r--dts/Bindings/dma/ti/k3-pktdma.yaml172
-rw-r--r--dts/Bindings/edac/aspeed-sdram-edac.txt9
-rw-r--r--dts/Bindings/eeprom/at24.yaml4
-rw-r--r--dts/Bindings/eeprom/at25.yaml4
-rw-r--r--dts/Bindings/extcon/extcon-fsa9480.txt21
-rw-r--r--dts/Bindings/extcon/extcon-usbc-tusb320.yaml41
-rw-r--r--dts/Bindings/extcon/fcs,fsa880.yaml52
-rw-r--r--dts/Bindings/fsi/ibm,p9-occ.txt12
-rw-r--r--dts/Bindings/gpio/gpio-pca95xx.yaml1
-rw-r--r--dts/Bindings/gpio/gpio-xilinx.txt2
-rw-r--r--dts/Bindings/gpio/mediatek,mt7621-gpio.txt35
-rw-r--r--dts/Bindings/gpio/mediatek,mt7621-gpio.yaml72
-rw-r--r--dts/Bindings/gpio/mstar,msc313-gpio.yaml59
-rw-r--r--dts/Bindings/gpu/arm,mali-bifrost.yaml17
-rw-r--r--dts/Bindings/gpu/arm,mali-midgard.yaml17
-rw-r--r--dts/Bindings/gpu/nvidia,gk20a.txt4
-rw-r--r--dts/Bindings/hwmon/ad741x.txt15
-rw-r--r--dts/Bindings/hwmon/adi,ad741x.yaml39
-rw-r--r--dts/Bindings/hwmon/adi,adm1275.yaml57
-rw-r--r--dts/Bindings/hwmon/adi,ltc2992.yaml80
-rw-r--r--dts/Bindings/hwmon/adm1275.txt25
-rw-r--r--dts/Bindings/hwmon/ads7828.txt25
-rw-r--r--dts/Bindings/hwmon/amd,sbtsi.yaml54
-rw-r--r--dts/Bindings/hwmon/ina2xx.txt24
-rw-r--r--dts/Bindings/hwmon/moortec,mr75203.yaml2
-rw-r--r--dts/Bindings/hwmon/pwm-fan.txt28
-rw-r--r--dts/Bindings/hwmon/sensirion,shtc1.yaml4
-rw-r--r--dts/Bindings/hwmon/ti,ads7828.yaml57
-rw-r--r--dts/Bindings/hwmon/ti,ina2xx.yaml55
-rw-r--r--dts/Bindings/hwmon/ti,tmp513.yaml2
-rw-r--r--dts/Bindings/i2c/i2c-gate.txt41
-rw-r--r--dts/Bindings/i2c/i2c-gate.yaml39
-rw-r--r--dts/Bindings/i2c/i2c-ocores.txt8
-rw-r--r--dts/Bindings/i2c/i2c-omap.txt1
-rw-r--r--dts/Bindings/i2c/i2c-owl.txt29
-rw-r--r--dts/Bindings/i2c/i2c-owl.yaml62
-rw-r--r--dts/Bindings/i2c/mellanox,i2c-mlxbf.txt42
-rw-r--r--dts/Bindings/i2c/mellanox,i2c-mlxbf.yaml78
-rw-r--r--dts/Bindings/i2c/snps,designware-i2c.yaml8
-rw-r--r--dts/Bindings/i3c/mipi-i3c-hci.yaml47
-rw-r--r--dts/Bindings/iio/accel/bma180.txt35
-rw-r--r--dts/Bindings/iio/accel/bosch,bma180.yaml62
-rw-r--r--dts/Bindings/iio/accel/bosch,bma255.yaml73
-rw-r--r--dts/Bindings/iio/accel/dmard06.txt19
-rw-r--r--dts/Bindings/iio/accel/fsl,mma8452.yaml65
-rw-r--r--dts/Bindings/iio/accel/kionix,kxcjk1013.txt24
-rw-r--r--dts/Bindings/iio/accel/kionix,kxcjk1013.yaml46
-rw-r--r--dts/Bindings/iio/accel/mma8452.txt35
-rw-r--r--dts/Bindings/iio/adc/adc.txt23
-rw-r--r--dts/Bindings/iio/adc/adc.yaml42
-rw-r--r--dts/Bindings/iio/adc/adi,ad7124.yaml14
-rw-r--r--dts/Bindings/iio/adc/adi,ad7292.yaml8
-rw-r--r--dts/Bindings/iio/adc/adi,ad7768-1.yaml32
-rw-r--r--dts/Bindings/iio/adc/at91-sama5d2_adc.txt50
-rw-r--r--dts/Bindings/iio/adc/at91_adc.txt83
-rw-r--r--dts/Bindings/iio/adc/atmel,sama5d2-adc.yaml101
-rw-r--r--dts/Bindings/iio/adc/atmel,sama9260-adc.yaml121
-rw-r--r--dts/Bindings/iio/adc/axp20x_adc.txt48
-rw-r--r--dts/Bindings/iio/adc/brcm,iproc-static-adc.txt40
-rw-r--r--dts/Bindings/iio/adc/brcm,iproc-static-adc.yaml70
-rw-r--r--dts/Bindings/iio/adc/envelope-detector.txt54
-rw-r--r--dts/Bindings/iio/adc/envelope-detector.yaml86
-rw-r--r--dts/Bindings/iio/adc/lltc,ltc2496.yaml3
-rw-r--r--dts/Bindings/iio/adc/maxim,max1027.yaml65
-rw-r--r--dts/Bindings/iio/adc/mediatek,mt2701-auxadc.yaml77
-rw-r--r--dts/Bindings/iio/adc/mediatek,mt6360-adc.yaml31
-rw-r--r--dts/Bindings/iio/adc/mt6577_auxadc.txt33
-rw-r--r--dts/Bindings/iio/adc/palmas-gpadc.txt48
-rw-r--r--dts/Bindings/iio/adc/qcom,pm8018-adc.yaml166
-rw-r--r--dts/Bindings/iio/adc/qcom,pm8xxx-xoadc.txt157
-rw-r--r--dts/Bindings/iio/adc/qcom,spmi-iadc.txt46
-rw-r--r--dts/Bindings/iio/adc/qcom,spmi-iadc.yaml60
-rw-r--r--dts/Bindings/iio/adc/qcom,spmi-vadc.yaml3
-rw-r--r--dts/Bindings/iio/adc/renesas,gyroadc.txt98
-rw-r--r--dts/Bindings/iio/adc/renesas,rcar-gyroadc.yaml143
-rw-r--r--dts/Bindings/iio/adc/samsung,exynos-adc.yaml4
-rw-r--r--dts/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml7
-rw-r--r--dts/Bindings/iio/adc/ti,adc084s021.yaml58
-rw-r--r--dts/Bindings/iio/adc/ti,ads124s08.yaml52
-rw-r--r--dts/Bindings/iio/adc/ti,palmas-gpadc.yaml87
-rw-r--r--dts/Bindings/iio/adc/ti-adc084s021.txt19
-rw-r--r--dts/Bindings/iio/adc/ti-ads124s08.txt25
-rw-r--r--dts/Bindings/iio/adc/x-powers,axp209-adc.yaml67
-rw-r--r--dts/Bindings/iio/afe/current-sense-amplifier.txt26
-rw-r--r--dts/Bindings/iio/afe/current-sense-amplifier.yaml54
-rw-r--r--dts/Bindings/iio/afe/current-sense-shunt.txt41
-rw-r--r--dts/Bindings/iio/afe/current-sense-shunt.yaml64
-rw-r--r--dts/Bindings/iio/afe/voltage-divider.txt53
-rw-r--r--dts/Bindings/iio/afe/voltage-divider.yaml86
-rw-r--r--dts/Bindings/iio/chemical/bme680.txt11
-rw-r--r--dts/Bindings/iio/chemical/sensirion,sgp30.txt15
-rw-r--r--dts/Bindings/iio/dac/ad5592r.txt155
-rw-r--r--dts/Bindings/iio/dac/ad5758.txt83
-rw-r--r--dts/Bindings/iio/dac/ad7303.txt23
-rw-r--r--dts/Bindings/iio/dac/adi,ad5592r.yaml204
-rw-r--r--dts/Bindings/iio/dac/adi,ad5686.yaml57
-rw-r--r--dts/Bindings/iio/dac/adi,ad5758.yaml129
-rw-r--r--dts/Bindings/iio/dac/adi,ad7303.yaml50
-rw-r--r--dts/Bindings/iio/dac/dpot-dac.txt41
-rw-r--r--dts/Bindings/iio/dac/dpot-dac.yaml64
-rw-r--r--dts/Bindings/iio/dac/ds4424.txt20
-rw-r--r--dts/Bindings/iio/dac/fsl,vf610-dac.yaml55
-rw-r--r--dts/Bindings/iio/dac/lpc1850-dac.txt19
-rw-r--r--dts/Bindings/iio/dac/max5821.txt14
-rw-r--r--dts/Bindings/iio/dac/maxim,ds4424.yaml45
-rw-r--r--dts/Bindings/iio/dac/maxim,max5821.yaml44
-rw-r--r--dts/Bindings/iio/dac/mcp4725.txt35
-rw-r--r--dts/Bindings/iio/dac/microchip,mcp4725.yaml71
-rw-r--r--dts/Bindings/iio/dac/nxp,lpc1850-dac.yaml58
-rw-r--r--dts/Bindings/iio/dac/ti,dac5571.txt24
-rw-r--r--dts/Bindings/iio/dac/ti,dac5571.yaml52
-rw-r--r--dts/Bindings/iio/dac/ti,dac7311.txt23
-rw-r--r--dts/Bindings/iio/dac/ti,dac7311.yaml49
-rw-r--r--dts/Bindings/iio/dac/ti,dac7512.txt20
-rw-r--r--dts/Bindings/iio/dac/ti,dac7512.yaml42
-rw-r--r--dts/Bindings/iio/dac/ti,dac7612.txt28
-rw-r--r--dts/Bindings/iio/dac/ti,dac7612.yaml53
-rw-r--r--dts/Bindings/iio/dac/vf610-dac.txt20
-rw-r--r--dts/Bindings/iio/frequency/adf4350.txt86
-rw-r--r--dts/Bindings/iio/frequency/adi,adf4350.yaml190
-rw-r--r--dts/Bindings/iio/gyroscope/bmg160.txt20
-rw-r--r--dts/Bindings/iio/gyroscope/bosch,bmg160.yaml46
-rw-r--r--dts/Bindings/iio/gyroscope/nxp,fxas21002c.txt31
-rw-r--r--dts/Bindings/iio/gyroscope/nxp,fxas21002c.yaml95
-rw-r--r--dts/Bindings/iio/health/afe4403.txt33
-rw-r--r--dts/Bindings/iio/health/afe4404.txt29
-rw-r--r--dts/Bindings/iio/health/max30100.txt28
-rw-r--r--dts/Bindings/iio/health/max30102.txt33
-rw-r--r--dts/Bindings/iio/health/maxim,max30100.yaml52
-rw-r--r--dts/Bindings/iio/health/maxim,max30102.yaml72
-rw-r--r--dts/Bindings/iio/health/ti,afe4403.yaml54
-rw-r--r--dts/Bindings/iio/health/ti,afe4404.yaml51
-rw-r--r--dts/Bindings/iio/humidity/dht11.txt14
-rw-r--r--dts/Bindings/iio/humidity/dht11.yaml41
-rw-r--r--dts/Bindings/iio/humidity/hdc100x.txt17
-rw-r--r--dts/Bindings/iio/humidity/hts221.txt30
-rw-r--r--dts/Bindings/iio/humidity/htu21.txt13
-rw-r--r--dts/Bindings/iio/humidity/st,hts221.yaml54
-rw-r--r--dts/Bindings/iio/humidity/ti,hdc2010.yaml3
-rw-r--r--dts/Bindings/iio/iio-bindings.txt102
-rw-r--r--dts/Bindings/iio/impedance-analyzer/ad5933.txt26
-rw-r--r--dts/Bindings/iio/impedance-analyzer/adi,ad5933.yaml59
-rw-r--r--dts/Bindings/iio/imu/adi,adis16480.txt86
-rw-r--r--dts/Bindings/iio/imu/adi,adis16480.yaml130
-rw-r--r--dts/Bindings/iio/imu/st,lsm6dsx.yaml93
-rw-r--r--dts/Bindings/iio/imu/st_lsm6dsx.txt48
-rw-r--r--dts/Bindings/iio/light/apds9300.txt21
-rw-r--r--dts/Bindings/iio/light/apds9960.txt21
-rw-r--r--dts/Bindings/iio/light/avago,apds9300.yaml44
-rw-r--r--dts/Bindings/iio/light/avago,apds9960.yaml44
-rw-r--r--dts/Bindings/iio/light/capella,cm3605.yaml79
-rw-r--r--dts/Bindings/iio/light/capella,cm36651.yaml48
-rw-r--r--dts/Bindings/iio/light/cm3605.txt41
-rw-r--r--dts/Bindings/iio/light/cm36651.txt26
-rw-r--r--dts/Bindings/iio/light/gp2ap020a00f.txt21
-rw-r--r--dts/Bindings/iio/light/max44009.txt24
-rw-r--r--dts/Bindings/iio/light/maxim,max44009.yaml45
-rw-r--r--dts/Bindings/iio/light/opt3001.txt25
-rw-r--r--dts/Bindings/iio/light/renesas,isl29501.txt13
-rw-r--r--dts/Bindings/iio/light/sharp,gp2ap020a00f.yaml48
-rw-r--r--dts/Bindings/iio/light/st,uvis25.yaml42
-rw-r--r--dts/Bindings/iio/light/st,vl6180.yaml45
-rw-r--r--dts/Bindings/iio/light/ti,opt3001.yaml47
-rw-r--r--dts/Bindings/iio/light/upisemi,us5182.yaml78
-rw-r--r--dts/Bindings/iio/light/us5182d.txt45
-rw-r--r--dts/Bindings/iio/light/uvis25.txt22
-rw-r--r--dts/Bindings/iio/light/vcnl4035.txt18
-rw-r--r--dts/Bindings/iio/light/vishay,vcnl4035.yaml45
-rw-r--r--dts/Bindings/iio/light/vl6180.txt15
-rw-r--r--dts/Bindings/iio/magnetometer/ak8974.txt31
-rw-r--r--dts/Bindings/iio/magnetometer/asahi-kasei,ak8974.yaml57
-rw-r--r--dts/Bindings/iio/magnetometer/bmc150_magn.txt25
-rw-r--r--dts/Bindings/iio/magnetometer/bosch,bmc150_magn.yaml55
-rw-r--r--dts/Bindings/iio/magnetometer/fsl,mag3110.yaml48
-rw-r--r--dts/Bindings/iio/magnetometer/hmc5843.txt21
-rw-r--r--dts/Bindings/iio/magnetometer/honeywell,hmc5843.yaml43
-rw-r--r--dts/Bindings/iio/magnetometer/mag3110.txt27
-rw-r--r--dts/Bindings/iio/magnetometer/mmc35240.txt13
-rw-r--r--dts/Bindings/iio/magnetometer/pni,rm3100.txt20
-rw-r--r--dts/Bindings/iio/magnetometer/pni,rm3100.yaml42
-rw-r--r--dts/Bindings/iio/potentiometer/ad5272.txt27
-rw-r--r--dts/Bindings/iio/potentiometer/adi,ad5272.yaml50
-rw-r--r--dts/Bindings/iio/potentiometer/ds1803.txt21
-rw-r--r--dts/Bindings/iio/potentiometer/max5481.txt23
-rw-r--r--dts/Bindings/iio/potentiometer/mcp41010.txt28
-rw-r--r--dts/Bindings/iio/potentiometer/mcp4131.txt84
-rw-r--r--dts/Bindings/iio/potentiometer/microchip,mcp41010.yaml48
-rw-r--r--dts/Bindings/iio/potentiometer/microchip,mcp4131.yaml103
-rw-r--r--dts/Bindings/iio/potentiometer/microchip,mcp4531.yaml116
-rw-r--r--dts/Bindings/iio/potentiostat/lmp91000.txt33
-rw-r--r--dts/Bindings/iio/potentiostat/ti,lmp91000.yaml68
-rw-r--r--dts/Bindings/iio/pressure/hoperf,hp03.yaml47
-rw-r--r--dts/Bindings/iio/pressure/hp03.txt17
-rw-r--r--dts/Bindings/iio/pressure/meas,ms5611.yaml57
-rw-r--r--dts/Bindings/iio/pressure/ms5611.txt19
-rw-r--r--dts/Bindings/iio/pressure/ms5637.txt17
-rw-r--r--dts/Bindings/iio/pressure/murata,zpa2326.yaml62
-rw-r--r--dts/Bindings/iio/pressure/zpa2326.txt29
-rw-r--r--dts/Bindings/iio/proximity/ams,as3935.yaml71
-rw-r--r--dts/Bindings/iio/proximity/as3935.txt34
-rw-r--r--dts/Bindings/iio/proximity/semtech,sx9310.yaml63
-rw-r--r--dts/Bindings/iio/proximity/semtech,sx9500.yaml50
-rw-r--r--dts/Bindings/iio/proximity/st,vl53l0x.yaml42
-rw-r--r--dts/Bindings/iio/proximity/sx9500.txt23
-rw-r--r--dts/Bindings/iio/proximity/vl53l0x.txt18
-rw-r--r--dts/Bindings/iio/resolver/ad2s90.txt31
-rw-r--r--dts/Bindings/iio/resolver/adi,ad2s90.yaml60
-rw-r--r--dts/Bindings/iio/samsung,sensorhub-rinato.yaml72
-rw-r--r--dts/Bindings/iio/sensorhub.txt24
-rw-r--r--dts/Bindings/iio/st,st-sensors.yaml123
-rw-r--r--dts/Bindings/iio/st-sensors.txt82
-rw-r--r--dts/Bindings/iio/temperature/max31856.txt24
-rw-r--r--dts/Bindings/iio/temperature/maxim,max31855k.yaml76
-rw-r--r--dts/Bindings/iio/temperature/maxim,max31856.yaml54
-rw-r--r--dts/Bindings/iio/temperature/maxim_thermocouple.txt24
-rw-r--r--dts/Bindings/iio/temperature/melexis,mlx90614.yaml50
-rw-r--r--dts/Bindings/iio/temperature/melexis,mlx90632.yaml55
-rw-r--r--dts/Bindings/iio/temperature/mlx90614.txt24
-rw-r--r--dts/Bindings/iio/temperature/mlx90632.txt28
-rw-r--r--dts/Bindings/iio/temperature/temperature-bindings.txt7
-rw-r--r--dts/Bindings/iio/temperature/ti,tmp007.yaml57
-rw-r--r--dts/Bindings/iio/temperature/tmp007.txt33
-rw-r--r--dts/Bindings/iio/temperature/tsys01.txt19
-rw-r--r--dts/Bindings/input/ariel-pwrbutton.yaml57
-rw-r--r--dts/Bindings/input/atmel,maxtouch.txt41
-rw-r--r--dts/Bindings/input/atmel,maxtouch.yaml81
-rw-r--r--dts/Bindings/input/cypress,tm2-touchkey.txt33
-rw-r--r--dts/Bindings/input/cypress,tm2-touchkey.yaml73
-rw-r--r--dts/Bindings/input/dlg,da7280.txt108
-rw-r--r--dts/Bindings/input/fsl,mpr121-touchkey.yaml3
-rw-r--r--dts/Bindings/input/gpio-keys.yaml12
-rw-r--r--dts/Bindings/input/sprd,sc27xx-vibra.txt23
-rw-r--r--dts/Bindings/input/sprd,sc27xx-vibrator.yaml48
-rw-r--r--dts/Bindings/input/touchscreen/edt-ft5x06.yaml3
-rw-r--r--dts/Bindings/input/touchscreen/ektf2127.txt2
-rw-r--r--dts/Bindings/interrupt-controller/arm,gic.yaml9
-rw-r--r--dts/Bindings/interrupt-controller/fsl,ls-extirq.txt8
-rw-r--r--dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt21
-rw-r--r--dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml64
-rw-r--r--dts/Bindings/interrupt-controller/mti,gic.yaml4
-rw-r--r--dts/Bindings/interrupt-controller/ti,pruss-intc.yaml2
-rw-r--r--dts/Bindings/interrupt-controller/ti,sci-inta.yaml2
-rw-r--r--dts/Bindings/iommu/arm,smmu.yaml9
-rw-r--r--dts/Bindings/leds/backlight/common.yaml4
-rw-r--r--dts/Bindings/leds/common.yaml16
-rw-r--r--dts/Bindings/leds/leds-lp55xx.yaml10
-rw-r--r--dts/Bindings/leds/leds-pwm.txt50
-rw-r--r--dts/Bindings/leds/leds-pwm.yaml70
-rw-r--r--dts/Bindings/mailbox/arm,mhu.yaml1
-rw-r--r--dts/Bindings/mailbox/arm,mhuv2.yaml209
-rw-r--r--dts/Bindings/media/allwinner,sun4i-a10-video-engine.yaml2
-rw-r--r--dts/Bindings/media/amlogic,axg-ge2d.yaml47
-rw-r--r--dts/Bindings/media/coda.txt31
-rw-r--r--dts/Bindings/media/coda.yaml108
-rw-r--r--dts/Bindings/media/i2c/adv7604.txt88
-rw-r--r--dts/Bindings/media/i2c/adv7604.yaml178
-rw-r--r--dts/Bindings/media/i2c/aptina,mt9v111.txt46
-rw-r--r--dts/Bindings/media/i2c/aptina,mt9v111.yaml75
-rw-r--r--dts/Bindings/media/i2c/maxim,max9286.yaml1
-rw-r--r--dts/Bindings/media/i2c/mipi-ccs.yaml133
-rw-r--r--dts/Bindings/media/i2c/nokia,smia.txt66
-rw-r--r--dts/Bindings/media/i2c/ov2680.txt46
-rw-r--r--dts/Bindings/media/i2c/ov772x.txt40
-rw-r--r--dts/Bindings/media/i2c/ovti,ov02a10.yaml159
-rw-r--r--dts/Bindings/media/i2c/ovti,ov2680.yaml99
-rw-r--r--dts/Bindings/media/i2c/ovti,ov772x.yaml134
-rw-r--r--dts/Bindings/media/i2c/sony,imx214.txt53
-rw-r--r--dts/Bindings/media/i2c/sony,imx214.yaml130
-rw-r--r--dts/Bindings/media/i2c/sony,imx274.yaml3
-rw-r--r--dts/Bindings/media/imx7-csi.txt42
-rw-r--r--dts/Bindings/media/imx7-mipi-csi2.txt90
-rw-r--r--dts/Bindings/media/nxp,imx7-csi.yaml71
-rw-r--r--dts/Bindings/media/nxp,imx7-mipi-csi2.yaml173
-rw-r--r--dts/Bindings/media/qcom,camss.txt7
-rw-r--r--dts/Bindings/media/rc.yaml2
-rw-r--r--dts/Bindings/media/rockchip-isp1.yaml215
-rw-r--r--dts/Bindings/media/st,stm32-dcmi.yaml38
-rw-r--r--dts/Bindings/memory-controllers/mediatek,smi-common.txt50
-rw-r--r--dts/Bindings/memory-controllers/mediatek,smi-common.yaml142
-rw-r--r--dts/Bindings/memory-controllers/mediatek,smi-larb.txt50
-rw-r--r--dts/Bindings/memory-controllers/mediatek,smi-larb.yaml132
-rw-r--r--dts/Bindings/memory-controllers/nvidia,tegra124-emc.yaml19
-rw-r--r--dts/Bindings/memory-controllers/nvidia,tegra124-mc.yaml5
-rw-r--r--dts/Bindings/memory-controllers/nvidia,tegra20-emc.txt28
-rw-r--r--dts/Bindings/memory-controllers/nvidia,tegra20-mc.txt3
-rw-r--r--dts/Bindings/memory-controllers/nvidia,tegra30-emc.yaml18
-rw-r--r--dts/Bindings/memory-controllers/nvidia,tegra30-mc.yaml5
-rw-r--r--dts/Bindings/mfd/aspeed-lpc.txt8
-rw-r--r--dts/Bindings/mfd/aspeed-scu.txt26
-rw-r--r--dts/Bindings/mfd/rohm,bd71837-pmic.yaml6
-rw-r--r--dts/Bindings/mfd/st,stm32-timers.yaml6
-rw-r--r--dts/Bindings/mfd/st,stmfx.yaml3
-rw-r--r--dts/Bindings/mfd/syscon.yaml4
-rw-r--r--dts/Bindings/mips/mscc.txt2
-rw-r--r--dts/Bindings/misc/fsl,dpaa2-console.txt11
-rw-r--r--dts/Bindings/misc/fsl,dpaa2-console.yaml25
-rw-r--r--dts/Bindings/mmc/arasan,sdhci.yaml2
-rw-r--r--dts/Bindings/mmc/fsl-imx-esdhc.yaml1
-rw-r--r--dts/Bindings/mmc/mtk-sd.txt75
-rw-r--r--dts/Bindings/mmc/mtk-sd.yaml176
-rw-r--r--dts/Bindings/mmc/owl-mmc.yaml4
-rw-r--r--dts/Bindings/mtd/gpmi-nand.yaml76
-rw-r--r--dts/Bindings/mtd/intel,lgm-nand.yaml99
-rw-r--r--dts/Bindings/mtd/nand-controller.yaml11
-rw-r--r--dts/Bindings/mtd/partition.txt131
-rw-r--r--dts/Bindings/mtd/partitions/fixed-partitions.yaml152
-rw-r--r--dts/Bindings/mtd/qcom_nandc.txt4
-rw-r--r--dts/Bindings/mtd/rockchip,nand-controller.yaml161
-rw-r--r--dts/Bindings/net/allwinner,sun8i-a83t-emac.yaml6
-rw-r--r--dts/Bindings/net/amlogic,meson-dwmac.yaml2
-rw-r--r--dts/Bindings/net/can/fsl,flexcan.yaml5
-rw-r--r--dts/Bindings/net/dsa/b53.txt149
-rw-r--r--dts/Bindings/net/dsa/brcm,b53.yaml249
-rw-r--r--dts/Bindings/net/dsa/dsa.yaml12
-rw-r--r--dts/Bindings/net/dsa/hirschmann,hellcreek.yaml127
-rw-r--r--dts/Bindings/net/dsa/ksz.txt125
-rw-r--r--dts/Bindings/net/dsa/microchip,ksz.yaml148
-rw-r--r--dts/Bindings/net/ethernet-controller.yaml25
-rw-r--r--dts/Bindings/net/ethernet-phy.yaml20
-rw-r--r--dts/Bindings/net/fsl,qoriq-mc-dpmac.yaml60
-rw-r--r--dts/Bindings/net/ftgmac100.txt25
-rw-r--r--dts/Bindings/net/macb.txt4
-rw-r--r--dts/Bindings/net/mdio.yaml2
-rw-r--r--dts/Bindings/net/mediatek,star-emac.yaml2
-rw-r--r--dts/Bindings/net/nfc/nxp-nci.txt2
-rw-r--r--dts/Bindings/net/nfc/samsung,s3fwrn5.yaml33
-rw-r--r--dts/Bindings/net/qcom,ipa.yaml3
-rw-r--r--dts/Bindings/net/snps,dwmac.yaml38
-rw-r--r--dts/Bindings/net/socionext,uniphier-ave4.yaml2
-rw-r--r--dts/Bindings/net/ti,cpsw-switch.yaml2
-rw-r--r--dts/Bindings/net/ti,dp83867.yaml12
-rw-r--r--dts/Bindings/net/ti,dp83869.yaml8
-rw-r--r--dts/Bindings/net/ti,k3-am654-cpsw-nuss.yaml4
-rw-r--r--dts/Bindings/net/wireless/qcom,ath11k.yaml8
-rw-r--r--dts/Bindings/nvmem/mtk-efuse.txt1
-rw-r--r--dts/Bindings/nvmem/qcom,qfprom.yaml17
-rw-r--r--dts/Bindings/opp/opp.txt54
-rw-r--r--dts/Bindings/pci/cdns-pcie-ep.yaml3
-rw-r--r--dts/Bindings/pci/qcom,pcie.txt6
-rw-r--r--dts/Bindings/pci/rcar-pci-ep.yaml9
-rw-r--r--dts/Bindings/pci/rcar-pci-host.yaml115
-rw-r--r--dts/Bindings/pci/rcar-pci.txt72
-rw-r--r--dts/Bindings/pci/samsung,exynos-pcie.yaml119
-rw-r--r--dts/Bindings/pci/samsung,exynos5440-pcie.txt58
-rw-r--r--dts/Bindings/pci/ti,j721e-pci-ep.yaml23
-rw-r--r--dts/Bindings/pci/ti,j721e-pci-host.yaml27
-rw-r--r--dts/Bindings/perf/fsl-imx-ddr.yaml3
-rw-r--r--dts/Bindings/phy/amlogic,axg-mipi-dphy.yaml70
-rw-r--r--dts/Bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml21
-rw-r--r--dts/Bindings/phy/brcm,sata-phy.yaml148
-rw-r--r--dts/Bindings/phy/brcm-sata-phy.txt58
-rw-r--r--dts/Bindings/phy/ingenic,phy-usb.yaml (renamed from dts/Bindings/usb/ingenic,jz4770-phy.yaml)4
-rw-r--r--dts/Bindings/phy/intel,phy-keembay-usb.yaml44
-rw-r--r--dts/Bindings/phy/marvell,mmp3-hsic-phy.yaml9
-rw-r--r--dts/Bindings/phy/mediatek,mt7621-pci-phy.yaml36
-rw-r--r--dts/Bindings/phy/phy-cadence-sierra.txt70
-rw-r--r--dts/Bindings/phy/phy-cadence-sierra.yaml152
-rw-r--r--dts/Bindings/phy/phy-stm32-usbphyc.txt73
-rw-r--r--dts/Bindings/phy/phy-stm32-usbphyc.yaml138
-rw-r--r--dts/Bindings/phy/qcom,qmp-phy.yaml6
-rw-r--r--dts/Bindings/phy/rockchip-emmc-phy.txt5
-rw-r--r--dts/Bindings/phy/samsung,exynos-pcie-phy.yaml51
-rw-r--r--dts/Bindings/phy/samsung-phy.txt1
-rw-r--r--dts/Bindings/phy/ti,omap-usb2.yaml4
-rw-r--r--dts/Bindings/pinctrl/microchip,sparx5-sgpio.yaml161
-rw-r--r--dts/Bindings/pinctrl/mscc,ocelot-pinctrl.txt3
-rw-r--r--dts/Bindings/pinctrl/nvidia,tegra194-pinmux.txt2
-rw-r--r--dts/Bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml130
-rw-r--r--dts/Bindings/pinctrl/qcom,msm8953-pinctrl.yaml167
-rw-r--r--dts/Bindings/pinctrl/qcom,pmic-gpio.txt3
-rw-r--r--dts/Bindings/pinctrl/qcom,sc7280-pinctrl.yaml158
-rw-r--r--dts/Bindings/pinctrl/qcom,sdx55-pinctrl.yaml154
-rw-r--r--dts/Bindings/pinctrl/ralink,rt2880-pinmux.yaml70
-rw-r--r--dts/Bindings/power/mediatek,power-controller.yaml293
-rw-r--r--dts/Bindings/power/qcom,rpmpd.yaml4
-rw-r--r--dts/Bindings/power/reset/ocelot-reset.txt4
-rw-r--r--dts/Bindings/power/reset/regulator-poweroff.yaml37
-rw-r--r--dts/Bindings/power/supply/cw2015_battery.yaml2
-rw-r--r--dts/Bindings/powerpc/sleep.yaml2
-rw-r--r--dts/Bindings/pwm/atmel-tcb-pwm.txt16
-rw-r--r--dts/Bindings/pwm/intel,keembay-pwm.yaml47
-rw-r--r--dts/Bindings/pwm/intel,lgm-pwm.yaml44
-rw-r--r--dts/Bindings/pwm/pwm-mediatek.txt1
-rw-r--r--dts/Bindings/pwm/pwm-mtk-disp.txt1
-rw-r--r--dts/Bindings/regulator/anatop-regulator.yaml1
-rw-r--r--dts/Bindings/regulator/dlg,da9121.yaml189
-rw-r--r--dts/Bindings/regulator/fixed-regulator.yaml47
-rw-r--r--dts/Bindings/regulator/mcp16502-regulator.txt2
-rw-r--r--dts/Bindings/regulator/nxp,pf8x00-regulator.yaml211
-rw-r--r--dts/Bindings/regulator/qcom,rpmh-regulator.txt6
-rw-r--r--dts/Bindings/regulator/rohm,bd71837-regulator.yaml48
-rw-r--r--dts/Bindings/regulator/rohm,bd71847-regulator.yaml49
-rw-r--r--dts/Bindings/remoteproc/qcom,q6v5.txt12
-rw-r--r--dts/Bindings/remoteproc/qcom,wcnss-pil.txt20
-rw-r--r--dts/Bindings/remoteproc/st,stm32-rproc.yaml21
-rw-r--r--dts/Bindings/remoteproc/ti,k3-r5f-rproc.yaml2
-rw-r--r--dts/Bindings/remoteproc/ti,pru-rproc.yaml214
-rw-r--r--dts/Bindings/reset/brcm,bcm6345-reset.yaml37
-rw-r--r--dts/Bindings/reset/snps,dw-reset.txt2
-rw-r--r--dts/Bindings/rtc/rtc.yaml5
-rw-r--r--dts/Bindings/serial/8250.yaml6
-rw-r--r--dts/Bindings/serial/litex,liteuart.yaml40
-rw-r--r--dts/Bindings/serial/omap_serial.txt1
-rw-r--r--dts/Bindings/serial/renesas,scif.yaml1
-rw-r--r--dts/Bindings/serial/sifive-serial.yaml4
-rw-r--r--dts/Bindings/soc/litex/litex,soc-controller.yaml41
-rw-r--r--dts/Bindings/soc/mediatek/devapc.yaml60
-rw-r--r--dts/Bindings/soc/microchip/atmel,at91rm9200-tcb.yaml34
-rw-r--r--dts/Bindings/soc/ti/k3-ringacc.yaml2
-rw-r--r--dts/Bindings/soc/xilinx/xlnx,vcu-settings.yaml43
-rw-r--r--dts/Bindings/soc/xilinx/xlnx,vcu.txt9
-rw-r--r--dts/Bindings/sound/adi,adau1372.yaml67
-rw-r--r--dts/Bindings/sound/adi,adau1977.txt61
-rw-r--r--dts/Bindings/sound/adi,adau1977.yaml92
-rw-r--r--dts/Bindings/sound/allwinner,sun4i-a10-codec.yaml2
-rw-r--r--dts/Bindings/sound/allwinner,sun4i-a10-i2s.yaml6
-rw-r--r--dts/Bindings/sound/audio-graph-card.txt337
-rw-r--r--dts/Bindings/sound/audio-graph-card.yaml57
-rw-r--r--dts/Bindings/sound/audio-graph-port.yaml84
-rw-r--r--dts/Bindings/sound/audio-graph.yaml45
-rw-r--r--dts/Bindings/sound/fsl,aud2htx.yaml66
-rw-r--r--dts/Bindings/sound/fsl,spdif.yaml1
-rw-r--r--dts/Bindings/sound/fsl,xcvr.yaml104
-rw-r--r--dts/Bindings/sound/fsl-asoc-card.txt2
-rw-r--r--dts/Bindings/sound/google,sc7180-trogdor.yaml138
-rw-r--r--dts/Bindings/sound/imx-audio-hdmi.yaml52
-rw-r--r--dts/Bindings/sound/marvell,mmp-sspa.yaml25
-rw-r--r--dts/Bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml44
-rw-r--r--dts/Bindings/sound/nau8315.txt18
-rw-r--r--dts/Bindings/sound/nvidia,tegra30-hda.txt35
-rw-r--r--dts/Bindings/sound/nvidia,tegra30-hda.yaml110
-rw-r--r--dts/Bindings/sound/qcom,lpass-va-macro.yaml67
-rw-r--r--dts/Bindings/sound/qcom,lpass-wsa-macro.yaml69
-rw-r--r--dts/Bindings/sound/qcom,sm8250.yaml159
-rw-r--r--dts/Bindings/sound/renesas,rsnd.txt520
-rw-r--r--dts/Bindings/sound/renesas,rsnd.yaml447
-rw-r--r--dts/Bindings/sound/rt5682.txt2
-rw-r--r--dts/Bindings/sound/simple-audio-mux.yaml41
-rw-r--r--dts/Bindings/sound/simple-card.yaml6
-rw-r--r--dts/Bindings/sound/st,stm32-adfsdm.txt63
-rw-r--r--dts/Bindings/sound/st,stm32-sai.txt107
-rw-r--r--dts/Bindings/sound/st,stm32-sai.yaml200
-rw-r--r--dts/Bindings/spi/snps,dw-apb-ssi.yaml2
-rw-r--r--dts/Bindings/spi/spi-controller.yaml27
-rw-r--r--dts/Bindings/spi/spi-sifive.yaml10
-rw-r--r--dts/Bindings/submitting-patches.rst3
-rw-r--r--dts/Bindings/thermal/mediatek-thermal.txt3
-rw-r--r--dts/Bindings/thermal/rcar-gen3-thermal.yaml17
-rw-r--r--dts/Bindings/thermal/rcar-thermal.yaml48
-rw-r--r--dts/Bindings/timer/renesas,tmu.txt49
-rw-r--r--dts/Bindings/timer/renesas,tmu.yaml99
-rw-r--r--dts/Bindings/timer/snps,dw-apb-timer.yaml7
-rw-r--r--dts/Bindings/trivial-devices.yaml206
-rw-r--r--dts/Bindings/usb/brcm,usb-pinmap.yaml70
-rw-r--r--dts/Bindings/usb/cdns,usb3.yaml5
-rw-r--r--dts/Bindings/usb/maxim,max33359.yaml75
-rw-r--r--dts/Bindings/usb/renesas,usb-xhci.yaml1
-rw-r--r--dts/Bindings/usb/renesas,usbhs.yaml3
-rw-r--r--dts/Bindings/usb/st,stusb160x.yaml87
-rw-r--r--dts/Bindings/vendor-prefixes.yaml48
-rw-r--r--dts/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml3
-rw-r--r--dts/Bindings/watchdog/fsl-imx-wdt.yaml16
-rw-r--r--dts/Bindings/watchdog/snps,dw-wdt.yaml10
544 files changed, 19348 insertions, 7109 deletions
diff --git a/dts/Bindings/Makefile b/dts/Bindings/Makefile
index f50420099a..8f2b054bec 100644
--- a/dts/Bindings/Makefile
+++ b/dts/Bindings/Makefile
@@ -27,17 +27,17 @@ find_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
-name '*.example.dt.yaml' \)
quiet_cmd_yamllint = LINT $(src)
- cmd_yamllint = $(find_cmd) | \
- xargs $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint
+ cmd_yamllint = ($(find_cmd) | \
+ xargs $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint) || true
quiet_cmd_chk_bindings = CHKDT $@
- cmd_chk_bindings = $(find_cmd) | \
- xargs -n200 -P$$(nproc) $(DT_DOC_CHECKER) -u $(srctree)/$(src)
+ cmd_chk_bindings = ($(find_cmd) | \
+ xargs -n200 -P$$(nproc) $(DT_DOC_CHECKER) -u $(srctree)/$(src)) || true
quiet_cmd_mk_schema = SCHEMA $@
cmd_mk_schema = f=$$(mktemp) ; \
$(if $(DT_MK_SCHEMA_FLAGS), \
- echo $(real-prereqs), \
+ printf '%s\n' $(real-prereqs), \
$(find_cmd)) > $$f ; \
$(DT_MK_SCHEMA) -j $(DT_MK_SCHEMA_FLAGS) @$$f > $@ ; \
rm -f $$f
diff --git a/dts/Bindings/arm/arm,scmi.txt b/dts/Bindings/arm/arm,scmi.txt
index 55deb68230..b5ce5b39bb 100644
--- a/dts/Bindings/arm/arm,scmi.txt
+++ b/dts/Bindings/arm/arm,scmi.txt
@@ -62,6 +62,20 @@ Required properties:
- #power-domain-cells : Should be 1. Contains the device or the power
domain ID value used by SCMI commands.
+Regulator bindings for the SCMI Regulator based on SCMI Message Protocol
+------------------------------------------------------------
+An SCMI Regulator is permanently bound to a well defined SCMI Voltage Domain,
+and should be always positioned as a root regulator.
+It does not support any current operation.
+
+SCMI Regulators are grouped under a 'regulators' node which in turn is a child
+of the SCMI Voltage protocol node inside the desired SCMI instance node.
+
+This binding uses the common regulator binding[6].
+
+Required properties:
+ - reg : shall identify an existent SCMI Voltage Domain.
+
Sensor bindings for the sensors based on SCMI Message Protocol
--------------------------------------------------------------
SCMI provides an API to access the various sensors on the SoC.
@@ -105,6 +119,7 @@ Required sub-node properties:
[3] Documentation/devicetree/bindings/thermal/thermal*.yaml
[4] Documentation/devicetree/bindings/sram/sram.yaml
[5] Documentation/devicetree/bindings/reset/reset.txt
+[6] Documentation/devicetree/bindings/regulator/regulator.yaml
Example:
@@ -169,6 +184,25 @@ firmware {
reg = <0x16>;
#reset-cells = <1>;
};
+
+ scmi_voltage: protocol@17 {
+ reg = <0x17>;
+
+ regulators {
+ regulator_devX: regulator@0 {
+ reg = <0x0>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ regulator_devY: regulator@9 {
+ reg = <0x9>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <4200000>;
+ };
+
+ ...
+ };
+ };
};
};
diff --git a/dts/Bindings/arm/bcm/brcm,bcm4908.yaml b/dts/Bindings/arm/bcm/brcm,bcm4908.yaml
new file mode 100644
index 0000000000..5fec063d9a
--- /dev/null
+++ b/dts/Bindings/arm/bcm/brcm,bcm4908.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm4908.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM4908 device tree bindings
+
+description:
+ Broadcom BCM4906 / BCM4908 / BCM49408 Wi-Fi/network SoCs with Brahma CPUs.
+
+maintainers:
+ - Rafał Miłecki <rafal@milecki.pl>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: BCM4906 based boards
+ items:
+ - const: brcm,bcm4906
+ - const: brcm,bcm4908
+
+ - description: BCM4908 based boards
+ items:
+ - enum:
+ - asus,gt-ac5300
+ - const: brcm,bcm4908
+
+ - description: BCM49408 based boards
+ items:
+ - const: brcm,bcm49408
+ - const: brcm,bcm4908
+
+additionalProperties: true
+
+...
diff --git a/dts/Bindings/arm/freescale/fsl,scu.txt b/dts/Bindings/arm/freescale/fsl,scu.txt
index 6064d98b10..395359dc94 100644
--- a/dts/Bindings/arm/freescale/fsl,scu.txt
+++ b/dts/Bindings/arm/freescale/fsl,scu.txt
@@ -89,7 +89,10 @@ Required properties:
"fsl,imx8qm-clock"
"fsl,imx8qxp-clock"
followed by "fsl,scu-clk"
-- #clock-cells: Should be 1. Contains the Clock ID value.
+- #clock-cells: Should be either
+ 2: Contains the Resource and Clock ID value.
+ or
+ 1: Contains the Clock ID value. (DEPRECATED)
- clocks: List of clock specifiers, must contain an entry for
each required entry in clock-names
- clock-names: Should include entries "xtal_32KHz", "xtal_24MHz"
@@ -208,7 +211,7 @@ firmware {
clk: clk {
compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
- #clock-cells = <1>;
+ #clock-cells = <2>;
};
iomuxc {
@@ -263,8 +266,7 @@ serial@5a060000 {
...
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
- clocks = <&clk IMX8QXP_UART0_CLK>,
- <&clk IMX8QXP_UART0_IPG_CLK>;
- clock-names = "per", "ipg";
+ clocks = <&uart0_clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
+ clock-names = "ipg";
power-domains = <&pd IMX_SC_R_UART_0>;
};
diff --git a/dts/Bindings/arm/fsl.yaml b/dts/Bindings/arm/fsl.yaml
index 934289446a..34000f7fbe 100644
--- a/dts/Bindings/arm/fsl.yaml
+++ b/dts/Bindings/arm/fsl.yaml
@@ -33,16 +33,57 @@ properties:
items:
- enum:
- fsl,imx25-pdk
+ - karo,imx25-tx25
- const: fsl,imx25
- - description: i.MX27 Product Development Kit
+ - description: i.MX25 Eukrea CPUIMX25 Boards
+ items:
+ - enum:
+ - eukrea,mbimxsd25-baseboard # Eukrea MBIMXSD25
+ - const: eukrea,cpuimx25
+ - const: fsl,imx25
+
+ - description: i.MX25 Eukrea MBIMXSD25 Boards
+ items:
+ - enum:
+ - eukrea,mbimxsd25-baseboard-cmo-qvga
+ - eukrea,mbimxsd25-baseboard-dvi-svga
+ - eukrea,mbimxsd25-baseboard-dvi-vga
+ - const: eukrea,mbimxsd25-baseboard
+ - const: eukrea,cpuimx25
+ - const: fsl,imx25
+
+ - description: i.MX27 based Boards
items:
- enum:
- armadeus,imx27-apf27 # APF27 SoM
- - armadeus,imx27-apf27dev # APF27 SoM on APF27Dev board
- fsl,imx27-pdk
- const: fsl,imx27
+ - description: i.MX27 APF27 SoM Board
+ items:
+ - const: armadeus,imx27-apf27dev
+ - const: armadeus,imx27-apf27
+ - const: fsl,imx27
+
+ - description: i.MX27 Eukrea CPUIMX27 SoM Board
+ items:
+ - const: eukrea,mbimxsd27-baseboard
+ - const: eukrea,cpuimx27
+ - const: fsl,imx27
+
+ - description: i.MX27 Phytec pca100 Board
+ items:
+ - const: phytec,imx27-pca100-rdk
+ - const: phytec,imx27-pca100
+ - const: fsl,imx27
+
+ - description: i.MX27 Phytec pcm970 Board
+ items:
+ - const: phytec,imx27-pcm970
+ - const: phytec,imx27-pcm038
+ - const: fsl,imx27
+
- description: i.MX28 based Boards
items:
- enum:
@@ -88,13 +129,33 @@ properties:
- kobo,aura
- const: fsl,imx50
- - description: i.MX51 Babbage Board
+ - description: i.MX51 based Boards
items:
- enum:
- - armadeus,imx51-apf51 # APF51 SoM
- - armadeus,imx51-apf51dev # APF51 SoM on APF51Dev board
+ - armadeus,imx51-apf51 # Armadeus Systems APF51 module
- fsl,imx51-babbage
- technologic,imx51-ts4800
+ - zii,imx51-scu3-esb
+ - zii,imx51-scu2-mezz
+ - zii,imx51-rdu1
+ - const: fsl,imx51
+
+ - description: i.MX51 based Armadeus Systems APF51Dev Board
+ items:
+ - const: armadeus,imx51-apf51dev
+ - const: armadeus,imx51-apf51
+ - const: fsl,imx51
+
+ - description: i.MX51 based Digi ConnectCore CC(W)-MX51 JSK Board
+ items:
+ - const: digi,connectcore-ccxmx51-jsk
+ - const: digi,connectcore-ccxmx51-som
+ - const: fsl,imx51
+
+ - description: i.MX51 based Eukrea CPUIMX51 Board
+ items:
+ - const: eukrea,mbimxsd51
+ - const: eukrea,cpuimx51
- const: fsl,imx51
- description: i.MX53 based Boards
@@ -104,36 +165,111 @@ properties:
- fsl,imx53-ard
- fsl,imx53-evk
- fsl,imx53-qsb
+ - fsl,imx53-qsrb # Freescale i.MX53 Quick Start-R Board
- fsl,imx53-smd
+ - ge,imx53-cpuvo # General Electric CS ONE
+ - inversepath,imx53-usbarmory # Inverse Path USB armory
+ - karo,tx53 # Ka-Ro electronics TX53 module
+ - kiebackpeter,imx53-ddc # K+P imx53 DDC
+ - kiebackpeter,imx53-hsc # K+P imx53 HSC
- menlo,m53menlo
+ - voipac,imx53-dmm-668 # Voipac i.MX53 X53-DMM-668
+ - const: fsl,imx53
+
+ - description: i.MX53 based Aries/DENX M53EVK Board
+ items:
+ - const: aries,imx53-m53evk
+ - const: denx,imx53-m53evk
+ - const: fsl,imx53
+
+ - description: i.MX53 based TQ MBa53 Board
+ items:
+ - const: tq,mba53
+ - const: tq,tqma53
- const: fsl,imx53
- description: i.MX6Q based Boards
items:
- enum:
- - armadeus,imx6q-apf6 # APF6 (Quad/Dual) SoM
- - armadeus,imx6q-apf6dev # APF6 (Quad/Dual) SoM on APF6Dev board
+ - auvidea,h100 # Auvidea H100
+ - boundary,imx6q-nitrogen6_max
+ - boundary,imx6q-nitrogen6_som2
+ - boundary,imx6q-nitrogen6x
+ - compulab,cm-fx6 # CompuLab CM-FX6
+ - dmo,imx6q-edmqmx6 # Data Modul eDM-QMX6 Board
+ - embest,imx6q-marsboard # Embest MarS Board i.MX6Dual
- emtrion,emcon-mx6 # emCON-MX6D or emCON-MX6Q SoM
- emtrion,emcon-mx6-avari # emCON-MX6D or emCON-MX6Q SoM on Avari Base
+ - engicam,imx6-icore # Engicam i.CoreM6 Starter Kit
+ - engicam,imx6-icore-rqs # Engicam i.CoreM6 RQS Starter Kit
- fsl,imx6q-arm2
- fsl,imx6q-sabreauto
- fsl,imx6q-sabrelite
- fsl,imx6q-sabresd
+ - karo,imx6q-tx6q # Ka-Ro electronics TX6Q Modules
+ - kiebackpeter,imx6q-tpc # K+P i.MX6 Quad TPC Board
- kontron,imx6q-samx6i # Kontron i.MX6 Dual/Quad SMARC Module
+ - kosagi,imx6q-novena # Kosagi Novena Dual/Quad
- logicpd,imx6q-logicpd
+ - lwn,display5 # Liebherr Display5 i.MX6 Quad Board
+ - lwn,mccmon6 # Liebherr Monitor6 i.MX6 Quad Board
+ - nutsboard,imx6q-pistachio # NutsBoard i.MX6 Quad Pistachio
+ - microsys,sbc6x # MicroSys sbc6x board
+ - poslab,imx6q-savageboard # Poslab SavageBoard Quad
- prt,prti6q # Protonic PRTI6Q board
- prt,prtwd2 # Protonic WD2 board
+ - rex,imx6q-rex-pro # Rex Pro i.MX6 Quad Board
+ - solidrun,cubox-i/q # SolidRun Cubox-i Dual/Quad
+ - solidrun,hummingboard/q
+ - solidrun,hummingboard2/q
+ - tbs,imx6q-tbs2910 # TBS2910 Matrix ARM mini PC
- technexion,imx6q-pico-dwarf # TechNexion i.MX6Q Pico-Dwarf
- technexion,imx6q-pico-hobbit # TechNexion i.MX6Q Pico-Hobbit
- technexion,imx6q-pico-nymph # TechNexion i.MX6Q Pico-Nymph
- technexion,imx6q-pico-pi # TechNexion i.MX6Q Pico-Pi
- technologic,imx6q-ts4900
- technologic,imx6q-ts7970
- - toradex,apalis_imx6q # Apalis iMX6 Module
- - toradex,apalis_imx6q-eval # Apalis iMX6 Module on Apalis Evaluation Board
- - toradex,apalis_imx6q-ixora # Apalis iMX6 Module on Ixora
- - toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6 Module on Ixora V1.1
+ - toradex,apalis_imx6q # Apalis iMX6 Module
+ - udoo,imx6q-udoo # Udoo i.MX6 Quad Board
+ - uniwest,imx6q-evi # Uniwest Evi
- variscite,dt6customboard
+ - wand,imx6q-wandboard # Wandboard i.MX6 Quad Board
+ - zealz,imx6q-gk802 # Zealz GK802
+ - zii,imx6q-zii-rdu2 # ZII RDU2 Board
+ - const: fsl,imx6q
+
+ - description: i.MX6Q Advantech DMS-BA16 Boards
+ items:
+ - enum:
+ - advantech,imx6q-dms-ba16 # Advantech DMS-BA16
+ - ge,imx6q-b450v3 # General Electric B450v3
+ - ge,imx6q-b650v3 # General Electric B650v3
+ - ge,imx6q-b850v3 # General Electric B850v3
+ - const: advantech,imx6q-ba16
+ - const: fsl,imx6q
+
+ - description: i.MX6Q Armadeus APF6 Boards
+ items:
+ - const: armadeus,imx6q-apf6dev
+ - const: armadeus,imx6q-apf6
+ - const: fsl,imx6q
+
+ - description: i.MX6Q CompuLab Utilite Pro Board
+ items:
+ - const: compulab,utilite-pro
+ - const: compulab,cm-fx6
+ - const: fsl,imx6q
+
+ - description: i.MX6Q DFI FS700-M60-6QD Board
+ items:
+ - const: dfi,fs700-m60-6qd
+ - const: dfi,fs700e-m60
+ - const: fsl,imx6q
+
+ - description: i.MX6Q DHCOM Premium Developer Kit Board
+ items:
+ - const: dh,imx6q-dhcom-pdk2
+ - const: dh,imx6q-dhcom-som
- const: fsl,imx6q
- description: i.MX6Q Gateworks Ventana Boards
@@ -172,11 +308,32 @@ properties:
- const: phytec,imx6q-pfla02 # PHYTEC phyFLEX-i.MX6 Quad
- const: fsl,imx6q
+ - description: i.MX6Q Boards with Toradex Apalis iMX6Q/D Module
+ items:
+ - enum:
+ - toradex,apalis_imx6q-ixora # Apalis iMX6Q/D Module on Ixora Carrier Board
+ - toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board
+ - const: toradex,apalis_imx6q
+ - const: fsl,imx6q
+
+ - description: i.MX6Q Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.1
+ items:
+ - const: toradex,apalis_imx6q-ixora-v1.1
+ - const: toradex,apalis_imx6q-ixora
+ - const: toradex,apalis_imx6q
+ - const: fsl,imx6q
+
- description: i.MX6QP based Boards
items:
- enum:
+ - boundary,imx6qp-nitrogen6_max
+ - boundary,imx6qp-nitrogen6_som2
- fsl,imx6qp-sabreauto # i.MX6 Quad Plus SABRE Automotive Board
- fsl,imx6qp-sabresd # i.MX6 Quad Plus SABRE Smart Device Board
+ - karo,imx6qp-tx6qp # Ka-Ro electronics TX6QP-8037 Module
+ - prt,prtwd3 # Protonic WD3 board
+ - wand,imx6qp-wandboard # Wandboard i.MX6 QuadPlus Board
+ - zii,imx6qp-zii-rdu2 # ZII RDU2+ Board
- const: fsl,imx6qp
- description: i.MX6QP PHYTEC phyBOARD-Mira
@@ -189,32 +346,59 @@ properties:
- description: i.MX6DL based Boards
items:
- enum:
- - armadeus,imx6dl-apf6 # APF6 (Solo) SoM
- - armadeus,imx6dl-apf6dev # APF6 (Solo) SoM on APF6Dev board
+ - abb,aristainetos-imx6dl-4 # aristainetos i.MX6 Dual Lite Board 4
+ - abb,aristainetos-imx6dl-7 # aristainetos i.MX6 Dual Lite Board 7
+ - abb,aristainetos2-imx6dl-4 # aristainetos2 i.MX6 Dual Lite Board 4
+ - abb,aristainetos2-imx6dl-7 # aristainetos2 i.MX6 Dual Lite Board 7
+ - alt,alti6p # Altesco I6P Board
+ - boundary,imx6dl-nit6xlite # Boundary Devices Nitrogen6 Lite
+ - boundary,imx6dl-nitrogen6x # Boundary Devices Nitrogen6x
+ - bticino,imx6dl-mamoj # BTicino i.MX6DL Mamoj
- eckelmann,imx6dl-ci4x10
- emtrion,emcon-mx6 # emCON-MX6S or emCON-MX6DL SoM
- emtrion,emcon-mx6-avari # emCON-MX6S or emCON-MX6DL SoM on Avari Base
+ - engicam,imx6-icore # Engicam i.CoreM6 Starter Kit
+ - engicam,imx6-icore-rqs # Engicam i.CoreM6 RQS Starter Kit
- fsl,imx6dl-sabreauto # i.MX6 DualLite/Solo SABRE Automotive Board
+ - fsl,imx6dl-sabrelite # i.MX6 DualLite SABRE Lite Board
- fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board
+ - karo,imx6dl-tx6dl # Ka-Ro electronics TX6U Modules
- kontron,imx6dl-samx6i # Kontron i.MX6 Solo SMARC Module
+ - poslab,imx6dl-savageboard # Poslab SavageBoard Dual
- prt,prtrvt # Protonic RVT board
- prt,prtvt7 # Protonic VT7 board
+ - rex,imx6dl-rex-basic # Rex Basic i.MX6 Dual Lite Board
+ - riot,imx6s-riotboard # RIoTboard i.MX6S
+ - solidrun,cubox-i/dl # SolidRun Cubox-i Solo/DualLite
+ - solidrun,hummingboard/dl
+ - solidrun,hummingboard2/dl # SolidRun HummingBoard2 Solo/DualLite
- technexion,imx6dl-pico-dwarf # TechNexion i.MX6DL Pico-Dwarf
- technexion,imx6dl-pico-hobbit # TechNexion i.MX6DL Pico-Hobbit
- technexion,imx6dl-pico-nymph # TechNexion i.MX6DL Pico-Nymph
- technexion,imx6dl-pico-pi # TechNexion i.MX6DL Pico-Pi
- technologic,imx6dl-ts4900
- technologic,imx6dl-ts7970
- - toradex,colibri_imx6dl # Colibri iMX6 Module
- - toradex,colibri_imx6dl-v1_1 # Colibri iMX6 Module V1.1
- - toradex,colibri_imx6dl-eval-v3 # Colibri iMX6 Module on Colibri Evaluation Board V3
- - toradex,colibri_imx6dl-v1_1-eval-v3 # Colibri iMX6 Module V1.1 on Colibri Evaluation Board V3
+ - udoo,imx6dl-udoo # Udoo i.MX6 Dual-lite Board
+ - vdl,lanmcu # Van der Laan LANMCU board
+ - wand,imx6dl-wandboard # Wandboard i.MX6 Dual Lite Board
- ysoft,imx6dl-yapp4-draco # i.MX6 DualLite Y Soft IOTA Draco board
- ysoft,imx6dl-yapp4-hydra # i.MX6 DualLite Y Soft IOTA Hydra board
- ysoft,imx6dl-yapp4-orion # i.MX6 DualLite Y Soft IOTA Orion board
- ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board
- const: fsl,imx6dl
+ - description: i.MX6DL based Armadeus AFP6 Board
+ items:
+ - const: armadeus,imx6dl-apf6dev
+ - const: armadeus,imx6dl-apf6 # APF6 (Solo) SoM
+ - const: fsl,imx6dl
+
+ - description: i.MX6DL based DFI FS700-M60-6DL Board
+ items:
+ - const: dfi,fs700-m60-6dl
+ - const: dfi,fs700e-m60
+ - const: fsl,imx6dl
+
- description: i.MX6DL Gateworks Ventana Boards
items:
- enum:
@@ -250,12 +434,29 @@ properties:
- const: phytec,imx6dl-pfla02 # PHYTEC phyFLEX-i.MX6 Quad
- const: fsl,imx6dl
+ - description: i.MX6DL Toradex Colibri iMX6 Module on Colibri
+ Evaluation Board V3
+ items:
+ - const: toradex,colibri_imx6dl-eval-v3
+ - const: toradex,colibri_imx6dl # Colibri iMX6 Module
+ - const: fsl,imx6dl
+
+ - description: i.MX6DL Toradex Colibri iMX6 Module V1.1 on Colibri
+ Evaluation Board V3
+ items:
+ - const: toradex,colibri_imx6dl-v1_1-eval-v3
+ - const: toradex,colibri_imx6dl-v1_1 # Colibri iMX6 Module V1.1
+ - const: toradex,colibri_imx6dl-eval-v3
+ - const: toradex,colibri_imx6dl # Colibri iMX6 Module
+ - const: fsl,imx6dl
+
- description: i.MX6SL based Boards
items:
- enum:
- fsl,imx6sl-evk # i.MX6 SoloLite EVK Board
- kobo,tolino-shine2hd
- kobo,tolino-shine3
+ - revotics,imx6sl-warp # Revotics WaRP Board
- const: fsl,imx6sl
- description: i.MX6SLL based Boards
@@ -268,17 +469,23 @@ properties:
- description: i.MX6SX based Boards
items:
- enum:
+ - boundary,imx6sx-nitrogen6sx
- fsl,imx6sx-sabreauto # i.MX6 SoloX Sabre Auto Board
- fsl,imx6sx-sdb # i.MX6 SoloX SDB Board
- fsl,imx6sx-sdb-reva # i.MX6 SoloX SDB Rev-A Board
+ - samtec,imx6sx-vining-2000 # Softing VIN|ING 2000 Board
+ - udoo,neobasic # UDOO Neo Basic Board
+ - udoo,neoextended # UDOO Neo Extended
+ - udoo,neofull # UDOO Neo Full
- const: fsl,imx6sx
- description: i.MX6UL based Boards
items:
- enum:
- - armadeus,imx6ul-opos6ul # OPOS6UL (i.MX6UL) SoM
- - armadeus,imx6ul-opos6uldev # OPOS6UL (i.MX6UL) SoM on OPOS6ULDev board
+ - engicam,imx6ul-geam # Engicam GEAM6UL Starter Kit
+ - engicam,imx6ul-isiot # Engicam Is.IoT MX6UL eMMC/NAND Starter kit
- fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board
+ - karo,imx6ul-tx6ul # Ka-Ro electronics TXUL-0010 Module
- kontron,imx6ul-n6310-som # Kontron N6310 SOM
- kontron,imx6ul-n6311-som # Kontron N6311 SOM
- technexion,imx6ul-pico-dwarf # TechNexion i.MX6UL Pico-Dwarf
@@ -286,6 +493,26 @@ properties:
- technexion,imx6ul-pico-pi # TechNexion i.MX6UL Pico-Pi
- const: fsl,imx6ul
+ - description: i.MX6UL Armadeus Systems OPOS6UL SoM Board
+ items:
+ - const: armadeus,imx6ul-opos6uldev # OPOS6UL (i.MX6UL) SoM on OPOS6ULDev board
+ - const: armadeus,imx6ul-opos6ul # OPOS6UL (i.MX6UL) SoM
+ - const: fsl,imx6ul
+
+ - description: i.MX6UL Digi International ConnectCore 6UL Boards
+ items:
+ - enum:
+ - digi,ccimx6ulsbcexpress # Digi International ConnectCore 6UL SBC Express
+ - digi,ccimx6ulsbcpro # Digi International ConnectCore 6UL SBC Pro
+ - const: digi,ccimx6ulsom
+ - const: fsl,imx6ul
+
+ - description: i.MX6UL Grinn liteBoard
+ items:
+ - const: grinn,imx6ul-liteboard
+ - const: grinn,imx6ul-litesom
+ - const: fsl,imx6ul
+
- description: i.MX6UL PHYTEC phyBOARD-Segin
items:
- enum:
@@ -317,8 +544,6 @@ properties:
- description: i.MX6ULL based Boards
items:
- enum:
- - armadeus,imx6ull-opos6ul # OPOS6UL (i.MX6ULL) SoM
- - armadeus,imx6ull-opos6uldev # OPOS6UL (i.MX6ULL) SoM on OPOS6ULDev board
- fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board
- kontron,imx6ull-n6411-som # Kontron N6411 SOM
- myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board
@@ -326,6 +551,12 @@ properties:
- toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT Module on Colibri Eval Board
- const: fsl,imx6ull
+ - description: i.MX6ULL Armadeus Systems OPOS6ULDev Board
+ items:
+ - const: armadeus,imx6ull-opos6uldev # OPOS6UL (i.MX6ULL) SoM on OPOS6ULDev board
+ - const: armadeus,imx6ull-opos6ul # OPOS6UL (i.MX6ULL) SoM
+ - const: fsl,imx6ull
+
- description: i.MX6ULL PHYTEC phyBOARD-Segin
items:
- enum:
@@ -351,17 +582,32 @@ properties:
- description: i.MX7S based Boards
items:
- enum:
- - toradex,colibri-imx7s # Colibri iMX7 Solo Module
- - toradex,colibri-imx7s-aster # Colibri iMX7 Solo Module on Aster Carrier Board
- - toradex,colibri-imx7s-eval-v3 # Colibri iMX7 Solo Module on Colibri Evaluation Board V3
- - tq,imx7s-mba7 # i.MX7S TQ MBa7 with TQMa7S SoM
+ - element14,imx7s-warp # Element14 Warp i.MX7 Board
+ - const: fsl,imx7s
+
+ - description: i.MX7S Boards with Toradex Colibri iMX7S Module
+ items:
+ - enum:
+ - toradex,colibri-imx7s-aster # Module on Aster Carrier Board
+ - toradex,colibri-imx7s-eval-v3 # Module on Colibri Evaluation Board V3
+ - const: toradex,colibri-imx7s
+ - const: fsl,imx7s
+
+ - description: TQ-Systems TQMa7S SoM on MBa7x board
+ items:
+ - const: tq,imx7s-mba7
+ - const: tq,imx7s-tqma7
- const: fsl,imx7s
- description: i.MX7D based Boards
items:
- enum:
+ - boundary,imx7d-nitrogen7
+ - compulab,cl-som-imx7 # CompuLab CL-SOM-iMX7
- fsl,imx7d-sdb # i.MX7 SabreSD Board
- fsl,imx7d-sdb-reva # i.MX7 SabreSD Rev-A Board
+ - kam,imx7d-flex-concentrator # Kamstrup OMNIA Flex Concentrator
+ - kam,imx7d-flex-concentrator-mfg # Kamstrup OMNIA Flex Concentrator in manufacturing mode
- novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board
- technexion,imx7d-pico-dwarf # TechNexion i.MX7D Pico-Dwarf
- technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit
@@ -376,11 +622,16 @@ properties:
# Colibri Evaluation Board V3
- toradex,colibri-imx7d-eval-v3 # Colibri iMX7 Dual Module on
# Colibri Evaluation Board V3
- - tq,imx7d-mba7 # i.MX7D TQ MBa7 with TQMa7D SoM
- zii,imx7d-rmu2 # ZII RMU2 Board
- zii,imx7d-rpu2 # ZII RPU2 Board
- const: fsl,imx7d
+ - description: TQ-Systems TQMa7D SoM on MBa7x board
+ items:
+ - const: tq,imx7d-mba7
+ - const: tq,imx7d-tqma7
+ - const: fsl,imx7d
+
- description:
Compulab SBC-iMX7 is a single board computer based on the
Freescale i.MX7 system-on-chip. SBC-iMX7 is implemented with
@@ -392,6 +643,22 @@ properties:
- const: compulab,cl-som-imx7
- const: fsl,imx7d
+ - description: i.MX7D Boards with Toradex Colibri i.MX7D Module
+ items:
+ - enum:
+ - toradex,colibri-imx7d-aster # Module on Aster Carrier Board
+ - toradex,colibri-imx7d-eval-v3 # Module on Colibri Evaluation Board V3
+ - const: toradex,colibri-imx7d
+ - const: fsl,imx7d
+
+ - description: i.MX7D Boards with Toradex Colibri i.MX7D eMMC Module
+ items:
+ - enum:
+ - toradex,colibri-imx7d-emmc-aster # Module on Aster Carrier Board
+ - toradex,colibri-imx7d-emmc-eval-v3 # Module on Colibri Evaluation Board V3
+ - const: toradex,colibri-imx7d-emmc
+ - const: fsl,imx7d
+
- description: i.MX7ULP based Boards
items:
- enum:
@@ -405,9 +672,16 @@ properties:
- beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit
- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
- fsl,imx8mm-evk # i.MX8MM EVK Board
+ - kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM
- variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module
- const: fsl,imx8mm
+ - description: Kontron BL i.MX8MM (N801X S) Board
+ items:
+ - const: kontron,imx8mm-n801x-s
+ - const: kontron,imx8mm-n801x-som
+ - const: fsl,imx8mm
+
- description: Variscite VAR-SOM-MX8MM based boards
items:
- const: variscite,var-som-mx8mm-symphony
@@ -491,10 +765,26 @@ properties:
- fsl,vf600
- fsl,vf610
- fsl,vf610m4
- - toradex,vf500-colibri_vf50 # Colibri VF50 Module
- - toradex,vf500-colibri_vf50-on-eval # Colibri VF50 Module on Colibri Evaluation Board
- - toradex,vf610-colibri_vf61 # Colibri VF61 Module
- - toradex,vf610-colibri_vf61-on-eval # Colibri VF61 Module on Colibri Evaluation Board
+
+ - description: Toradex Colibri VF50 Module on Colibri Evaluation Board
+ items:
+ - const: toradex,vf500-colibri_vf50-on-eval
+ - const: toradex,vf500-colibri_vf50
+ - const: fsl,vf500
+
+ - description: VF610 based Boards
+ items:
+ - enum:
+ - lwn,bk4 # Liebherr BK4 controller
+ - phytec,vf610-cosmic # PHYTEC Cosmic/Cosmic+ Board
+ - fsl,vf610-twr # VF610 Tower Board
+ - const: fsl,vf610
+
+ - description: Toradex Colibri VF61 Module on Colibri Evaluation Board
+ items:
+ - const: toradex,vf610-colibri_vf61-on-eval
+ - const: toradex,vf610-colibri_vf61
+ - const: fsl,vf610
- description: ZII's VF610 based Boards
items:
@@ -515,6 +805,7 @@ properties:
- ebs-systart,oxalis
- fsl,ls1012a-rdb
- fsl,ls1012a-frdm
+ - fsl,ls1012a-frwy
- fsl,ls1012a-qds
- const: fsl,ls1012a
@@ -613,6 +904,15 @@ properties:
- enum:
- fsl,lx2160a-qds
- fsl,lx2160a-rdb
+ - fsl,lx2162a-qds
+ - const: fsl,lx2160a
+
+ - description: SolidRun LX2160A based Boards
+ items:
+ - enum:
+ - solidrun,clearfog-cx
+ - solidrun,honeycomb
+ - const: solidrun,lx2160a-cex7
- const: fsl,lx2160a
- description: S32V234 based Boards
diff --git a/dts/Bindings/arm/idle-states.yaml b/dts/Bindings/arm/idle-states.yaml
index ea805c1e6b..52bce5dbb1 100644
--- a/dts/Bindings/arm/idle-states.yaml
+++ b/dts/Bindings/arm/idle-states.yaml
@@ -313,7 +313,7 @@ patternProperties:
wakeup-latency-us by this duration.
idle-state-name:
- $ref: /schemas/types.yaml#definitions/string
+ $ref: /schemas/types.yaml#/definitions/string
description:
A string used as a descriptive name for the idle state.
diff --git a/dts/Bindings/arm/mediatek.yaml b/dts/Bindings/arm/mediatek.yaml
index f736e8c859..53f0d4e3ea 100644
--- a/dts/Bindings/arm/mediatek.yaml
+++ b/dts/Bindings/arm/mediatek.yaml
@@ -84,6 +84,10 @@ properties:
- enum:
- mediatek,mt8135-evbp1
- const: mediatek,mt8135
+ - items:
+ - enum:
+ - mediatek,mt8167-pumpkin
+ - const: mediatek,mt8167
- description: Google Elm (Acer Chromebook R13)
items:
- const: google,elm-rev8
diff --git a/dts/Bindings/arm/msm/qcom,llcc.yaml b/dts/Bindings/arm/msm/qcom,llcc.yaml
index c3a8604dfa..0a9889debc 100644
--- a/dts/Bindings/arm/msm/qcom,llcc.yaml
+++ b/dts/Bindings/arm/msm/qcom,llcc.yaml
@@ -23,6 +23,7 @@ properties:
enum:
- qcom,sc7180-llcc
- qcom,sdm845-llcc
+ - qcom,sm8150-llcc
reg:
items:
diff --git a/dts/Bindings/arm/mstar/mstar,smpctrl.yaml b/dts/Bindings/arm/mstar/mstar,smpctrl.yaml
new file mode 100644
index 0000000000..599c65980f
--- /dev/null
+++ b/dts/Bindings/arm/mstar/mstar,smpctrl.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2020 thingy.jp.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/mstar/mstar,smpctrl.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: MStar/SigmaStar Armv7 SoC SMP control registers
+
+maintainers:
+ - Daniel Palmer <daniel@thingy.jp>
+
+description: |
+ MStar/SigmaStar's Armv7 SoCs that have more than one processor
+ have a region of registers that allow setting the boot address
+ and a magic number that allows secondary processors to leave
+ the loop they are parked in by the boot ROM.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - sstar,ssd201-smpctrl # SSD201/SSD202D
+ - const: mstar,smpctrl
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ smpctrl@204000 {
+ compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl";
+ reg = <0x204000 0x200>;
+ };
diff --git a/dts/Bindings/arm/mstar/mstar.yaml b/dts/Bindings/arm/mstar/mstar.yaml
index 7c787405bb..61d08c473e 100644
--- a/dts/Bindings/arm/mstar/mstar.yaml
+++ b/dts/Bindings/arm/mstar/mstar.yaml
@@ -20,6 +20,12 @@ properties:
- thingyjp,breadbee-crust # thingy.jp BreadBee Crust
- const: mstar,infinity
+ - description: infinity2m boards
+ items:
+ - enum:
+ - honestar,ssd201htv2 # Honestar SSD201_HT_V2 devkit
+ - const: mstar,infinity2m
+
- description: infinity3 boards
items:
- enum:
diff --git a/dts/Bindings/arm/picoxcell.txt b/dts/Bindings/arm/picoxcell.txt
deleted file mode 100644
index e75c0ef51e..0000000000
--- a/dts/Bindings/arm/picoxcell.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-Picochip picoXcell device tree bindings.
-========================================
-
-Required root node properties:
- - compatible:
- - "picochip,pc7302-pc3x3" : PC7302 development board with PC3X3 device.
- - "picochip,pc7302-pc3x2" : PC7302 development board with PC3X2 device.
- - "picochip,pc3x3" : picoXcell PC3X3 device based board.
- - "picochip,pc3x2" : picoXcell PC3X2 device based board.
-
-Timers required properties:
- - compatible = "picochip,pc3x2-timer"
- - interrupts : The single IRQ line for the timer.
- - clock-freq : The frequency in HZ of the timer.
- - reg : The register bank for the timer.
-
-Note: two timers are required - one for the scheduler clock and one for the
-event tick/NOHZ.
-
-VIC required properties:
- - compatible = "arm,pl192-vic".
- - interrupt-controller.
- - reg : The register bank for the device.
- - #interrupt-cells : Must be 1.
diff --git a/dts/Bindings/arm/renesas.yaml b/dts/Bindings/arm/renesas.yaml
index ff94c45eef..fe11be6503 100644
--- a/dts/Bindings/arm/renesas.yaml
+++ b/dts/Bindings/arm/renesas.yaml
@@ -245,6 +245,7 @@ properties:
- enum:
- renesas,r8a7795
- renesas,r8a7796
+ - renesas,r8a77961
- renesas,r8a77965
- description: R-Car M3-N (R8A77965)
diff --git a/dts/Bindings/arm/rockchip.yaml b/dts/Bindings/arm/rockchip.yaml
index b621752aaa..ef4544ad6f 100644
--- a/dts/Bindings/arm/rockchip.yaml
+++ b/dts/Bindings/arm/rockchip.yaml
@@ -70,6 +70,24 @@ properties:
- const: elgin,rv1108-r1
- const: rockchip,rv1108
+ - description: Engicam PX30.Core C.TOUCH 2.0
+ items:
+ - const: engicam,px30-core-ctouch2
+ - const: engicam,px30-core
+ - const: rockchip,px30
+
+ - description: Engicam PX30.Core C.TOUCH 2.0 10.1" Open Frame
+ items:
+ - const: engicam,px30-core-ctouch2-of10
+ - const: engicam,px30-core
+ - const: rockchip,px30
+
+ - description: Engicam PX30.Core EDIMM2.2 Starter Kit
+ items:
+ - const: engicam,px30-core-edimm2.2
+ - const: engicam,px30-core
+ - const: rockchip,px30
+
- description: Firefly Firefly-RK3288
items:
- enum:
@@ -381,6 +399,11 @@ properties:
- khadas,edge-v
- const: rockchip,rk3399
+ - description: Kobol Helios64
+ items:
+ - const: kobol,helios64
+ - const: rockchip,rk3399
+
- description: Mecer Xtreme Mini S6
items:
- const: mecer,xms6
diff --git a/dts/Bindings/arm/samsung/samsung-boards.yaml b/dts/Bindings/arm/samsung/samsung-boards.yaml
index 272508010b..0796f0c877 100644
--- a/dts/Bindings/arm/samsung/samsung-boards.yaml
+++ b/dts/Bindings/arm/samsung/samsung-boards.yaml
@@ -14,6 +14,19 @@ properties:
const: '/'
compatible:
oneOf:
+ - description: S3C2416 based boards
+ items:
+ - enum:
+ - samsung,smdk2416 # Samsung SMDK2416
+ - const: samsung,s3c2416
+
+ - description: S3C6410 based boards
+ items:
+ - enum:
+ - friendlyarm,mini6410 # FriendlyARM Mini6410
+ - samsung,smdk6410 # Samsung SMDK6410
+ - const: samsung,s3c6410
+
- description: S5PV210 based boards
items:
- enum:
@@ -83,6 +96,14 @@ properties:
- const: samsung,exynos4412
- const: samsung,exynos4
+ - description: Samsung p4note family boards
+ items:
+ - enum:
+ - samsung,n8010 # Samsung GT-N8010/GT-N8013
+ - const: samsung,p4note
+ - const: samsung,exynos4412
+ - const: samsung,exynos4
+
- description: Exynos5250 based boards
items:
- enum:
diff --git a/dts/Bindings/arm/stm32/st,stm32-syscon.yaml b/dts/Bindings/arm/stm32/st,stm32-syscon.yaml
index 6f1cd0103c..149afb5df5 100644
--- a/dts/Bindings/arm/stm32/st,stm32-syscon.yaml
+++ b/dts/Bindings/arm/stm32/st,stm32-syscon.yaml
@@ -19,7 +19,12 @@ properties:
- st,stm32mp151-pwr-mcu
- st,stm32-syscfg
- st,stm32-power-config
+ - st,stm32-tamp
- const: syscon
+ - items:
+ - const: st,stm32-tamp
+ - const: syscon
+ - const: simple-mfd
reg:
maxItems: 1
diff --git a/dts/Bindings/arm/stm32/stm32.yaml b/dts/Bindings/arm/stm32/stm32.yaml
index 009b424e45..e7525a3395 100644
--- a/dts/Bindings/arm/stm32/stm32.yaml
+++ b/dts/Bindings/arm/stm32/stm32.yaml
@@ -14,6 +14,20 @@ properties:
const: "/"
compatible:
oneOf:
+ - description: DH STM32MP1 SoM based Boards
+ items:
+ - enum:
+ - arrow,stm32mp157a-avenger96 # Avenger96
+ - dh,stm32mp153c-dhcom-drc02
+ - dh,stm32mp157c-dhcom-pdk2
+ - dh,stm32mp157c-dhcom-picoitx
+ - enum:
+ - dh,stm32mp153c-dhcom-som
+ - dh,stm32mp157a-dhcor-som
+ - dh,stm32mp157c-dhcom-som
+ - enum:
+ - st,stm32mp153
+ - st,stm32mp157
- items:
- enum:
- st,stm32f429i-disco
@@ -39,8 +53,6 @@ properties:
- const: st,stm32h743
- items:
- enum:
- - arrow,stm32mp157a-avenger96 # Avenger96
- - lxa,stm32mp157c-mc1
- shiratech,stm32mp157a-iot-box # IoT Box
- shiratech,stm32mp157a-stinger96 # Stinger96
- st,stm32mp157c-ed1
@@ -52,6 +64,13 @@ properties:
- const: st,stm32mp157c-ev1
- const: st,stm32mp157c-ed1
- const: st,stm32mp157
+ - description: Octavo OSD32MP15x System-in-Package based boards
+ items:
+ - enum:
+ - lxa,stm32mp157c-mc1 # Linux Automation MC-1
+ - const: oct,stm32mp15xx-osd32
+ - enum:
+ - st,stm32mp157
- description: Odyssey STM32MP1 SoM based Boards
items:
- enum:
diff --git a/dts/Bindings/arm/sunxi.yaml b/dts/Bindings/arm/sunxi.yaml
index cab8e1b641..6db32fbf81 100644
--- a/dts/Bindings/arm/sunxi.yaml
+++ b/dts/Bindings/arm/sunxi.yaml
@@ -201,6 +201,19 @@ properties:
- const: dserve,dsrv9703c
- const: allwinner,sun4i-a10
+ - description: Elimo Engineering Impetus SoM
+ items:
+ - const: elimo,impetus
+ - const: sochip,s3
+ - const: allwinner,sun8i-v3
+
+ - description: Elimo Engineering Initium
+ items:
+ - const: elimo,initium
+ - const: elimo,impetus
+ - const: sochip,s3
+ - const: allwinner,sun8i-v3
+
- description: Empire Electronix D709 Tablet
items:
- const: empire-electronix,d709
@@ -251,6 +264,16 @@ properties:
- const: friendlyarm,nanopi-neo-plus2
- const: allwinner,sun50i-h5
+ - description: FriendlyARM NanoPi R1
+ items:
+ - const: friendlyarm,nanopi-r1
+ - const: allwinner,sun8i-h3
+
+ - description: FriendlyARM ZeroPi
+ items:
+ - const: friendlyarm,zeropi
+ - const: allwinner,sun8i-h3
+
- description: Gemei G9 Tablet
items:
- const: gemei,g9
diff --git a/dts/Bindings/arm/tegra.yaml b/dts/Bindings/arm/tegra.yaml
index 767e86354c..c5fbf869aa 100644
--- a/dts/Bindings/arm/tegra.yaml
+++ b/dts/Bindings/arm/tegra.yaml
@@ -72,6 +72,9 @@ properties:
- const: asus,grouper
- const: nvidia,tegra30
- items:
+ - const: ouya,ouya
+ - const: nvidia,tegra30
+ - items:
- enum:
- nvidia,dalmore
- nvidia,roth
diff --git a/dts/Bindings/arm/tegra/nvidia,tegra30-actmon.txt b/dts/Bindings/arm/tegra/nvidia,tegra30-actmon.txt
index ea670a5d7e..897eedfa2b 100644
--- a/dts/Bindings/arm/tegra/nvidia,tegra30-actmon.txt
+++ b/dts/Bindings/arm/tegra/nvidia,tegra30-actmon.txt
@@ -18,8 +18,30 @@ clock-names. See ../../clock/clock-bindings.txt for details.
../../reset/reset.txt for details.
- reset-names: Must include the following entries:
- actmon
+- operating-points-v2: See ../bindings/opp/opp.txt for details.
+- interconnects: Should contain entries for memory clients sitting on
+ MC->EMC memory interconnect path.
+- interconnect-names: Should include name of the interconnect path for each
+ interconnect entry. Consult TRM documentation for
+ information about available memory clients, see MEMORY
+ CONTROLLER section.
+
+For each opp entry in 'operating-points-v2' table:
+- opp-supported-hw: bitfield indicating SoC speedo ID mask
+- opp-peak-kBps: peak bandwidth of the memory channel
Example:
+ dfs_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp@12750000 {
+ opp-hz = /bits/ 64 <12750000>;
+ opp-supported-hw = <0x000F>;
+ opp-peak-kBps = <51000>;
+ };
+ ...
+ };
+
actmon@6000c800 {
compatible = "nvidia,tegra124-actmon";
reg = <0x0 0x6000c800 0x0 0x400>;
@@ -29,4 +51,7 @@ Example:
clock-names = "actmon", "emc";
resets = <&tegra_car 119>;
reset-names = "actmon";
+ operating-points-v2 = <&dfs_opp_table>;
+ interconnects = <&mc TEGRA124_MC_MPCORER &emc>;
+ interconnect-names = "cpu";
};
diff --git a/dts/Bindings/arm/vt8500.yaml b/dts/Bindings/arm/vt8500.yaml
index 29ff399551..7b762bfc11 100644
--- a/dts/Bindings/arm/vt8500.yaml
+++ b/dts/Bindings/arm/vt8500.yaml
@@ -21,6 +21,5 @@ properties:
- wm,wm8650
- wm,wm8750
- wm,wm8850
-
-additionalProperties: true
+additionalProperties: true
diff --git a/dts/Bindings/auxdisplay/modtronix,lcd2s.yaml b/dts/Bindings/auxdisplay/modtronix,lcd2s.yaml
new file mode 100644
index 0000000000..a1d55a2634
--- /dev/null
+++ b/dts/Bindings/auxdisplay/modtronix,lcd2s.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/auxdisplay/modtronix,lcd2s.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Modtronix engineering LCD2S Character LCD Display
+
+maintainers:
+ - Lars Poeschel <poeschel@lemonage.de>
+
+description:
+ The LCD2S is a Character LCD Display manufactured by Modtronix Engineering.
+ The display supports a serial I2C and SPI interface. The driver currently
+ only supports the I2C interface.
+
+properties:
+ compatible:
+ const: modtronix,lcd2s
+
+ reg:
+ maxItems: 1
+ description:
+ I2C bus address of the display.
+
+ display-height-chars:
+ description: Height of the display, in character cells.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 4
+
+ display-width-chars:
+ description: Width of the display, in character cells.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 16
+ maximum: 20
+
+required:
+ - compatible
+ - reg
+ - display-height-chars
+ - display-width-chars
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lcd2s: auxdisplay@28 {
+ compatible = "modtronix,lcd2s";
+ reg = <0x28>;
+ display-height-chars = <4>;
+ display-width-chars = <20>;
+ };
+ };
diff --git a/dts/Bindings/bus/allwinner,sun50i-a64-de2.yaml b/dts/Bindings/bus/allwinner,sun50i-a64-de2.yaml
index 0503651cd2..863a287ebc 100644
--- a/dts/Bindings/bus/allwinner,sun50i-a64-de2.yaml
+++ b/dts/Bindings/bus/allwinner,sun50i-a64-de2.yaml
@@ -34,7 +34,7 @@ properties:
description:
The SRAM that needs to be claimed to access the display engine
bus.
- $ref: /schemas/types.yaml#definitions/phandle-array
+ $ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
ranges: true
diff --git a/dts/Bindings/bus/baikal,bt1-axi.yaml b/dts/Bindings/bus/baikal,bt1-axi.yaml
index 0bee469457..4ac78b44e4 100644
--- a/dts/Bindings/bus/baikal,bt1-axi.yaml
+++ b/dts/Bindings/bus/baikal,bt1-axi.yaml
@@ -46,7 +46,7 @@ properties:
const: 1
syscon:
- $ref: /schemas/types.yaml#definitions/phandle
+ $ref: /schemas/types.yaml#/definitions/phandle
description: Phandle to the Baikal-T1 System Controller DT node
interrupts:
diff --git a/dts/Bindings/bus/nvidia,tegra210-aconnect.txt b/dts/Bindings/bus/nvidia,tegra210-aconnect.txt
deleted file mode 100644
index 3108d03802..0000000000
--- a/dts/Bindings/bus/nvidia,tegra210-aconnect.txt
+++ /dev/null
@@ -1,44 +0,0 @@
-NVIDIA Tegra ACONNECT Bus
-
-The Tegra ACONNECT bus is an AXI switch which is used to connnect various
-components inside the Audio Processing Engine (APE). All CPU accesses to
-the APE subsystem go through the ACONNECT via an APB to AXI wrapper.
-
-Required properties:
-- compatible: Must be "nvidia,tegra210-aconnect".
-- clocks: Must contain the entries for the APE clock (TEGRA210_CLK_APE),
- and APE interface clock (TEGRA210_CLK_APB2APE).
-- clock-names: Must contain the names "ape" and "apb2ape" for the corresponding
- 'clocks' entries.
-- power-domains: Must contain a phandle that points to the audio powergate
- (namely 'aud') for Tegra210.
-- #address-cells: The number of cells used to represent physical base addresses
- in the aconnect address space. Should be 1.
-- #size-cells: The number of cells used to represent the size of an address
- range in the aconnect address space. Should be 1.
-- ranges: Mapping of the aconnect address space to the CPU address space.
-
-All devices accessed via the ACONNNECT are described by child-nodes.
-
-Example:
-
- aconnect@702c0000 {
- compatible = "nvidia,tegra210-aconnect";
- clocks = <&tegra_car TEGRA210_CLK_APE>,
- <&tegra_car TEGRA210_CLK_APB2APE>;
- clock-names = "ape", "apb2ape";
- power-domains = <&pd_audio>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
-
-
- child1 {
- ...
- };
-
- child2 {
- ...
- };
- };
diff --git a/dts/Bindings/bus/nvidia,tegra210-aconnect.yaml b/dts/Bindings/bus/nvidia,tegra210-aconnect.yaml
new file mode 100644
index 0000000000..7b1a08c62a
--- /dev/null
+++ b/dts/Bindings/bus/nvidia,tegra210-aconnect.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/nvidia,tegra210-aconnect.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra ACONNECT Bus
+
+description: |
+ The Tegra ACONNECT bus is an AXI switch which is used to connnect various
+ components inside the Audio Processing Engine (APE). All CPU accesses to
+ the APE subsystem go through the ACONNECT via an APB to AXI wrapper. All
+ devices accessed via the ACONNNECT are described by child-nodes.
+
+maintainers:
+ - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+ compatible:
+ oneOf:
+ - const: nvidia,tegra210-aconnect
+ - items:
+ - enum:
+ - nvidia,tegra186-aconnect
+ - nvidia,tegra194-aconnect
+ - const: nvidia,tegra210-aconnect
+
+ clocks:
+ items:
+ - description: Must contain the entry for APE clock
+ - description: Must contain the entry for APE interface clock
+
+ clock-names:
+ items:
+ - const: ape
+ - const: apb2ape
+
+ power-domains:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+patternProperties:
+ "@[0-9a-f]+$":
+ type: object
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - power-domains
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include<dt-bindings/clock/tegra210-car.h>
+
+ aconnect@702c0000 {
+ compatible = "nvidia,tegra210-aconnect";
+ clocks = <&tegra_car TEGRA210_CLK_APE>,
+ <&tegra_car TEGRA210_CLK_APB2APE>;
+ clock-names = "ape", "apb2ape";
+ power-domains = <&pd_audio>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x702c0000 0x702c0000 0x00040000>;
+
+ // Child device nodes follow ...
+ };
+
+...
diff --git a/dts/Bindings/clock/adi,axi-clkgen.yaml b/dts/Bindings/clock/adi,axi-clkgen.yaml
new file mode 100644
index 0000000000..0d06387184
--- /dev/null
+++ b/dts/Bindings/clock/adi,axi-clkgen.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Binding for Analog Devices AXI clkgen pcore clock generator
+
+maintainers:
+ - Lars-Peter Clausen <lars@metafoo.de>
+ - Michael Hennerich <michael.hennerich@analog.com>
+
+description: |
+ The axi_clkgen IP core is a software programmable clock generator,
+ that can be synthesized on various FPGA platforms.
+
+ Link: https://wiki.analog.com/resources/fpga/docs/axi_clkgen
+
+properties:
+ compatible:
+ enum:
+ - adi,axi-clkgen-2.00.a
+
+ clocks:
+ description:
+ Specifies the reference clock(s) from which the output frequency is
+ derived. This must either reference one clock if only the first clock
+ input is connected or two if both clock inputs are connected.
+ minItems: 1
+ maxItems: 2
+
+ '#clock-cells':
+ const: 0
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@ff000000 {
+ compatible = "adi,axi-clkgen-2.00.a";
+ #clock-cells = <0>;
+ reg = <0xff000000 0x1000>;
+ clocks = <&osc 1>;
+ };
diff --git a/dts/Bindings/clock/axi-clkgen.txt b/dts/Bindings/clock/axi-clkgen.txt
deleted file mode 100644
index aca94fe941..0000000000
--- a/dts/Bindings/clock/axi-clkgen.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Binding for the axi-clkgen clock generator
-
-This binding uses the common clock binding[1].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-- compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a".
-- #clock-cells : from common clock binding; Should always be set to 0.
-- reg : Address and length of the axi-clkgen register set.
-- clocks : Phandle and clock specifier for the parent clock(s). This must
- either reference one clock if only the first clock input is connected or two
- if both clock inputs are connected. For the later case the clock connected
- to the first input must be specified first.
-
-Optional properties:
-- clock-output-names : From common clock binding.
-
-Example:
- clock@ff000000 {
- compatible = "adi,axi-clkgen";
- #clock-cells = <0>;
- reg = <0xff000000 0x1000>;
- clocks = <&osc 1>;
- };
diff --git a/dts/Bindings/clock/canaan,k210-clk.yaml b/dts/Bindings/clock/canaan,k210-clk.yaml
new file mode 100644
index 0000000000..565ca468cb
--- /dev/null
+++ b/dts/Bindings/clock/canaan,k210-clk.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/canaan,k210-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Canaan Kendryte K210 Clock Device Tree Bindings
+
+maintainers:
+ - Damien Le Moal <damien.lemoal@wdc.com>
+
+description: |
+ Canaan Kendryte K210 SoC clocks driver bindings. The clock
+ controller node must be defined as a child node of the K210
+ system controller node.
+
+ See also:
+ - dt-bindings/clock/k210-clk.h
+
+properties:
+ compatible:
+ const: canaan,k210-clk
+
+ clocks:
+ description:
+ Phandle of the SoC 26MHz fixed-rate oscillator clock.
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - '#clock-cells'
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/k210-clk.h>
+ clocks {
+ in0: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+ };
+
+ /* ... */
+ sysclk: clock-controller {
+ #clock-cells = <1>;
+ compatible = "canaan,k210-clk";
+ clocks = <&in0>;
+ };
diff --git a/dts/Bindings/clock/fsl,flexspi-clock.yaml b/dts/Bindings/clock/fsl,flexspi-clock.yaml
new file mode 100644
index 0000000000..1fa390ee7b
--- /dev/null
+++ b/dts/Bindings/clock/fsl,flexspi-clock.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/fsl,flexspi-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale FlexSPI clock driver for Layerscape SoCs
+
+maintainers:
+ - Michael Walle <michael@walle.cc>
+
+description:
+ The Freescale Layerscape SoCs have a special FlexSPI clock which is
+ derived from the platform PLL.
+
+properties:
+ compatible:
+ enum:
+ - fsl,ls1028a-flexspi-clk
+ - fsl,lx2160a-flexspi-clk
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 0
+
+ clock-output-names:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ dcfg {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ fspi_clk: clock-controller@900 {
+ compatible = "fsl,ls1028a-flexspi-clk";
+ reg = <0x900 0x4>;
+ #clock-cells = <0>;
+ clocks = <&parentclk>;
+ clock-output-names = "fspi_clk";
+ };
+ };
diff --git a/dts/Bindings/clock/imx8qxp-lpcg.yaml b/dts/Bindings/clock/imx8qxp-lpcg.yaml
index 33f3010f48..940486ef10 100644
--- a/dts/Bindings/clock/imx8qxp-lpcg.yaml
+++ b/dts/Bindings/clock/imx8qxp-lpcg.yaml
@@ -21,27 +21,58 @@ description: |
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See the full list of clock IDs from:
- include/dt-bindings/clock/imx8-clock.h
+ include/dt-bindings/clock/imx8-lpcg.h
properties:
compatible:
- enum:
- - fsl,imx8qxp-lpcg-adma
- - fsl,imx8qxp-lpcg-conn
- - fsl,imx8qxp-lpcg-dc
- - fsl,imx8qxp-lpcg-dsp
- - fsl,imx8qxp-lpcg-gpu
- - fsl,imx8qxp-lpcg-hsio
- - fsl,imx8qxp-lpcg-img
- - fsl,imx8qxp-lpcg-lsio
- - fsl,imx8qxp-lpcg-vpu
-
+ oneOf:
+ - const: fsl,imx8qxp-lpcg
+ - items:
+ - enum:
+ - fsl,imx8qm-lpcg
+ - const: fsl,imx8qxp-lpcg
+ - enum:
+ - fsl,imx8qxp-lpcg-adma
+ - fsl,imx8qxp-lpcg-conn
+ - fsl,imx8qxp-lpcg-dc
+ - fsl,imx8qxp-lpcg-dsp
+ - fsl,imx8qxp-lpcg-gpu
+ - fsl,imx8qxp-lpcg-hsio
+ - fsl,imx8qxp-lpcg-img
+ - fsl,imx8qxp-lpcg-lsio
+ - fsl,imx8qxp-lpcg-vpu
+ deprecated: true
reg:
maxItems: 1
'#clock-cells':
const: 1
+ clocks:
+ description: |
+ Input parent clocks phandle array for each clock
+ minItems: 1
+ maxItems: 8
+
+ clock-indices:
+ description: |
+ An integer array indicating the bit offset for each clock.
+ Refer to <include/dt-bindings/clock/imx8-lpcg.h> for the
+ supported LPCG clock indices.
+ minItems: 1
+ maxItems: 8
+
+ clock-output-names:
+ description: |
+ Shall be the corresponding names of the outputs.
+ NOTE this property must be specified in the same order
+ as the clock-indices property.
+ minItems: 1
+ maxItems: 8
+
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- reg
@@ -51,23 +82,33 @@ additionalProperties: false
examples:
- |
- #include <dt-bindings/clock/imx8-clock.h>
+ #include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
- clock-controller@5b200000 {
- compatible = "fsl,imx8qxp-lpcg-conn";
- reg = <0x5b200000 0xb0000>;
+ sdhc0_lpcg: clock-controller@5b200000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b200000 0x10000>;
#clock-cells = <1>;
+ clocks = <&sdhc0_clk IMX_SC_PM_CLK_PER>,
+ <&conn_ipg_clk>,
+ <&conn_axi_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>,
+ <IMX_LPCG_CLK_4>,
+ <IMX_LPCG_CLK_5>;
+ clock-output-names = "sdhc0_lpcg_per_clk",
+ "sdhc0_lpcg_ipg_clk",
+ "sdhc0_lpcg_ahb_clk";
+ power-domains = <&pd IMX_SC_R_SDHC_0>;
};
mmc@5b010000 {
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
- clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
- <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
+ clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
+ <&sdhc0_lpcg IMX_LPCG_CLK_0>,
+ <&sdhc0_lpcg IMX_LPCG_CLK_5>;
clock-names = "ipg", "per", "ahb";
power-domains = <&pd IMX_SC_R_SDHC_0>;
};
diff --git a/dts/Bindings/clock/ingenic,cgu.yaml b/dts/Bindings/clock/ingenic,cgu.yaml
index 5dd7ea8a78..c65b9458c0 100644
--- a/dts/Bindings/clock/ingenic,cgu.yaml
+++ b/dts/Bindings/clock/ingenic,cgu.yaml
@@ -92,7 +92,7 @@ required:
patternProperties:
"^usb-phy@[a-f0-9]+$":
- allOf: [ $ref: "../usb/ingenic,jz4770-phy.yaml#" ]
+ allOf: [ $ref: "../phy/ingenic,phy-usb.yaml#" ]
additionalProperties: false
diff --git a/dts/Bindings/clock/qcom,aoncc-sm8250.yaml b/dts/Bindings/clock/qcom,aoncc-sm8250.yaml
new file mode 100644
index 0000000000..c40a74b5d6
--- /dev/null
+++ b/dts/Bindings/clock/qcom,aoncc-sm8250.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,aoncc-sm8250.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Clock bindings for LPASS Always ON Clock Controller on SM8250 SoCs
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description: |
+ The clock consumer should specify the desired clock by having the clock
+ ID in its "clocks" phandle cell.
+ See include/dt-bindings/clock/qcom,sm8250-lpass-aoncc.h for the full list
+ of Audio Clock controller clock IDs.
+
+properties:
+ compatible:
+ const: qcom,sm8250-lpass-aon
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ items:
+ - description: LPASS Core voting clock
+ - description: Glitch Free Mux register clock
+
+ clock-names:
+ items:
+ - const: core
+ - const: bus
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
+ #include <dt-bindings/sound/qcom,q6afe.h>
+ clock-controller@3800000 {
+ #clock-cells = <1>;
+ compatible = "qcom,sm8250-lpass-aon";
+ reg = <0x03380000 0x40000>;
+ clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "core", "bus";
+ };
diff --git a/dts/Bindings/clock/qcom,audiocc-sm8250.yaml b/dts/Bindings/clock/qcom,audiocc-sm8250.yaml
new file mode 100644
index 0000000000..915d76206a
--- /dev/null
+++ b/dts/Bindings/clock/qcom,audiocc-sm8250.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,audiocc-sm8250.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Clock bindings for LPASS Audio Clock Controller on SM8250 SoCs
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description: |
+ The clock consumer should specify the desired clock by having the clock
+ ID in its "clocks" phandle cell.
+ See include/dt-bindings/clock/qcom,sm8250-lpass-audiocc.h for the full list
+ of Audio Clock controller clock IDs.
+
+properties:
+ compatible:
+ const: qcom,sm8250-lpass-audiocc
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ items:
+ - description: LPASS Core voting clock
+ - description: Glitch Free Mux register clock
+
+ clock-names:
+ items:
+ - const: core
+ - const: bus
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
+ #include <dt-bindings/sound/qcom,q6afe.h>
+ clock-controller@3300000 {
+ #clock-cells = <1>;
+ compatible = "qcom,sm8250-lpass-audiocc";
+ reg = <0x03300000 0x30000>;
+ clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "core", "bus";
+ };
diff --git a/dts/Bindings/clock/qcom,gcc-sdx55.yaml b/dts/Bindings/clock/qcom,gcc-sdx55.yaml
new file mode 100644
index 0000000000..1121b3934c
--- /dev/null
+++ b/dts/Bindings/clock/qcom,gcc-sdx55.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx55.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller Binding for SDX55
+
+maintainers:
+ - Vinod Koul <vkoul@kernel.org>
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+description: |
+ Qualcomm global clock control module which supports the clocks, resets and
+ power domains on SDX55
+
+ See also:
+ - dt-bindings/clock/qcom,gcc-sdx55.h
+
+properties:
+ compatible:
+ const: qcom,gcc-sdx55
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Sleep clock source
+ - description: PLL test clock source (Optional clock)
+ minItems: 2
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: bi_tcxo
+ - const: sleep_clk
+ - const: core_bi_pll_test_se # Optional clock
+ minItems: 2
+ maxItems: 3
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - reg
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@100000 {
+ compatible = "qcom,gcc-sdx55";
+ reg = <0x00100000 0x1f0000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>, <&pll_test_clk>;
+ clock-names = "bi_tcxo", "sleep_clk", "core_bi_pll_test_se";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+...
diff --git a/dts/Bindings/clock/qcom,rpmhcc.yaml b/dts/Bindings/clock/qcom,rpmhcc.yaml
index a46a3a799a..12c9cbc0eb 100644
--- a/dts/Bindings/clock/qcom,rpmhcc.yaml
+++ b/dts/Bindings/clock/qcom,rpmhcc.yaml
@@ -19,8 +19,10 @@ properties:
enum:
- qcom,sc7180-rpmh-clk
- qcom,sdm845-rpmh-clk
+ - qcom,sdx55-rpmh-clk
- qcom,sm8150-rpmh-clk
- qcom,sm8250-rpmh-clk
+ - qcom,sm8350-rpmh-clk
clocks:
maxItems: 1
diff --git a/dts/Bindings/clock/qcom,sc7180-camcc.yaml b/dts/Bindings/clock/qcom,sc7180-camcc.yaml
new file mode 100644
index 0000000000..f49027edfc
--- /dev/null
+++ b/dts/Bindings/clock/qcom,sc7180-camcc.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sc7180-camcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Camera Clock & Reset Controller Binding for SC7180
+
+maintainers:
+ - Taniya Das <tdas@codeaurora.org>
+
+description: |
+ Qualcomm camera clock control module which supports the clocks, resets and
+ power domains on SC7180.
+
+ See also:
+ - dt-bindings/clock/qcom,camcc-sc7180.h
+
+properties:
+ compatible:
+ const: qcom,sc7180-camcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Camera_ahb clock from GCC
+ - description: Camera XO clock from GCC
+
+ clock-names:
+ items:
+ - const: bi_tcxo
+ - const: iface
+ - const: xo
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sc7180.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@ad00000 {
+ compatible = "qcom,sc7180-camcc";
+ reg = <0x0ad00000 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_CAMERA_AHB_CLK>,
+ <&gcc GCC_CAMERA_XO_CLK>;
+ clock-names = "bi_tcxo", "iface", "xo";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/dts/Bindings/clock/renesas,rcar-usb2-clock-sel.txt b/dts/Bindings/clock/renesas,rcar-usb2-clock-sel.txt
deleted file mode 100644
index da92f5748d..0000000000
--- a/dts/Bindings/clock/renesas,rcar-usb2-clock-sel.txt
+++ /dev/null
@@ -1,68 +0,0 @@
-* Renesas R-Car USB 2.0 clock selector
-
-This file provides information on what the device node for the R-Car USB 2.0
-clock selector.
-
-If you connect an external clock to the USB_EXTAL pin only, you should set
-the clock rate to "usb_extal" node only.
-If you connect an oscillator to both the USB_XTAL and USB_EXTAL, this module
-is not needed because this is default setting. (Of course, you can set the
-clock rates to both "usb_extal" and "usb_xtal" nodes.
-
-Case 1: An external clock connects to R-Car SoC
- +----------+ +--- R-Car ---------------------+
- |External |---|USB_EXTAL ---> all usb channels|
- |clock | |USB_XTAL |
- +----------+ +-------------------------------+
-In this case, we need this driver with "usb_extal" clock.
-
-Case 2: An oscillator connects to R-Car SoC
- +----------+ +--- R-Car ---------------------+
- |Oscillator|---|USB_EXTAL -+-> all usb channels|
- | |---|USB_XTAL --+ |
- +----------+ +-------------------------------+
-In this case, we don't need this selector.
-
-Required properties:
-- compatible: "renesas,r8a7795-rcar-usb2-clock-sel" if the device is a part of
- an R8A7795 SoC.
- "renesas,r8a7796-rcar-usb2-clock-sel" if the device if a part of
- an R8A77960 SoC.
- "renesas,r8a77961-rcar-usb2-clock-sel" if the device if a part of
- an R8A77961 SoC.
- "renesas,rcar-gen3-usb2-clock-sel" for a generic R-Car Gen3
- compatible device.
-
- When compatible with the generic version, nodes must list the
- SoC-specific version corresponding to the platform first
- followed by the generic version.
-
-- reg: offset and length of the USB 2.0 clock selector register block.
-- clocks: A list of phandles and specifier pairs.
-- clock-names: Name of the clocks.
- - The functional clock of USB 2.0 host side must be "ehci_ohci"
- - The functional clock of HS-USB side must be "hs-usb-if"
- - The USB_EXTAL clock pin must be "usb_extal"
- - The USB_XTAL clock pin must be "usb_xtal"
-- #clock-cells: Must be 0
-- power-domains: A phandle and symbolic PM domain specifier.
- See power/renesas,rcar-sysc.yaml.
-- resets: A list of phandles and specifier pairs.
-- reset-names: Name of the resets.
- - The reset of USB 2.0 host side must be "ehci_ohci"
- - The reset of HS-USB side must be "hs-usb-if"
-
-Example (R-Car H3):
-
- usb2_clksel: clock-controller@e6590630 {
- compatible = "renesas,r8a7795-rcar-usb2-clock-sel",
- "renesas,rcar-gen3-usb2-clock-sel";
- reg = <0 0xe6590630 0 0x02>;
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
- <&usb_extal>, <&usb_xtal>;
- clock-names = "ehci_ohci", "hs-usb-if", "usb_extal", "usb_xtal";
- #clock-cells = <0>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 703>, <&cpg 704>;
- reset-names = "ehci_ohci", "hs-usb-if";
- };
diff --git a/dts/Bindings/clock/renesas,rcar-usb2-clock-sel.yaml b/dts/Bindings/clock/renesas,rcar-usb2-clock-sel.yaml
new file mode 100644
index 0000000000..5be1229b3d
--- /dev/null
+++ b/dts/Bindings/clock/renesas,rcar-usb2-clock-sel.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/clock/renesas,rcar-usb2-clock-sel.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Renesas R-Car USB 2.0 clock selector
+
+maintainers:
+ - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+
+description: |
+ If you connect an external clock to the USB_EXTAL pin only, you should set
+ the clock rate to "usb_extal" node only.
+ If you connect an oscillator to both the USB_XTAL and USB_EXTAL, this module
+ is not needed because this is default setting. (Of course, you can set the
+ clock rates to both "usb_extal" and "usb_xtal" nodes.
+
+ Case 1: An external clock connects to R-Car SoC
+ +----------+ +--- R-Car ---------------------+
+ |External |---|USB_EXTAL ---> all usb channels|
+ |clock | |USB_XTAL |
+ +----------+ +-------------------------------+
+
+ In this case, we need this driver with "usb_extal" clock.
+
+ Case 2: An oscillator connects to R-Car SoC
+ +----------+ +--- R-Car ---------------------+
+ |Oscillator|---|USB_EXTAL -+-> all usb channels|
+ | |---|USB_XTAL --+ |
+ +----------+ +-------------------------------+
+ In this case, we don't need this selector.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r8a7795-rcar-usb2-clock-sel # R-Car H3
+ - renesas,r8a7796-rcar-usb2-clock-sel # R-Car M3-W
+ - renesas,r8a77961-rcar-usb2-clock-sel # R-Car M3-W+
+ - const: renesas,rcar-gen3-usb2-clock-sel
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 4
+ maxItems: 4
+
+ clock-names:
+ items:
+ - const: ehci_ohci
+ - const: hs-usb-if
+ - const: usb_extal
+ - const: usb_xtal
+
+ '#clock-cells':
+ const: 0
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ minItems: 2
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: ehci_ohci
+ - const: hs-usb-if
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - power-domains
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
+ #include <dt-bindings/power/r8a7795-sysc.h>
+
+ usb2_clksel: clock-controller@e6590630 {
+ compatible = "renesas,r8a7795-rcar-usb2-clock-sel",
+ "renesas,rcar-gen3-usb2-clock-sel";
+ reg = <0xe6590630 0x02>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
+ <&usb_extal>, <&usb_xtal>;
+ clock-names = "ehci_ohci", "hs-usb-if", "usb_extal", "usb_xtal";
+ #clock-cells = <0>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 703>, <&cpg 704>;
+ reset-names = "ehci_ohci", "hs-usb-if";
+ };
diff --git a/dts/Bindings/clock/sifive/fu740-prci.yaml b/dts/Bindings/clock/sifive/fu740-prci.yaml
new file mode 100644
index 0000000000..e17143cac3
--- /dev/null
+++ b/dts/Bindings/clock/sifive/fu740-prci.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 SiFive, Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sifive/fu740-prci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive FU740 Power Reset Clock Interrupt Controller (PRCI)
+
+maintainers:
+ - Zong Li <zong.li@sifive.com>
+ - Paul Walmsley <paul.walmsley@sifive.com>
+
+description:
+ On the FU740 family of SoCs, most system-wide clock and reset integration
+ is via the PRCI IP block.
+ The clock consumer should specify the desired clock via the clock ID
+ macros defined in include/dt-bindings/clock/sifive-fu740-prci.h.
+ These macros begin with PRCI_CLK_.
+
+ The hfclk and rtcclk nodes are required, and represent physical
+ crystals or resonators located on the PCB. These nodes should be present
+ underneath /, rather than /soc.
+
+properties:
+ compatible:
+ const: sifive,fu740-c000-prci
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: high frequency clock.
+ - description: RTL clock.
+
+ clock-names:
+ items:
+ - const: hfclk
+ - const: rtcclk
+
+ "#clock-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ prci: clock-controller@10000000 {
+ compatible = "sifive,fu740-c000-prci";
+ reg = <0x10000000 0x1000>;
+ clocks = <&hfclk>, <&rtcclk>;
+ #clock-cells = <1>;
+ };
diff --git a/dts/Bindings/connector/usb-connector.yaml b/dts/Bindings/connector/usb-connector.yaml
index 728f82db07..4286ed767a 100644
--- a/dts/Bindings/connector/usb-connector.yaml
+++ b/dts/Bindings/connector/usb-connector.yaml
@@ -37,7 +37,7 @@ properties:
description: Size of the connector, should be specified in case of
non-fullsize 'usb-a-connector' or 'usb-b-connector' compatible
connectors.
- $ref: /schemas/types.yaml#definitions/string
+ $ref: /schemas/types.yaml#/definitions/string
enum:
- mini
@@ -67,7 +67,7 @@ properties:
power-role:
description: Determines the power role that the Type C connector will
support. "dual" refers to Dual Role Port (DRP).
- $ref: /schemas/types.yaml#definitions/string
+ $ref: /schemas/types.yaml#/definitions/string
enum:
- source
@@ -76,7 +76,7 @@ properties:
try-power-role:
description: Preferred power role.
- $ref: /schemas/types.yaml#definitions/string
+ $ref: /schemas/types.yaml#/definitions/string
enum:
- source
@@ -86,13 +86,31 @@ properties:
data-role:
description: Data role if Type C connector supports USB data. "dual" refers
Dual Role Device (DRD).
- $ref: /schemas/types.yaml#definitions/string
+ $ref: /schemas/types.yaml#/definitions/string
enum:
- host
- device
- dual
+ typec-power-opmode:
+ description: Determines the power operation mode that the Type C connector
+ will support and will advertise through CC pins when it has no power
+ delivery support.
+ - "default" corresponds to default USB voltage and current defined by the
+ USB 2.0 and USB 3.2 specifications, 5V 500mA for USB 2.0 ports and
+ 5V 900mA or 1500mA for USB 3.2 ports in single-lane or dual-lane
+ operation respectively.
+ - "1.5A" and "3.0A", 5V 1.5A and 5V 3.0A respectively, as defined in USB
+ Type-C Cable and Connector specification, when Power Delivery is not
+ supported.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/string
+ enum:
+ - default
+ - 1.5A
+ - 3.0A
+
# The following are optional properties for "usb-c-connector" with power
# delivery support.
source-pdos:
@@ -147,6 +165,25 @@ properties:
required:
- port@0
+ new-source-frs-typec-current:
+ description: Initial current capability of the new source when vSafe5V
+ is applied during PD3.0 Fast Role Swap. "Table 6-14 Fixed Supply PDO - Sink"
+ of "USB Power Delivery Specification Revision 3.0, Version 1.2" provides the
+ different power levels and "6.4.1.3.1.6 Fast Role Swap USB Type-C Current"
+ provides a detailed description of the field. The sink PDO from current source
+ reflects the current source's(i.e. transmitter of the FRS signal) power
+ requirement during fr swap. The current sink (i.e. receiver of the FRS signal),
+ a.k.a new source, should check if it will be able to satisfy the current source's,
+ new sink's, requirement during frswap before enabling the frs signal reception.
+ This property refers to maximum current capability that the current sink can
+ satisfy. During FRS, VBUS voltage is at 5V, as the partners are in implicit
+ contract, hence, the power level is only a function of the current capability.
+ "1" refers to default USB power level as described by "Table 6-14 Fixed Supply PDO - Sink".
+ "2" refers to 1.5A@5V.
+ "3" refers to 3.0A@5V.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 3]
+
required:
- compatible
@@ -173,6 +210,12 @@ allOf:
type:
const: micro
+anyOf:
+ - not:
+ required:
+ - typec-power-opmode
+ - new-source-frs-typec-current
+
additionalProperties: true
examples:
diff --git a/dts/Bindings/crypto/intel,keembay-ocs-aes.yaml b/dts/Bindings/crypto/intel,keembay-ocs-aes.yaml
new file mode 100644
index 0000000000..ee2c099981
--- /dev/null
+++ b/dts/Bindings/crypto/intel,keembay-ocs-aes.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-aes.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Keem Bay OCS AES Device Tree Bindings
+
+maintainers:
+ - Daniele Alessandrelli <daniele.alessandrelli@intel.com>
+
+description:
+ The Intel Keem Bay Offload and Crypto Subsystem (OCS) AES engine provides
+ hardware-accelerated AES/SM4 encryption/decryption.
+
+properties:
+ compatible:
+ const: intel,keembay-ocs-aes
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ crypto@30008000 {
+ compatible = "intel,keembay-ocs-aes";
+ reg = <0x30008000 0x1000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 95>;
+ };
diff --git a/dts/Bindings/crypto/picochip-spacc.txt b/dts/Bindings/crypto/picochip-spacc.txt
deleted file mode 100644
index df1151f877..0000000000
--- a/dts/Bindings/crypto/picochip-spacc.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Picochip picoXcell SPAcc (Security Protocol Accelerator) bindings
-
-Picochip picoXcell devices contain crypto offload engines that may be used for
-IPSEC and femtocell layer 2 ciphering.
-
-Required properties:
- - compatible : "picochip,spacc-ipsec" for the IPSEC offload engine
- "picochip,spacc-l2" for the femtocell layer 2 ciphering engine.
- - reg : Offset and length of the register set for this device
- - interrupts : The interrupt line from the SPAcc.
- - ref-clock : The input clock that drives the SPAcc.
-
-Example SPAcc node:
-
-spacc@10000 {
- compatible = "picochip,spacc-ipsec";
- reg = <0x100000 0x10000>;
- interrupt-parent = <&vic0>;
- interrupts = <24>;
- ref-clock = <&ipsec_clk>, "ref";
-};
diff --git a/dts/Bindings/devfreq/exynos-bus.txt b/dts/Bindings/devfreq/exynos-bus.txt
index e71f752cc1..bcaa2c08ac 100644
--- a/dts/Bindings/devfreq/exynos-bus.txt
+++ b/dts/Bindings/devfreq/exynos-bus.txt
@@ -51,6 +51,19 @@ Optional properties only for parent bus device:
- exynos,saturation-ratio: the percentage value which is used to calibrate
the performance count against total cycle count.
+Optional properties for the interconnect functionality (QoS frequency
+constraints):
+- #interconnect-cells: should be 0.
+- interconnects: as documented in ../interconnect.txt, describes a path at the
+ higher level interconnects used by this interconnect provider.
+ If this interconnect provider is directly linked to a top level interconnect
+ provider the property contains only one phandle. The provider extends
+ the interconnect graph by linking its node to a node registered by provider
+ pointed to by first phandle in the 'interconnects' property.
+
+- samsung,data-clock-ratio: ratio of the data throughput in B/s to minimum data
+ clock frequency in Hz, default value is 8 when this property is missing.
+
Detailed correlation between sub-blocks and power line according to Exynos SoC:
- In case of Exynos3250, there are two power line as following:
VDD_MIF |--- DMC
@@ -135,7 +148,7 @@ Detailed correlation between sub-blocks and power line according to Exynos SoC:
|--- PERIC (Fixed clock rate)
|--- FSYS (Fixed clock rate)
-Example1:
+Example 1:
Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
power line (regulator). The MIF (Memory Interface) AXI bus is used to
transfer data between DRAM and CPU and uses the VDD_MIF regulator.
@@ -184,7 +197,7 @@ Example1:
|L5 |200000 |200000 |400000 |300000 | ||1000000 |
----------------------------------------------------------
-Example2 :
+Example 2:
The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
is listed below:
@@ -419,3 +432,57 @@ Example2 :
devfreq = <&bus_leftbus>;
status = "okay";
};
+
+Example 3:
+ An interconnect path "bus_display -- bus_leftbus -- bus_dmc" on
+ Exynos4412 SoC with video mixer as an interconnect consumer device.
+
+ soc {
+ bus_dmc: bus_dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DIV_DMC>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_dmc_opp_table>;
+ samsung,data-clock-ratio = <4>;
+ #interconnect-cells = <0>;
+ };
+
+ bus_leftbus: bus_leftbus {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DIV_GDL>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ #interconnect-cells = <0>;
+ interconnects = <&bus_dmc>;
+ };
+
+ bus_display: bus_display {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_ACLK160>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_display_opp_table>;
+ #interconnect-cells = <0>;
+ interconnects = <&bus_leftbus &bus_dmc>;
+ };
+
+ bus_dmc_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ /* ... */
+ }
+
+ bus_leftbus_opp_table: opp_table3 {
+ compatible = "operating-points-v2";
+ /* ... */
+ };
+
+ bus_display_opp_table: opp_table4 {
+ compatible = "operating-points-v2";
+ /* .. */
+ };
+
+ &mixer {
+ compatible = "samsung,exynos4212-mixer";
+ interconnects = <&bus_display &bus_dmc>;
+ /* ... */
+ };
+ };
diff --git a/dts/Bindings/display/bridge/analogix,anx7625.yaml b/dts/Bindings/display/bridge/analogix,anx7625.yaml
new file mode 100644
index 0000000000..9392b5502a
--- /dev/null
+++ b/dts/Bindings/display/bridge/analogix,anx7625.yaml
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 Analogix Semiconductor, Inc.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/bridge/analogix,anx7625.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Analogix ANX7625 SlimPort (4K Mobile HD Transmitter)
+
+maintainers:
+ - Xin Ji <xji@analogixsemi.com>
+
+description: |
+ The ANX7625 is an ultra-low power 4K Mobile HD Transmitter
+ designed for portable devices.
+
+properties:
+ compatible:
+ items:
+ - const: analogix,anx7625
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: used for interrupt pin B8.
+ maxItems: 1
+
+ enable-gpios:
+ description: used for power on chip control, POWER_EN pin D2.
+ maxItems: 1
+
+ reset-gpios:
+ description: used for reset chip control, RESET_N pin B7.
+ maxItems: 1
+
+ ports:
+ type: object
+
+ properties:
+ port@0:
+ type: object
+ description:
+ Video port for MIPI DSI input.
+
+ port@1:
+ type: object
+ description:
+ Video port for panel or connector.
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ encoder@58 {
+ compatible = "analogix,anx7625";
+ reg = <0x58>;
+ enable-gpios = <&pio 45 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 73 GPIO_ACTIVE_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi2dp_bridge_in: port@0 {
+ reg = <0>;
+ anx7625_in: endpoint {
+ remote-endpoint = <&mipi_dsi>;
+ };
+ };
+
+ mipi2dp_bridge_out: port@1 {
+ reg = <1>;
+ anx7625_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/display/bridge/anx6345.yaml b/dts/Bindings/display/bridge/anx6345.yaml
index 8c0e4f285f..fccd63521a 100644
--- a/dts/Bindings/display/bridge/anx6345.yaml
+++ b/dts/Bindings/display/bridge/anx6345.yaml
@@ -26,11 +26,9 @@ properties:
description: GPIO connected to active low reset
dvdd12-supply:
- maxItems: 1
description: Regulator for 1.2V digital core power.
dvdd25-supply:
- maxItems: 1
description: Regulator for 2.5V digital core power.
ports:
diff --git a/dts/Bindings/display/bridge/intel,keembay-dsi.yaml b/dts/Bindings/display/bridge/intel,keembay-dsi.yaml
new file mode 100644
index 0000000000..35c9dfd866
--- /dev/null
+++ b/dts/Bindings/display/bridge/intel,keembay-dsi.yaml
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/intel,keembay-dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Devicetree bindings for Intel Keem Bay mipi dsi controller
+
+maintainers:
+ - Anitha Chrisanthus <anitha.chrisanthus@intel.com>
+ - Edmond J Dea <edmund.j.dea@intel.com>
+
+properties:
+ compatible:
+ const: intel,keembay-dsi
+
+ reg:
+ items:
+ - description: MIPI registers range
+
+ reg-names:
+ items:
+ - const: mipi
+
+ clocks:
+ items:
+ - description: MIPI DSI clock
+ - description: MIPI DSI econfig clock
+ - description: MIPI DSI config clock
+
+ clock-names:
+ items:
+ - const: clk_mipi
+ - const: clk_mipi_ecfg
+ - const: clk_mipi_cfg
+
+ ports:
+ type: object
+
+ properties:
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ port@0:
+ type: object
+ description: MIPI DSI input port.
+
+ port@1:
+ type: object
+ description: DSI output port.
+
+ required:
+ - port@0
+ - port@1
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ mipi-dsi@20900000 {
+ compatible = "intel,keembay-dsi";
+ reg = <0x20900000 0x4000>;
+ reg-names = "mipi";
+ clocks = <&scmi_clk 0x86>,
+ <&scmi_clk 0x88>,
+ <&scmi_clk 0x89>;
+ clock-names = "clk_mipi", "clk_mipi_ecfg",
+ "clk_mipi_cfg";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <&disp_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&adv7535_input>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/display/bridge/ite,it6505.yaml b/dts/Bindings/display/bridge/ite,it6505.yaml
index efbb3d0117..02cfc0a3b5 100644
--- a/dts/Bindings/display/bridge/ite,it6505.yaml
+++ b/dts/Bindings/display/bridge/ite,it6505.yaml
@@ -35,11 +35,9 @@ properties:
maxItems: 1
ovdd-supply:
- maxItems: 1
description: I/O voltage
pwr18-supply:
- maxItems: 1
description: core voltage
interrupts:
diff --git a/dts/Bindings/display/bridge/lontium,lt9611.yaml b/dts/Bindings/display/bridge/lontium,lt9611.yaml
index d602083592..7a1c89b995 100644
--- a/dts/Bindings/display/bridge/lontium,lt9611.yaml
+++ b/dts/Bindings/display/bridge/lontium,lt9611.yaml
@@ -4,18 +4,19 @@
$id: http://devicetree.org/schemas/display/bridge/lontium,lt9611.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Lontium LT9611 2 Port MIPI to HDMI Bridge
+title: Lontium LT9611(UXC) 2 Port MIPI to HDMI Bridge
maintainers:
- Vinod Koul <vkoul@kernel.org>
description: |
- The LT9611 is a bridge device which converts DSI to HDMI
+ The LT9611 and LT9611UXC are bridge devices which convert DSI to HDMI
properties:
compatible:
enum:
- lontium,lt9611
+ - lontium,lt9611uxc
reg:
maxItems: 1
diff --git a/dts/Bindings/display/bridge/lvds-codec.yaml b/dts/Bindings/display/bridge/lvds-codec.yaml
index e5e3c72630..66a14d60ce 100644
--- a/dts/Bindings/display/bridge/lvds-codec.yaml
+++ b/dts/Bindings/display/bridge/lvds-codec.yaml
@@ -79,8 +79,7 @@ properties:
The GPIO used to control the power down line of this device.
maxItems: 1
- power-supply:
- maxItems: 1
+ power-supply: true
required:
- compatible
diff --git a/dts/Bindings/display/bridge/ps8640.yaml b/dts/Bindings/display/bridge/ps8640.yaml
index 7e27cfcf77..763c790947 100644
--- a/dts/Bindings/display/bridge/ps8640.yaml
+++ b/dts/Bindings/display/bridge/ps8640.yaml
@@ -35,11 +35,9 @@ properties:
description: GPIO connected to active low reset.
vdd12-supply:
- maxItems: 1
description: Regulator for 1.2V digital core power.
vdd33-supply:
- maxItems: 1
description: Regulator for 3.3V digital core power.
ports:
diff --git a/dts/Bindings/display/bridge/sii902x.txt b/dts/Bindings/display/bridge/sii902x.txt
index 0d1db3f9da..02c21b5847 100644
--- a/dts/Bindings/display/bridge/sii902x.txt
+++ b/dts/Bindings/display/bridge/sii902x.txt
@@ -8,6 +8,8 @@ Optional properties:
- interrupts: describe the interrupt line used to inform the host
about hotplug events.
- reset-gpios: OF device-tree gpio specification for RST_N pin.
+ - iovcc-supply: I/O Supply Voltage (1.8V or 3.3V)
+ - cvcc12-supply: Digital Core Supply Voltage (1.2V)
HDMI audio properties:
- #sound-dai-cells: <0> or <1>. <0> if only i2s or spdif pin
@@ -54,6 +56,8 @@ Example:
compatible = "sil,sii9022";
reg = <0x39>;
reset-gpios = <&pioA 1 0>;
+ iovcc-supply = <&v3v3_hdmi>;
+ cvcc12-supply = <&v1v2_hdmi>;
#sound-dai-cells = <0>;
sil,i2s-data-lanes = < 0 1 2 >;
diff --git a/dts/Bindings/display/bridge/simple-bridge.yaml b/dts/Bindings/display/bridge/simple-bridge.yaml
index 3ddb35fcf0..64e8a1c24b 100644
--- a/dts/Bindings/display/bridge/simple-bridge.yaml
+++ b/dts/Bindings/display/bridge/simple-bridge.yaml
@@ -60,7 +60,6 @@ properties:
description: GPIO controlling bridge enable
vdd-supply:
- maxItems: 1
description: Power supply for the bridge
required:
diff --git a/dts/Bindings/display/bridge/thine,thc63lvd1024.yaml b/dts/Bindings/display/bridge/thine,thc63lvd1024.yaml
index 469ac4a342..3d5ce08a57 100644
--- a/dts/Bindings/display/bridge/thine,thc63lvd1024.yaml
+++ b/dts/Bindings/display/bridge/thine,thc63lvd1024.yaml
@@ -74,7 +74,6 @@ properties:
description: Power down GPIO signal, pin name "/PDWN", active low.
vcc-supply:
- maxItems: 1
description:
Power supply for the TTL output, TTL CLOCKOUT signal, LVDS input, PLL and
digital circuitry.
diff --git a/dts/Bindings/display/bridge/toshiba,tc358775.yaml b/dts/Bindings/display/bridge/toshiba,tc358775.yaml
index fd3113aa9c..b5959cc78b 100644
--- a/dts/Bindings/display/bridge/toshiba,tc358775.yaml
+++ b/dts/Bindings/display/bridge/toshiba,tc358775.yaml
@@ -28,11 +28,9 @@ properties:
description: i2c address of the bridge, 0x0f
vdd-supply:
- maxItems: 1
description: 1.2V LVDS Power Supply
vddio-supply:
- maxItems: 1
description: 1.8V IO Power Supply
stby-gpios:
diff --git a/dts/Bindings/display/imx/fsl-imx-drm.txt b/dts/Bindings/display/imx/fsl-imx-drm.txt
index 5a99490c17..3c35338a28 100644
--- a/dts/Bindings/display/imx/fsl-imx-drm.txt
+++ b/dts/Bindings/display/imx/fsl-imx-drm.txt
@@ -12,7 +12,7 @@ Required properties:
example:
display-subsystem {
- compatible = "fsl,display-subsystem";
+ compatible = "fsl,imx-display-subsystem";
ports = <&ipu_di0>;
};
diff --git a/dts/Bindings/display/intel,keembay-display.yaml b/dts/Bindings/display/intel,keembay-display.yaml
new file mode 100644
index 0000000000..0a697d45c2
--- /dev/null
+++ b/dts/Bindings/display/intel,keembay-display.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/intel,keembay-display.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Devicetree bindings for Intel Keem Bay display controller
+
+maintainers:
+ - Anitha Chrisanthus <anitha.chrisanthus@intel.com>
+ - Edmond J Dea <edmund.j.dea@intel.com>
+
+properties:
+ compatible:
+ const: intel,keembay-display
+
+ reg:
+ items:
+ - description: LCD registers range
+
+ reg-names:
+ items:
+ - const: lcd
+
+ clocks:
+ items:
+ - description: LCD controller clock
+ - description: pll0 clock
+
+ clock-names:
+ items:
+ - const: clk_lcd
+ - const: clk_pll0
+
+ interrupts:
+ maxItems: 1
+
+ port:
+ type: object
+ description: Display output node to DSI.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ display@20930000 {
+ compatible = "intel,keembay-display";
+ reg = <0x20930000 0x3000>;
+ reg-names = "lcd";
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 0x83>,
+ <&scmi_clk 0x0>;
+ clock-names = "clk_lcd", "clk_pll0";
+
+ port {
+ disp_out: endpoint {
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+ };
diff --git a/dts/Bindings/display/intel,keembay-msscam.yaml b/dts/Bindings/display/intel,keembay-msscam.yaml
new file mode 100644
index 0000000000..a222b52d8b
--- /dev/null
+++ b/dts/Bindings/display/intel,keembay-msscam.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/intel,keembay-msscam.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Devicetree bindings for Intel Keem Bay MSSCAM
+
+maintainers:
+ - Anitha Chrisanthus <anitha.chrisanthus@intel.com>
+ - Edmond J Dea <edmund.j.dea@intel.com>
+
+description: |
+ MSSCAM controls local clocks in the display subsystem namely LCD clocks and
+ MIPI DSI clocks. It also configures the interconnect between LCD and
+ MIPI DSI.
+
+properties:
+ compatible:
+ items:
+ - const: intel,keembay-msscam
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ reg-io-width:
+ const: 4
+
+required:
+ - compatible
+ - reg
+ - reg-io-width
+
+additionalProperties: false
+
+examples:
+ - |
+ msscam:msscam@20910000 {
+ compatible = "intel,keembay-msscam", "syscon";
+ reg = <0x20910000 0x30>;
+ reg-io-width = <4>;
+ };
diff --git a/dts/Bindings/display/mediatek/mediatek,disp.txt b/dts/Bindings/display/mediatek/mediatek,disp.txt
index 121220745d..33977e15be 100644
--- a/dts/Bindings/display/mediatek/mediatek,disp.txt
+++ b/dts/Bindings/display/mediatek/mediatek,disp.txt
@@ -43,7 +43,7 @@ Required properties (all function blocks):
"mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
"mediatek,<chip>-disp-mutex" - display mutex
"mediatek,<chip>-disp-od" - overdrive
- the supported chips are mt2701, mt7623, mt2712 and mt8173.
+ the supported chips are mt2701, mt7623, mt2712, mt8167 and mt8173.
- reg: Physical base address and length of the function block register space
- interrupts: The interrupt signal from the function block (required, except for
merge and split function blocks).
@@ -59,7 +59,7 @@ Required properties (DMA function blocks):
"mediatek,<chip>-disp-ovl"
"mediatek,<chip>-disp-rdma"
"mediatek,<chip>-disp-wdma"
- the supported chips are mt2701 and mt8173.
+ the supported chips are mt2701, mt8167 and mt8173.
- larb: Should contain a phandle pointing to the local arbiter device as defined
in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
- iommus: Should point to the respective IOMMU block with master port as
diff --git a/dts/Bindings/display/mediatek/mediatek,dpi.txt b/dts/Bindings/display/mediatek/mediatek,dpi.txt
deleted file mode 100644
index dc1ebd13cc..0000000000
--- a/dts/Bindings/display/mediatek/mediatek,dpi.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-Mediatek DPI Device
-===================
-
-The Mediatek DPI function block is a sink of the display subsystem and
-provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
-output bus.
-
-Required properties:
-- compatible: "mediatek,<chip>-dpi"
- the supported chips are mt2701, mt7623, mt8173 and mt8183.
-- reg: Physical base address and length of the controller's registers
-- interrupts: The interrupt signal from the function block.
-- clocks: device clocks
- See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- clock-names: must contain "pixel", "engine", and "pll"
-- port: Output port node with endpoint definitions as described in
- Documentation/devicetree/bindings/graph.txt. This port should be connected
- to the input port of an attached HDMI or LVDS encoder chip.
-
-Optional properties:
-- pinctrl-names: Contain "default" and "sleep".
-
-Example:
-
-dpi0: dpi@1401d000 {
- compatible = "mediatek,mt8173-dpi";
- reg = <0 0x1401d000 0 0x1000>;
- interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&mmsys CLK_MM_DPI_PIXEL>,
- <&mmsys CLK_MM_DPI_ENGINE>,
- <&apmixedsys CLK_APMIXED_TVDPLL>;
- clock-names = "pixel", "engine", "pll";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&dpi_pin_func>;
- pinctrl-1 = <&dpi_pin_idle>;
-
- port {
- dpi0_out: endpoint {
- remote-endpoint = <&hdmi0_in>;
- };
- };
-};
diff --git a/dts/Bindings/display/mediatek/mediatek,dpi.yaml b/dts/Bindings/display/mediatek/mediatek,dpi.yaml
new file mode 100644
index 0000000000..6cdb734c91
--- /dev/null
+++ b/dts/Bindings/display/mediatek/mediatek,dpi.yaml
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek DPI Controller Device Tree Bindings
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Jitao shi <jitao.shi@mediatek.com>
+
+description: |
+ The Mediatek DPI function block is a sink of the display subsystem and
+ provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
+ output bus.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt2701-dpi
+ - mediatek,mt7623-dpi
+ - mediatek,mt8173-dpi
+ - mediatek,mt8183-dpi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Pixel Clock
+ - description: Engine Clock
+ - description: DPI PLL
+
+ clock-names:
+ items:
+ - const: pixel
+ - const: engine
+ - const: pll
+
+ pinctrl-0: true
+ pinctrl-1: true
+
+ pinctrl-names:
+ items:
+ - const: default
+ - const: sleep
+
+ port:
+ type: object
+ description:
+ Output port node with endpoint definitions as described in
+ Documentation/devicetree/bindings/graph.txt. This port should be connected
+ to the input port of an attached HDMI or LVDS encoder chip.
+
+ properties:
+ endpoint:
+ type: object
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ dpi0: dpi@1401d000 {
+ compatible = "mediatek,mt8173-dpi";
+ reg = <0x1401d000 0x1000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys CLK_MM_DPI_PIXEL>,
+ <&mmsys CLK_MM_DPI_ENGINE>,
+ <&apmixedsys CLK_APMIXED_TVDPLL>;
+ clock-names = "pixel", "engine", "pll";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&dpi_pin_func>;
+ pinctrl-1 = <&dpi_pin_idle>;
+
+ port {
+ dpi0_out: endpoint {
+ remote-endpoint = <&hdmi0_in>;
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/display/msm/gpu.txt b/dts/Bindings/display/msm/gpu.txt
index 1af0ff102b..090dcb3fc3 100644
--- a/dts/Bindings/display/msm/gpu.txt
+++ b/dts/Bindings/display/msm/gpu.txt
@@ -39,6 +39,10 @@ Required properties:
a4xx Snapdragon SoCs. See
Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.
+Optional properties:
+- #cooling-cells: The value must be 2. For details, please refer
+ Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml.
+
Example 3xx/4xx:
/ {
@@ -61,6 +65,7 @@ Example 3xx/4xx:
power-domains = <&mmcc OXILICX_GDSC>;
operating-points-v2 = <&gpu_opp_table>;
iommus = <&gpu_iommu 0>;
+ #cooling-cells = <2>;
};
gpu_sram: ocmem@fdd00000 {
@@ -98,6 +103,8 @@ Example a6xx (with GMU):
reg = <0x5000000 0x40000>, <0x509e000 0x10>;
reg-names = "kgsl_3d0_reg_memory", "cx_mem";
+ #cooling-cells = <2>;
+
/*
* Look ma, no clocks! The GPU clocks and power are
* controlled entirely by the GMU
diff --git a/dts/Bindings/display/panel/abt,y030xx067a.yaml b/dts/Bindings/display/panel/abt,y030xx067a.yaml
new file mode 100644
index 0000000000..a108029ecf
--- /dev/null
+++ b/dts/Bindings/display/panel/abt,y030xx067a.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/abt,y030xx067a.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Asia Better Technology 3.0" (320x480 pixels) 24-bit IPS LCD panel
+
+description: |
+ The panel must obey the rules for a SPI slave device as specified in
+ spi/spi-controller.yaml
+
+maintainers:
+ - Paul Cercueil <paul@crapouillou.net>
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ const: abt,y030xx067a
+
+ backlight: true
+ port: true
+ power-supply: true
+ reg: true
+ reset-gpios: true
+
+required:
+ - compatible
+ - reg
+ - power-supply
+ - reset-gpios
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel@0 {
+ compatible = "abt,y030xx067a";
+ reg = <0>;
+
+ spi-max-frequency = <3125000>;
+
+ reset-gpios = <&gpe 2 GPIO_ACTIVE_LOW>;
+
+ backlight = <&backlight>;
+ power-supply = <&vcc>;
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&panel_output>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/display/panel/novatek,nt36672a.yaml b/dts/Bindings/display/panel/novatek,nt36672a.yaml
new file mode 100644
index 0000000000..2f5df1d235
--- /dev/null
+++ b/dts/Bindings/display/panel/novatek,nt36672a.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/novatek,nt36672a.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Novatek NT36672A based DSI display Panels
+
+maintainers:
+ - Sumit Semwal <sumit.semwal@linaro.org>
+
+description: |
+ The nt36672a IC from Novatek is a generic DSI Panel IC used to drive dsi
+ panels.
+ Right now, support is added only for a Tianma FHD+ LCD display panel with a
+ resolution of 1080x2246. It is a video mode DSI panel.
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - tianma,fhd-video
+ - const: novatek,nt36672a
+ description: This indicates the panel manufacturer of the panel that is
+ in turn using the NT36672A panel driver. This compatible string
+ determines how the NT36672A panel driver is configured for the indicated
+ panel. The novatek,nt36672a compatible shall always be provided as a fallback.
+
+ reset-gpios:
+ description: phandle of gpio for reset line - This should be 8mA, gpio
+ can be configured using mux, pinctrl, pinctrl-names (active high)
+
+ vddio-supply:
+ description: phandle of the regulator that provides the supply voltage
+ Power IC supply
+
+ vddpos-supply:
+ description: phandle of the positive boost supply regulator
+
+ vddneg-supply:
+ description: phandle of the negative boost supply regulator
+
+ reg: true
+ port: true
+
+required:
+ - compatible
+ - reg
+ - vddi0-supply
+ - vddpos-supply
+ - vddneg-supply
+ - reset-gpios
+ - port
+
+unevaluatedProperties: false
+
+examples:
+ - |+
+ #include <dt-bindings/gpio/gpio.h>
+
+ dsi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel@0 {
+ compatible = "tianma,fhd-video", "novatek,nt36672a";
+ reg = <0>;
+ vddi0-supply = <&vreg_l14a_1p88>;
+ vddpos-supply = <&lab>;
+ vddneg-supply = <&ibb>;
+
+ reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port {
+ tianma_nt36672a_in_0: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/display/panel/panel-simple-dsi.yaml b/dts/Bindings/display/panel/panel-simple-dsi.yaml
index c0dd9fa29f..72e4b6d4d5 100644
--- a/dts/Bindings/display/panel/panel-simple-dsi.yaml
+++ b/dts/Bindings/display/panel/panel-simple-dsi.yaml
@@ -47,6 +47,12 @@ properties:
- panasonic,vvx10f004b00
# Panasonic 10" WUXGA TFT LCD panel
- panasonic,vvx10f034n00
+ # Samsung s6e3fc2x01 1080x2340 AMOLED panel
+ - samsung,s6e3fc2x01
+ # Samsung sofef00 1080x2280 AMOLED panel
+ - samsung,sofef00
+ # Shangai Top Display Optoelectronics 7" TL070WSH30 1024x600 TFT LCD panel
+ - tdo,tl070wsh30
reg:
maxItems: 1
@@ -54,6 +60,7 @@ properties:
backlight: true
enable-gpios: true
+ reset-gpios: true
port: true
power-supply: true
diff --git a/dts/Bindings/display/panel/panel-simple.yaml b/dts/Bindings/display/panel/panel-simple.yaml
index edb53ab0d9..27fffafe5b 100644
--- a/dts/Bindings/display/panel/panel-simple.yaml
+++ b/dts/Bindings/display/panel/panel-simple.yaml
@@ -159,6 +159,8 @@ properties:
- innolux,g121x1-l03
# Innolux Corporation 11.6" WXGA (1366x768) TFT LCD panel
- innolux,n116bge
+ # InnoLux 13.3" FHD (1920x1080) eDP TFT LCD panel
+ - innolux,n125hce-gn1
# InnoLux 15.6" WXGA TFT LCD panel
- innolux,n156bge-l21
# Innolux Corporation 7.0" WSVGA (1024x600) TFT LCD panel
@@ -282,6 +284,8 @@ properties:
- vxt,vl050-8048nt-c01
# Winstar Display Corporation 3.5" QVGA (320x240) TFT LCD panel
- winstar,wf35ltiacd
+ # Yes Optoelectronics YTC700TLAG-05-201C 7" TFT LCD panel
+ - yes-optoelectronics,ytc700tlag-05-201c
backlight: true
enable-gpios: true
diff --git a/dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt b/dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt
index ac63ae4a38..34d9933384 100644
--- a/dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt
+++ b/dts/Bindings/display/tegra/nvidia,tegra20-host1x.txt
@@ -20,6 +20,10 @@ Required properties:
- reset-names: Must include the following entries:
- host1x
+Each host1x client module having to perform DMA through the Memory Controller
+should have the interconnect endpoints set to the Memory Client and External
+Memory respectively.
+
The host1x top-level node defines a number of children, each representing one
of the following host1x client modules:
@@ -36,6 +40,12 @@ of the following host1x client modules:
- reset-names: Must include the following entries:
- mpe
+ Optional properties:
+ - interconnects: Must contain entry for the MPE memory clients.
+ - interconnect-names: Must include name of the interconnect path for each
+ interconnect entry. Consult TRM documentation for information about
+ available memory clients, see MEMORY CONTROLLER section.
+
- vi: video input
Required properties:
@@ -113,6 +123,12 @@ of the following host1x client modules:
Required properties:
- remote-endpoint: phandle to vi port 'endpoint' node.
+ Optional properties:
+ - interconnects: Must contain entry for the VI memory clients.
+ - interconnect-names: Must include name of the interconnect path for each
+ interconnect entry. Consult TRM documentation for information about
+ available memory clients, see MEMORY CONTROLLER section.
+
- epp: encoder pre-processor
Required properties:
@@ -126,6 +142,12 @@ of the following host1x client modules:
- reset-names: Must include the following entries:
- epp
+ Optional properties:
+ - interconnects: Must contain entry for the EPP memory clients.
+ - interconnect-names: Must include name of the interconnect path for each
+ interconnect entry. Consult TRM documentation for information about
+ available memory clients, see MEMORY CONTROLLER section.
+
- isp: image signal processor
Required properties:
@@ -139,6 +161,12 @@ of the following host1x client modules:
- reset-names: Must include the following entries:
- isp
+ Optional properties:
+ - interconnects: Must contain entry for the ISP memory clients.
+ - interconnect-names: Must include name of the interconnect path for each
+ interconnect entry. Consult TRM documentation for information about
+ available memory clients, see MEMORY CONTROLLER section.
+
- gr2d: 2D graphics engine
Required properties:
@@ -152,6 +180,12 @@ of the following host1x client modules:
- reset-names: Must include the following entries:
- 2d
+ Optional properties:
+ - interconnects: Must contain entry for the GR2D memory clients.
+ - interconnect-names: Must include name of the interconnect path for each
+ interconnect entry. Consult TRM documentation for information about
+ available memory clients, see MEMORY CONTROLLER section.
+
- gr3d: 3D graphics engine
Required properties:
@@ -170,6 +204,12 @@ of the following host1x client modules:
- 3d
- 3d2 (Only required on SoCs with two 3D clocks)
+ Optional properties:
+ - interconnects: Must contain entry for the GR3D memory clients.
+ - interconnect-names: Must include name of the interconnect path for each
+ interconnect entry. Consult TRM documentation for information about
+ available memory clients, see MEMORY CONTROLLER section.
+
- dc: display controller
Required properties:
@@ -197,6 +237,10 @@ of the following host1x client modules:
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
- nvidia,edid: supplies a binary EDID blob
- nvidia,panel: phandle of a display panel
+ - interconnects: Must contain entry for the DC memory clients.
+ - interconnect-names: Must include name of the interconnect path for each
+ interconnect entry. Consult TRM documentation for information about
+ available memory clients, see MEMORY CONTROLLER section.
- hdmi: High Definition Multimedia Interface
@@ -345,6 +389,12 @@ of the following host1x client modules:
- reset-names: Must include the following entries:
- vic
+ Optional properties:
+ - interconnects: Must contain entry for the VIC memory clients.
+ - interconnect-names: Must include name of the interconnect path for each
+ interconnect entry. Consult TRM documentation for information about
+ available memory clients, see MEMORY CONTROLLER section.
+
Example:
/ {
@@ -498,6 +548,15 @@ Example:
resets = <&tegra_car 27>;
reset-names = "dc";
+ interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>,
+ <&mc TEGRA20_MC_DISPLAY0B &emc>,
+ <&mc TEGRA20_MC_DISPLAY0C &emc>,
+ <&mc TEGRA20_MC_DISPLAYHC &emc>;
+ interconnect-names = "wina",
+ "winb",
+ "winc",
+ "cursor";
+
rgb {
status = "disabled";
};
@@ -513,6 +572,15 @@ Example:
resets = <&tegra_car 26>;
reset-names = "dc";
+ interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>,
+ <&mc TEGRA20_MC_DISPLAY0BB &emc>,
+ <&mc TEGRA20_MC_DISPLAY0CB &emc>,
+ <&mc TEGRA20_MC_DISPLAYHCB &emc>;
+ interconnect-names = "wina",
+ "winb",
+ "winc",
+ "cursor";
+
rgb {
status = "disabled";
};
diff --git a/dts/Bindings/display/ti/ti,am65x-dss.yaml b/dts/Bindings/display/ti/ti,am65x-dss.yaml
index 4f9185462e..4dc30738ee 100644
--- a/dts/Bindings/display/ti/ti,am65x-dss.yaml
+++ b/dts/Bindings/display/ti/ti,am65x-dss.yaml
@@ -55,6 +55,14 @@ properties:
- const: vp1
- const: vp2
+ assigned-clocks:
+ minItems: 1
+ maxItems: 3
+
+ assigned-clock-parents:
+ minItems: 1
+ maxItems: 3
+
interrupts:
maxItems: 1
@@ -62,6 +70,9 @@ properties:
maxItems: 1
description: phandle to the associated power domain
+ dma-coherent:
+ type: boolean
+
ports:
type: object
description:
diff --git a/dts/Bindings/display/ti/ti,j721e-dss.yaml b/dts/Bindings/display/ti/ti,j721e-dss.yaml
index 173730d563..c9a947d55f 100644
--- a/dts/Bindings/display/ti/ti,j721e-dss.yaml
+++ b/dts/Bindings/display/ti/ti,j721e-dss.yaml
@@ -77,6 +77,14 @@ properties:
- const: vp3
- const: vp4
+ assigned-clocks:
+ minItems: 1
+ maxItems: 5
+
+ assigned-clock-parents:
+ minItems: 1
+ maxItems: 5
+
interrupts:
items:
- description: common_m DSS Master common
@@ -95,6 +103,9 @@ properties:
maxItems: 1
description: phandle to the associated power domain
+ dma-coherent:
+ type: boolean
+
ports:
type: object
description:
diff --git a/dts/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml b/dts/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml
index 7b9d468c3e..403d57977e 100644
--- a/dts/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml
+++ b/dts/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml
@@ -98,7 +98,6 @@ properties:
maxItems: 1
dmas:
- maxItems: 4
items:
- description: Video layer, plane 0 (RGB or luma)
- description: Video layer, plane 1 (U/V or U)
diff --git a/dts/Bindings/dma/allwinner,sun50i-a64-dma.yaml b/dts/Bindings/dma/allwinner,sun50i-a64-dma.yaml
index 372679dbd2..b6e1ebfaf3 100644
--- a/dts/Bindings/dma/allwinner,sun50i-a64-dma.yaml
+++ b/dts/Bindings/dma/allwinner,sun50i-a64-dma.yaml
@@ -21,6 +21,7 @@ properties:
compatible:
oneOf:
- const: allwinner,sun50i-a64-dma
+ - const: allwinner,sun50i-a100-dma
- const: allwinner,sun50i-h6-dma
- items:
- const: allwinner,sun8i-r40-dma
@@ -56,7 +57,9 @@ required:
if:
properties:
compatible:
- const: allwinner,sun50i-h6-dma
+ enum:
+ - allwinner,sun50i-a100-dma
+ - allwinner,sun50i-h6-dma
then:
properties:
diff --git a/dts/Bindings/dma/atmel-xdma.txt b/dts/Bindings/dma/atmel-xdma.txt
index 4dc398e1a3..510b7f25ba 100644
--- a/dts/Bindings/dma/atmel-xdma.txt
+++ b/dts/Bindings/dma/atmel-xdma.txt
@@ -2,7 +2,8 @@
* XDMA Controller
Required properties:
-- compatible: Should be "atmel,sama5d4-dma" or "microchip,sam9x60-dma".
+- compatible: Should be "atmel,sama5d4-dma", "microchip,sam9x60-dma" or
+ "microchip,sama7g5-dma".
- reg: Should contain DMA registers location and length.
- interrupts: Should contain DMA interrupt.
- #dma-cells: Must be <1>, used to represent the number of integer cells in
diff --git a/dts/Bindings/dma/dma-common.yaml b/dts/Bindings/dma/dma-common.yaml
index 307b499e89..ad06d36af2 100644
--- a/dts/Bindings/dma/dma-common.yaml
+++ b/dts/Bindings/dma/dma-common.yaml
@@ -38,12 +38,12 @@ properties:
maxItems: 255
dma-channels:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description:
Number of DMA channels supported by the controller.
dma-requests:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description:
Number of DMA request signals supported by the controller.
diff --git a/dts/Bindings/dma/dma-router.yaml b/dts/Bindings/dma/dma-router.yaml
index 4cee5667b8..e72748496f 100644
--- a/dts/Bindings/dma/dma-router.yaml
+++ b/dts/Bindings/dma/dma-router.yaml
@@ -23,7 +23,7 @@ properties:
pattern: "^dma-router(@.*)?$"
dma-masters:
- $ref: /schemas/types.yaml#definitions/phandle-array
+ $ref: /schemas/types.yaml#/definitions/phandle-array
description:
Array of phandles to the DMA controllers the router can direct
the signal to.
diff --git a/dts/Bindings/dma/ingenic,dma.yaml b/dts/Bindings/dma/ingenic,dma.yaml
index 00f19b3cac..6a2043721b 100644
--- a/dts/Bindings/dma/ingenic,dma.yaml
+++ b/dts/Bindings/dma/ingenic,dma.yaml
@@ -48,7 +48,7 @@ properties:
ingenic,reserved-channels property.
ingenic,reserved-channels:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description: >
Bitmask of channels to reserve for devices that need a specific
channel. These channels will only be assigned when explicitely
diff --git a/dts/Bindings/dma/mtk-uart-apdma.txt b/dts/Bindings/dma/mtk-uart-apdma.txt
index 2117db0ce4..fef9c1eeb2 100644
--- a/dts/Bindings/dma/mtk-uart-apdma.txt
+++ b/dts/Bindings/dma/mtk-uart-apdma.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible should contain:
* "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA
* "mediatek,mt6577-uart-dma" for MT6577 and all of the above
+ * "mediatek,mt8516-uart-dma", "mediatek,mt6577" for MT8516 SoC
- reg: The base address of the APDMA register bank.
diff --git a/dts/Bindings/dma/nvidia,tegra210-adma.txt b/dts/Bindings/dma/nvidia,tegra210-adma.txt
deleted file mode 100644
index 245d306371..0000000000
--- a/dts/Bindings/dma/nvidia,tegra210-adma.txt
+++ /dev/null
@@ -1,56 +0,0 @@
-* NVIDIA Tegra Audio DMA (ADMA) controller
-
-The Tegra Audio DMA controller that is used for transferring data
-between system memory and the Audio Processing Engine (APE).
-
-Required properties:
-- compatible: Should contain one of the following:
- - "nvidia,tegra210-adma": for Tegra210
- - "nvidia,tegra186-adma": for Tegra186 and Tegra194
-- reg: Should contain DMA registers location and length. This should be
- a single entry that includes all of the per-channel registers in one
- contiguous bank.
-- interrupts: Should contain all of the per-channel DMA interrupts in
- ascending order with respect to the DMA channel index.
-- clocks: Must contain one entry for the ADMA module clock
- (TEGRA210_CLK_D_AUDIO).
-- clock-names: Must contain the name "d_audio" for the corresponding
- 'clocks' entry.
-- #dma-cells : Must be 1. The first cell denotes the receive/transmit
- request number and should be between 1 and the maximum number of
- requests supported. This value corresponds to the RX/TX_REQUEST_SELECT
- fields in the ADMA_CHn_CTRL register.
-
-
-Example:
-
-adma: dma@702e2000 {
- compatible = "nvidia,tegra210-adma";
- reg = <0x0 0x702e2000 0x0 0x2000>;
- interrupt-parent = <&tegra_agic>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
- clock-names = "d_audio";
- #dma-cells = <1>;
-};
diff --git a/dts/Bindings/dma/nvidia,tegra210-adma.yaml b/dts/Bindings/dma/nvidia,tegra210-adma.yaml
new file mode 100644
index 0000000000..5c2e2f156e
--- /dev/null
+++ b/dts/Bindings/dma/nvidia,tegra210-adma.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/nvidia,tegra210-adma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Audio DMA (ADMA) controller
+
+description: |
+ The Tegra Audio DMA controller is used for transferring data
+ between system memory and the Audio Processing Engine (APE).
+
+maintainers:
+ - Jon Hunter <jonathanh@nvidia.com>
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - nvidia,tegra210-adma
+ - nvidia,tegra186-adma
+ - items:
+ - const: nvidia,tegra194-adma
+ - const: nvidia,tegra186-adma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: |
+ Should contain all of the per-channel DMA interrupts in
+ ascending order with respect to the DMA channel index.
+ minItems: 1
+ maxItems: 32
+
+ clocks:
+ description: Must contain one entry for the ADMA module clock
+ maxItems: 1
+
+ clock-names:
+ const: d_audio
+
+ "#dma-cells":
+ description: |
+ The first cell denotes the receive/transmit request number and
+ should be between 1 and the maximum number of requests supported.
+ This value corresponds to the RX/TX_REQUEST_SELECT fields in the
+ ADMA_CHn_CTRL register.
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include<dt-bindings/clock/tegra210-car.h>
+
+ dma-controller@702e2000 {
+ compatible = "nvidia,tegra210-adma";
+ reg = <0x702e2000 0x2000>;
+ interrupt-parent = <&tegra_agic>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
+ clock-names = "d_audio";
+ #dma-cells = <1>;
+ };
+
+...
diff --git a/dts/Bindings/dma/qcom,gpi.yaml b/dts/Bindings/dma/qcom,gpi.yaml
new file mode 100644
index 0000000000..f8142adf9a
--- /dev/null
+++ b/dts/Bindings/dma/qcom,gpi.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies Inc GPI DMA controller
+
+maintainers:
+ - Vinod Koul <vkoul@kernel.org>
+
+description: |
+ QCOM GPI DMA controller provides DMA capabilities for
+ peripheral buses such as I2C, UART, and SPI.
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ compatible:
+ enum:
+ - qcom,sdm845-gpi-dma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ Interrupt lines for each GPI instance
+ maxItems: 13
+
+ "#dma-cells":
+ const: 3
+ description: >
+ DMA clients must use the format described in dma.txt, giving a phandle
+ to the DMA controller plus the following 3 integer cells:
+ - channel: if set to 0xffffffff, any available channel will be allocated
+ for the client. Otherwise, the exact channel specified will be used.
+ - seid: serial id of the client as defined in the SoC documentation.
+ - client: type of the client as defined in dt-bindings/dma/qcom-gpi.h
+
+ iommus:
+ maxItems: 1
+
+ dma-channels:
+ maximum: 31
+
+ dma-channel-mask:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#dma-cells"
+ - iommus
+ - dma-channels
+ - dma-channel-mask
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/dma/qcom-gpi.h>
+ gpi_dma0: dma-controller@800000 {
+ compatible = "qcom,gpi-dma";
+ #dma-cells = <3>;
+ reg = <0x00800000 0x60000>;
+ iommus = <&apps_smmu 0x0016 0x0>;
+ dma-channels = <13>;
+ dma-channel-mask = <0xfa>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+...
diff --git a/dts/Bindings/dma/renesas,rcar-dmac.yaml b/dts/Bindings/dma/renesas,rcar-dmac.yaml
index b548e47239..c07eb6f2fc 100644
--- a/dts/Bindings/dma/renesas,rcar-dmac.yaml
+++ b/dts/Bindings/dma/renesas,rcar-dmac.yaml
@@ -73,7 +73,6 @@ properties:
maxItems: 1
clock-names:
- maxItems: 1
items:
- const: fck
diff --git a/dts/Bindings/dma/snps,dma-spear1340.yaml b/dts/Bindings/dma/snps,dma-spear1340.yaml
index ef1d6879c1..6b35089ac0 100644
--- a/dts/Bindings/dma/snps,dma-spear1340.yaml
+++ b/dts/Bindings/dma/snps,dma-spear1340.yaml
@@ -54,7 +54,7 @@ properties:
maximum: 16
dma-masters:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description: |
Number of DMA masters supported by the controller. In case if
not specified the driver will try to auto-detect this and
@@ -63,7 +63,7 @@ properties:
maximum: 4
chan_allocation_order:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description: |
DMA channels allocation order specifier. Zero means ascending order
(first free allocated), while one - descending (last free allocated).
@@ -71,7 +71,7 @@ properties:
enum: [0, 1]
chan_priority:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description: |
DMA channels priority order. Zero means ascending channels priority
so the very first channel has the highest priority. While 1 means
@@ -80,7 +80,7 @@ properties:
enum: [0, 1]
block_size:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description: Maximum block size supported by the DMA controller.
enum: [3, 7, 15, 31, 63, 127, 255, 511, 1023, 2047, 4095]
@@ -139,7 +139,7 @@ properties:
default: 256
snps,dma-protection-control:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description: |
Bits one-to-one passed to the AHB HPROT[3:1] bus. Each bit setting
indicates the following features: bit 0 - privileged mode,
diff --git a/dts/Bindings/dma/ti/k3-bcdma.yaml b/dts/Bindings/dma/ti/k3-bcdma.yaml
new file mode 100644
index 0000000000..b15f68c499
--- /dev/null
+++ b/dts/Bindings/dma/ti/k3-bcdma.yaml
@@ -0,0 +1,164 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/ti/k3-bcdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments K3 DMSS BCDMA Device Tree Bindings
+
+maintainers:
+ - Peter Ujfalusi <peter.ujfalusi@ti.com>
+
+description: |
+ The Block Copy DMA (BCDMA) is intended to perform similar functions as the TR
+ mode channels of K3 UDMA-P.
+ BCDMA includes block copy channels and Split channels.
+
+ Block copy channels mainly used for memory to memory transfers, but with
+ optional triggers a block copy channel can service peripherals by accessing
+ directly to memory mapped registers or area.
+
+ Split channels can be used to service PSI-L based peripherals.
+ The peripherals can be PSI-L native or legacy, non PSI-L native peripherals
+ with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the
+ legacy peripheral.
+
+ PDMAs can be configured via BCDMA split channel's peer registers to match with
+ the configuration of the legacy peripheral.
+
+allOf:
+ - $ref: /schemas/dma/dma-controller.yaml#
+
+properties:
+ compatible:
+ const: ti,am64-dmss-bcdma
+
+ "#dma-cells":
+ const: 3
+ description: |
+ cell 1: type of the BCDMA channel to be used to service the peripheral:
+ 0 - split channel
+ 1 - block copy channel using global trigger 1
+ 2 - block copy channel using global trigger 2
+ 3 - block copy channel using local trigger
+
+ cell 2: parameter for the channel:
+ if cell 1 is 0 (split channel):
+ PSI-L thread ID of the remote (to BCDMA) end.
+ Valid ranges for thread ID depends on the data movement direction:
+ for source thread IDs (rx): 0 - 0x7fff
+ for destination thread IDs (tx): 0x8000 - 0xffff
+
+ Please refer to the device documentation for the PSI-L thread map and
+ also the PSI-L peripheral chapter for the correct thread ID.
+ if cell 1 is 1 or 2 (block copy channel using global trigger):
+ Unused, ignored
+
+ The trigger must be configured for the channel externally to BCDMA,
+ channels using global triggers should not be requested directly, but
+ via DMA event router.
+ if cell 1 is 3 (block copy channel using local trigger):
+ bchan number of the locally triggered channel
+
+ cell 3: ASEL value for the channel
+
+ reg:
+ maxItems: 5
+
+ reg-names:
+ items:
+ - const: gcfg
+ - const: bchanrt
+ - const: rchanrt
+ - const: tchanrt
+ - const: ringrt
+
+ msi-parent: true
+
+ ti,asel:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: ASEL value for non slave channels
+
+ ti,sci-rm-range-bchan:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ Array of BCDMA block-copy channel resource subtypes for resource
+ allocation for this host
+ minItems: 1
+ # Should be enough
+ maxItems: 255
+ items:
+ maximum: 0x3f
+
+ ti,sci-rm-range-tchan:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ Array of BCDMA split tx channel resource subtypes for resource allocation
+ for this host
+ minItems: 1
+ # Should be enough
+ maxItems: 255
+ items:
+ maximum: 0x3f
+
+ ti,sci-rm-range-rchan:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ Array of BCDMA split rx channel resource subtypes for resource allocation
+ for this host
+ minItems: 1
+ # Should be enough
+ maxItems: 255
+ items:
+ maximum: 0x3f
+
+required:
+ - compatible
+ - "#dma-cells"
+ - reg
+ - reg-names
+ - msi-parent
+ - ti,sci
+ - ti,sci-dev-id
+ - ti,sci-rm-range-bchan
+ - ti,sci-rm-range-tchan
+ - ti,sci-rm-range-rchan
+
+unevaluatedProperties: false
+
+examples:
+ - |+
+ cbass_main {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ main_dmss {
+ compatible = "simple-mfd";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges;
+ ranges;
+
+ ti,sci-dev-id = <25>;
+
+ main_bcdma: dma-controller@485c0100 {
+ compatible = "ti,am64-dmss-bcdma";
+
+ reg = <0x0 0x485c0100 0x0 0x100>,
+ <0x0 0x4c000000 0x0 0x20000>,
+ <0x0 0x4a820000 0x0 0x20000>,
+ <0x0 0x4aa40000 0x0 0x20000>,
+ <0x0 0x4bc00000 0x0 0x100000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
+ msi-parent = <&inta_main_dmss>;
+ #dma-cells = <3>;
+
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <26>;
+
+ ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
+ ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
+ ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
+ };
+ };
+ };
diff --git a/dts/Bindings/dma/ti/k3-pktdma.yaml b/dts/Bindings/dma/ti/k3-pktdma.yaml
new file mode 100644
index 0000000000..b13ab60cd7
--- /dev/null
+++ b/dts/Bindings/dma/ti/k3-pktdma.yaml
@@ -0,0 +1,172 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/ti/k3-pktdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments K3 DMSS PKTDMA Device Tree Bindings
+
+maintainers:
+ - Peter Ujfalusi <peter.ujfalusi@ti.com>
+
+description: |
+ The Packet DMA (PKTDMA) is intended to perform similar functions as the packet
+ mode channels of K3 UDMA-P.
+ PKTDMA only includes Split channels to service PSI-L based peripherals.
+
+ The peripherals can be PSI-L native or legacy, non PSI-L native peripherals
+ with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the
+ legacy peripheral.
+
+ PDMAs can be configured via PKTDMA split channel's peer registers to match
+ with the configuration of the legacy peripheral.
+
+allOf:
+ - $ref: /schemas/dma/dma-controller.yaml#
+
+properties:
+ compatible:
+ const: ti,am64-dmss-pktdma
+
+ "#dma-cells":
+ const: 2
+ description: |
+ The first cell is the PSI-L thread ID of the remote (to PKTDMA) end.
+ Valid ranges for thread ID depends on the data movement direction:
+ for source thread IDs (rx): 0 - 0x7fff
+ for destination thread IDs (tx): 0x8000 - 0xffff
+
+ Please refer to the device documentation for the PSI-L thread map and also
+ the PSI-L peripheral chapter for the correct thread ID.
+
+ The second cell is the ASEL value for the channel
+
+ reg:
+ maxItems: 4
+
+ reg-names:
+ items:
+ - const: gcfg
+ - const: rchanrt
+ - const: tchanrt
+ - const: ringrt
+
+ msi-parent: true
+
+ ti,sci-rm-range-tchan:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ Array of PKTDMA split tx channel resource subtypes for resource allocation
+ for this host
+ minItems: 1
+ # Should be enough
+ maxItems: 255
+ items:
+ maximum: 0x3f
+
+ ti,sci-rm-range-tflow:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ Array of PKTDMA split tx flow resource subtypes for resource allocation
+ for this host
+ minItems: 1
+ # Should be enough
+ maxItems: 255
+ items:
+ maximum: 0x3f
+
+ ti,sci-rm-range-rchan:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ Array of PKTDMA split rx channel resource subtypes for resource allocation
+ for this host
+ minItems: 1
+ # Should be enough
+ maxItems: 255
+ items:
+ maximum: 0x3f
+
+ ti,sci-rm-range-rflow:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ Array of PKTDMA split rx flow resource subtypes for resource allocation
+ for this host
+ minItems: 1
+ # Should be enough
+ maxItems: 255
+ items:
+ maximum: 0x3f
+
+required:
+ - compatible
+ - "#dma-cells"
+ - reg
+ - reg-names
+ - msi-parent
+ - ti,sci
+ - ti,sci-dev-id
+ - ti,sci-rm-range-tchan
+ - ti,sci-rm-range-tflow
+ - ti,sci-rm-range-rchan
+ - ti,sci-rm-range-rflow
+
+unevaluatedProperties: false
+
+examples:
+ - |+
+ cbass_main {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ main_dmss {
+ compatible = "simple-mfd";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges;
+ ranges;
+
+ ti,sci-dev-id = <25>;
+
+ main_pktdma: dma-controller@485c0000 {
+ compatible = "ti,am64-dmss-pktdma";
+
+ reg = <0x0 0x485c0000 0x0 0x100>,
+ <0x0 0x4a800000 0x0 0x20000>,
+ <0x0 0x4aa00000 0x0 0x40000>,
+ <0x0 0x4b800000 0x0 0x400000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
+ msi-parent = <&inta_main_dmss>;
+ #dma-cells = <2>;
+
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <30>;
+
+ ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
+ <0x24>, /* CPSW_TX_CHAN */
+ <0x25>, /* SAUL_TX_0_CHAN */
+ <0x26>, /* SAUL_TX_1_CHAN */
+ <0x27>, /* ICSSG_0_TX_CHAN */
+ <0x28>; /* ICSSG_1_TX_CHAN */
+ ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
+ <0x11>, /* RING_CPSW_TX_CHAN */
+ <0x12>, /* RING_SAUL_TX_0_CHAN */
+ <0x13>, /* RING_SAUL_TX_1_CHAN */
+ <0x14>, /* RING_ICSSG_0_TX_CHAN */
+ <0x15>; /* RING_ICSSG_1_TX_CHAN */
+ ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
+ <0x2b>, /* CPSW_RX_CHAN */
+ <0x2d>, /* SAUL_RX_0_CHAN */
+ <0x2f>, /* SAUL_RX_1_CHAN */
+ <0x31>, /* SAUL_RX_2_CHAN */
+ <0x33>, /* SAUL_RX_3_CHAN */
+ <0x35>, /* ICSSG_0_RX_CHAN */
+ <0x37>; /* ICSSG_1_RX_CHAN */
+ ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
+ <0x2c>, /* FLOW_CPSW_RX_CHAN */
+ <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
+ <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
+ <0x36>, /* FLOW_ICSSG_0_RX_CHAN */
+ <0x38>; /* FLOW_ICSSG_1_RX_CHAN */
+ };
+ };
+ };
diff --git a/dts/Bindings/edac/aspeed-sdram-edac.txt b/dts/Bindings/edac/aspeed-sdram-edac.txt
index 6a0f3d90d6..8ca9e0a049 100644
--- a/dts/Bindings/edac/aspeed-sdram-edac.txt
+++ b/dts/Bindings/edac/aspeed-sdram-edac.txt
@@ -1,6 +1,6 @@
-Aspeed AST2500 SoC EDAC node
+Aspeed BMC SoC EDAC node
-The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC (error
+The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
correction check).
The memory controller supports SECDED (single bit error correction, double bit
@@ -11,7 +11,10 @@ Note, the bootloader must configure ECC mode in the memory controller.
Required properties:
-- compatible: should be "aspeed,ast2500-sdram-edac"
+- compatible: should be one of
+ - "aspeed,ast2400-sdram-edac"
+ - "aspeed,ast2500-sdram-edac"
+ - "aspeed,ast2600-sdram-edac"
- reg: sdram controller register set should be <0x1e6e0000 0x174>
- interrupts: should be AVIC interrupt #0
diff --git a/dts/Bindings/eeprom/at24.yaml b/dts/Bindings/eeprom/at24.yaml
index 6edfa705b4..d5117c638b 100644
--- a/dts/Bindings/eeprom/at24.yaml
+++ b/dts/Bindings/eeprom/at24.yaml
@@ -131,7 +131,7 @@ properties:
default: 1
read-only:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
Disables writes to the eeprom.
@@ -141,7 +141,7 @@ properties:
Total eeprom size in bytes.
no-read-rollover:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
Indicates that the multi-address eeprom does not automatically roll
over reads to the next slave address. Please consult the manual of
diff --git a/dts/Bindings/eeprom/at25.yaml b/dts/Bindings/eeprom/at25.yaml
index 7449736376..121a601db2 100644
--- a/dts/Bindings/eeprom/at25.yaml
+++ b/dts/Bindings/eeprom/at25.yaml
@@ -45,13 +45,13 @@ properties:
spi-max-frequency: true
pagesize:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, 131072]
description:
Size of the eeprom page.
size:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description:
Total eeprom size in bytes.
diff --git a/dts/Bindings/extcon/extcon-fsa9480.txt b/dts/Bindings/extcon/extcon-fsa9480.txt
deleted file mode 100644
index 624bd76f46..0000000000
--- a/dts/Bindings/extcon/extcon-fsa9480.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-FAIRCHILD SEMICONDUCTOR FSA9480 MICROUSB SWITCH
-
-The FSA9480 is a USB port accessory detector and switch. The FSA9480 is fully
-controlled using I2C and enables USB data, stereo and mono audio, video,
-microphone, and UART data to use a common connector port.
-
-Required properties:
- - compatible : Must be one of
- "fcs,fsa9480"
- "fcs,fsa880"
- - reg : Specifies i2c slave address. Must be 0x25.
- - interrupts : Should contain one entry specifying interrupt signal of
- interrupt parent to which interrupt pin of the chip is connected.
-
- Example:
- musb@25 {
- compatible = "fcs,fsa9480";
- reg = <0x25>;
- interrupt-parent = <&gph2>;
- interrupts = <7 0>;
- };
diff --git a/dts/Bindings/extcon/extcon-usbc-tusb320.yaml b/dts/Bindings/extcon/extcon-usbc-tusb320.yaml
new file mode 100644
index 0000000000..9875b4d5c3
--- /dev/null
+++ b/dts/Bindings/extcon/extcon-usbc-tusb320.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/extcon/extcon-usbc-tusb320.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI TUSB320 USB Type-C CC Logic controller
+
+maintainers:
+ - Michael Auchter <michael.auchter@ni.com>
+
+properties:
+ compatible:
+ const: ti,tusb320
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ tusb320@61 {
+ compatible = "ti,tusb320";
+ reg = <0x61>;
+ interrupt-parent = <&gpio>;
+ interrupts = <27 1>;
+ };
+ };
+...
diff --git a/dts/Bindings/extcon/fcs,fsa880.yaml b/dts/Bindings/extcon/fcs,fsa880.yaml
new file mode 100644
index 0000000000..ef6a246a13
--- /dev/null
+++ b/dts/Bindings/extcon/fcs,fsa880.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/extcon/fcs,fsa880.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Fairchild Semiconductor FSA880, FSA9480 and compatibles
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+description:
+ The FSA880 and FSA9480 are USB port accessory detectors and switches.
+ The switch is fully controlled using I2C and enables USB data, stereo
+ and mono audio, video, microphone, and UART data to use a common
+ connector port. Compatible switches exist from other manufacturers.
+
+properties:
+ compatible:
+ enum:
+ - fcs,fsa880
+ - fcs,fsa9480
+ - ti,tsu6111
+
+ reg:
+ maxItems: 1
+ description: The I2C address for an FSA880 compatible device is
+ usually 0x25.
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ usb-switch@25 {
+ compatible = "fcs,fsa880";
+ reg = <0x25>;
+ interrupt-parent = <&gpio>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
diff --git a/dts/Bindings/fsi/ibm,p9-occ.txt b/dts/Bindings/fsi/ibm,p9-occ.txt
index 99ca9862a5..e73358075a 100644
--- a/dts/Bindings/fsi/ibm,p9-occ.txt
+++ b/dts/Bindings/fsi/ibm,p9-occ.txt
@@ -1,13 +1,13 @@
-Device-tree bindings for FSI-attached POWER9 On-Chip Controller (OCC)
----------------------------------------------------------------------
+Device-tree bindings for FSI-attached POWER9/POWER10 On-Chip Controller (OCC)
+-----------------------------------------------------------------------------
-This is the binding for the P9 On-Chip Controller accessed over FSI from a
-service processor. See fsi.txt for details on bindings for FSI slave and CFAM
+This is the binding for the P9 or P10 On-Chip Controller accessed over FSI from
+a service processor. See fsi.txt for details on bindings for FSI slave and CFAM
nodes. The OCC is not an FSI slave device itself, rather it is accessed
-through the SBE fifo.
+through the SBE FIFO.
Required properties:
- - compatible = "ibm,p9-occ"
+ - compatible = "ibm,p9-occ" or "ibm,p10-occ"
Examples:
diff --git a/dts/Bindings/gpio/gpio-pca95xx.yaml b/dts/Bindings/gpio/gpio-pca95xx.yaml
index 183ec23eda..f5ee23c2df 100644
--- a/dts/Bindings/gpio/gpio-pca95xx.yaml
+++ b/dts/Bindings/gpio/gpio-pca95xx.yaml
@@ -48,6 +48,7 @@ properties:
- nxp,pcal6416
- nxp,pcal6524
- nxp,pcal9535
+ - nxp,pcal9554b
- nxp,pcal9555a
- onnn,cat9554
- onnn,pca9654
diff --git a/dts/Bindings/gpio/gpio-xilinx.txt b/dts/Bindings/gpio/gpio-xilinx.txt
index 08eed2335d..e506f30e1a 100644
--- a/dts/Bindings/gpio/gpio-xilinx.txt
+++ b/dts/Bindings/gpio/gpio-xilinx.txt
@@ -13,6 +13,7 @@ Required properties:
- gpio-controller : Marks the device node as a GPIO controller.
Optional properties:
+- clocks : Input clock specifier. Refer to common clock bindings.
- interrupts : Interrupt mapping for GPIO IRQ.
- xlnx,all-inputs : if n-th bit is setup, GPIO-n is input
- xlnx,dout-default : if n-th bit is 1, GPIO-n default value is 1
@@ -29,6 +30,7 @@ Example:
gpio: gpio@40000000 {
#gpio-cells = <2>;
compatible = "xlnx,xps-gpio-1.00.a";
+ clocks = <&clkc25>;
gpio-controller ;
interrupt-parent = <&microblaze_0_intc>;
interrupts = < 6 2 >;
diff --git a/dts/Bindings/gpio/mediatek,mt7621-gpio.txt b/dts/Bindings/gpio/mediatek,mt7621-gpio.txt
deleted file mode 100644
index e1c49b660d..0000000000
--- a/dts/Bindings/gpio/mediatek,mt7621-gpio.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-Mediatek MT7621 SoC GPIO controller bindings
-
-The IP core used inside these SoCs has 3 banks of 32 GPIOs each.
-The registers of all the banks are interwoven inside one single IO range.
-We load one GPIO controller instance per bank. Also the GPIO controller can receive
-interrupts on any of the GPIOs, either edge or level. It then interrupts the CPU
-using GIC INT12.
-
-Required properties for the top level node:
-- #gpio-cells : Should be two. The first cell is the GPIO pin number and the
- second cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>.
- Only the GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
-- #interrupt-cells : Specifies the number of cells needed to encode an
- interrupt. Should be 2. The first cell defines the interrupt number,
- the second encodes the trigger flags encoded as described in
- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
-- compatible:
- - "mediatek,mt7621-gpio" for Mediatek controllers
-- reg : Physical base address and length of the controller's registers
-- interrupt-parent : phandle of the parent interrupt controller.
-- interrupts : Interrupt specifier for the controllers interrupt.
-- interrupt-controller : Mark the device node as an interrupt controller.
-- gpio-controller : Marks the device node as a GPIO controller.
-
-Example:
- gpio@600 {
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- compatible = "mediatek,mt7621-gpio";
- gpio-controller;
- interrupt-controller;
- reg = <0x600 0x100>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
- };
diff --git a/dts/Bindings/gpio/mediatek,mt7621-gpio.yaml b/dts/Bindings/gpio/mediatek,mt7621-gpio.yaml
new file mode 100644
index 0000000000..5bbb2a3126
--- /dev/null
+++ b/dts/Bindings/gpio/mediatek,mt7621-gpio.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/mediatek,mt7621-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek MT7621 SoC GPIO controller
+
+maintainers:
+ - Sergio Paracuellos <sergio.paracuellos@gmail.com>
+
+description: |
+ The IP core used inside these SoCs has 3 banks of 32 GPIOs each.
+ The registers of all the banks are interwoven inside one single IO range.
+ We load one GPIO controller instance per bank. Also the GPIO controller can receive
+ interrupts on any of the GPIOs, either edge or level. It then interrupts the CPU
+ using GIC INT12.
+
+properties:
+ $nodename:
+ pattern: "^gpio@[0-9a-f]+$"
+
+ compatible:
+ const: mediatek,mt7621-gpio
+
+ reg:
+ maxItems: 1
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-controller: true
+ gpio-ranges: true
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 2
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - "#gpio-cells"
+ - gpio-controller
+ - gpio-ranges
+ - interrupt-controller
+ - "#interrupt-cells"
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/mips-gic.h>
+
+ gpio@600 {
+ compatible = "mediatek,mt7621-gpio";
+ reg = <0x600 0x100>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 95>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+...
diff --git a/dts/Bindings/gpio/mstar,msc313-gpio.yaml b/dts/Bindings/gpio/mstar,msc313-gpio.yaml
new file mode 100644
index 0000000000..1f2ef408bb
--- /dev/null
+++ b/dts/Bindings/gpio/mstar,msc313-gpio.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/mstar,msc313-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MStar/SigmaStar GPIO controller
+
+maintainers:
+ - Daniel Palmer <daniel@thingy.jp>
+
+properties:
+ $nodename:
+ pattern: "^gpio@[0-9a-f]+$"
+
+ compatible:
+ const: mstar,msc313-gpio
+
+ reg:
+ maxItems: 1
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-ranges: true
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - "#gpio-cells"
+ - interrupt-controller
+ - "#interrupt-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/msc313-gpio.h>
+
+ gpio: gpio@207800 {
+ compatible = "mstar,msc313e-gpio";
+ #gpio-cells = <2>;
+ reg = <0x207800 0x200>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 36 22>,
+ <&pinctrl 22 63 4>,
+ <&pinctrl 26 68 6>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&intc_fiq>;
+ };
diff --git a/dts/Bindings/gpu/arm,mali-bifrost.yaml b/dts/Bindings/gpu/arm,mali-bifrost.yaml
index b1844b9c29..184492162e 100644
--- a/dts/Bindings/gpu/arm,mali-bifrost.yaml
+++ b/dts/Bindings/gpu/arm,mali-bifrost.yaml
@@ -52,6 +52,23 @@ properties:
"#cooling-cells":
const: 2
+ dynamic-power-coefficient:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description:
+ A u32 value that represents the running time dynamic
+ power coefficient in units of uW/MHz/V^2. The
+ coefficient can either be calculated from power
+ measurements or derived by analysis.
+
+ The dynamic power consumption of the GPU is
+ proportional to the square of the Voltage (V) and
+ the clock frequency (f). The coefficient is used to
+ calculate the dynamic power as below -
+
+ Pdyn = dynamic-power-coefficient * V^2 * f
+
+ where voltage is in V, frequency is in MHz.
+
required:
- compatible
- reg
diff --git a/dts/Bindings/gpu/arm,mali-midgard.yaml b/dts/Bindings/gpu/arm,mali-midgard.yaml
index e9c42b59f3..696c17aedb 100644
--- a/dts/Bindings/gpu/arm,mali-midgard.yaml
+++ b/dts/Bindings/gpu/arm,mali-midgard.yaml
@@ -90,6 +90,23 @@ properties:
dma-coherent: true
+ dynamic-power-coefficient:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description:
+ A u32 value that represents the running time dynamic
+ power coefficient in units of uW/MHz/V^2. The
+ coefficient can either be calculated from power
+ measurements or derived by analysis.
+
+ The dynamic power consumption of the GPU is
+ proportional to the square of the Voltage (V) and
+ the clock frequency (f). The coefficient is used to
+ calculate the dynamic power as below -
+
+ Pdyn = dynamic-power-coefficient * V^2 * f
+
+ where voltage is in V, frequency is in MHz.
+
required:
- compatible
- reg
diff --git a/dts/Bindings/gpu/nvidia,gk20a.txt b/dts/Bindings/gpu/nvidia,gk20a.txt
index 662a3c8a7d..cc6ce5221a 100644
--- a/dts/Bindings/gpu/nvidia,gk20a.txt
+++ b/dts/Bindings/gpu/nvidia,gk20a.txt
@@ -97,8 +97,8 @@ Example for GV11B:
gpu@17000000 {
compatible = "nvidia,gv11b";
- reg = <0x17000000 0x10000000>,
- <0x18000000 0x10000000>;
+ reg = <0x17000000 0x1000000>,
+ <0x18000000 0x1000000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "stall", "nonstall";
diff --git a/dts/Bindings/hwmon/ad741x.txt b/dts/Bindings/hwmon/ad741x.txt
deleted file mode 100644
index 9102152c84..0000000000
--- a/dts/Bindings/hwmon/ad741x.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-* AD7416/AD7417/AD7418 Temperature Sensor Device Tree Bindings
-
-Required properties:
-- compatible: one of
- "adi,ad7416"
- "adi,ad7417"
- "adi,ad7418"
-- reg: I2C address
-
-Example:
-
-hwmon@28 {
- compatible = "adi,ad7418";
- reg = <0x28>;
-};
diff --git a/dts/Bindings/hwmon/adi,ad741x.yaml b/dts/Bindings/hwmon/adi,ad741x.yaml
new file mode 100644
index 0000000000..ce7f8ce9da
--- /dev/null
+++ b/dts/Bindings/hwmon/adi,ad741x.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+
+$id: http://devicetree.org/schemas/hwmon/adi,ad741x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD7416/AD7417/AD7418 temperature sensors
+
+maintainers:
+ - Krzysztof Kozlowski <krzk@kernel.org>
+
+properties:
+ compatible:
+ enum:
+ - adi,ad7416
+ - adi,ad7417
+ - adi,ad7418
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ temperature-sensor@28 {
+ compatible = "adi,ad7418";
+ reg = <0x28>;
+ };
+ };
diff --git a/dts/Bindings/hwmon/adi,adm1275.yaml b/dts/Bindings/hwmon/adi,adm1275.yaml
new file mode 100644
index 0000000000..223393d7ca
--- /dev/null
+++ b/dts/Bindings/hwmon/adi,adm1275.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+
+$id: http://devicetree.org/schemas/hwmon/adi,adm1275.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices ADM1075/ADM127x/ADM129x digital power monitors
+
+maintainers:
+ - Krzysztof Kozlowski <krzk@kernel.org>
+
+description: |
+ The ADM1293 and ADM1294 are high accuracy integrated digital power monitors
+ that offer digital current, voltage, and power monitoring using an on-chip,
+ 12-bit analog-to-digital converter (ADC), communicated through a PMBus
+ compliant I2C interface.
+
+ Datasheets:
+ https://www.analog.com/en/products/adm1294.html
+
+properties:
+ compatible:
+ enum:
+ - adi,adm1075
+ - adi,adm1272
+ - adi,adm1275
+ - adi,adm1276
+ - adi,adm1278
+ - adi,adm1293
+ - adi,adm1294
+
+ reg:
+ maxItems: 1
+
+ shunt-resistor-micro-ohms:
+ description:
+ Shunt resistor value in micro-Ohm.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-sensor@10 {
+ compatible = "adi,adm1272";
+ reg = <0x10>;
+ shunt-resistor-micro-ohms = <500>;
+ };
+ };
diff --git a/dts/Bindings/hwmon/adi,ltc2992.yaml b/dts/Bindings/hwmon/adi,ltc2992.yaml
new file mode 100644
index 0000000000..64a8fcb7bc
--- /dev/null
+++ b/dts/Bindings/hwmon/adi,ltc2992.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/adi,ltc2992.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Linear Technology 2992 Power Monitor
+
+maintainers:
+ - Alexandru Tachici <alexandru.tachici@analog.com>
+
+description: |
+ Linear Technology 2992 Dual Wide Range Power Monitor
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ltc2992.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,ltc2992
+
+ reg:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ avcc-supply: true
+
+patternProperties:
+ "^channel@([0-1])$":
+ type: object
+ description: |
+ Represents the two supplies to be monitored.
+
+ properties:
+ reg:
+ description: |
+ The channel number. LTC2992 can monitor two supplies.
+ items:
+ minimum: 0
+ maximum: 1
+
+ shunt-resistor-micro-ohms:
+ description:
+ The value of curent sense resistor in microohms.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ltc2992@6F {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "adi,ltc2992";
+ reg = <0x6F>;
+
+ channel@0 {
+ reg = <0x0>;
+ shunt-resistor-micro-ohms = <10000>;
+ };
+
+ channel@1 {
+ reg = <0x1>;
+ shunt-resistor-micro-ohms = <10000>;
+ };
+ };
+ };
+...
diff --git a/dts/Bindings/hwmon/adm1275.txt b/dts/Bindings/hwmon/adm1275.txt
deleted file mode 100644
index 1ecd03f3da..0000000000
--- a/dts/Bindings/hwmon/adm1275.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-adm1275 properties
-
-Required properties:
-- compatible: Must be one of the supported compatible strings:
- - "adi,adm1075" for adm1075
- - "adi,adm1272" for adm1272
- - "adi,adm1275" for adm1275
- - "adi,adm1276" for adm1276
- - "adi,adm1278" for adm1278
- - "adi,adm1293" for adm1293
- - "adi,adm1294" for adm1294
-- reg: I2C address
-
-Optional properties:
-
-- shunt-resistor-micro-ohms
- Shunt resistor value in micro-Ohm
-
-Example:
-
-adm1272@10 {
- compatible = "adi,adm1272";
- reg = <0x10>;
- shunt-resistor-micro-ohms = <500>;
-};
diff --git a/dts/Bindings/hwmon/ads7828.txt b/dts/Bindings/hwmon/ads7828.txt
deleted file mode 100644
index fe0cc4ad7e..0000000000
--- a/dts/Bindings/hwmon/ads7828.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-ads7828 properties
-
-Required properties:
-- compatible: Should be one of
- ti,ads7828
- ti,ads7830
-- reg: I2C address
-
-Optional properties:
-
-- ti,differential-input
- Set to use the device in differential mode.
-- vref-supply
- The external reference on the device is set to this regulators output. If it
- does not exists the internal reference will be used and output by the ads78xx
- on the "external vref" pin.
-
- Example ADS7828 node:
-
- ads7828: ads@48 {
- comatible = "ti,ads7828";
- reg = <0x48>;
- vref-supply = <&vref>;
- ti,differential-input;
- };
diff --git a/dts/Bindings/hwmon/amd,sbtsi.yaml b/dts/Bindings/hwmon/amd,sbtsi.yaml
new file mode 100644
index 0000000000..446b09f1ce
--- /dev/null
+++ b/dts/Bindings/hwmon/amd,sbtsi.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/amd,sbtsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: >
+ Sideband interface Temperature Sensor Interface (SB-TSI) compliant
+ AMD SoC temperature device
+
+maintainers:
+ - Kun Yi <kunyi@google.com>
+ - Supreeth Venkatesh <supreeth.venkatesh@amd.com>
+
+description: |
+ SB Temperature Sensor Interface (SB-TSI) is an SMBus compatible
+ interface that reports AMD SoC's Ttcl (normalized temperature),
+ and resembles a typical 8-pin remote temperature sensor's I2C interface
+ to BMC. The emulated thermal sensor can report temperatures in increments
+ of 0.125 degrees, ranging from 0 to 255.875.
+
+properties:
+ compatible:
+ enum:
+ - amd,sbtsi
+
+ reg:
+ maxItems: 1
+ description: |
+ I2C bus address of the device as specified in Section 6.3.1 of the
+ SoC register reference. The SB-TSI address is normally 98h for socket
+ 0 and 90h for socket 1, but it could vary based on hardware address
+ select pins.
+ \[open source SoC register reference\]
+ https://www.amd.com/system/files/TechDocs/56255_OSRR.pdf
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sbtsi@4c {
+ compatible = "amd,sbtsi";
+ reg = <0x4c>;
+ };
+ };
+...
diff --git a/dts/Bindings/hwmon/ina2xx.txt b/dts/Bindings/hwmon/ina2xx.txt
deleted file mode 100644
index 02af0d94e9..0000000000
--- a/dts/Bindings/hwmon/ina2xx.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-ina2xx properties
-
-Required properties:
-- compatible: Must be one of the following:
- - "ti,ina209" for ina209
- - "ti,ina219" for ina219
- - "ti,ina220" for ina220
- - "ti,ina226" for ina226
- - "ti,ina230" for ina230
- - "ti,ina231" for ina231
-- reg: I2C address
-
-Optional properties:
-
-- shunt-resistor
- Shunt resistor value in micro-Ohm
-
-Example:
-
-ina220@44 {
- compatible = "ti,ina220";
- reg = <0x44>;
- shunt-resistor = <1000>;
-};
diff --git a/dts/Bindings/hwmon/moortec,mr75203.yaml b/dts/Bindings/hwmon/moortec,mr75203.yaml
index 6f3e3c01f7..b79f069a04 100644
--- a/dts/Bindings/hwmon/moortec,mr75203.yaml
+++ b/dts/Bindings/hwmon/moortec,mr75203.yaml
@@ -32,7 +32,7 @@ properties:
PVT controller has 5 VM (voltage monitor) sensors.
vm-map defines CPU core to VM instance mapping. A
value of 0xff means that VM sensor is unused.
- $ref: /schemas/types.yaml#definitions/uint8-array
+ $ref: /schemas/types.yaml#/definitions/uint8-array
maxItems: 5
clocks:
diff --git a/dts/Bindings/hwmon/pwm-fan.txt b/dts/Bindings/hwmon/pwm-fan.txt
index 41b7676295..4509e68862 100644
--- a/dts/Bindings/hwmon/pwm-fan.txt
+++ b/dts/Bindings/hwmon/pwm-fan.txt
@@ -8,15 +8,16 @@ Required properties:
Optional properties:
- fan-supply : phandle to the regulator that provides power to the fan
-- interrupts : This contains a single interrupt specifier which
- describes the tachometer output of the fan as an
- interrupt source. The output signal must generate a
- defined number of interrupts per fan revolution, which
- require that it must be self resetting edge interrupts.
- See interrupt-controller/interrupts.txt for the format.
-- pulses-per-revolution : define the tachometer pulses per fan revolution as
- an integer (default is 2 interrupts per revolution).
- The value must be greater than zero.
+- interrupts : This contains an interrupt specifier for each fan
+ tachometer output connected to an interrupt source.
+ The output signal must generate a defined number of
+ interrupts per fan revolution, which require that
+ it must be self resetting edge interrupts. See
+ interrupt-controller/interrupts.txt for the format.
+- pulses-per-revolution : define the number of pulses per fan revolution for
+ each tachometer input as an integer (default is 2
+ interrupts per revolution). The value must be
+ greater than zero.
Example:
fan0: pwm-fan {
@@ -55,3 +56,12 @@ Example 2:
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
pulses-per-revolution = <2>;
};
+
+Example 3:
+ fan0: pwm-fan {
+ compatible = "pwm-fan";
+ pwms = <&pwm1 0 25000 0>;
+ interrupts-extended = <&gpio1 1 IRQ_TYPE_EDGE_FALLING>,
+ <&gpio2 5 IRQ_TYPE_EDGE_FALLING>;
+ pulses-per-revolution = <2>, <1>;
+ };
diff --git a/dts/Bindings/hwmon/sensirion,shtc1.yaml b/dts/Bindings/hwmon/sensirion,shtc1.yaml
index c523a1beb2..7d49478d96 100644
--- a/dts/Bindings/hwmon/sensirion,shtc1.yaml
+++ b/dts/Bindings/hwmon/sensirion,shtc1.yaml
@@ -29,12 +29,12 @@ properties:
const: 0x70
sensirion,blocking-io:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
If set, the driver hold the i2c bus until measurement is finished.
sensirion,low-precision:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
If set, the sensor aquire data with low precision (not recommended).
The driver aquire data with high precision by default.
diff --git a/dts/Bindings/hwmon/ti,ads7828.yaml b/dts/Bindings/hwmon/ti,ads7828.yaml
new file mode 100644
index 0000000000..33ee575bb0
--- /dev/null
+++ b/dts/Bindings/hwmon/ti,ads7828.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+
+$id: http://devicetree.org/schemas/hwmon/ti,ads7828.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments ADS7828/ADS7830 Analog to Digital Converter (ADC)
+
+maintainers:
+ - Krzysztof Kozlowski <krzk@kernel.org>
+
+description: |
+ The ADS7828 is 12-Bit, 8-Channel Sampling Analog to Digital Converter (ADC)
+ with an I2C interface.
+
+ Datasheets:
+ https://www.ti.com/product/ADS7828
+
+properties:
+ compatible:
+ enum:
+ - ti,ads7828
+ - ti,ads7830
+
+ reg:
+ maxItems: 1
+
+ ti,differential-input:
+ description:
+ Set to use the device in differential mode.
+ type: boolean
+
+ vref-supply:
+ description:
+ The regulator to use as an external reference. If it does not exists the
+ internal reference will be used.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@48 {
+ comatible = "ti,ads7828";
+ reg = <0x48>;
+ vref-supply = <&vref>;
+ ti,differential-input;
+ };
+ };
diff --git a/dts/Bindings/hwmon/ti,ina2xx.yaml b/dts/Bindings/hwmon/ti,ina2xx.yaml
new file mode 100644
index 0000000000..6f0443322a
--- /dev/null
+++ b/dts/Bindings/hwmon/ti,ina2xx.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+
+$id: http://devicetree.org/schemas/hwmon/ti,ina2xx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments INA209 family of power/voltage monitors
+
+maintainers:
+ - Krzysztof Kozlowski <krzk@kernel.org>
+
+description: |
+ The INA209 is a high-side current shunt and power monitor with
+ an I2C interface.
+
+ Datasheets:
+ https://www.ti.com/product/INA209
+
+properties:
+ compatible:
+ enum:
+ - ti,ina209
+ - ti,ina219
+ - ti,ina220
+ - ti,ina226
+ - ti,ina230
+ - ti,ina231
+
+ reg:
+ maxItems: 1
+
+ shunt-resistor:
+ description:
+ Shunt resistor value in micro-Ohm.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-sensor@44 {
+ compatible = "ti,ina220";
+ reg = <0x44>;
+ shunt-resistor = <1000>;
+ };
+ };
diff --git a/dts/Bindings/hwmon/ti,tmp513.yaml b/dts/Bindings/hwmon/ti,tmp513.yaml
index c17e5d3ee3..8020d739a0 100644
--- a/dts/Bindings/hwmon/ti,tmp513.yaml
+++ b/dts/Bindings/hwmon/ti,tmp513.yaml
@@ -61,7 +61,7 @@ properties:
Array of three(TMP513) or two(TMP512) n-Factor value for each remote
temperature channel.
See datasheet Table 11 for n-Factor range list and value interpretation.
- $ref: /schemas/types.yaml#definitions/uint32-array
+ $ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 2
maxItems: 3
items:
diff --git a/dts/Bindings/i2c/i2c-gate.txt b/dts/Bindings/i2c/i2c-gate.txt
deleted file mode 100644
index 1846d236e6..0000000000
--- a/dts/Bindings/i2c/i2c-gate.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-An i2c gate is useful to e.g. reduce the digital noise for RF tuners connected
-to the i2c bus. Gates are similar to arbitrators in that you need to perform
-some kind of operation to access the i2c bus past the arbitrator/gate, but
-there are no competing masters to consider for gates and therefore there is
-no arbitration happening for gates.
-
-Common i2c gate properties.
-
-- i2c-gate child node
-
-Required properties for the i2c-gate child node:
-- #address-cells = <1>;
-- #size-cells = <0>;
-
-Optional properties for i2c-gate child node:
-- Child nodes conforming to i2c bus binding
-
-
-Example :
-
- /*
- An Invensense mpu9150 at address 0x68 featuring an on-chip Asahi
- Kasei ak8975 compass behind a gate.
- */
-
- mpu9150@68 {
- compatible = "invensense,mpu9150";
- reg = <0x68>;
- interrupt-parent = <&gpio1>;
- interrupts = <18 1>;
-
- i2c-gate {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ax8975@c {
- compatible = "ak,ak8975";
- reg = <0x0c>;
- };
- };
- };
diff --git a/dts/Bindings/i2c/i2c-gate.yaml b/dts/Bindings/i2c/i2c-gate.yaml
new file mode 100644
index 0000000000..66472f12a7
--- /dev/null
+++ b/dts/Bindings/i2c/i2c-gate.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/i2c-gate.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Common i2c gate properties
+
+maintainers:
+ - Peter Rosin <peda@axentia.se>
+
+description: |
+ An i2c gate is useful to e.g. reduce the digital noise for RF tuners connected
+ to the i2c bus. Gates are similar to arbitrators in that you need to perform
+ some kind of operation to access the i2c bus past the arbitrator/gate, but
+ there are no competing masters to consider for gates and therefore there is
+ no arbitration happening for gates.
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml
+
+properties:
+ $nodename:
+ const: i2c-gate
+
+additionalProperties: true
+
+examples:
+ - |
+ i2c-gate {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ak8975@c {
+ compatible = "ak,ak8975";
+ reg = <0x0c>;
+ };
+ };
+...
+
diff --git a/dts/Bindings/i2c/i2c-ocores.txt b/dts/Bindings/i2c/i2c-ocores.txt
index 6b25a80ae8..a37c9455b2 100644
--- a/dts/Bindings/i2c/i2c-ocores.txt
+++ b/dts/Bindings/i2c/i2c-ocores.txt
@@ -5,8 +5,12 @@ Required properties:
"aeroflexgaisler,i2cmst"
"sifive,fu540-c000-i2c", "sifive,i2c0"
For Opencore based I2C IP block reimplemented in
- FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt
- for additional details.
+ FU540-C000 SoC.
+ "sifive,fu740-c000-i2c", "sifive,i2c0"
+ For Opencore based I2C IP block reimplemented in
+ FU740-C000 SoC.
+ Please refer to sifive-blocks-ip-versioning.txt for
+ additional details.
- reg : bus address start and address range size of device
- clocks : handle to the controller clock; see the note below.
Mutually exclusive with opencores,ip-clock-frequency
diff --git a/dts/Bindings/i2c/i2c-omap.txt b/dts/Bindings/i2c/i2c-omap.txt
index a44573d7c1..a425b91af4 100644
--- a/dts/Bindings/i2c/i2c-omap.txt
+++ b/dts/Bindings/i2c/i2c-omap.txt
@@ -8,6 +8,7 @@ Required properties :
"ti,omap4-i2c" for OMAP4+ SoCs
"ti,am654-i2c", "ti,omap4-i2c" for AM654 SoCs
"ti,j721e-i2c", "ti,omap4-i2c" for J721E SoCs
+ "ti,am64-i2c", "ti,omap4-i2c" for AM64 SoCs
- ti,hwmods : Must be "i2c<n>", n being the instance number (1-based)
- #address-cells = <1>;
- #size-cells = <0>;
diff --git a/dts/Bindings/i2c/i2c-owl.txt b/dts/Bindings/i2c/i2c-owl.txt
deleted file mode 100644
index 54c05dbdb2..0000000000
--- a/dts/Bindings/i2c/i2c-owl.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-Actions Semiconductor Owl I2C controller
-
-Required properties:
-
-- compatible : Should be one of the following:
- - "actions,s700-i2c" for S700 SoC
- - "actions,s900-i2c" for S900 SoC
-- reg : Offset and length of the register set for the device.
-- #address-cells : Should be 1.
-- #size-cells : Should be 0.
-- interrupts : A single interrupt specifier.
-- clocks : Phandle of the clock feeding the I2C controller.
-
-Optional properties:
-
-- clock-frequency : Desired I2C bus clock frequency in Hz. As only Normal and
- Fast modes are supported, possible values are 100000 and
- 400000.
-Examples:
-
- i2c0: i2c@e0170000 {
- compatible = "actions,s900-i2c";
- reg = <0 0xe0170000 0 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_I2C0>;
- clock-frequency = <100000>;
- };
diff --git a/dts/Bindings/i2c/i2c-owl.yaml b/dts/Bindings/i2c/i2c-owl.yaml
new file mode 100644
index 0000000000..d96908badf
--- /dev/null
+++ b/dts/Bindings/i2c/i2c-owl.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/i2c-owl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Actions Semi Owl I2C Controller
+
+maintainers:
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+description: |
+ This I2C controller is found in the Actions Semi Owl SoCs:
+ S500, S700 and S900.
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - actions,s500-i2c # Actions Semi S500 compatible SoCs
+ - actions,s700-i2c # Actions Semi S700 compatible SoCs
+ - actions,s900-i2c # Actions Semi S900 compatible SoCs
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ description: Phandle of the clock feeding the I2C controller.
+ minItems: 1
+
+ clock-frequency:
+ description: |
+ Desired I2C bus clock frequency in Hz. As only Standard and Fast
+ modes are supported, possible values are 100000 and 400000.
+ enum: [100000, 400000]
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/actions,s900-cmu.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ i2c@e0170000 {
+ compatible = "actions,s900-i2c";
+ reg = <0xe0170000 0x1000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_I2C0>;
+ clock-frequency = <100000>;
+ };
+
+...
diff --git a/dts/Bindings/i2c/mellanox,i2c-mlxbf.txt b/dts/Bindings/i2c/mellanox,i2c-mlxbf.txt
deleted file mode 100644
index 566ea861aa..0000000000
--- a/dts/Bindings/i2c/mellanox,i2c-mlxbf.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-Device tree configuration for the Mellanox I2C SMBus on BlueField SoCs
-
-Required Properties:
-
-- compatible : should be "mellanox,i2c-mlxbf1" or "mellanox,i2c-mlxbf2".
-
-- reg : address offset and length of the device registers. The
- registers consist of the following set of resources:
- 1) Smbus block registers.
- 2) Cause master registers.
- 3) Cause slave registers.
- 4) Cause coalesce registers (if compatible isn't set
- to "mellanox,i2c-mlxbf1").
-
-- interrupts : interrupt number.
-
-Optional Properties:
-
-- clock-frequency : bus frequency used to configure timing registers;
- allowed values are 100000, 400000 and 1000000;
- those are expressed in Hz. Default is 100000.
-
-Example:
-
-i2c@2804000 {
- compatible = "mellanox,i2c-mlxbf1";
- reg = <0x02804000 0x800>,
- <0x02801200 0x020>,
- <0x02801260 0x020>;
- interrupts = <57>;
- clock-frequency = <100000>;
-};
-
-i2c@2808800 {
- compatible = "mellanox,i2c-mlxbf2";
- reg = <0x02808800 0x600>,
- <0x02808e00 0x020>,
- <0x02808e20 0x020>,
- <0x02808e40 0x010>;
- interrupts = <57>;
- clock-frequency = <400000>;
-};
diff --git a/dts/Bindings/i2c/mellanox,i2c-mlxbf.yaml b/dts/Bindings/i2c/mellanox,i2c-mlxbf.yaml
new file mode 100644
index 0000000000..d2b401d062
--- /dev/null
+++ b/dts/Bindings/i2c/mellanox,i2c-mlxbf.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/mellanox,i2c-mlxbf.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mellanox I2C SMBus on BlueField SoCs
+
+maintainers:
+ - Khalil Blaiech <kblaiech@nvidia.com>
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - mellanox,i2c-mlxbf1
+ - mellanox,i2c-mlxbf2
+
+ reg:
+ minItems: 3
+ maxItems: 4
+ items:
+ - description: Smbus block registers
+ - description: Cause master registers
+ - description: Cause slave registers
+ - description: Cause coalesce registers
+
+ interrupts:
+ maxItems: 1
+
+ clock-frequency:
+ enum: [ 100000, 400000, 1000000 ]
+ description:
+ bus frequency used to configure timing registers;
+ The frequency is expressed in Hz. Default is 100000.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+unevaluatedProperties: false
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mellanox,i2c-mlxbf1
+
+then:
+ properties:
+ reg:
+ maxItems: 3
+
+examples:
+ - |
+ i2c@2804000 {
+ compatible = "mellanox,i2c-mlxbf1";
+ reg = <0x02804000 0x800>,
+ <0x02801200 0x020>,
+ <0x02801260 0x020>;
+ interrupts = <57>;
+ clock-frequency = <100000>;
+ };
+
+ - |
+ i2c@2808800 {
+ compatible = "mellanox,i2c-mlxbf2";
+ reg = <0x02808800 0x600>,
+ <0x02808e00 0x020>,
+ <0x02808e20 0x020>,
+ <0x02808e40 0x010>;
+ interrupts = <57>;
+ clock-frequency = <400000>;
+ };
diff --git a/dts/Bindings/i2c/snps,designware-i2c.yaml b/dts/Bindings/i2c/snps,designware-i2c.yaml
index 4f746bef23..c22b66b621 100644
--- a/dts/Bindings/i2c/snps,designware-i2c.yaml
+++ b/dts/Bindings/i2c/snps,designware-i2c.yaml
@@ -101,8 +101,6 @@ unevaluatedProperties: false
required:
- compatible
- reg
- - "#address-cells"
- - "#size-cells"
- interrupts
examples:
@@ -110,8 +108,6 @@ examples:
i2c@f0000 {
compatible = "snps,designware-i2c";
reg = <0xf0000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
interrupts = <11>;
clock-frequency = <400000>;
};
@@ -119,8 +115,6 @@ examples:
i2c@1120000 {
compatible = "snps,designware-i2c";
reg = <0x1120000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
interrupts = <12 1>;
clock-frequency = <400000>;
i2c-sda-hold-time-ns = <300>;
@@ -148,8 +142,6 @@ examples:
reg = <0x100400 0x100>, <0x198 0x8>;
pinctrl-0 = <&i2c_pins>;
pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
interrupts = <8>;
clocks = <&ahb_clk>;
};
diff --git a/dts/Bindings/i3c/mipi-i3c-hci.yaml b/dts/Bindings/i3c/mipi-i3c-hci.yaml
new file mode 100644
index 0000000000..07a7b10163
--- /dev/null
+++ b/dts/Bindings/i3c/mipi-i3c-hci.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/i3c/mipi-i3c-hci.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: MIPI I3C HCI Device Tree Bindings
+
+maintainers:
+ - Nicolas Pitre <npitre@baylibre.com>
+
+description: |
+ MIPI I3C Host Controller Interface
+
+ The MIPI I3C HCI (Host Controller Interface) specification defines
+ a common software driver interface to support compliant MIPI I3C
+ host controller hardware implementations from multiple vendors.
+
+ The hardware is self-advertising for differences in implementation
+ capabilities, including the spec version it is based on, so there
+ isn't much to describe here (yet).
+
+ For details, please see:
+ https://www.mipi.org/specifications/i3c-hci
+
+properties:
+ compatible:
+ const: mipi-i3c-hci
+ reg:
+ maxItems: 1
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ i3c@a0000000 {
+ compatible = "mipi-i3c-hci";
+ reg = <0xa0000000 0x2000>;
+ interrupts = <89>;
+ };
diff --git a/dts/Bindings/iio/accel/bma180.txt b/dts/Bindings/iio/accel/bma180.txt
deleted file mode 100644
index 33da4a6fdb..0000000000
--- a/dts/Bindings/iio/accel/bma180.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-* Bosch BMA023 / BMA150/ BMA180 / BMA25x / SMB380 triaxial acceleration sensor
-
-https://media.digikey.com/pdf/Data%20Sheets/Bosch/BMA150.pdf
-http://omapworld.com/BMA180_111_1002839.pdf
-http://ae-bst.resource.bosch.com/media/products/dokumente/bma250/bst-bma250-ds002-05.pdf
-
-Required properties:
-
- - compatible : should be one of:
- "bosch,bma023"
- "bosch,bma150"
- "bosch,bma180"
- "bosch,bma250"
- "bosch,bma254"
- "bosch,smb380"
- - reg : the I2C address of the sensor
- - vdd-supply : regulator phandle connected to the VDD pin
- - vddio-supply : regulator phandle connected to the VDDIO pin
-
-Optional properties:
-
- - interrupts : interrupt mapping for GPIO IRQ, it should by configured with
- flags IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING
- For the bma250 the first interrupt listed must be the one
- connected to the INT1 pin, the second (optional) interrupt
- listed must be the one connected to the INT2 pin.
-
-Example:
-
-bma180@40 {
- compatible = "bosch,bma180";
- reg = <0x40>;
- interrupt-parent = <&gpio6>;
- interrupts = <18 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>;
-};
diff --git a/dts/Bindings/iio/accel/bosch,bma180.yaml b/dts/Bindings/iio/accel/bosch,bma180.yaml
new file mode 100644
index 0000000000..45b3abde29
--- /dev/null
+++ b/dts/Bindings/iio/accel/bosch,bma180.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/accel/bosch,bma180.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bosch BMA023 / BMA150/ BMA180 / BMA25x / SMB380 triaxial accelerometers
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+description: |
+ https://media.digikey.com/pdf/Data%20Sheets/Bosch/BMA150.pdf
+ http://omapworld.com/BMA180_111_1002839.pdf
+ http://ae-bst.resource.bosch.com/media/products/dokumente/bma250/bst-bma250-ds002-05.pdf
+
+properties:
+ compatible:
+ enum:
+ - bosch,bma023
+ - bosch,bma150
+ - bosch,bma180
+ - bosch,bma250
+ - bosch,bma254
+ - bosch,smb380
+
+ reg:
+ maxItems: 1
+
+ vdd-supply: true
+
+ vddio-supply: true
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+ description: |
+ Type should be either IRQ_TYPE_LEVEL_HIGH or IRQ_TYPE_EDGE_RISING.
+ For the bma250 the first interrupt listed must be the one
+ connected to the INT1 pin, the second (optional) interrupt
+ listed must be the one connected to the INT2 pin.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ accel@40 {
+ compatible = "bosch,bma180";
+ reg = <0x40>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <18 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/accel/bosch,bma255.yaml b/dts/Bindings/iio/accel/bosch,bma255.yaml
new file mode 100644
index 0000000000..6eef3480ea
--- /dev/null
+++ b/dts/Bindings/iio/accel/bosch,bma255.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/accel/bosch,bma255.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bosch BMA255 and Similar Accelerometers
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+description:
+ 3 axis accelerometers with varying range and I2C or SPI
+ 4-wire interface.
+
+properties:
+ compatible:
+ enum:
+ - bosch,bmc150
+ - bosch,bmi055
+ - bosch,bma255
+ - bosch,bma250e
+ - bosch,bma222
+ - bosch,bma222e
+ - bosch,bma280
+
+ reg:
+ maxItems: 1
+
+ vdd-supply: true
+ vddio-supply: true
+
+ interrupts:
+ maxItems: 1
+
+ mount-matrix:
+ description: an optional 3x3 mounting rotation matrix.
+
+ spi-max-frequency:
+ maximum: 10000000
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ accelerometer@8 {
+ compatible = "bosch,bma222";
+ reg = <0x08>;
+ vddio-supply = <&vddio>;
+ vdd-supply = <&vdd>;
+ interrupts = <57 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
+ - |
+ # include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ accel@0 {
+ compatible = "bosch,bma222";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/accel/dmard06.txt b/dts/Bindings/iio/accel/dmard06.txt
deleted file mode 100644
index ce105a12c6..0000000000
--- a/dts/Bindings/iio/accel/dmard06.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-Device tree bindings for Domintech DMARD05, DMARD06, DMARD07 accelerometers
-
-Required properties:
- - compatible : Should be "domintech,dmard05"
- or "domintech,dmard06"
- or "domintech,dmard07"
- - reg : I2C address of the chip. Should be 0x1c
-
-Example:
- &i2c1 {
- /* ... */
-
- accelerometer@1c {
- compatible = "domintech,dmard06";
- reg = <0x1c>;
- };
-
- /* ... */
- };
diff --git a/dts/Bindings/iio/accel/fsl,mma8452.yaml b/dts/Bindings/iio/accel/fsl,mma8452.yaml
new file mode 100644
index 0000000000..b0dd2b4e11
--- /dev/null
+++ b/dts/Bindings/iio/accel/fsl,mma8452.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/accel/fsl,mma8452.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title:
+ Freescale MMA8451Q, MMA8452Q, MMA8453Q, MMA8652FC, MMA8653FC or FXLS8471Q
+ triaxial accelerometer
+
+maintainers:
+ - Martin Kepplinger <martin.kepplinger@theobroma-systems.com>
+
+properties:
+ compatible:
+ enum:
+ - fsl,mma8451
+ - fsl,mma8452
+ - fsl,mma8453
+ - fsl,mma8652
+ - fsl,mma8653
+ - fsl,fxls8471
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ 2 highly configurable interrupt lines exist.
+ minItems: 1
+ maxItems: 2
+
+ interrupt-names:
+ description: Specify which interrupt line is in use.
+ items:
+ enum:
+ - INT1
+ - INT2
+ minItems: 1
+ maxItems: 2
+
+ vdd-supply: true
+ vddio-supply: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ accel@1d {
+ compatible = "fsl,mma8453";
+ reg = <0x1d>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <5 0>;
+ interrupt-names = "INT2";
+ };
+ };
+...
diff --git a/dts/Bindings/iio/accel/kionix,kxcjk1013.txt b/dts/Bindings/iio/accel/kionix,kxcjk1013.txt
deleted file mode 100644
index ce950e162d..0000000000
--- a/dts/Bindings/iio/accel/kionix,kxcjk1013.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-Kionix KXCJK-1013 Accelerometer device tree bindings
-
-Required properties:
-
-- compatible: Must be one of:
- "kionix,kxcjk1013"
- "kionix,kxcj91008"
- "kionix,kxtj21009"
- "kionix,kxtf9"
- - reg: i2c slave address
-
-Optional properties:
-
- - mount-matrix: an optional 3x3 mounting rotation matrix
-
-Example:
-
-kxtf9@f {
- compatible = "kionix,kxtf9";
- reg = <0x0F>;
- mount-matrix = "0", "1", "0",
- "1", "0", "0",
- "0", "0", "1";
-};
diff --git a/dts/Bindings/iio/accel/kionix,kxcjk1013.yaml b/dts/Bindings/iio/accel/kionix,kxcjk1013.yaml
new file mode 100644
index 0000000000..5667d09dfe
--- /dev/null
+++ b/dts/Bindings/iio/accel/kionix,kxcjk1013.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/accel/kionix,kxcjk1013.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Kionix KXCJK-1013 Accelerometer
+
+maintainers:
+ - Robert Yang <decatf@gmail.com>
+
+properties:
+ compatible:
+ enum:
+ - kionix,kxcjk1013
+ - kionix,kxcj91008
+ - kionix,kxtj21009
+ - kionix,kxtf9
+
+ reg:
+ maxItems: 1
+
+ mount-matrix:
+ description: an optional 3x3 mounting rotation matrix.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ accel@f {
+ compatible = "kionix,kxtf9";
+ reg = <0x0F>;
+ mount-matrix = "0", "1", "0",
+ "1", "0", "0",
+ "0", "0", "1";
+ };
+ };
+...
diff --git a/dts/Bindings/iio/accel/mma8452.txt b/dts/Bindings/iio/accel/mma8452.txt
deleted file mode 100644
index e132394375..0000000000
--- a/dts/Bindings/iio/accel/mma8452.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-Freescale MMA8451Q, MMA8452Q, MMA8453Q, MMA8652FC, MMA8653FC or FXLS8471Q
-triaxial accelerometer
-
-Required properties:
-
- - compatible: should contain one of
- * "fsl,mma8451"
- * "fsl,mma8452"
- * "fsl,mma8453"
- * "fsl,mma8652"
- * "fsl,mma8653"
- * "fsl,fxls8471"
-
- - reg: the I2C address of the chip
-
-Optional properties:
-
- - interrupts: interrupt mapping for GPIO IRQ
-
- - interrupt-names: should contain "INT1" and/or "INT2", the accelerometer's
- interrupt line in use.
-
- - vdd-supply: phandle to the regulator that provides vdd power to the accelerometer.
-
- - vddio-supply: phandle to the regulator that provides vddio power to the accelerometer.
-
-Example:
-
- mma8453fc@1d {
- compatible = "fsl,mma8453";
- reg = <0x1d>;
- interrupt-parent = <&gpio1>;
- interrupts = <5 0>;
- interrupt-names = "INT2";
- };
diff --git a/dts/Bindings/iio/adc/adc.txt b/dts/Bindings/iio/adc/adc.txt
deleted file mode 100644
index 5bbaa330a2..0000000000
--- a/dts/Bindings/iio/adc/adc.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-Common ADCs properties
-
-Optional properties for child nodes:
-- bipolar : Boolean, if set the channel is used in bipolar mode.
-- diff-channels : Differential channels muxed for this ADC. The first value
- specifies the positive input pin, the second value the negative
- input pin.
-
-Example:
- adc@0 {
- compatible = "some,adc";
- ...
- channel@0 {
- bipolar;
- diff-channels = <0 1>;
- ...
- };
-
- channel@1 {
- diff-channels = <2 3>;
- ...
- };
- };
diff --git a/dts/Bindings/iio/adc/adc.yaml b/dts/Bindings/iio/adc/adc.yaml
new file mode 100644
index 0000000000..912a7635ed
--- /dev/null
+++ b/dts/Bindings/iio/adc/adc.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic IIO bindings for ADC channels
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+description:
+ A few properties are defined in a common way ADC channels.
+
+properties:
+ $nodename:
+ pattern: "^channel(@[0-9a-f]+)?$"
+ description:
+ A channel index should match reg.
+
+ reg:
+ maxItems: 1
+
+ label:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: Unique name to identify which channel this is.
+
+ bipolar:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: If provided, the channel is to be used in bipolar mode.
+
+ diff-channels:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ maxItems: 2
+ minItems: 2
+ description:
+ Many ADCs have dual Muxes to allow different input pins to be routed
+ to both the positive and negative inputs of a differential ADC.
+ The first value specifies the positive input pin, the second
+ specifies the negative input pin.
+
+additionalProperties: true
diff --git a/dts/Bindings/iio/adc/adi,ad7124.yaml b/dts/Bindings/iio/adc/adi,ad7124.yaml
index f1c574c896..fb3d0dae9b 100644
--- a/dts/Bindings/iio/adc/adi,ad7124.yaml
+++ b/dts/Bindings/iio/adc/adi,ad7124.yaml
@@ -63,10 +63,10 @@ required:
patternProperties:
"^channel@([0-9]|1[0-5])$":
+ $ref: "adc.yaml"
type: object
description: |
Represents the external channels which are connected to the ADC.
- See Documentation/devicetree/bindings/iio/adc/adc.txt.
properties:
reg:
@@ -88,15 +88,9 @@ patternProperties:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 3]
- diff-channels:
- description: see Documentation/devicetree/bindings/iio/adc/adc.txt
- items:
- minimum: 0
- maximum: 15
+ diff-channels: true
- bipolar:
- description: see Documentation/devicetree/bindings/iio/adc/adc.txt
- type: boolean
+ bipolar: true
adi,buffered-positive:
description: Enable buffered mode for positive input.
@@ -110,6 +104,8 @@ patternProperties:
- reg
- diff-channels
+ additionalProperties: false
+
additionalProperties: false
examples:
diff --git a/dts/Bindings/iio/adc/adi,ad7292.yaml b/dts/Bindings/iio/adc/adi,ad7292.yaml
index 108d202b28..a3e39a40c9 100644
--- a/dts/Bindings/iio/adc/adi,ad7292.yaml
+++ b/dts/Bindings/iio/adc/adi,ad7292.yaml
@@ -45,10 +45,10 @@ required:
patternProperties:
"^channel@[0-7]$":
+ $ref: "adc.yaml"
type: object
description: |
Represents the external channels which are connected to the ADC.
- See Documentation/devicetree/bindings/iio/adc/adc.txt.
properties:
reg:
@@ -58,13 +58,13 @@ patternProperties:
- minimum: 0
maximum: 7
- diff-channels:
- description: see Documentation/devicetree/bindings/iio/adc/adc.txt
- maxItems: 1
+ diff-channels: true
required:
- reg
+ additionalProperties: true
+
additionalProperties: false
examples:
diff --git a/dts/Bindings/iio/adc/adi,ad7768-1.yaml b/dts/Bindings/iio/adc/adi,ad7768-1.yaml
index 8f32800fe5..924477dfb8 100644
--- a/dts/Bindings/iio/adc/adi,ad7768-1.yaml
+++ b/dts/Bindings/iio/adc/adi,ad7768-1.yaml
@@ -29,6 +29,12 @@ properties:
interrupts:
maxItems: 1
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
vref-supply:
description:
ADC reference voltage supply
@@ -62,6 +68,24 @@ required:
- spi-cpha
- adi,sync-in-gpios
+patternProperties:
+ "^channel@([0-9]|1[0-5])$":
+ type: object
+ description: |
+ Represents the external channels which are connected to the device.
+
+ properties:
+ reg:
+ description: |
+ The channel number.
+
+ label:
+ description: |
+ Unique name to identify which channel this is.
+ required:
+ - reg
+ additionalProperties: false
+
additionalProperties: false
examples:
@@ -85,6 +109,14 @@ examples:
reset-gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
clocks = <&ad7768_mclk>;
clock-names = "mclk";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ label = "channel_0";
+ };
};
};
...
diff --git a/dts/Bindings/iio/adc/at91-sama5d2_adc.txt b/dts/Bindings/iio/adc/at91-sama5d2_adc.txt
deleted file mode 100644
index 07c59f301b..0000000000
--- a/dts/Bindings/iio/adc/at91-sama5d2_adc.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-* AT91 SAMA5D2 Analog to Digital Converter (ADC)
-
-Required properties:
- - compatible: Should be "atmel,sama5d2-adc" or "microchip,sam9x60-adc".
- - reg: Should contain ADC registers location and length.
- - interrupts: Should contain the IRQ line for the ADC.
- - clocks: phandle to device clock.
- - clock-names: Must be "adc_clk".
- - vref-supply: Supply used as reference for conversions.
- - vddana-supply: Supply for the adc device.
- - atmel,min-sample-rate-hz: Minimum sampling rate, it depends on SoC.
- - atmel,max-sample-rate-hz: Maximum sampling rate, it depends on SoC.
- - atmel,startup-time-ms: Startup time expressed in ms, it depends on SoC.
- - atmel,trigger-edge-type: One of possible edge types for the ADTRG hardware
- trigger pin. When the specific edge type is detected, the conversion will
- start. Possible values are rising, falling, or both.
- This property uses the IRQ edge types values: IRQ_TYPE_EDGE_RISING ,
- IRQ_TYPE_EDGE_FALLING or IRQ_TYPE_EDGE_BOTH
-
-Optional properties:
- - dmas: Phandle to dma channel for the ADC.
- - dma-names: Must be "rx" when dmas property is being used.
- See ../../dma/dma.txt for details.
- - #io-channel-cells: in case consumer drivers are attached, this must be 1.
- See <Documentation/devicetree/bindings/iio/iio-bindings.txt> for details.
-
-Properties for consumer drivers:
- - Consumer drivers can be connected to this producer device, as specified
- in <Documentation/devicetree/bindings/iio/iio-bindings.txt>
- - Channels exposed are specified in:
- <dt-bindings/iio/adc/at91-sama5d2_adc.txt>
-
-Example:
-
-adc: adc@fc030000 {
- compatible = "atmel,sama5d2-adc";
- reg = <0xfc030000 0x100>;
- interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&adc_clk>;
- clock-names = "adc_clk";
- atmel,min-sample-rate-hz = <200000>;
- atmel,max-sample-rate-hz = <20000000>;
- atmel,startup-time-ms = <4>;
- vddana-supply = <&vdd_3v3_lp_reg>;
- vref-supply = <&vdd_3v3_lp_reg>;
- atmel,trigger-edge-type = <IRQ_TYPE_EDGE_BOTH>;
- dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
- dma-names = "rx";
- #io-channel-cells = <1>;
-}
diff --git a/dts/Bindings/iio/adc/at91_adc.txt b/dts/Bindings/iio/adc/at91_adc.txt
deleted file mode 100644
index f65b04fb79..0000000000
--- a/dts/Bindings/iio/adc/at91_adc.txt
+++ /dev/null
@@ -1,83 +0,0 @@
-* AT91's Analog to Digital Converter (ADC)
-
-Required properties:
- - compatible: Should be "atmel,<chip>-adc"
- <chip> can be "at91sam9260", "at91sam9g45" or "at91sam9x5"
- - reg: Should contain ADC registers location and length
- - interrupts: Should contain the IRQ line for the ADC
- - clock-names: tuple listing input clock names.
- Required elements: "adc_clk", "adc_op_clk".
- - clocks: phandles to input clocks.
- - atmel,adc-channels-used: Bitmask of the channels muxed and enabled for this
- device
- - atmel,adc-startup-time: Startup Time of the ADC in microseconds as
- defined in the datasheet
- - atmel,adc-vref: Reference voltage in millivolts for the conversions
- - atmel,adc-res: List of resolutions in bits supported by the ADC. List size
- must be two at least.
- - atmel,adc-res-names: Contains one identifier string for each resolution
- in atmel,adc-res property. "lowres" and "highres"
- identifiers are required.
-
-Optional properties:
- - atmel,adc-use-external-triggers: Boolean to enable the external triggers
- - atmel,adc-use-res: String corresponding to an identifier from
- atmel,adc-res-names property. If not specified, the highest
- resolution will be used.
- - atmel,adc-sleep-mode: Boolean to enable sleep mode when no conversion
- - atmel,adc-sample-hold-time: Sample and Hold Time in microseconds
- - atmel,adc-ts-wires: Number of touchscreen wires. Should be 4 or 5. If this
- value is set, then the adc driver will enable touchscreen
- support.
- NOTE: when adc touchscreen is enabled, the adc hardware trigger will be
- disabled. Since touchscreen will occupy the trigger register.
- - atmel,adc-ts-pressure-threshold: a pressure threshold for touchscreen. It
- makes touch detection more precise.
-
-Optional trigger Nodes:
- - Required properties:
- * trigger-name: Name of the trigger exposed to the user
- * trigger-value: Value to put in the Trigger register
- to activate this trigger
- - Optional properties:
- * trigger-external: Is the trigger an external trigger?
-
-Examples:
-adc0: adc@fffb0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "atmel,at91sam9260-adc";
- reg = <0xfffb0000 0x100>;
- interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&adc_clk>, <&adc_op_clk>;
- clock-names = "adc_clk", "adc_op_clk";
- atmel,adc-channels-used = <0xff>;
- atmel,adc-startup-time = <40>;
- atmel,adc-use-external-triggers;
- atmel,adc-vref = <3300>;
- atmel,adc-res = <8 10>;
- atmel,adc-res-names = "lowres", "highres";
- atmel,adc-use-res = "lowres";
-
- trigger0 {
- trigger-name = "external-rising";
- trigger-value = <0x1>;
- trigger-external;
- };
- trigger1 {
- trigger-name = "external-falling";
- trigger-value = <0x2>;
- trigger-external;
- };
-
- trigger2 {
- trigger-name = "external-any";
- trigger-value = <0x3>;
- trigger-external;
- };
-
- trigger3 {
- trigger-name = "continuous";
- trigger-value = <0x6>;
- };
-};
diff --git a/dts/Bindings/iio/adc/atmel,sama5d2-adc.yaml b/dts/Bindings/iio/adc/atmel,sama5d2-adc.yaml
new file mode 100644
index 0000000000..79c13b408e
--- /dev/null
+++ b/dts/Bindings/iio/adc/atmel,sama5d2-adc.yaml
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/atmel,sama5d2-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AT91 SAMA5D2 Analog to Digital Converter (ADC)
+
+maintainers:
+ - Ludovic Desroches <ludovic.desroches@atmel.com>
+ - Eugen Hristev <eugen.hristev@microchip.com>
+
+properties:
+ compatible:
+ enum:
+ - atmel,sama5d2-adc
+ - microchip,sam9x60-adc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: adc_clk
+
+ vref-supply: true
+ vddana-supply: true
+
+ atmel,min-sample-rate-hz:
+ description: Minimum sampling rate, it depends on SoC.
+
+ atmel,max-sample-rate-hz:
+ description: Maximum sampling rate, it depends on SoC.
+
+ atmel,startup-time-ms:
+ description: Startup time expressed in ms, it depends on SoC.
+
+ atmel,trigger-edge-type:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description:
+ One of possible edge types for the ADTRG hardware trigger pin.
+ When the specific edge type is detected, the conversion will
+ start. Should be one of IRQ_TYPE_EDGE_RISING, IRQ_TYPE_EDGE_FALLING
+ or IRQ_TYPE_EDGE_BOTH.
+ enum: [1, 2, 3]
+
+ dmas:
+ maxItems: 1
+
+ dma-names:
+ const: rx
+
+ "#io-channel-cells":
+ const: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - vref-supply
+ - vddana-supply
+ - atmel,min-sample-rate-hz
+ - atmel,max-sample-rate-hz
+ - atmel,startup-time-ms
+ - atmel,trigger-edge-type
+
+examples:
+ - |
+ #include <dt-bindings/dma/at91.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ adc@fc030000 {
+ compatible = "atmel,sama5d2-adc";
+ reg = <0xfc030000 0x100>;
+ interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&adc_clk>;
+ clock-names = "adc_clk";
+ atmel,min-sample-rate-hz = <200000>;
+ atmel,max-sample-rate-hz = <20000000>;
+ atmel,startup-time-ms = <4>;
+ vddana-supply = <&vdd_3v3_lp_reg>;
+ vref-supply = <&vdd_3v3_lp_reg>;
+ atmel,trigger-edge-type = <IRQ_TYPE_EDGE_BOTH>;
+ dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
+ dma-names = "rx";
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/atmel,sama9260-adc.yaml b/dts/Bindings/iio/adc/atmel,sama9260-adc.yaml
new file mode 100644
index 0000000000..e6a1f915b5
--- /dev/null
+++ b/dts/Bindings/iio/adc/atmel,sama9260-adc.yaml
@@ -0,0 +1,121 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/atmel,sama9260-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AT91 sama9260 and similar Analog to Digital Converter (ADC)
+
+maintainers:
+ - Alexandre Belloni <alexandre.belloni@bootlin.com>
+
+properties:
+ compatible:
+ enum:
+ - atmel,at91sam9260-adc
+ - atmel,at91sam9rl-adc
+ - atmel,at91sam9g45-adc
+ - atmel,at91sam9x5-adc
+ - atmel,at91sama5d3-adc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: adc_clk
+ - const: adc_op_clk
+
+ atmel,adc-channels-used:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Bitmask of the channels muxed and enabled for this device
+
+ atmel,adc-startup-time:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Startup Time of the ADC in microseconds as defined in the datasheet
+
+ atmel,adc-vref:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Reference voltage in millivolts for the conversions
+
+ atmel,adc-use-external-triggers:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Enable the external triggers
+
+ atmel,adc-use-res:
+ $ref: /schemas/types.yaml#/definitions/string
+ description:
+ String corresponding to an identifier from atmel,adc-res-names property.
+ If not specified, the highest resolution will be used.
+ enum:
+ - "lowres"
+ - "highres"
+
+ atmel,adc-sleep-mode:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Enable sleep mode when no conversion
+
+ atmel,adc-sample-hold-time:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Sample and Hold Time in microseconds
+
+ atmel,adc-ts-wires:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Number of touchscreen wires. Must be set to enable touchscreen.
+ NOTE: when adc touchscreen is enabled, the adc hardware trigger will be
+ disabled. Since touchscreen will occupy the trigger register.
+ enum:
+ - 4
+ - 5
+
+ atmel,adc-ts-pressure-threshold:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Pressure threshold for touchscreen.
+
+ "#io-channel-cells":
+ const: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - atmel,adc-channels-used
+ - atmel,adc-startup-time
+ - atmel,adc-vref
+
+examples:
+ - |
+ #include <dt-bindings/dma/at91.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ adc@fffb0000 {
+ compatible = "atmel,at91sam9260-adc";
+ reg = <0xfffb0000 0x100>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&adc_clk>, <&adc_op_clk>;
+ clock-names = "adc_clk", "adc_op_clk";
+ atmel,adc-channels-used = <0xff>;
+ atmel,adc-startup-time = <40>;
+ atmel,adc-use-external-triggers;
+ atmel,adc-vref = <3300>;
+ atmel,adc-use-res = "lowres";
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/axp20x_adc.txt b/dts/Bindings/iio/adc/axp20x_adc.txt
deleted file mode 100644
index 7a63139139..0000000000
--- a/dts/Bindings/iio/adc/axp20x_adc.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-* X-Powers AXP ADC bindings
-
-Required properties:
- - compatible: should be one of:
- - "x-powers,axp209-adc",
- - "x-powers,axp221-adc",
- - "x-powers,axp813-adc",
- - #io-channel-cells: should be 1,
-
-Example:
-
-&axp22x {
- adc {
- compatible = "x-powers,axp221-adc";
- #io-channel-cells = <1>;
- };
-};
-
-ADC channels and their indexes per variant:
-
-AXP209
-------
- 0 | acin_v
- 1 | acin_i
- 2 | vbus_v
- 3 | vbus_i
- 4 | pmic_temp
- 5 | gpio0_v
- 6 | gpio1_v
- 7 | ipsout_v
- 8 | batt_v
- 9 | batt_chrg_i
-10 | batt_dischrg_i
-
-AXP22x
-------
- 0 | pmic_temp
- 1 | batt_v
- 2 | batt_chrg_i
- 3 | batt_dischrg_i
-
-AXP813
-------
- 0 | pmic_temp
- 1 | gpio0_v
- 2 | batt_v
- 3 | batt_chrg_i
- 4 | batt_dischrg_i
diff --git a/dts/Bindings/iio/adc/brcm,iproc-static-adc.txt b/dts/Bindings/iio/adc/brcm,iproc-static-adc.txt
deleted file mode 100644
index 7b1b1e4086..0000000000
--- a/dts/Bindings/iio/adc/brcm,iproc-static-adc.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-* Broadcom's IPROC Static ADC controller
-
-Broadcom iProc ADC controller has 8 channels 10bit ADC.
-Allows user to convert analog input voltage values to digital.
-
-Required properties:
-
-- compatible: Must be "brcm,iproc-static-adc"
-
-- adc-syscon: Handler of syscon node defining physical base address of the
- controller and length of memory mapped region.
-
-- #io-channel-cells = <1>; As ADC has multiple outputs
- refer to Documentation/devicetree/bindings/iio/iio-bindings.txt for details.
-
-- io-channel-ranges:
- refer to Documentation/devicetree/bindings/iio/iio-bindings.txt for details.
-
-- clocks: Clock used for this block.
-
-- clock-names: Clock name should be given as tsc_clk.
-
-- interrupts: interrupt line number.
-
-For example:
-
- ts_adc_syscon: ts_adc_syscon@180a6000 {
- compatible = "brcm,iproc-ts-adc-syscon","syscon";
- reg = <0x180a6000 0xc30>;
- };
-
- adc: adc@180a6000 {
- compatible = "brcm,iproc-static-adc";
- adc-syscon = <&ts_adc_syscon>;
- #io-channel-cells = <1>;
- io-channel-ranges;
- clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
- clock-names = "tsc_clk";
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- };
diff --git a/dts/Bindings/iio/adc/brcm,iproc-static-adc.yaml b/dts/Bindings/iio/adc/brcm,iproc-static-adc.yaml
new file mode 100644
index 0000000000..c562d25bee
--- /dev/null
+++ b/dts/Bindings/iio/adc/brcm,iproc-static-adc.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/brcm,iproc-static-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom's IPROC Static ADC controller
+
+maintainers:
+ - Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
+
+description: |
+ Broadcom iProc ADC controller has 8 10bit channels
+
+properties:
+ compatible:
+ const: brcm,iproc-static-adc
+
+ adc-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ syscon node defining physical base address of the controller and length
+ of memory mapped region.
+
+ "#io-channel-cells":
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: tsc_clk
+
+ interrupts:
+ maxItems: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - adc-syscon
+ - "#io-channel-cells"
+ - clocks
+ - clock-names
+ - interrupts
+
+examples:
+ - |
+ #include <dt-bindings/clock/bcm-cygnus.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ts_adc_syscon: ts_adc_syscon@180a6000 {
+ compatible = "brcm,iproc-ts-adc-syscon","syscon";
+ reg = <0x180a6000 0xc30>;
+ };
+
+ adc {
+ compatible = "brcm,iproc-static-adc";
+ adc-syscon = <&ts_adc_syscon>;
+ #io-channel-cells = <1>;
+ clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
+ clock-names = "tsc_clk";
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/envelope-detector.txt b/dts/Bindings/iio/adc/envelope-detector.txt
deleted file mode 100644
index 27544bdd44..0000000000
--- a/dts/Bindings/iio/adc/envelope-detector.txt
+++ /dev/null
@@ -1,54 +0,0 @@
-Bindings for ADC envelope detector using a DAC and a comparator
-
-The DAC is used to find the peak level of an alternating voltage input
-signal by a binary search using the output of a comparator wired to
-an interrupt pin. Like so:
- _
- | \
- input +------>-------|+ \
- | \
- .-------. | }---.
- | | | / |
- | dac|-->--|- / |
- | | |_/ |
- | | |
- | | |
- | irq|------<-------'
- | |
- '-------'
-
-Required properties:
-- compatible: Should be "axentia,tse850-envelope-detector"
-- io-channels: Channel node of the dac to be used for comparator input.
-- io-channel-names: Should be "dac".
-- interrupt specification for one client interrupt,
- see ../../interrupt-controller/interrupts.txt for details.
-- interrupt-names: Should be "comp".
-
-Example:
-
- &i2c {
- dpot: mcp4651-104@28 {
- compatible = "microchip,mcp4651-104";
- reg = <0x28>;
- #io-channel-cells = <1>;
- };
- };
-
- dac: dac {
- compatible = "dpot-dac";
- vref-supply = <&reg_3v3>;
- io-channels = <&dpot 0>;
- io-channel-names = "dpot";
- #io-channel-cells = <1>;
- };
-
- envelope-detector {
- compatible = "axentia,tse850-envelope-detector";
- io-channels = <&dac 0>;
- io-channel-names = "dac";
-
- interrupt-parent = <&gpio>;
- interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
- interrupt-names = "comp";
- };
diff --git a/dts/Bindings/iio/adc/envelope-detector.yaml b/dts/Bindings/iio/adc/envelope-detector.yaml
new file mode 100644
index 0000000000..296d5459b4
--- /dev/null
+++ b/dts/Bindings/iio/adc/envelope-detector.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/envelope-detector.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ADC envelope detector using a DAC and a comparator
+
+maintainers:
+ - Peter Rosin <peda@axentia.se>
+
+description: |
+ The DAC is used to find the peak level of an alternating voltage input
+ signal by a binary search using the output of a comparator wired to
+ an interrupt pin. Like so:
+ _
+ | \
+ input +------>-------|+ \
+ | \
+ .-------. | }---.
+ | | | / |
+ | dac|-->--|- / |
+ | | |_/ |
+ | | |
+ | | |
+ | irq|------<-------'
+ | |
+ '-------'
+
+properties:
+ compatible:
+ const: axentia,tse850-envelope-detector
+
+ io-channels:
+ maxItems: 1
+ description: Channel node of the dac to be used for comparator input.
+
+ io-channel-names:
+ const: dac
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ const: comp
+
+required:
+ - compatible
+ - io-channels
+ - io-channel-names
+ - interrupts
+ - interrupt-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dpot: dpot@28 {
+ compatible = "microchip,mcp4651-104";
+ reg = <0x28>;
+ #io-channel-cells = <1>;
+ };
+ };
+
+ dac: dac {
+ compatible = "dpot-dac";
+ vref-supply = <&reg_3v3>;
+ io-channels = <&dpot 0>;
+ io-channel-names = "dpot";
+ #io-channel-cells = <1>;
+ };
+
+ envelope-detector {
+ compatible = "axentia,tse850-envelope-detector";
+ io-channels = <&dac 0>;
+ io-channel-names = "dac";
+
+ interrupt-parent = <&gpio>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "comp";
+ };
+...
diff --git a/dts/Bindings/iio/adc/lltc,ltc2496.yaml b/dts/Bindings/iio/adc/lltc,ltc2496.yaml
index 6a991e9f78..2716d4e953 100644
--- a/dts/Bindings/iio/adc/lltc,ltc2496.yaml
+++ b/dts/Bindings/iio/adc/lltc,ltc2496.yaml
@@ -17,8 +17,7 @@ properties:
- lltc,ltc2496
vref-supply:
- description: phandle to an external regulator providing the reference voltage
- $ref: /schemas/types.yaml#/definitions/phandle
+ description: Power supply for the reference voltage
reg:
description: spi chipselect number according to the usual spi bindings
diff --git a/dts/Bindings/iio/adc/maxim,max1027.yaml b/dts/Bindings/iio/adc/maxim,max1027.yaml
new file mode 100644
index 0000000000..46b7747076
--- /dev/null
+++ b/dts/Bindings/iio/adc/maxim,max1027.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/maxim,max1027.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX1027 and similar ADCs
+
+maintainers:
+ - Miquel Raynal <miquel.raynal@bootlin.com>
+ - Philippe Reynes <tremyfr@yahoo.fr>
+
+description: |
+ 300ks/s SPI ADCs with temperature sensors.
+
+properties:
+ compatible:
+ enum:
+ # 10-bit 8 channels
+ - maxim,max1027
+ # 10-bit 12 channels
+ - maxim,max1029
+ # 10-bit 16 channels
+ - maxim,max1031
+ # 12-bit 8 channels
+ - maxim,max1227
+ # 12-bit 12 channels
+ - maxim,max1229
+ # 12-bit 16 channels
+ - maxim,max1231
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 10000000
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ maxadc: adc@0 {
+ compatible = "maxim,max1027";
+ reg = <0>;
+ #io-channel-cells = <1>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <15 IRQ_TYPE_EDGE_RISING>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/mediatek,mt2701-auxadc.yaml b/dts/Bindings/iio/adc/mediatek,mt2701-auxadc.yaml
new file mode 100644
index 0000000000..5b21a9fba5
--- /dev/null
+++ b/dts/Bindings/iio/adc/mediatek,mt2701-auxadc.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/mediatek,mt2701-auxadc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek AUXADC - ADC on Mediatek mobile SoC (mt65xx/mt81xx/mt27xx)
+
+maintainers:
+ - Zhiyong Tao <zhiyong.tao@mediatek.com>
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+ The Auxiliary Analog/Digital Converter (AUXADC) is an ADC found
+ in some Mediatek SoCs which among other things measures the temperatures
+ in the SoC. It can be used directly with register accesses, but it is also
+ used by thermal controller which reads the temperatures from the AUXADC
+ directly via its own bus interface. See mediatek-thermal bindings
+ for the Thermal Controller which holds a phandle to the AUXADC.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - mediatek,mt2701-auxadc
+ - mediatek,mt2712-auxadc
+ - mediatek,mt6765-auxadc
+ - mediatek,mt7622-auxadc
+ - mediatek,mt8173-auxadc
+ - items:
+ - enum:
+ - mediatek,mt7623-auxadc
+ - const: mediatek,mt2701-auxadc
+ - items:
+ - enum:
+ - mediatek,mt8183-auxadc
+ - mediatek,mt8516-auxadc
+ - const: mediatek,mt8173-auxadc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: main
+
+ "#io-channel-cells":
+ const: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#io-channel-cells"
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ adc@11001000 {
+ compatible = "mediatek,mt8183-auxadc",
+ "mediatek,mt8173-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/mediatek,mt6360-adc.yaml b/dts/Bindings/iio/adc/mediatek,mt6360-adc.yaml
new file mode 100644
index 0000000000..db4e3613c1
--- /dev/null
+++ b/dts/Bindings/iio/adc/mediatek,mt6360-adc.yaml
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/mediatek,mt6360-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek MT6360 and similar ADCs
+
+maintainers:
+ - Gene Chen <gene_chen@richtek.com>
+
+properties:
+ compatible:
+ const: mediatek,mt6360-adc
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - "#io-channel-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ adc {
+ compatible = "mediatek,mt6360-adc";
+ #io-channel-cells = <1>;
+ };
+...
diff --git a/dts/Bindings/iio/adc/mt6577_auxadc.txt b/dts/Bindings/iio/adc/mt6577_auxadc.txt
deleted file mode 100644
index 78c06e05c8..0000000000
--- a/dts/Bindings/iio/adc/mt6577_auxadc.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-* Mediatek AUXADC - Analog to Digital Converter on Mediatek mobile soc (mt65xx/mt81xx/mt27xx)
-===============
-
-The Auxiliary Analog/Digital Converter (AUXADC) is an ADC found
-in some Mediatek SoCs which among other things measures the temperatures
-in the SoC. It can be used directly with register accesses, but it is also
-used by thermal controller which reads the temperatures from the AUXADC
-directly via its own bus interface. See
-Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
-for the Thermal Controller which holds a phandle to the AUXADC.
-
-Required properties:
- - compatible: Should be one of:
- - "mediatek,mt2701-auxadc": For MT2701 family of SoCs
- - "mediatek,mt2712-auxadc": For MT2712 family of SoCs
- - "mediatek,mt6765-auxadc": For MT6765 family of SoCs
- - "mediatek,mt7622-auxadc": For MT7622 family of SoCs
- - "mediatek,mt8173-auxadc": For MT8173 family of SoCs
- - "mediatek,mt8183-auxadc", "mediatek,mt8173-auxadc": For MT8183 family of SoCs
- - reg: Address range of the AUXADC unit.
- - clocks: Should contain a clock specifier for each entry in clock-names
- - clock-names: Should contain "main".
- - #io-channel-cells: Should be 1, see ../iio-bindings.txt
-
-Example:
-
-auxadc: adc@11001000 {
- compatible = "mediatek,mt2701-auxadc";
- reg = <0 0x11001000 0 0x1000>;
- clocks = <&pericfg CLK_PERI_AUXADC>;
- clock-names = "main";
- #io-channel-cells = <1>;
-};
diff --git a/dts/Bindings/iio/adc/palmas-gpadc.txt b/dts/Bindings/iio/adc/palmas-gpadc.txt
deleted file mode 100644
index 4bb9a86065..0000000000
--- a/dts/Bindings/iio/adc/palmas-gpadc.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-* Palmas general purpose ADC IP block devicetree bindings
-
-Channels list:
- 0 battery type
- 1 battery temp NTC (optional current source)
- 2 GP
- 3 temp (with ext. diode, optional current source)
- 4 GP
- 5 GP
- 6 VBAT_SENSE
- 7 VCC_SENSE
- 8 Backup Battery voltage
- 9 external charger (VCHG)
- 10 VBUS
- 11 DC-DC current probe (how does this work?)
- 12 internal die temp
- 13 internal die temp
- 14 USB ID pin voltage
- 15 test network
-
-Required properties:
-- compatible : Must be "ti,palmas-gpadc".
-- #io-channel-cells: Should be set to <1>.
-
-Optional sub-nodes:
-ti,channel0-current-microamp: Channel 0 current in uA.
- Values are rounded to derive 0uA, 5uA, 15uA, 20uA.
-ti,channel3-current-microamp: Channel 3 current in uA.
- Values are rounded to derive 0uA, 10uA, 400uA, 800uA.
-ti,enable-extended-delay: Enable extended delay.
-
-Example:
-
-pmic {
- compatible = "ti,twl6035-pmic", "ti,palmas-pmic";
- ...
- gpadc {
- compatible = "ti,palmas-gpadc";
- interrupts = <18 0
- 16 0
- 17 0>;
- #io-channel-cells = <1>;
- ti,channel0-current-microamp = <5>;
- ti,channel3-current-microamp = <10>;
- };
- };
- ...
-};
diff --git a/dts/Bindings/iio/adc/qcom,pm8018-adc.yaml b/dts/Bindings/iio/adc/qcom,pm8018-adc.yaml
new file mode 100644
index 0000000000..d186b713d6
--- /dev/null
+++ b/dts/Bindings/iio/adc/qcom,pm8018-adc.yaml
@@ -0,0 +1,166 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/qcom,pm8018-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm's PM8xxx voltage XOADC
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+description: |
+ The Qualcomm PM8xxx PMICs contain a HK/XO ADC (Housekeeping/Crystal
+ oscillator ADC) encompassing PM8018, PM8038, PM8058 and PM8921.
+
+properties:
+ compatible:
+ enum:
+ - qcom,pm8018-adc
+ - qcom,pm8038-adc
+ - qcom,pm8058-adc
+ - qcom,pm8921-adc
+
+ reg:
+ maxItems: 1
+ description:
+ ADC base address in the PMIC, typically 0x197.
+
+ xoadc-ref-supply:
+ description:
+ The reference voltage may vary with PMIC variant but is typically
+ something like 2.2 or 1.8V.
+
+ interrupts:
+ maxItems: 1
+
+ "#address-cells":
+ const: 2
+ description:
+ The first cell is the prescaler (on PM8058) or premux (on PM8921)
+ with two valid bits so legal values are 0x00, 0x01 or 0x02.
+ The second cell is the main analog mux setting (0x00..0x0f).
+ The combination of prescaler/premux and analog mux uniquely addresses
+ a hardware channel on all systems.
+
+ "#size-cells":
+ const: 0
+
+ "#io-channel-cells":
+ const: 2
+ description:
+ The cells are precaler or premux followed by the analog muxing line.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - "#io-channel-cells"
+ - "#address-cells"
+ - "#size-cells"
+ - adc-channel@c
+ - adc-channel@d
+ - adc-channel@f
+
+patternProperties:
+ "^(adc-channel@)[0-9a-f]$":
+ type: object
+ description: |
+ ADC channel specific configuration.
+ Note that channels c, d and f must be present for calibration.
+ These three nodes are used for absolute and ratiometric calibration
+ and only need to have these reg values: they are by hardware definition
+ 1:1 ratio converters that sample 625, 1250 and 0 milliV and create
+ an interpolation calibration for all other ADCs.
+
+ properties:
+ reg:
+ maxItems: 1
+
+ qcom,decimation:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ This parameter is used to decrease the ADC sampling rate.
+ Quicker measurements can be made by reducing the decimation ratio.
+ Valid values are 512, 1024, 2048, 4096.
+ If the property is not found, a default value of 512 will be used.
+
+ qcom,ratiometric:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Channel calibration type. If this property is specified
+ VADC will use a special voltage references for channel
+ calibration. The available references are specified in the
+ as a u32 value setting (see below) and it is compulsory
+ to also specify this reference if ratiometric calibration
+ is selected.
+
+ If the property is not found, the channel will be
+ calibrated with the 0.625V and 1.25V reference channels, also
+ known as an absolute calibration.
+
+ The reference voltage pairs when using ratiometric calibration:
+ 0 = XO_IN/XOADC_GND
+ 1 = PMIC_IN/XOADC_GND
+ 2 = PMIC_IN/BMS_CSP
+ 3 (invalid)
+ 4 = XOADC_GND/XOADC_GND
+ 5 = XOADC_VREF/XOADC_GND
+
+ additionalProperties: false
+
+ required:
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ pmic {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@197 {
+ compatible = "qcom,pm8058-adc";
+ reg = <0x197>;
+ interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #io-channel-cells = <2>;
+
+ vcoin: adc-channel@0 {
+ reg = <0x00 0x00>;
+ };
+ vbat: adc-channel@1 {
+ reg = <0x00 0x01>;
+ };
+ dcin: adc-channel@2 {
+ reg = <0x00 0x02>;
+ };
+ ichg: adc-channel@3 {
+ reg = <0x00 0x03>;
+ };
+ vph_pwr: adc-channel@4 {
+ reg = <0x00 0x04>;
+ };
+ usb_vbus: adc-channel@a {
+ reg = <0x00 0x0a>;
+ };
+ die_temp: adc-channel@b {
+ reg = <0x00 0x0b>;
+ };
+ ref_625mv: adc-channel@c {
+ reg = <0x00 0x0c>;
+ };
+ ref_1250mv: adc-channel@d {
+ reg = <0x00 0x0d>;
+ };
+ ref_325mv: adc-channel@e {
+ reg = <0x00 0x0e>;
+ };
+ ref_muxoff: adc-channel@f {
+ reg = <0x00 0x0f>;
+ };
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/qcom,pm8xxx-xoadc.txt b/dts/Bindings/iio/adc/qcom,pm8xxx-xoadc.txt
deleted file mode 100644
index 3ae0612778..0000000000
--- a/dts/Bindings/iio/adc/qcom,pm8xxx-xoadc.txt
+++ /dev/null
@@ -1,157 +0,0 @@
-Qualcomm's PM8xxx voltage XOADC
-
-The Qualcomm PM8xxx PMICs contain a HK/XO ADC (Housekeeping/Crystal
-oscillator ADC) encompassing PM8018, PM8038, PM8058 and PM8921.
-
-Required properties:
-
-- compatible: should be one of:
- "qcom,pm8018-adc"
- "qcom,pm8038-adc"
- "qcom,pm8058-adc"
- "qcom,pm8921-adc"
-
-- reg: should contain the ADC base address in the PMIC, typically
- 0x197.
-
-- xoadc-ref-supply: should reference a regulator that can supply
- a reference voltage on demand. The reference voltage may vary
- with PMIC variant but is typically something like 2.2 or 1.8V.
-
-The following required properties are standard for IO channels, see
-iio-bindings.txt for more details, but notice that this particular
-ADC has a special addressing scheme that require two cells for
-identifying each ADC channel:
-
-- #address-cells: should be set to <2>, the first cell is the
- prescaler (on PM8058) or premux (on PM8921) with two valid bits
- so legal values are 0x00, 0x01 or 0x02. The second cell
- is the main analog mux setting (0x00..0x0f). The combination
- of prescaler/premux and analog mux uniquely addresses a hardware
- channel on all systems.
-
-- #size-cells: should be set to <0>
-
-- #io-channel-cells: should be set to <2>, again the cells are
- precaler or premux followed by the analog muxing line.
-
-- interrupts: should refer to the parent PMIC interrupt controller
- and reference the proper ADC interrupt.
-
-Required subnodes:
-
-The ADC channels are configured as subnodes of the ADC.
-
-Since some of them are used for calibrating the ADC, these nodes are
-compulsory:
-
-adc-channel@c {
- reg = <0x00 0x0c>;
-};
-
-adc-channel@d {
- reg = <0x00 0x0d>;
-};
-
-adc-channel@f {
- reg = <0x00 0x0f>;
-};
-
-These three nodes are used for absolute and ratiometric calibration
-and only need to have these reg values: they are by hardware definition
-1:1 ratio converters that sample 625, 1250 and 0 milliV and create
-an interpolation calibration for all other ADCs.
-
-Optional subnodes: any channels other than channels [0x00 0x0c],
-[0x00 0x0d] and [0x00 0x0f] are optional.
-
-Required channel node properties:
-
-- reg: should contain the hardware channel number in the range
- 0 .. 0xff (8 bits).
-
-Optional channel node properties:
-
-- qcom,decimation:
- Value type: <u32>
- Definition: This parameter is used to decrease the ADC sampling rate.
- Quicker measurements can be made by reducing the decimation ratio.
- Valid values are 512, 1024, 2048, 4096.
- If the property is not found, a default value of 512 will be used.
-
-- qcom,ratiometric:
- Value type: <u32>
- Definition: Channel calibration type. If this property is specified
- VADC will use a special voltage references for channel
- calibration. The available references are specified in the
- as a u32 value setting (see below) and it is compulsory
- to also specify this reference if ratiometric calibration
- is selected.
-
- If the property is not found, the channel will be
- calibrated with the 0.625V and 1.25V reference channels, also
- known as an absolute calibration.
- The reference voltage pairs when using ratiometric calibration:
- 0 = XO_IN/XOADC_GND
- 1 = PMIC_IN/XOADC_GND
- 2 = PMIC_IN/BMS_CSP
- 3 (invalid)
- 4 = XOADC_GND/XOADC_GND
- 5 = XOADC_VREF/XOADC_GND
-
-Example:
-
-xoadc: xoadc@197 {
- compatible = "qcom,pm8058-adc";
- reg = <0x197>;
- interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <2>;
- #size-cells = <0>;
- #io-channel-cells = <2>;
-
- vcoin: adc-channel@0 {
- reg = <0x00 0x00>;
- };
- vbat: adc-channel@1 {
- reg = <0x00 0x01>;
- };
- dcin: adc-channel@2 {
- reg = <0x00 0x02>;
- };
- ichg: adc-channel@3 {
- reg = <0x00 0x03>;
- };
- vph_pwr: adc-channel@4 {
- reg = <0x00 0x04>;
- };
- usb_vbus: adc-channel@a {
- reg = <0x00 0x0a>;
- };
- die_temp: adc-channel@b {
- reg = <0x00 0x0b>;
- };
- ref_625mv: adc-channel@c {
- reg = <0x00 0x0c>;
- };
- ref_1250mv: adc-channel@d {
- reg = <0x00 0x0d>;
- };
- ref_325mv: adc-channel@e {
- reg = <0x00 0x0e>;
- };
- ref_muxoff: adc-channel@f {
- reg = <0x00 0x0f>;
- };
-};
-
-/* IIO client node */
-iio-hwmon {
- compatible = "iio-hwmon";
- io-channels = <&xoadc 0x00 0x01>, /* Battery */
- <&xoadc 0x00 0x02>, /* DC in (charger) */
- <&xoadc 0x00 0x04>, /* VPH the main system voltage */
- <&xoadc 0x00 0x0b>, /* Die temperature */
- <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
- <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
- <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */
-};
diff --git a/dts/Bindings/iio/adc/qcom,spmi-iadc.txt b/dts/Bindings/iio/adc/qcom,spmi-iadc.txt
deleted file mode 100644
index 4e36d6e2f7..0000000000
--- a/dts/Bindings/iio/adc/qcom,spmi-iadc.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-Qualcomm's SPMI PMIC current ADC
-
-QPNP PMIC current ADC (IADC) provides interface to clients to read current.
-A 16 bit ADC is used for current measurements. IADC can measure the current
-through an external resistor (channel 1) or internal (built-in) resistor
-(channel 0). When using an external resistor it is to be described by
-qcom,external-resistor-micro-ohms property.
-
-IADC node:
-
-- compatible:
- Usage: required
- Value type: <string>
- Definition: Should contain "qcom,spmi-iadc".
-
-- reg:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: IADC base address and length in the SPMI PMIC register map
-
-- interrupts:
- Usage: optional
- Value type: <prop-encoded-array>
- Definition: End of ADC conversion.
-
-- qcom,external-resistor-micro-ohms:
- Usage: optional
- Value type: <u32>
- Definition: Sense resister value in micro Ohm.
- If not defined value of 10000 micro Ohms will be used.
-
-Example:
- /* IADC node */
- pmic_iadc: iadc@3600 {
- compatible = "qcom,spmi-iadc";
- reg = <0x3600 0x100>;
- interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>;
- qcom,external-resistor-micro-ohms = <10000>;
- #io-channel-cells = <1>;
- };
-
- /* IIO client node */
- bat {
- io-channels = <&pmic_iadc 0>;
- io-channel-names = "iadc";
- };
diff --git a/dts/Bindings/iio/adc/qcom,spmi-iadc.yaml b/dts/Bindings/iio/adc/qcom,spmi-iadc.yaml
new file mode 100644
index 0000000000..27e3108661
--- /dev/null
+++ b/dts/Bindings/iio/adc/qcom,spmi-iadc.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-iadc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm's SPMI PMIC current ADC
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+description: |
+ QPNP PMIC current ADC (IADC) provides interface to clients to read current.
+ A 16 bit ADC is used for current measurements. IADC can measure the current
+ through an external resistor (channel 1) or internal (built-in) resistor
+ (channel 0). When using an external resistor it is to be described by
+ qcom,external-resistor-micro-ohms property.
+
+properties:
+ compatible:
+ const: qcom,spmi-iadc
+
+ reg:
+ description: IADC base address and length in the SPMI PMIC register map
+ maxItems: 1
+
+ qcom,external-resistor-micro-ohms:
+ description:
+ Sensor resistor value. If not defined value of 10000 micro Ohms
+ will be used.
+
+ interrupts:
+ maxItems: 1
+ description:
+ End of conversion interrupt.
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spmi_bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pmic_iadc: adc@3600 {
+ compatible = "qcom,spmi-iadc";
+ reg = <0x3600 0x100>;
+ interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>;
+ qcom,external-resistor-micro-ohms = <10000>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/qcom,spmi-vadc.yaml b/dts/Bindings/iio/adc/qcom,spmi-vadc.yaml
index 7f4f827c57..95cc705b96 100644
--- a/dts/Bindings/iio/adc/qcom,spmi-vadc.yaml
+++ b/dts/Bindings/iio/adc/qcom,spmi-vadc.yaml
@@ -48,8 +48,6 @@ properties:
description:
End of conversion interrupt.
- io-channel-ranges: true
-
required:
- compatible
- reg
@@ -249,7 +247,6 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
- io-channel-ranges;
/* Channel node */
adc-chan@39 {
diff --git a/dts/Bindings/iio/adc/renesas,gyroadc.txt b/dts/Bindings/iio/adc/renesas,gyroadc.txt
deleted file mode 100644
index df5b9f2ad8..0000000000
--- a/dts/Bindings/iio/adc/renesas,gyroadc.txt
+++ /dev/null
@@ -1,98 +0,0 @@
-* Renesas R-Car GyroADC device driver
-
-The GyroADC block is a reduced SPI block with up to 8 chipselect lines,
-which supports the SPI protocol of a selected few SPI ADCs. The SPI ADCs
-are sampled by the GyroADC block in a round-robin fashion and the result
-presented in the GyroADC registers.
-
-Required properties:
-- compatible: Should be "<soc-specific>", "renesas,rcar-gyroadc".
- The <soc-specific> should be one of:
- renesas,r8a7791-gyroadc - for the GyroADC block present
- in r8a7791 SoC
- renesas,r8a7792-gyroadc - for the GyroADC with interrupt
- block present in r8a7792 SoC
-- reg: Address and length of the register set for the device
-- clocks: References to all the clocks specified in the clock-names
- property as specified in
- Documentation/devicetree/bindings/clock/clock-bindings.txt.
-- clock-names: Shall contain "fck". The "fck" is the GyroADC block clock.
-- power-domains: Must contain a reference to the PM domain, if available.
-- #address-cells: Should be <1> (setting for the subnodes) for all ADCs
- except for "fujitsu,mb88101a". Should be <0> (setting for
- only subnode) for "fujitsu,mb88101a".
-- #size-cells: Should be <0> (setting for the subnodes)
-
-Sub-nodes:
-You must define subnode(s) which select the connected ADC type and reference
-voltage for the GyroADC channels.
-
-Required properties for subnodes:
-- compatible: Should be either of:
- "fujitsu,mb88101a"
- - Fujitsu MB88101A compatible mode,
- 12bit sampling, up to 4 channels can be sampled in
- round-robin fashion. One Fujitsu chip supplies four
- GyroADC channels with data as it contains four ADCs
- on the chip and thus for 4-channel operation, single
- MB88101A is required. The Cx chipselect lines of the
- MB88101A connect directly to two CHS lines of the
- GyroADC, no demuxer is required. The data out line
- of each MB88101A connects to a shared input pin of
- the GyroADC.
- "ti,adcs7476" or "ti,adc121" or "adi,ad7476"
- - TI ADCS7476 / TI ADC121 / ADI AD7476 compatible mode,
- 15bit sampling, up to 8 channels can be sampled in
- round-robin fashion. One TI/ADI chip supplies single
- ADC channel with data, thus for 8-channel operation,
- 8 chips are required. A 3:8 chipselect demuxer is
- required to connect the nCS line of the TI/ADI chips
- to the GyroADC, while MISO line of each TI/ADI ADC
- connects to a shared input pin of the GyroADC.
- "maxim,max1162" or "maxim,max11100"
- - Maxim MAX1162 / Maxim MAX11100 compatible mode,
- 16bit sampling, up to 8 channels can be sampled in
- round-robin fashion. One Maxim chip supplies single
- ADC channel with data, thus for 8-channel operation,
- 8 chips are required. A 3:8 chipselect demuxer is
- required to connect the nCS line of the MAX chips
- to the GyroADC, while MISO line of each Maxim ADC
- connects to a shared input pin of the GyroADC.
-- reg: Should be the number of the analog input. Should be present
- for all ADCs except "fujitsu,mb88101a".
-- vref-supply: Reference to the channel reference voltage regulator.
-
-Example:
- vref_max1162: regulator-vref-max1162 {
- compatible = "regulator-fixed";
-
- regulator-name = "MAX1162 Vref";
- regulator-min-microvolt = <4096000>;
- regulator-max-microvolt = <4096000>;
- };
-
- adc@e6e54000 {
- compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc";
- reg = <0 0xe6e54000 0 64>;
- clocks = <&mstp9_clks R8A7791_CLK_GYROADC>;
- clock-names = "fck";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-
- pinctrl-0 = <&adc_pins>;
- pinctrl-names = "default";
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- adc@0 {
- reg = <0>;
- compatible = "maxim,max1162";
- vref-supply = <&vref_max1162>;
- };
-
- adc@1 {
- reg = <1>;
- compatible = "maxim,max1162";
- vref-supply = <&vref_max1162>;
- };
- };
diff --git a/dts/Bindings/iio/adc/renesas,rcar-gyroadc.yaml b/dts/Bindings/iio/adc/renesas,rcar-gyroadc.yaml
new file mode 100644
index 0000000000..c115e2e99b
--- /dev/null
+++ b/dts/Bindings/iio/adc/renesas,rcar-gyroadc.yaml
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/renesas,rcar-gyroadc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car GyroADC
+
+maintainers:
+ - Marek Vasut <marek.vasut+renesas@gmail.com>
+
+description: |
+ The GyroADC block is a reduced SPI block with up to 8 chipselect lines,
+ which supports the SPI protocol of a selected few SPI ADCs. The SPI ADCs
+ are sampled by the GyroADC block in a round-robin fashion and the result
+ presented in the GyroADC registers.
+ The ADC bindings should match with that of the devices connected to a
+ full featured SPI bus.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r8a7791-gyroadc
+ - renesas,r8a7792-gyroadc
+ - const: renesas,rcar-gyroadc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: fck
+
+ power-domains: true
+
+ resets: true
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#address-cells"
+ - "#size-cells"
+
+patternProperties:
+ "@[0-7]$":
+ type: object
+ properties:
+ compatible:
+ description: |
+ fujitsu,mb88101a
+ - Fujitsu MB88101A compatible mode,
+ 12bit sampling, up to 4 channels can be sampled in round-robin
+ fashion. One Fujitsu chip supplies four GyroADC channels with
+ data as it contains four ADCs on the chip and thus for 4-channel
+ operation, single MB88101A is required. The Cx chipselect lines
+ of the MB88101A connect directly to two CHS lines of the GyroADC,
+ no demuxer is required. The data out line of each MB88101A
+ connects to a shared input pin of the GyroADC.
+ ti,adcs7476 or ti,adc121 or adi,ad7476
+ - TI ADCS7476 / TI ADC121 / ADI AD7476 compatible mode, 15bit
+ sampling, up to 8 channels can be sampled in round-robin
+ fashion. One TI/ADI chip supplies single ADC channel with data,
+ thus for 8-channel operation, 8 chips are required.
+ A 3:8 chipselect demuxer is required to connect the nCS line
+ of the TI/ADI chips to the GyroADC, while MISO line of each
+ TI/ADI ADC connects to a shared input pin of the GyroADC.
+ maxim,max1162 or maxim,max11100
+ - Maxim MAX1162 / Maxim MAX11100 compatible mode, 16bit sampling,
+ up to 8 channels can be sampled in round-robin fashion. One
+ Maxim chip supplies single ADC channel with data, thus for
+ 8-channel operation, 8 chips are required.
+ A 3:8 chipselect demuxer is required to connect the nCS line
+ of the MAX chips to the GyroADC, while MISO line of each Maxim
+ ADC connects to a shared input pin of the GyroADC.
+ enum:
+ - adi,7476
+ - fujitsu,mb88101a
+ - maxim,max1162
+ - maxim,max11100
+ - ti,adcs7476
+ - ti,adc121
+
+ reg:
+ minimum: 0
+ maximum: 7
+
+ vref-supply: true
+
+ additionalProperties: false
+
+ required:
+ - compatible
+ - reg
+ - vref-supply
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7791-clock.h>
+ #include <dt-bindings/power/r8a7791-sysc.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ adc@e6e54000 {
+ compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc";
+ reg = <0 0xe6e54000 0 64>;
+ clocks = <&mstp9_clks R8A7791_CLK_GYROADC>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+
+ pinctrl-0 = <&adc_pins>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ reg = <0>;
+ compatible = "maxim,max1162";
+ vref-supply = <&vref_max1162>;
+ };
+
+ adc@1 {
+ reg = <1>;
+ compatible = "maxim,max1162";
+ vref-supply = <&vref_max1162>;
+ };
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/samsung,exynos-adc.yaml b/dts/Bindings/iio/adc/samsung,exynos-adc.yaml
index 5ebb0ab250..c65921e66d 100644
--- a/dts/Bindings/iio/adc/samsung,exynos-adc.yaml
+++ b/dts/Bindings/iio/adc/samsung,exynos-adc.yaml
@@ -49,8 +49,6 @@ properties:
"#io-channel-cells":
const: 1
- io-channel-ranges: true
-
vdd-supply: true
samsung,syscon-phandle:
@@ -130,7 +128,6 @@ examples:
reg = <0x12d10000 0x100>;
interrupts = <0 106 0>;
#io-channel-cells = <1>;
- io-channel-ranges;
clocks = <&clock 303>;
clock-names = "adc";
@@ -156,7 +153,6 @@ examples:
reg = <0x126C0000 0x100>;
interrupts = <0 137 0>;
#io-channel-cells = <1>;
- io-channel-ranges;
clocks = <&cmu CLK_TSADC>,
<&cmu CLK_SCLK_TSADC>;
diff --git a/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml
index d61bc011e8..6f2398cdc8 100644
--- a/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml
+++ b/dts/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml
@@ -199,8 +199,6 @@ patternProperties:
description:
From common IIO binding. Used to pipe external sigma delta
modulator or internal ADC output to DFSDM channel.
- This is not required for "st,stm32-dfsdm-pdm" compatibility as
- PDM microphone is binded in Audio DT node.
required:
- io-channels
@@ -235,6 +233,10 @@ patternProperties:
description: child node
properties:
+ compatible:
+ enum:
+ - st,stm32h7-dfsdm-dai
+
"#sound-dai-cells":
const: 0
@@ -244,6 +246,7 @@ patternProperties:
modulator or internal ADC output to DFSDM channel.
required:
+ - compatible
- "#sound-dai-cells"
- io-channels
diff --git a/dts/Bindings/iio/adc/ti,adc084s021.yaml b/dts/Bindings/iio/adc/ti,adc084s021.yaml
new file mode 100644
index 0000000000..1a113b30a4
--- /dev/null
+++ b/dts/Bindings/iio/adc/ti,adc084s021.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,adc084s021.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments ADC084S021 ADC
+
+maintainers:
+ - Mårten Lindahl <martenli@axis.com>
+
+description: |
+ 8 bit ADC with 4 channels
+
+properties:
+ compatible:
+ const: ti,adc084s021
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency: true
+
+ vref-supply:
+ description: External reference, needed to establish input scaling
+
+ spi-cpol: true
+ spi-cpha: true
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+ - spi-cpol
+ - spi-cpha
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,adc084s021";
+ reg = <0>;
+ vref-supply = <&adc_vref>;
+ spi-cpol;
+ spi-cpha;
+ spi-max-frequency = <16000000>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/ti,ads124s08.yaml b/dts/Bindings/iio/adc/ti,ads124s08.yaml
new file mode 100644
index 0000000000..9f5e96439c
--- /dev/null
+++ b/dts/Bindings/iio/adc/ti,ads124s08.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,ads124s08.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments' ads124s08 and ads124s06 ADC chip
+
+maintainers:
+ - Dan Murphy <dmurphy@ti.com>
+
+properties:
+ compatible:
+ enum:
+ - ti,ads124s06
+ - ti,ads124s08
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency: true
+
+ spi-cpha: true
+
+ reset-gpios:
+ maxItems: 1
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,ads124s08";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ spi-cpha;
+ reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/ti,palmas-gpadc.yaml b/dts/Bindings/iio/adc/ti,palmas-gpadc.yaml
new file mode 100644
index 0000000000..692dacd0fe
--- /dev/null
+++ b/dts/Bindings/iio/adc/ti,palmas-gpadc.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,palmas-gpadc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Palmas general purpose ADC IP block devicetree bindings
+
+maintainers:
+ - Tony Lindgren <tony@atomide.com>
+
+description: |
+ This ADC is often used to provide channels via the io-channels
+ consumer framework.
+ Channels list:
+ 0 battery type
+ 1 battery temp NTC (optional current source)
+ 2 GP
+ 3 temp (with ext. diode, optional current source)
+ 4 GP
+ 5 GP
+ 6 VBAT_SENSE
+ 7 VCC_SENSE
+ 8 Backup Battery voltage
+ 9 external charger (VCHG)
+ 10 VBUS
+ 11 DC-DC current probe (how does this work?)
+ 12 internal die temp
+ 13 internal die temp
+ 14 USB ID pin voltage
+ 15 test network
+
+properties:
+ compatible:
+ const: ti,palmas-gpadc
+
+ interrupts:
+ minItems: 1
+ maxItems: 3
+
+ "#io-channel-cells":
+ const: 1
+
+ ti,channel0-current-microamp:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Channel 0 current in uA.
+ enum:
+ - 0
+ - 5
+ - 15
+ - 20
+
+ ti,channel3-current-microamp:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Channel 3 current in uA.
+ enum:
+ - 0
+ - 10
+ - 400
+ - 800
+
+ ti,enable-extended-delay:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Enable extended delay.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - "#io-channel-cells"
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ pmic {
+ compatible = "ti,twl6035-pmic", "ti,palmas-pmic";
+ adc {
+ compatible = "ti,palmas-gpadc";
+ interrupts = <18 0
+ 16 0
+ 17 0>;
+ #io-channel-cells = <1>;
+ ti,channel0-current-microamp = <5>;
+ ti,channel3-current-microamp = <10>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/adc/ti-adc084s021.txt b/dts/Bindings/iio/adc/ti-adc084s021.txt
deleted file mode 100644
index 4259e50620..0000000000
--- a/dts/Bindings/iio/adc/ti-adc084s021.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-* Texas Instruments' ADC084S021
-
-Required properties:
- - compatible : Must be "ti,adc084s021"
- - reg : SPI chip select number for the device
- - vref-supply : The regulator supply for ADC reference voltage
- - spi-cpol : Per spi-bus bindings
- - spi-cpha : Per spi-bus bindings
- - spi-max-frequency : Per spi-bus bindings
-
-Example:
-adc@0 {
- compatible = "ti,adc084s021";
- reg = <0>;
- vref-supply = <&adc_vref>;
- spi-cpol;
- spi-cpha;
- spi-max-frequency = <16000000>;
-};
diff --git a/dts/Bindings/iio/adc/ti-ads124s08.txt b/dts/Bindings/iio/adc/ti-ads124s08.txt
deleted file mode 100644
index ecf807bb32..0000000000
--- a/dts/Bindings/iio/adc/ti-ads124s08.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-* Texas Instruments' ads124s08 and ads124s06 ADC chip
-
-Required properties:
- - compatible :
- "ti,ads124s08"
- "ti,ads124s06"
- - reg : spi chip select number for the device
-
-Recommended properties:
- - spi-max-frequency : Definition as per
- Documentation/devicetree/bindings/spi/spi-bus.txt
- - spi-cpha : Definition as per
- Documentation/devicetree/bindings/spi/spi-bus.txt
-
-Optional properties:
- - reset-gpios : GPIO pin used to reset the device.
-
-Example:
-adc@0 {
- compatible = "ti,ads124s08";
- reg = <0>;
- spi-max-frequency = <1000000>;
- spi-cpha;
- reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
-};
diff --git a/dts/Bindings/iio/adc/x-powers,axp209-adc.yaml b/dts/Bindings/iio/adc/x-powers,axp209-adc.yaml
new file mode 100644
index 0000000000..5ccbb1f819
--- /dev/null
+++ b/dts/Bindings/iio/adc/x-powers,axp209-adc.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/x-powers,axp209-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: X-Powers AXP ADC bindings
+
+maintainers:
+ - Chen-Yu Tsai <wens@csie.org>
+
+description: |
+ ADC is frequently used as a provider to consumers of the ADC channels.
+ Device is a child of an axp209 multifunction device
+ ADC channels and their indexes per variant:
+
+ AXP209
+ ------
+ 0 | acin_v
+ 1 | acin_i
+ 2 | vbus_v
+ 3 | vbus_i
+ 4 | pmic_temp
+ 5 | gpio0_v
+ 6 | gpio1_v
+ 7 | ipsout_v
+ 8 | batt_v
+ 9 | batt_chrg_i
+ 10 | batt_dischrg_i
+
+ AXP22x
+ ------
+ 0 | pmic_temp
+ 1 | batt_v
+ 2 | batt_chrg_i
+ 3 | batt_dischrg_i
+
+ AXP813
+ ------
+ 0 | pmic_temp
+ 1 | gpio0_v
+ 2 | batt_v
+ 3 | batt_chrg_i
+ 4 | batt_dischrg_i
+
+
+properties:
+ compatible:
+ enum:
+ - x-powers,axp209-adc
+ - x-powers,axp221-adc
+ - x-powers,axp813-adc
+
+ "#io-channel-cells":
+ const: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ axp221 {
+ adc {
+ compatible = "x-powers,axp221-adc";
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/afe/current-sense-amplifier.txt b/dts/Bindings/iio/afe/current-sense-amplifier.txt
deleted file mode 100644
index 821b61b8c5..0000000000
--- a/dts/Bindings/iio/afe/current-sense-amplifier.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-Current Sense Amplifier
-=======================
-
-When an io-channel measures the output voltage from a current sense
-amplifier, the interesting measurement is almost always the current
-through the sense resistor, not the voltage output. This binding
-describes such a current sense circuit.
-
-Required properties:
-- compatible : "current-sense-amplifier"
-- io-channels : Channel node of a voltage io-channel.
-- sense-resistor-micro-ohms : The sense resistance in microohms.
-
-Optional properties:
-- sense-gain-mult: Amplifier gain multiplier. The default is <1>.
-- sense-gain-div: Amplifier gain divider. The default is <1>.
-
-Example:
-
-sysi {
- compatible = "current-sense-amplifier";
- io-channels = <&tiadc 0>;
-
- sense-resistor-micro-ohms = <20000>;
- sense-gain-mul = <50>;
-};
diff --git a/dts/Bindings/iio/afe/current-sense-amplifier.yaml b/dts/Bindings/iio/afe/current-sense-amplifier.yaml
new file mode 100644
index 0000000000..527501c1d6
--- /dev/null
+++ b/dts/Bindings/iio/afe/current-sense-amplifier.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/afe/current-sense-amplifier.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Current Sense Amplifier
+
+maintainers:
+ - Peter Rosin <peda@axentia.se>
+
+description: |
+ When an io-channel measures the output voltage from a current sense
+ amplifier, the interesting measurement is almost always the current
+ through the sense resistor, not the voltage output. This binding
+ describes such a current sense circuit.
+
+properties:
+ compatible:
+ const: current-sense-amplifier
+
+ io-channels:
+ maxItems: 1
+ description: |
+ Channel node of a voltage io-channel.
+
+ sense-resistor-micro-ohms:
+ description: The sense resistance.
+
+ sense-gain-mult:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Amplifier gain multiplier. The default is <1>.
+
+ sense-gain-div:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Amplifier gain divider. The default is <1>.
+
+required:
+ - compatible
+ - io-channels
+ - sense-resistor-micro-ohms
+
+additionalProperties: false
+
+examples:
+ - |
+ sysi {
+ compatible = "current-sense-amplifier";
+ io-channels = <&tiadc 0>;
+
+ sense-resistor-micro-ohms = <20000>;
+ sense-gain-mult = <50>;
+ };
+...
diff --git a/dts/Bindings/iio/afe/current-sense-shunt.txt b/dts/Bindings/iio/afe/current-sense-shunt.txt
deleted file mode 100644
index 0f67108a07..0000000000
--- a/dts/Bindings/iio/afe/current-sense-shunt.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-Current Sense Shunt
-===================
-
-When an io-channel measures the voltage over a current sense shunt,
-the interesting measurement is almost always the current through the
-shunt, not the voltage over it. This binding describes such a current
-sense circuit.
-
-Required properties:
-- compatible : "current-sense-shunt"
-- io-channels : Channel node of a voltage io-channel.
-- shunt-resistor-micro-ohms : The shunt resistance in microohms.
-
-Example:
-The system current is measured by measuring the voltage over a
-3.3 ohms shunt resistor.
-
-sysi {
- compatible = "current-sense-shunt";
- io-channels = <&tiadc 0>;
-
- /* Divide the voltage by 3300000/1000000 (or 3.3) for the current. */
- shunt-resistor-micro-ohms = <3300000>;
-};
-
-&i2c {
- tiadc: adc@48 {
- compatible = "ti,ads1015";
- reg = <0x48>;
- #io-channel-cells = <1>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- channel@0 { /* IN0,IN1 differential */
- reg = <0>;
- ti,gain = <1>;
- ti,datarate = <4>;
- };
- };
-};
diff --git a/dts/Bindings/iio/afe/current-sense-shunt.yaml b/dts/Bindings/iio/afe/current-sense-shunt.yaml
new file mode 100644
index 0000000000..90439a8dc7
--- /dev/null
+++ b/dts/Bindings/iio/afe/current-sense-shunt.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/afe/current-sense-shunt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Current Sense Shunt
+
+maintainers:
+ - Peter Rosin <peda@axentia.se>
+
+description: |
+ When an io-channel measures the voltage over a current sense shunt,
+ the interesting measurement is almost always the current through the
+ shunt, not the voltage over it. This binding describes such a current
+ sense circuit.
+
+properties:
+ compatible:
+ const: current-sense-shunt
+
+ io-channels:
+ maxItems: 1
+ description: |
+ Channel node of a voltage io-channel.
+
+ shunt-resistor-micro-ohms:
+ description: The shunt resistance.
+
+required:
+ - compatible
+ - io-channels
+ - shunt-resistor-micro-ohms
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ tiadc: adc@48 {
+ compatible = "ti,ads1015";
+ reg = <0x48>;
+ #io-channel-cells = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 { /* IN0,IN1 differential */
+ reg = <0>;
+ ti,gain = <1>;
+ ti,datarate = <4>;
+ };
+ };
+ };
+ sysi {
+ compatible = "current-sense-shunt";
+ io-channels = <&tiadc 0>;
+
+ /* Divide the voltage by 3300000/1000000 (or 3.3) for the current. */
+ shunt-resistor-micro-ohms = <3300000>;
+ };
+...
diff --git a/dts/Bindings/iio/afe/voltage-divider.txt b/dts/Bindings/iio/afe/voltage-divider.txt
deleted file mode 100644
index b452a84061..0000000000
--- a/dts/Bindings/iio/afe/voltage-divider.txt
+++ /dev/null
@@ -1,53 +0,0 @@
-Voltage divider
-===============
-
-When an io-channel measures the midpoint of a voltage divider, the
-interesting voltage is often the voltage over the full resistance
-of the divider. This binding describes the voltage divider in such
-a curcuit.
-
- Vin ----.
- |
- .-----.
- | R |
- '-----'
- |
- +---- Vout
- |
- .-----.
- | Rout|
- '-----'
- |
- GND
-
-Required properties:
-- compatible : "voltage-divider"
-- io-channels : Channel node of a voltage io-channel measuring Vout.
-- output-ohms : Resistance Rout over which the output voltage is measured.
- See full-ohms.
-- full-ohms : Resistance R + Rout for the full divider. The io-channel
- is scaled by the Rout / (R + Rout) quotient.
-
-Example:
-The system voltage is circa 12V, but divided down with a 22/222
-voltage divider (R = 200 Ohms, Rout = 22 Ohms) and fed to an ADC.
-
-sysv {
- compatible = "voltage-divider";
- io-channels = <&maxadc 1>;
-
- /* Scale the system voltage by 22/222 to fit the ADC range. */
- output-ohms = <22>;
- full-ohms = <222>; /* 200 + 22 */
-};
-
-&spi {
- maxadc: adc@0 {
- compatible = "maxim,max1027";
- reg = <0>;
- #io-channel-cells = <1>;
- interrupt-parent = <&gpio5>;
- interrupts = <15 IRQ_TYPE_EDGE_RISING>;
- spi-max-frequency = <1000000>;
- };
-};
diff --git a/dts/Bindings/iio/afe/voltage-divider.yaml b/dts/Bindings/iio/afe/voltage-divider.yaml
new file mode 100644
index 0000000000..df2589f214
--- /dev/null
+++ b/dts/Bindings/iio/afe/voltage-divider.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/afe/voltage-divider.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Voltage divider
+
+maintainers:
+ - Peter Rosin <peda@axentia.se>
+
+description: |
+ When an io-channel measures the midpoint of a voltage divider, the
+ interesting voltage is often the voltage over the full resistance
+ of the divider. This binding describes the voltage divider in such
+ a curcuit.
+
+ Vin ----.
+ |
+ .-----.
+ | R |
+ '-----'
+ |
+ +---- Vout
+ |
+ .-----.
+ | Rout|
+ '-----'
+ |
+ GND
+
+
+properties:
+ compatible:
+ const: voltage-divider
+
+ io-channels:
+ maxItems: 1
+ description: |
+ Channel node of a voltage io-channel.
+
+ output-ohms:
+ description:
+ Resistance Rout over which the output voltage is measured. See full-ohms.
+
+ full-ohms:
+ description:
+ Resistance R + Rout for the full divider. The io-channel is scaled by
+ the Rout / (R + Rout) quotient.
+
+required:
+ - compatible
+ - io-channels
+ - output-ohms
+ - full-ohms
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ /*
+ * The system voltage is circa 12V, but divided down with a 22/222
+ * voltage divider (R = 200 Ohms, Rout = 22 Ohms) and fed to an ADC.
+ */
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ maxadc: adc@0 {
+ compatible = "maxim,max1027";
+ reg = <0>;
+ #io-channel-cells = <1>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <15 IRQ_TYPE_EDGE_RISING>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+ sysv {
+ compatible = "voltage-divider";
+ io-channels = <&maxadc 1>;
+
+ /* Scale the system voltage by 22/222 to fit the ADC range. */
+ output-ohms = <22>;
+ full-ohms = <222>; /* 200 + 22 */
+ };
+...
diff --git a/dts/Bindings/iio/chemical/bme680.txt b/dts/Bindings/iio/chemical/bme680.txt
deleted file mode 100644
index 7f3827cfb2..0000000000
--- a/dts/Bindings/iio/chemical/bme680.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-Bosch Sensortec BME680 pressure/temperature/humidity/voc sensors
-
-Required properties:
-- compatible: must be "bosch,bme680"
-
-Example:
-
-bme680@76 {
- compatible = "bosch,bme680";
- reg = <0x76>;
-};
diff --git a/dts/Bindings/iio/chemical/sensirion,sgp30.txt b/dts/Bindings/iio/chemical/sensirion,sgp30.txt
deleted file mode 100644
index 5844ed5817..0000000000
--- a/dts/Bindings/iio/chemical/sensirion,sgp30.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-* Sensirion SGP30/SGPC3 multi-pixel Gas Sensor
-
-Required properties:
-
- - compatible: must be one of
- "sensirion,sgp30"
- "sensirion,sgpc3"
- - reg: the I2C address of the sensor
-
-Example:
-
-gas@58 {
- compatible = "sensirion,sgp30";
- reg = <0x58>;
-};
diff --git a/dts/Bindings/iio/dac/ad5592r.txt b/dts/Bindings/iio/dac/ad5592r.txt
deleted file mode 100644
index 989f96f31c..0000000000
--- a/dts/Bindings/iio/dac/ad5592r.txt
+++ /dev/null
@@ -1,155 +0,0 @@
-Analog Devices AD5592R/AD5593R DAC/ADC device driver
-
-Required properties for the AD5592R:
- - compatible: Must be "adi,ad5592r"
- - reg: SPI chip select number for the device
- - spi-max-frequency: Max SPI frequency to use (< 30000000)
- - spi-cpol: The AD5592R requires inverse clock polarity (CPOL) mode
-
-Required properties for the AD5593R:
- - compatible: Must be "adi,ad5593r"
- - reg: I2C address of the device
-
-Required properties for all supported chips:
- - #address-cells: Should be 1.
- - #size-cells: Should be 0.
- - channel nodes:
- Each child node represents one channel and has the following
- Required properties:
- * reg: Pin on which this channel is connected to.
- * adi,mode: Mode or function of this channel.
- Macros specifying the valid values
- can be found in <dt-bindings/iio/adi,ad5592r.h>.
-
- The following values are currently supported:
- * CH_MODE_UNUSED (the pin is unused)
- * CH_MODE_ADC (the pin is ADC input)
- * CH_MODE_DAC (the pin is DAC output)
- * CH_MODE_DAC_AND_ADC (the pin is DAC output
- but can be monitored by an ADC, since
- there is no disadvantage this
- this should be considered as the
- preferred DAC mode)
- * CH_MODE_GPIO (the pin is registered
- with GPIOLIB)
- Optional properties:
- * adi,off-state: State of this channel when unused or the
- device gets removed. Macros specifying the
- valid values can be found in
- <dt-bindings/iio/adi,ad5592r.h>.
-
- * CH_OFFSTATE_PULLDOWN (the pin is pulled down)
- * CH_OFFSTATE_OUT_LOW (the pin is output low)
- * CH_OFFSTATE_OUT_HIGH (the pin is output high)
- * CH_OFFSTATE_OUT_TRISTATE (the pin is
- tristated output)
-
-
-Optional properties:
- - vref-supply: Phandle to the external reference voltage supply. This should
- only be set if there is an external reference voltage connected to the VREF
- pin. If the property is not set the internal 2.5V reference is used.
- - reset-gpios : GPIO spec for the RESET pin. If specified, it will be
- asserted during driver probe.
- - gpio-controller: Marks the device node as a GPIO controller.
- - #gpio-cells: Should be 2. The first cell is the GPIO number and the second
- cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>.
-
-AD5592R Example:
-
- #include <dt-bindings/iio/adi,ad5592r.h>
-
- vref: regulator-vref {
- compatible = "regulator-fixed";
- regulator-name = "vref-ad559x";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- ad5592r@0 {
- #size-cells = <0>;
- #address-cells = <1>;
- #gpio-cells = <2>;
- compatible = "adi,ad5592r";
- reg = <0>;
-
- spi-max-frequency = <1000000>;
- spi-cpol;
-
- vref-supply = <&vref>; /* optional */
- reset-gpios = <&gpio0 86 0>; /* optional */
- gpio-controller;
-
- channel@0 {
- reg = <0>;
- adi,mode = <CH_MODE_DAC>;
- };
- channel@1 {
- reg = <1>;
- adi,mode = <CH_MODE_ADC>;
- };
- channel@2 {
- reg = <2>;
- adi,mode = <CH_MODE_DAC_AND_ADC>;
- };
- channel@3 {
- reg = <3>;
- adi,mode = <CH_MODE_DAC_AND_ADC>;
- adi,off-state = <CH_OFFSTATE_PULLDOWN>;
- };
- channel@4 {
- reg = <4>;
- adi,mode = <CH_MODE_UNUSED>;
- adi,off-state = <CH_OFFSTATE_PULLDOWN>;
- };
- channel@5 {
- reg = <5>;
- adi,mode = <CH_MODE_GPIO>;
- adi,off-state = <CH_OFFSTATE_PULLDOWN>;
- };
- channel@6 {
- reg = <6>;
- adi,mode = <CH_MODE_GPIO>;
- adi,off-state = <CH_OFFSTATE_PULLDOWN>;
- };
- channel@7 {
- reg = <7>;
- adi,mode = <CH_MODE_GPIO>;
- adi,off-state = <CH_OFFSTATE_PULLDOWN>;
- };
- };
-
-AD5593R Example:
-
- #include <dt-bindings/iio/adi,ad5592r.h>
-
- ad5593r@10 {
- #size-cells = <0>;
- #address-cells = <1>;
- #gpio-cells = <2>;
- compatible = "adi,ad5593r";
- reg = <0x10>;
- gpio-controller;
-
- channel@0 {
- reg = <0>;
- adi,mode = <CH_MODE_DAC>;
- adi,off-state = <CH_OFFSTATE_PULLDOWN>;
- };
- channel@1 {
- reg = <1>;
- adi,mode = <CH_MODE_ADC>;
- adi,off-state = <CH_OFFSTATE_PULLDOWN>;
- };
- channel@2 {
- reg = <2>;
- adi,mode = <CH_MODE_DAC_AND_ADC>;
- adi,off-state = <CH_OFFSTATE_PULLDOWN>;
- };
- channel@6 {
- reg = <6>;
- adi,mode = <CH_MODE_GPIO>;
- adi,off-state = <CH_OFFSTATE_PULLDOWN>;
- };
- };
diff --git a/dts/Bindings/iio/dac/ad5758.txt b/dts/Bindings/iio/dac/ad5758.txt
deleted file mode 100644
index 2f607f41f9..0000000000
--- a/dts/Bindings/iio/dac/ad5758.txt
+++ /dev/null
@@ -1,83 +0,0 @@
-Analog Devices AD5758 DAC device driver
-
-Required properties for the AD5758:
- - compatible: Must be "adi,ad5758"
- - reg: SPI chip select number for the device
- - spi-max-frequency: Max SPI frequency to use (< 50000000)
- - spi-cpha: is the only mode that is supported
-
-Required properties:
-
- - adi,dc-dc-mode: Mode of operation of the dc-to-dc converter
- Dynamic Power Control (DPC)
- In this mode, the AD5758 circuitry senses the output
- voltage and dynamically regulates the supply voltage,
- VDPC+, to meet compliance requirements plus an optimized
- headroom voltage for the output buffer.
-
- Programmable Power Control (PPC)
- In this mode, the VDPC+ voltage is user-programmable to
- a fixed level that needs to accommodate the maximum output
- load required.
-
- The output of the DAC core is either converted to a
- current or voltage output at the VIOUT pin. Only one mode
- can be enabled at any one time.
-
- The following values are currently supported:
- * 1: DPC current mode
- * 2: DPC voltage mode
- * 3: PPC current mode
-
- Depending on the selected output mode (voltage or current) one of the
- two properties must
- be present:
-
- - adi,range-microvolt: Voltage output range
- The array of voltage output ranges must contain two fields:
- * <0 5000000>: 0 V to 5 V voltage range
- * <0 10000000>: 0 V to 10 V voltage range
- * <(-5000000) 5000000>: ±5 V voltage range
- * <(-10000000) 10000000>: ±10 V voltage range
- - adi,range-microamp: Current output range
- The array of current output ranges must contain two fields:
- * <0 20000>: 0 mA to 20 mA current range
- * <0 24000>: 0 mA to 24 mA current range
- * <4 24000>: 4 mA to 20 mA current range
- * <(-20000) 20000>: ±20 mA current range
- * <(-24000) 24000>: ±24 mA current range
- * <(-1000) 22000>: −1 mA to +22 mA current range
-
-Optional properties:
-
- - reset-gpios : GPIO spec for the RESET pin. If specified, it will be
- asserted during driver probe.
-
- - adi,dc-dc-ilim-microamp: The dc-to-dc converter current limit
- The following values are currently supported [uA]:
- * 150000
- * 200000
- * 250000
- * 300000
- * 350000
- * 400000
-
- - adi,slew-time-us: The time it takes for the output to reach the
- full scale [uS]
- The supported range is between 133us up to 1023984375us
-
-AD5758 Example:
-
- dac@0 {
- compatible = "adi,ad5758";
- reg = <0>;
- spi-max-frequency = <1000000>;
- spi-cpha;
-
- reset-gpios = <&gpio 22 0>;
-
- adi,dc-dc-mode = <2>;
- adi,range-microvolt = <0 10000000>;
- adi,dc-dc-ilim-microamp = <200000>;
- adi,slew-time-us = <125000>;
- };
diff --git a/dts/Bindings/iio/dac/ad7303.txt b/dts/Bindings/iio/dac/ad7303.txt
deleted file mode 100644
index 914610f055..0000000000
--- a/dts/Bindings/iio/dac/ad7303.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-Analog Devices AD7303 DAC device driver
-
-Required properties:
- - compatible: Must be "adi,ad7303"
- - reg: SPI chip select number for the device
- - spi-max-frequency: Max SPI frequency to use (< 30000000)
- - Vdd-supply: Phandle to the Vdd power supply
-
-Optional properties:
- - REF-supply: Phandle to the external reference voltage supply. This should
- only be set if there is an external reference voltage connected to the REF
- pin. If the property is not set Vdd/2 is used as the reference voltage.
-
-Example:
-
- ad7303@4 {
- compatible = "adi,ad7303";
- reg = <4>;
- spi-max-frequency = <10000000>;
- Vdd-supply = <&vdd_supply>;
- adi,use-external-reference;
- REF-supply = <&vref_supply>;
- };
diff --git a/dts/Bindings/iio/dac/adi,ad5592r.yaml b/dts/Bindings/iio/dac/adi,ad5592r.yaml
new file mode 100644
index 0000000000..30194880f4
--- /dev/null
+++ b/dts/Bindings/iio/dac/adi,ad5592r.yaml
@@ -0,0 +1,204 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/adi,ad5592r.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD5592R/AD5593R DAC/ADC
+
+maintainers:
+ - Michael Hennerich <michael.hennerich@analog.com>
+
+properties:
+ compatible:
+ enum:
+ - adi,ad5592r
+ - adi,ad5593r
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 30000000
+
+ spi-cpol: true
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ "#io-channel-cells":
+ const: 1
+
+ vref-supply:
+ description: If not set internal 2.5V reference used.
+
+ reset-gpios:
+ maxItems: 1
+
+ gpio-controller:
+ description: Marks the device node as a GPIO controller.
+
+ "#gpio-cells":
+ const: 2
+ description:
+ The first cell is the GPIO number and the second cell specifies
+ GPIO flags, as defined in <dt-bindings/gpio/gpio.h>.
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: adi,ad5592r
+ then:
+ required:
+ - spi-cpol
+ else:
+ properties:
+ spi-cpol: false
+
+additionalProperties: false
+
+patternProperties:
+ "^(channel@)[0-7]$":
+ type: object
+ description: Child node to describe a channel
+ properties:
+ reg:
+ minimum: 0
+ maximum: 7
+
+ adi,mode:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3, 8]
+ description: |
+ Mode or function of this channel.
+ Macros specifying the valid values can be found in
+ <dt-bindings/iio/adi,ad5592r.h>.
+
+ The following values are currently supported:
+ * CH_MODE_UNUSED (the pin is unused)
+ * CH_MODE_ADC (the pin is ADC input)
+ * CH_MODE_DAC (the pin is DAC output)
+ * CH_MODE_DAC_AND_ADC (the pin is DAC output but can be monitored
+ by an ADC, since there is no disadvantage this should be
+ considered as the preferred DAC mode)
+ * CH_MODE_GPIO (the pin is registered with GPIOLIB)
+
+ adi,off-state:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ description: |
+ State of this channel when unused or the device gets removed.
+ Macros specifying the valid values can be found in
+ <dt-bindings/iio/adi,ad5592r.h>.
+ * CH_OFFSTATE_PULLDOWN (the pin is pulled down)
+ * CH_OFFSTATE_OUT_LOW (the pin is output low)
+ * CH_OFFSTATE_OUT_HIGH (the pin is output high)
+ * CH_OFFSTATE_OUT_TRISTATE (the pin is tristated output)
+
+ required:
+ - reg
+ - adi,mode
+
+ additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/iio/adi,ad5592r.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ addac@0 {
+ compatible = "adi,ad5592r";
+ #size-cells = <0>;
+ #address-cells = <1>;
+ #gpio-cells = <2>;
+ reg = <0>;
+
+ spi-max-frequency = <1000000>;
+ spi-cpol;
+
+ vref-supply = <&vref>;
+ reset-gpios = <&gpio0 86 0>;
+ gpio-controller;
+
+ channel@0 {
+ reg = <0>;
+ adi,mode = <CH_MODE_DAC>;
+ };
+ channel@1 {
+ reg = <1>;
+ adi,mode = <CH_MODE_ADC>;
+ };
+ channel@2 {
+ reg = <2>;
+ adi,mode = <CH_MODE_DAC_AND_ADC>;
+ };
+ channel@3 {
+ reg = <3>;
+ adi,mode = <CH_MODE_DAC_AND_ADC>;
+ adi,off-state = <CH_OFFSTATE_PULLDOWN>;
+ };
+ channel@4 {
+ reg = <4>;
+ adi,mode = <CH_MODE_UNUSED>;
+ adi,off-state = <CH_OFFSTATE_PULLDOWN>;
+ };
+ channel@5 {
+ reg = <5>;
+ adi,mode = <CH_MODE_GPIO>;
+ adi,off-state = <CH_OFFSTATE_PULLDOWN>;
+ };
+ channel@6 {
+ reg = <6>;
+ adi,mode = <CH_MODE_GPIO>;
+ adi,off-state = <CH_OFFSTATE_PULLDOWN>;
+ };
+ channel@7 {
+ reg = <7>;
+ adi,mode = <CH_MODE_GPIO>;
+ adi,off-state = <CH_OFFSTATE_PULLDOWN>;
+ };
+ };
+ ad5593r@10 {
+ compatible = "adi,ad5593r";
+ #size-cells = <0>;
+ #address-cells = <1>;
+ #gpio-cells = <2>;
+ reg = <0x10>;
+ gpio-controller;
+
+ channel@0 {
+ reg = <0>;
+ adi,mode = <CH_MODE_DAC>;
+ adi,off-state = <CH_OFFSTATE_PULLDOWN>;
+ };
+ channel@1 {
+ reg = <1>;
+ adi,mode = <CH_MODE_ADC>;
+ adi,off-state = <CH_OFFSTATE_PULLDOWN>;
+ };
+ channel@2 {
+ reg = <2>;
+ adi,mode = <CH_MODE_DAC_AND_ADC>;
+ adi,off-state = <CH_OFFSTATE_PULLDOWN>;
+ };
+ channel@6 {
+ reg = <6>;
+ adi,mode = <CH_MODE_GPIO>;
+ adi,off-state = <CH_OFFSTATE_PULLDOWN>;
+ };
+ };
+ };
+...
diff --git a/dts/Bindings/iio/dac/adi,ad5686.yaml b/dts/Bindings/iio/dac/adi,ad5686.yaml
new file mode 100644
index 0000000000..8065228e5d
--- /dev/null
+++ b/dts/Bindings/iio/dac/adi,ad5686.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/adi,ad5686.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD5686 and similar multi-channel DACs
+
+maintainers:
+ - Michael Auchter <michael.auchter@ni.com>
+
+description: |
+ Binding for Analog Devices AD5686 and similar multi-channel DACs
+
+properties:
+ compatible:
+ enum:
+ - adi,ad5311r
+ - adi,ad5338r
+ - adi,ad5671r
+ - adi,ad5675r
+ - adi,ad5691r
+ - adi,ad5692r
+ - adi,ad5693
+ - adi,ad5693r
+ - adi,ad5694
+ - adi,ad5694r
+ - adi,ad5695r
+ - adi,ad5696
+ - adi,ad5696r
+
+ reg:
+ maxItems: 1
+
+ vcc-supply:
+ description: |
+ The regulator supply for DAC reference voltage.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ad5686: dac@0 {
+ compatible = "adi,ad5686";
+ reg = <0>;
+ vcc-supply = <&dac_vref>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/dac/adi,ad5758.yaml b/dts/Bindings/iio/dac/adi,ad5758.yaml
new file mode 100644
index 0000000000..626ccb6fe2
--- /dev/null
+++ b/dts/Bindings/iio/dac/adi,ad5758.yaml
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/adi,ad5758.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD5758 DAC
+
+maintainers:
+ - Michael Hennerich <Michael.Hennerich@analog.com>
+
+properties:
+ compatible:
+ const: adi,ad5758
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency: true
+ spi-cpha: true
+
+ adi,dc-dc-mode:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 3]
+ description: |
+ Mode of operation of the dc-to-dc converter
+ Dynamic Power Control (DPC)
+ In this mode, the AD5758 circuitry senses the output voltage and
+ dynamically regulates the supply voltage, VDPC+, to meet compliance
+ requirements plus an optimized headroom voltage for the output buffer.
+
+ Programmable Power Control (PPC)
+ In this mode, the VDPC+ voltage is user-programmable to a fixed level
+ that needs to accommodate the maximum output load required.
+
+ The output of the DAC core is either converted to a current or
+ voltage output at the VIOUT pin. Only one mode can be enabled at
+ any one time.
+
+ The following values are currently supported:
+ * 1: DPC current mode
+ * 2: DPC voltage mode
+ * 3: PPC current mode
+
+ Depending on the selected output mode (voltage or current) one of the
+ two properties must be present:
+
+ adi,range-microvolt:
+ $ref: /schemas/types.yaml#/definitions/int32-array
+ description: |
+ Voltage output range specified as <minimum, maximum>
+ enum:
+ - [[0, 5000000]]
+ - [[0, 10000000]]
+ - [[-5000000, 5000000]]
+ - [[-10000000, 10000000]]
+
+ adi,range-microamp:
+ $ref: /schemas/types.yaml#/definitions/int32-array
+ description: |
+ Current output range specified as <minimum, maximum>
+ enum:
+ - [[0, 20000]]
+ - [[0, 24000]]
+ - [[4, 24000]]
+ - [[-20000, 20000]]
+ - [[-24000, 24000]]
+ - [[-1000, 22000]]
+
+ reset-gpios: true
+
+ adi,dc-dc-ilim-microamp:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [150000, 200000, 250000, 300000, 350000, 400000]
+ description: |
+ The dc-to-dc converter current limit.
+
+ adi,slew-time-us:
+ description: |
+ The time it takes for the output to reach the full scale [uS]
+ minimum: 133
+ maximum: 1023984375
+
+required:
+ - compatible
+ - reg
+ - spi-cpha
+ - adi,dc-dc-mode
+
+allOf:
+ - if:
+ properties:
+ adi,dc-dc-mode:
+ contains:
+ enum: [1, 3]
+ then:
+ properties:
+ adi,range-microvolt: false
+ required:
+ - adi,range-microamp
+ else:
+ properties:
+ adi,range-microamp: false
+ required:
+ - adi,range-microvolt
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dac@0 {
+ compatible = "adi,ad5758";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ spi-cpha;
+
+ reset-gpios = <&gpio 22 0>;
+
+ adi,dc-dc-mode = <2>;
+ adi,range-microvolt = <0 10000000>;
+ adi,dc-dc-ilim-microamp = <200000>;
+ adi,slew-time-us = <125000>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/dac/adi,ad7303.yaml b/dts/Bindings/iio/dac/adi,ad7303.yaml
new file mode 100644
index 0000000000..1f00371520
--- /dev/null
+++ b/dts/Bindings/iio/dac/adi,ad7303.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/adi,ad7303.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD7303 DAC
+
+maintainers:
+ - Lars-Peter Clausen <lars@metafoo.de>
+
+properties:
+ compatible:
+ const: adi,ad7303
+
+ reg:
+ maxItems: 1
+
+ Vdd-supply:
+ description:
+ Used to calculate output channel scalling if REF-supply not specified.
+ REF-supply:
+ description:
+ If not provided, Vdd/2 is used as the reference voltage.
+
+ spi-max-frequency:
+ maximum: 30000000
+
+required:
+ - compatible
+ - reg
+ - Vdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dac@4 {
+ compatible = "adi,ad7303";
+ reg = <4>;
+ spi-max-frequency = <10000000>;
+ Vdd-supply = <&vdd_supply>;
+ REF-supply = <&vref_supply>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/dac/dpot-dac.txt b/dts/Bindings/iio/dac/dpot-dac.txt
deleted file mode 100644
index fdf47a01bf..0000000000
--- a/dts/Bindings/iio/dac/dpot-dac.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-Bindings for DAC emulation using a digital potentiometer
-
-It is assumed that the dpot is used as a voltage divider between the
-current dpot wiper setting and the maximum resistance of the dpot. The
-divided voltage is provided by a vref regulator.
-
- .------.
- .-----------. | |
- | vref |--' .---.
- | regulator |--. | |
- '-----------' | | d |
- | | p |
- | | o | wiper
- | | t |<---------+
- | | |
- | '---' dac output voltage
- | |
- '------+------------+
-
-Required properties:
-- compatible: Should be "dpot-dac"
-- vref-supply: The regulator supplying the voltage divider.
-- io-channels: Channel node of the dpot to be used for the voltage division.
-- io-channel-names: Should be "dpot".
-
-Example:
-
- &i2c {
- dpot: mcp4651-503@28 {
- compatible = "microchip,mcp4651-503";
- reg = <0x28>;
- #io-channel-cells = <1>;
- };
- };
-
- dac {
- compatible = "dpot-dac";
- vref-supply = <&reg_3v3>;
- io-channels = <&dpot 0>;
- io-channel-names = "dpot";
- };
diff --git a/dts/Bindings/iio/dac/dpot-dac.yaml b/dts/Bindings/iio/dac/dpot-dac.yaml
new file mode 100644
index 0000000000..6a7ca8e432
--- /dev/null
+++ b/dts/Bindings/iio/dac/dpot-dac.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/dpot-dac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: DAC emulation using a digital potentiometer
+
+maintainers:
+ - Peter Rosin <peda@axentia.se>
+
+description: |
+ It is assumed that the dpot is used as a voltage divider between the
+ current dpot wiper setting and the maximum resistance of the dpot. The
+ divided voltage is provided by a vref regulator.
+
+ .------.
+ .-----------. | |
+ | vref |--' .---.
+ | regulator |--. | |
+ '-----------' | | d |
+ | | p |
+ | | o | wiper
+ | | t |<---------+
+ | | |
+ | '---' dac output voltage
+ | |
+ '------+------------+
+
+properties:
+ compatible:
+ const: dpot-dac
+
+ vref-supply:
+ description: Regulator supplying the voltage divider.
+
+ io-channels:
+ maxItems: 1
+ description: |
+ Channel node of the dpot to be used for the voltage division.
+
+ io-channel-names:
+ const: dpot
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - vref-supply
+ - io-channels
+ - io-channel-names
+
+additionalProperties: false
+
+examples:
+ - |
+ dac {
+ compatible = "dpot-dac";
+ vref-supply = <&reg_3v3>;
+ io-channels = <&dpot 0>;
+ io-channel-names = "dpot";
+ };
+...
diff --git a/dts/Bindings/iio/dac/ds4424.txt b/dts/Bindings/iio/dac/ds4424.txt
deleted file mode 100644
index eaebbf8dab..0000000000
--- a/dts/Bindings/iio/dac/ds4424.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Maxim Integrated DS4422/DS4424 7-bit Sink/Source Current DAC Device Driver
-
-Datasheet publicly available at:
-https://datasheets.maximintegrated.com/en/ds/DS4422-DS4424.pdf
-
-Required properties:
- - compatible: Should be one of
- maxim,ds4422
- maxim,ds4424
- - reg: Should contain the DAC I2C address
-
-Optional properties:
- - vcc-supply: Power supply is optional. If not defined, driver will ignore it.
-
-Example:
- ds4224@10 {
- compatible = "maxim,ds4424";
- reg = <0x10>; /* When A0, A1 pins are ground */
- vcc-supply = <&vcc_3v3>;
- };
diff --git a/dts/Bindings/iio/dac/fsl,vf610-dac.yaml b/dts/Bindings/iio/dac/fsl,vf610-dac.yaml
new file mode 100644
index 0000000000..999c715c61
--- /dev/null
+++ b/dts/Bindings/iio/dac/fsl,vf610-dac.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/fsl,vf610-dac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale vf610 Digital to Analog Converter
+
+maintainers:
+ - Sanchayan Maity <maitysanchayan@gmail.com>
+
+properties:
+ compatible:
+ const: fsl,vf610-dac
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: dac
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/vf610-clock.h>
+ bus@40000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x40000000 0x00070000>;
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dac@400cc000 {
+ compatible = "fsl,vf610-dac";
+ reg = <0x400cc000 0x1000>;
+ interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "dac";
+ clocks = <&clks VF610_CLK_DAC0>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/dac/lpc1850-dac.txt b/dts/Bindings/iio/dac/lpc1850-dac.txt
deleted file mode 100644
index 42db783c4e..0000000000
--- a/dts/Bindings/iio/dac/lpc1850-dac.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-NXP LPC1850 DAC bindings
-
-Required properties:
-- compatible: Should be "nxp,lpc1850-dac"
-- reg: Offset and length of the register set for the ADC device
-- interrupts: The interrupt number for the ADC device
-- clocks: The root clock of the ADC controller
-- vref-supply: The regulator supply ADC reference voltage
-- resets: phandle to reset controller and line specifier
-
-Example:
-dac: dac@400e1000 {
- compatible = "nxp,lpc1850-dac";
- reg = <0x400e1000 0x1000>;
- interrupts = <0>;
- clocks = <&ccu1 CLK_APB3_DAC>;
- vref-supply = <&reg_vdda>;
- resets = <&rgu 42>;
-};
diff --git a/dts/Bindings/iio/dac/max5821.txt b/dts/Bindings/iio/dac/max5821.txt
deleted file mode 100644
index 54276ce8c9..0000000000
--- a/dts/Bindings/iio/dac/max5821.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-Maxim max5821 DAC device driver
-
-Required properties:
- - compatible: Must be "maxim,max5821"
- - reg: Should contain the DAC I2C address
- - vref-supply: Phandle to the vref power supply
-
-Example:
-
- max5821@38 {
- compatible = "maxim,max5821";
- reg = <0x38>;
- vref-supply = <&reg_max5821>;
- };
diff --git a/dts/Bindings/iio/dac/maxim,ds4424.yaml b/dts/Bindings/iio/dac/maxim,ds4424.yaml
new file mode 100644
index 0000000000..264fa7c5fe
--- /dev/null
+++ b/dts/Bindings/iio/dac/maxim,ds4424.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/maxim,ds4424.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim Integrated DS4422/DS4424 7-bit Sink/Source Current DAC
+
+maintainers:
+ - Ismail Kose <ihkose@gmail.com>
+
+description: |
+ Datasheet publicly available at:
+ https://datasheets.maximintegrated.com/en/ds/DS4422-DS4424.pdf
+
+properties:
+ compatible:
+ enum:
+ - maxim,ds4422
+ - maxim,ds4424
+
+ reg:
+ maxItems: 1
+
+ vcc-supply: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dac@10 {
+ compatible = "maxim,ds4424";
+ reg = <0x10>; /* When A0, A1 pins are ground */
+ vcc-supply = <&vcc_3v3>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/dac/maxim,max5821.yaml b/dts/Bindings/iio/dac/maxim,max5821.yaml
new file mode 100644
index 0000000000..c43fb5f3f8
--- /dev/null
+++ b/dts/Bindings/iio/dac/maxim,max5821.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/maxim,max5821.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim max5821 dual 10-bit DAC
+
+maintainers:
+ - Philippe Reynes <tremyfr@yahoo.fr>
+
+description: |
+ Datasheet publicly available at:
+ https://datasheets.maximintegrated.com/en/ds/MAX5821.pdf
+
+properties:
+ compatible:
+ const: maxim,max5821
+
+ reg:
+ maxItems: 1
+
+ vref-supply: true
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dac@38 {
+ compatible = "maxim,max5821";
+ reg = <0x38>;
+ vref-supply = <&reg_max5821>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/dac/mcp4725.txt b/dts/Bindings/iio/dac/mcp4725.txt
deleted file mode 100644
index 1bc6c093fb..0000000000
--- a/dts/Bindings/iio/dac/mcp4725.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-Microchip mcp4725 and mcp4726 DAC device driver
-
-Required properties:
- - compatible: Must be "microchip,mcp4725" or "microchip,mcp4726"
- - reg: Should contain the DAC I2C address
- - vdd-supply: Phandle to the Vdd power supply. This supply is used as a
- voltage reference on mcp4725. It is used as a voltage reference on
- mcp4726 if there is no vref-supply specified.
-
-Optional properties (valid only for mcp4726):
- - vref-supply: Optional phandle to the Vref power supply. Vref pin is
- used as a voltage reference when this supply is specified.
- - microchip,vref-buffered: Boolean to enable buffering of the external
- Vref pin. This boolean is not valid without the vref-supply. Quoting
- the datasheet: This is offered in cases where the reference voltage
- does not have the current capability not to drop its voltage when
- connected to the internal resistor ladder circuit.
-
-Examples:
-
- /* simple mcp4725 */
- mcp4725@60 {
- compatible = "microchip,mcp4725";
- reg = <0x60>;
- vdd-supply = <&vdac_vdd>;
- };
-
- /* mcp4726 with the buffered external reference voltage */
- mcp4726@60 {
- compatible = "microchip,mcp4726";
- reg = <0x60>;
- vdd-supply = <&vdac_vdd>;
- vref-supply = <&vdac_vref>;
- microchip,vref-buffered;
- };
diff --git a/dts/Bindings/iio/dac/microchip,mcp4725.yaml b/dts/Bindings/iio/dac/microchip,mcp4725.yaml
new file mode 100644
index 0000000000..271998610c
--- /dev/null
+++ b/dts/Bindings/iio/dac/microchip,mcp4725.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/microchip,mcp4725.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip mcp4725 and mcp4726 DAC
+
+maintainers:
+ - Tomas Novotny <tomas@novotny.cz>
+
+properties:
+ compatible:
+ enum:
+ - microchip,mcp4725
+ - microchip,mcp4726
+
+ reg:
+ maxItems: 1
+
+ vdd-supply:
+ description: |
+ Provides both power and acts as the reference supply on the mcp4725.
+ For the mcp4726 it will be used as the reference voltage if vref-supply
+ is not provided.
+
+ vref-supply:
+ description:
+ Vref pin is used as a voltage reference when this supply is specified.
+
+ microchip,vref-buffered:
+ type: boolean
+ description: |
+ Enable buffering of the external Vref pin. This boolean is not valid
+ without the vref-supply. Quoting the datasheet: This is offered in
+ cases where the reference voltage does not have the current
+ capability not to drop its voltage when connected to the internal
+ resistor ladder circuit.
+
+allOf:
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: microchip,mcp4726
+ then:
+ properties:
+ vref-supply: false
+ microchip,vref-buffered: false
+
+required:
+ - compatible
+ - reg
+ - vdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mcp4725@60 {
+ compatible = "microchip,mcp4725";
+ reg = <0x60>;
+ vdd-supply = <&vdac_vdd>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/dac/nxp,lpc1850-dac.yaml b/dts/Bindings/iio/dac/nxp,lpc1850-dac.yaml
new file mode 100644
index 0000000000..595f481c54
--- /dev/null
+++ b/dts/Bindings/iio/dac/nxp,lpc1850-dac.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/nxp,lpc1850-dac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP LPC1850 DAC bindings
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+description:
+ Supports the DAC found on the LPC1850 SoC.
+
+properties:
+ compatible:
+ const: nxp,lpc1850-dac
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ vref-supply: true
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - vref-supply
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/lpc18xx-ccu.h>
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dac: dac@400e1000 {
+ compatible = "nxp,lpc1850-dac";
+ reg = <0x400e1000 0x1000>;
+ interrupts = <0>;
+ clocks = <&ccu1 CLK_APB3_DAC>;
+ vref-supply = <&reg_vdda>;
+ resets = <&rgu 42>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/dac/ti,dac5571.txt b/dts/Bindings/iio/dac/ti,dac5571.txt
deleted file mode 100644
index 03af6b9a4d..0000000000
--- a/dts/Bindings/iio/dac/ti,dac5571.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-* Texas Instruments DAC5571 Family
-
-Required properties:
- - compatible: Should contain
- "ti,dac5571"
- "ti,dac6571"
- "ti,dac7571"
- "ti,dac5574"
- "ti,dac6574"
- "ti,dac7574"
- "ti,dac5573"
- "ti,dac6573"
- "ti,dac7573"
- - reg: Should contain the DAC I2C address
-
-Optional properties:
- - vref-supply: The regulator supply for DAC reference voltage
-
-Example:
-dac@0 {
- compatible = "ti,dac5571";
- reg = <0x4C>;
- vref-supply = <&vdd_supply>;
-};
diff --git a/dts/Bindings/iio/dac/ti,dac5571.yaml b/dts/Bindings/iio/dac/ti,dac5571.yaml
new file mode 100644
index 0000000000..714191724f
--- /dev/null
+++ b/dts/Bindings/iio/dac/ti,dac5571.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/ti,dac5571.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments DAC5571 Family
+
+maintainers:
+ - Sean Nyekjaer <sean@geanix.com>
+
+properties:
+ compatible:
+ enum:
+ - ti,dac5571
+ - ti,dac6571
+ - ti,dac7571
+ - ti,dac5574
+ - ti,dac6574
+ - ti,dac7574
+ - ti,dac5573
+ - ti,dac6573
+ - ti,dac7573
+
+ reg:
+ maxItems: 1
+
+ vref-supply:
+ description:
+ Reference voltage must be supplied to establish the scaling of the
+ output voltage.
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dac@4c {
+ compatible = "ti,dac5571";
+ reg = <0x4C>;
+ vref-supply = <&vdd_supply>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/dac/ti,dac7311.txt b/dts/Bindings/iio/dac/ti,dac7311.txt
deleted file mode 100644
index e5a507db5e..0000000000
--- a/dts/Bindings/iio/dac/ti,dac7311.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-TI DAC7311 device tree bindings
-
-Required properties:
-- compatible: must be set to:
- * "ti,dac7311"
- * "ti,dac6311"
- * "ti,dac5311"
-- reg: spi chip select number for the device
-- vref-supply: The regulator supply for ADC reference voltage
-
-Optional properties:
-- spi-max-frequency: Max SPI frequency to use
-
-Example:
-
- spi_master {
- dac@0 {
- compatible = "ti,dac7311";
- reg = <0>; /* CS0 */
- spi-max-frequency = <1000000>;
- vref-supply = <&vdd_supply>;
- };
- };
diff --git a/dts/Bindings/iio/dac/ti,dac7311.yaml b/dts/Bindings/iio/dac/ti,dac7311.yaml
new file mode 100644
index 0000000000..10be98d1f1
--- /dev/null
+++ b/dts/Bindings/iio/dac/ti,dac7311.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/ti,dac7311.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments DAC5311 and similar SPI DACs
+
+maintainers:
+ - Charles-Antoine Couret <charles-antoine.couret@essensium.com>
+
+properties:
+ compatible:
+ enum:
+ - ti,dac7311
+ - ti,dac6311
+ - ti,dac5311
+
+ reg:
+ maxItems: 1
+
+ vref-supply:
+ description:
+ Reference voltage must be supplied to establish the scaling of the
+ output voltage.
+
+ spi-max-frequency: true
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dac@0 {
+ compatible = "ti,dac7311";
+ reg = <0>; /* CS0 */
+ spi-max-frequency = <1000000>;
+ vref-supply = <&vdd_supply>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/dac/ti,dac7512.txt b/dts/Bindings/iio/dac/ti,dac7512.txt
deleted file mode 100644
index 1db45939da..0000000000
--- a/dts/Bindings/iio/dac/ti,dac7512.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-TI DAC7512 DEVICETREE BINDINGS
-
-Required properties:
-
- - "compatible" Must be set to "ti,dac7512"
-
-Property rules described in Documentation/devicetree/bindings/spi/spi-bus.txt
-apply. In particular, "reg" and "spi-max-frequency" properties must be given.
-
-
-Example:
-
- spi_master {
- dac7512: dac7512@0 {
- compatible = "ti,dac7512";
- reg = <0>; /* CS0 */
- spi-max-frequency = <1000000>;
- };
- };
-
diff --git a/dts/Bindings/iio/dac/ti,dac7512.yaml b/dts/Bindings/iio/dac/ti,dac7512.yaml
new file mode 100644
index 0000000000..4277cf8a4a
--- /dev/null
+++ b/dts/Bindings/iio/dac/ti,dac7512.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/ti,dac7512.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments DAC7512 DAC
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+properties:
+ compatible:
+ const: ti,dac7512
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ description:
+ Maximum frequency is reduced for supply voltage of less than 3.6V
+ maximum: 30000000
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dac@0 {
+ compatible = "ti,dac7512";
+ reg = <0>; /* CS0 */
+ spi-max-frequency = <1000000>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/dac/ti,dac7612.txt b/dts/Bindings/iio/dac/ti,dac7612.txt
deleted file mode 100644
index 17af395b99..0000000000
--- a/dts/Bindings/iio/dac/ti,dac7612.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-* Texas Instruments Dual, 12-Bit Serial Input Digital-to-Analog Converter
-
-The DAC7612 is a dual, 12-bit digital-to-analog converter (DAC) with guaranteed
-12-bit monotonicity performance over the industrial temperature range.
-Is is programmable through an SPI interface.
-
-The internal DACs are loaded when the LOADDACS pin is pulled down.
-
-https://www.ti.com/lit/ds/sbas106/sbas106.pdf
-
-Required Properties:
-- compatible: Should be one of:
- "ti,dac7612"
- "ti,dac7612u"
- "ti,dac7612ub"
-- reg: Definition as per Documentation/devicetree/bindings/spi/spi-bus.txt
-
-Optional Properties:
-- ti,loaddacs-gpios: GPIO descriptor for the LOADDACS pin.
-- spi-*: Definition as per Documentation/devicetree/bindings/spi/spi-bus.txt
-
-Example:
-
- dac@1 {
- compatible = "ti,dac7612";
- reg = <0x1>;
- ti,loaddacs-gpios = <&msmgpio 25 GPIO_ACTIVE_LOW>;
- };
diff --git a/dts/Bindings/iio/dac/ti,dac7612.yaml b/dts/Bindings/iio/dac/ti,dac7612.yaml
new file mode 100644
index 0000000000..d172b142f6
--- /dev/null
+++ b/dts/Bindings/iio/dac/ti,dac7612.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/ti,dac7612.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments DAC7612 family of DACs
+
+description:
+ The DAC7612 is a dual, 12-bit digital-to-analog converter (DAC) with
+ guaranteed 12-bit monotonicity performance over the industrial temperature
+ range. Is is programmable through an SPI interface.
+
+maintainers:
+ - Ricardo Ribalda Delgado <ricardo@ribalda.com>
+
+properties:
+ compatible:
+ enum:
+ - ti,dac7612
+ - ti,dac7612u
+ - ti,dac7612ub
+
+ reg:
+ maxItems: 1
+
+ ti,loaddacs-gpios:
+ description:
+ DACs are loaded when the pin connected to this GPIO is pulled low.
+ maxItems: 1
+
+ spi-max-frequency: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dac@1 {
+ compatible = "ti,dac7612";
+ reg = <0x1>;
+ ti,loaddacs-gpios = <&msmgpio 25 GPIO_ACTIVE_LOW>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/dac/vf610-dac.txt b/dts/Bindings/iio/dac/vf610-dac.txt
deleted file mode 100644
index 20c6c7ae96..0000000000
--- a/dts/Bindings/iio/dac/vf610-dac.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Freescale vf610 Digital to Analog Converter bindings
-
-The devicetree bindings are for the new DAC driver written for
-vf610 SoCs from Freescale.
-
-Required properties:
-- compatible: Should contain "fsl,vf610-dac"
-- reg: Offset and length of the register set for the device
-- interrupts: Should contain the interrupt for the device
-- clocks: The clock is needed by the DAC controller
-- clock-names: Must contain "dac" matching entry in the clocks property.
-
-Example:
-dac0: dac@400cc000 {
- compatible = "fsl,vf610-dac";
- reg = <0x400cc000 0x1000>;
- interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "dac";
- clocks = <&clks VF610_CLK_DAC0>;
-};
diff --git a/dts/Bindings/iio/frequency/adf4350.txt b/dts/Bindings/iio/frequency/adf4350.txt
deleted file mode 100644
index f8c181d81d..0000000000
--- a/dts/Bindings/iio/frequency/adf4350.txt
+++ /dev/null
@@ -1,86 +0,0 @@
-Analog Devices ADF4350/ADF4351 device driver
-
-Required properties:
- - compatible: Should be one of
- * "adi,adf4350": When using the ADF4350 device
- * "adi,adf4351": When using the ADF4351 device
- - reg: SPI chip select numbert for the device
- - spi-max-frequency: Max SPI frequency to use (< 20000000)
- - clocks: From common clock binding. Clock is phandle to clock for
- ADF435x Reference Clock (CLKIN).
-
-Optional properties:
- - gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,
- pll lock state is tested upon read.
- - adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
- - adi,power-up-frequency: If set in Hz the PLL tunes to
- the desired frequency on probe.
- - adi,reference-div-factor: If set the driver skips dynamic calculation
- and uses this default value instead.
- - adi,reference-doubler-enable: Enables reference doubler.
- - adi,reference-div2-enable: Enables reference divider.
- - adi,phase-detector-polarity-positive-enable: Enables positive phase
- detector polarity. Default = negative.
- - adi,lock-detect-precision-6ns-enable: Enables 6ns lock detect precision.
- Default = 10ns.
- - adi,lock-detect-function-integer-n-enable: Enables lock detect
- for integer-N mode. Default = factional-N mode.
- - adi,charge-pump-current: Charge pump current in mA.
- Default = 2500mA.
- - adi,muxout-select: On chip multiplexer output selection.
- Valid values for the multiplexer output are:
- 0: Three-State Output (default)
- 1: DVDD
- 2: DGND
- 3: R-Counter output
- 4: N-Divider output
- 5: Analog lock detect
- 6: Digital lock detect
- - adi,low-spur-mode-enable: Enables low spur mode.
- Default = Low noise mode.
- - adi,cycle-slip-reduction-enable: Enables cycle slip reduction.
- - adi,charge-cancellation-enable: Enabled charge pump
- charge cancellation for integer-N modes.
- - adi,anti-backlash-3ns-enable: Enables 3ns antibacklash pulse width
- for integer-N modes.
- - adi,band-select-clock-mode-high-enable: Enables faster band
- selection logic.
- - adi,12bit-clk-divider: Clock divider value used when
- adi,12bit-clkdiv-mode != 0
- - adi,clk-divider-mode:
- Valid values for the clkdiv mode are:
- 0: Clock divider off (default)
- 1: Fast lock enable
- 2: Phase resync enable
- - adi,aux-output-enable: Enables auxiliary RF output.
- - adi,aux-output-fundamental-enable: Selects fundamental VCO output on
- the auxiliary RF output. Default = Output of RF dividers.
- - adi,mute-till-lock-enable: Enables Mute-Till-Lock-Detect function.
- - adi,output-power: Output power selection.
- Valid values for the power mode are:
- 0: -4dBm (default)
- 1: -1dBm
- 2: +2dBm
- 3: +5dBm
- - adi,aux-output-power: Auxiliary output power selection.
- Valid values for the power mode are:
- 0: -4dBm (default)
- 1: -1dBm
- 2: +2dBm
- 3: +5dBm
-
-
-Example:
- lo_pll0_rx_adf4351: adf4351-rx-lpc@4 {
- compatible = "adi,adf4351";
- reg = <4>;
- spi-max-frequency = <10000000>;
- clocks = <&clk0_ad9523 9>;
- clock-names = "clkin";
- adi,channel-spacing = <10000>;
- adi,power-up-frequency = <2400000000>;
- adi,phase-detector-polarity-positive-enable;
- adi,charge-pump-current = <2500>;
- adi,output-power = <3>;
- adi,mute-till-lock-enable;
- };
diff --git a/dts/Bindings/iio/frequency/adi,adf4350.yaml b/dts/Bindings/iio/frequency/adi,adf4350.yaml
new file mode 100644
index 0000000000..d7f20b8518
--- /dev/null
+++ b/dts/Bindings/iio/frequency/adi,adf4350.yaml
@@ -0,0 +1,190 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/frequency/adi,adf4350.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices ADF4350/ADF4351 wideband synthesizer
+
+maintainers:
+ - Michael Hennerich <michael.hennerich@analog.com>
+
+properties:
+ compatible:
+ enum:
+ - adi,adf4350
+ - adi,adf4351
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 20000000
+
+ clocks:
+ maxItems: 1
+ description: Clock to provide CLKIN reference clock signal.
+
+ clock-names:
+ const: clkin
+
+ gpios:
+ maxItems: 1
+ description: Lock detect GPIO.
+
+ adi,channel-spacing:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Channel spacing in Hz (influences MODULUS).
+
+ adi,power-up-frequency:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ If set the PLL tunes to this frequency (in Hz) on driver probe.
+
+ adi,reference-div-factor:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ If set the driver skips dynamic calculation and uses this default
+ value instead.
+
+ adi,reference-doubler-enable:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Enables reference doubler.
+
+ adi,reference-div2-enable:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Enables reference divider.
+
+ adi,phase-detector-polarity-positive-enable:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Enables positive phase detector polarity. Default negative.
+
+ adi,lock-detect-precision-6ns-enable:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Enables 6ns lock detect precision. Default = 10ns.
+
+ adi,lock-detect-function-integer-n-enable:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Enables lock detect for integer-N mode. Default = factional-N mode.
+
+ adi,charge-pump-current:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Charge pump current in mA. Default = 2500mA.
+
+ adi,muxout-select:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 6
+ description: |
+ On chip multiplexer output selection.
+ Valid values for the multiplexer output are:
+ 0: Three-State Output (default)
+ 1: DVDD
+ 2: DGND
+ 3: R-Counter output
+ 4: N-Divider output
+ 5: Analog lock detect
+ 6: Digital lock detect
+
+ adi,low-spur-mode-enable:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Enables low spur mode. Default = Low noise mode.
+
+ adi,cycle-slip-reduction-enable:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Enables cycle slip reduction.
+
+ adi,charge-cancellation-enable:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Enabled charge pump charge cancellation for integer-N modes.
+
+ adi,anti-backlash-3ns-enable:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Enables 3ns antibacklash pulse width for integer-N modes.
+
+ adi,band-select-clock-mode-high-enable:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Enables faster band selection logic.
+
+ adi,12bit-clk-divider:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Clock divider value used when adi,12bit-clkdiv-mode != 0
+
+ adi,clk-divider-mode:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+ description: |
+ Valid values for the clkdiv mode are:
+ 0: Clock divider off (default)
+ 1: Fast lock enable
+ 2: Phase resync enable
+
+ adi,aux-output-enable:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Enables auxiliary RF output.
+
+ adi,aux-output-fundamental-enable:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: |
+ Selects fundamental VCO output on the auxiliary RF output.
+ Default = Output of RF dividers.
+
+ adi,mute-till-lock-enable:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Enables Mute-Till-Lock-Detect function.
+
+ adi,output-power:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ description: |
+ Output power selection.
+ Valid values for the power mode are:
+ 0: -4dBm (default)
+ 1: -1dBm
+ 2: +2dBm
+ 3: +5dBm
+
+ adi,aux-output-power:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ description: |
+ Auxiliary output power selection.
+ Valid values for the power mode are:
+ 0: -4dBm (default)
+ 1: -1dBm
+ 2: +2dBm
+ 3: +5dBm
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pll@4 {
+ compatible = "adi,adf4351";
+ reg = <4>;
+ spi-max-frequency = <10000000>;
+ clocks = <&clk0_ad9523 9>;
+ clock-names = "clkin";
+ adi,channel-spacing = <10000>;
+ adi,power-up-frequency = <2400000000>;
+ adi,phase-detector-polarity-positive-enable;
+ adi,charge-pump-current = <2500>;
+ adi,output-power = <3>;
+ adi,mute-till-lock-enable;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/gyroscope/bmg160.txt b/dts/Bindings/iio/gyroscope/bmg160.txt
deleted file mode 100644
index bb43d1ad9c..0000000000
--- a/dts/Bindings/iio/gyroscope/bmg160.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-* Bosch BMG160 triaxial rotation sensor (gyroscope)
-
-Required properties:
-
- - compatible : should be "bosch,bmg160", "bosch,bmi055_gyro" or "bosch,bmi088_gyro"
- - reg : the I2C address of the sensor (0x69)
-
-Optional properties:
-
- - interrupts : interrupt mapping for GPIO IRQ, it should by configured with
- flags IRQ_TYPE_EDGE_RISING
-
-Example:
-
-bmg160@69 {
- compatible = "bosch,bmg160";
- reg = <0x69>;
- interrupt-parent = <&gpio6>;
- interrupts = <18 (IRQ_TYPE_EDGE_RISING)>;
-};
diff --git a/dts/Bindings/iio/gyroscope/bosch,bmg160.yaml b/dts/Bindings/iio/gyroscope/bosch,bmg160.yaml
new file mode 100644
index 0000000000..0466483be6
--- /dev/null
+++ b/dts/Bindings/iio/gyroscope/bosch,bmg160.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/gyroscope/bosch,bmg160.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bosch BMG160 triaxial rotation sensor (gyroscope)
+
+maintainers:
+ - H. Nikolaus Schaller <hns@goldelico.com>
+
+properties:
+ compatible:
+ enum:
+ - bosch,bmg160
+ - bosch,bmi055_gyro
+ - bosch,bmi088_gyro
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ description:
+ Should be configured with type IRQ_TYPE_EDGE_RISING.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gyroscope@69 {
+ compatible = "bosch,bmg160";
+ reg = <0x69>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <18 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/gyroscope/nxp,fxas21002c.txt b/dts/Bindings/iio/gyroscope/nxp,fxas21002c.txt
deleted file mode 100644
index 465e104bbf..0000000000
--- a/dts/Bindings/iio/gyroscope/nxp,fxas21002c.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-* NXP FXAS21002C Gyroscope device tree bindings
-
-http://www.nxp.com/products/sensors/gyroscopes/3-axis-digital-gyroscope:FXAS21002C
-
-Required properties:
- - compatible : should be "nxp,fxas21002c"
- - reg : the I2C address of the sensor or SPI chip select number for the
- device.
- - vdd-supply: phandle to the regulator that provides power to the sensor.
- - vddio-supply: phandle to the regulator that provides power to the bus.
-
-Optional properties:
- - reset-gpios : gpio used to reset the device, see gpio/gpio.txt
- - interrupts : device support 2 interrupts, INT1 and INT2,
- the interrupts can be triggered on rising or falling edges.
- See interrupt-controller/interrupts.txt
- - interrupt-names: should contain "INT1" or "INT2", the gyroscope interrupt
- line in use.
- - drive-open-drain: the interrupt/data ready line will be configured
- as open drain, which is useful if several sensors share
- the same interrupt line. This is a boolean property.
- (This binding is taken from pinctrl/pinctrl-bindings.txt)
-
-Example:
-
-gyroscope@20 {
- compatible = "nxp,fxas21002c";
- reg = <0x20>;
- vdd-supply = <&reg_peri_3p15v>;
- vddio-supply = <&reg_peri_3p15v>;
-};
diff --git a/dts/Bindings/iio/gyroscope/nxp,fxas21002c.yaml b/dts/Bindings/iio/gyroscope/nxp,fxas21002c.yaml
new file mode 100644
index 0000000000..d97ee774d6
--- /dev/null
+++ b/dts/Bindings/iio/gyroscope/nxp,fxas21002c.yaml
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/gyroscope/nxp,fxas21002c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP FXAS21002C Gyroscope
+
+maintainers:
+ - Rui Miguel Silva <rmfrfs@gmail.com>
+
+description: |
+ 3 axis digital gyroscope device with an I2C and SPI interface.
+ http://www.nxp.com/products/sensors/gyroscopes/3-axis-digital-gyroscope:FXAS21002C
+
+properties:
+ compatible:
+ const: nxp,fxas21002c
+
+ reg:
+ maxItems: 1
+
+ vdd-supply:
+ description: Regulator that provides power to the sensor
+
+ vddio-supply:
+ description: Regulator that provides power to the bus
+
+ reset-gpios:
+ maxItems: 1
+ description: GPIO connected to reset
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+ description: Either interrupt may be triggered on rising or falling edges.
+
+ interrupt-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ enum:
+ - INT1
+ - INT2
+
+ drive-open-drain:
+ type: boolean
+ description: the interrupt/data ready line will be configured as open drain,
+ which is useful if several sensors share the same interrupt
+ line.
+
+ spi-max-frequency:
+ maximum: 2000000
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gyroscope@20 {
+ compatible = "nxp,fxas21002c";
+ reg = <0x20>;
+
+ vdd-supply = <&reg_peri_3p15v>;
+ vddio-supply = <&reg_peri_3p15v>;
+
+ interrupt-parent = <&gpio1>;
+ interrupts = <7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "INT1";
+ };
+ };
+ spi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gyroscope@0 {
+ compatible = "nxp,fxas2102c";
+ reg = <0x0>;
+
+ spi-max-frequency = <2000000>;
+
+ interrupt-parent = <&gpio2>;
+ interrupts = <7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "INT2";
+ };
+ };
diff --git a/dts/Bindings/iio/health/afe4403.txt b/dts/Bindings/iio/health/afe4403.txt
deleted file mode 100644
index 8e412054d6..0000000000
--- a/dts/Bindings/iio/health/afe4403.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-Texas Instruments AFE4403 Heart rate and Pulse Oximeter
-
-Required properties:
- - compatible : Should be "ti,afe4403".
- - reg : SPI chip select address of device.
- - tx-supply : Regulator supply to transmitting LEDs.
- - interrupts : The interrupt line the device ADC_RDY pin is
- connected to. For details refer to,
- ../../interrupt-controller/interrupts.txt.
-
-Optional properties:
- - reset-gpios : GPIO used to reset the device.
- For details refer to, ../../gpio/gpio.txt.
-
-For other required and optional properties of SPI slave nodes
-please refer to ../../spi/spi-bus.txt.
-
-Example:
-
-&spi0 {
- heart_mon@0 {
- compatible = "ti,afe4403";
- reg = <0>;
- spi-max-frequency = <10000000>;
-
- tx-supply = <&vbat>;
-
- interrupt-parent = <&gpio1>;
- interrupts = <28 IRQ_TYPE_EDGE_RISING>;
-
- reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
- };
-};
diff --git a/dts/Bindings/iio/health/afe4404.txt b/dts/Bindings/iio/health/afe4404.txt
deleted file mode 100644
index 0b52830a0d..0000000000
--- a/dts/Bindings/iio/health/afe4404.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-Texas Instruments AFE4404 Heart rate and Pulse Oximeter
-
-Required properties:
- - compatible : Should be "ti,afe4404".
- - reg : I2C address of the device.
- - tx-supply : Regulator supply to transmitting LEDs.
- - interrupts : The interrupt line the device ADC_RDY pin is
- connected to. For details refer to,
- ../interrupt-controller/interrupts.txt.
-
-Optional properties:
- - reset-gpios : GPIO used to reset the device.
- For details refer to, ../gpio/gpio.txt.
-
-Example:
-
-&i2c2 {
- heart_mon@58 {
- compatible = "ti,afe4404";
- reg = <0x58>;
-
- tx-supply = <&vbat>;
-
- interrupt-parent = <&gpio1>;
- interrupts = <28 IRQ_TYPE_EDGE_RISING>;
-
- reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
- };
-};
diff --git a/dts/Bindings/iio/health/max30100.txt b/dts/Bindings/iio/health/max30100.txt
deleted file mode 100644
index 0054908a6e..0000000000
--- a/dts/Bindings/iio/health/max30100.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-Maxim MAX30100 heart rate and pulse oximeter sensor
-
-* https://datasheets.maximintegrated.com/en/ds/MAX30100.pdf
-
-Required properties:
- - compatible: must be "maxim,max30100"
- - reg: the I2C address of the sensor
- - interrupts: the sole interrupt generated by the device
-
- Refer to interrupt-controller/interrupts.txt for generic
- interrupt client node bindings.
-
-Optional properties:
- - maxim,led-current-microamp: configuration for LED current in microamperes
- while the engine is running. First indexed value is the configuration for
- the RED LED, and second value is for the IR LED.
-
- Refer to the datasheet for the allowed current values.
-
-Example:
-
-max30100@57 {
- compatible = "maxim,max30100";
- reg = <0x57>;
- maxim,led-current-microamp = <24000 50000>;
- interrupt-parent = <&gpio1>;
- interrupts = <16 2>;
-};
diff --git a/dts/Bindings/iio/health/max30102.txt b/dts/Bindings/iio/health/max30102.txt
deleted file mode 100644
index 7ef7ae40ae..0000000000
--- a/dts/Bindings/iio/health/max30102.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-Maxim MAX30102 heart rate and pulse oximeter sensor
-Maxim MAX30105 optical particle-sensing module
-
-* https://datasheets.maximintegrated.com/en/ds/MAX30102.pdf
-* https://datasheets.maximintegrated.com/en/ds/MAX30105.pdf
-
-Required properties:
- - compatible: must be "maxim,max30102" or "maxim,max30105"
- - reg: the I2C address of the sensor
- - interrupts: the sole interrupt generated by the device
-
- Refer to interrupt-controller/interrupts.txt for generic
- interrupt client node bindings.
-
-Optional properties:
- - maxim,red-led-current-microamp: configuration for red LED current
- - maxim,ir-led-current-microamp: configuration for IR LED current
- - maxim,green-led-current-microamp: configuration for green LED current
- (max30105 only)
-
- Note that each step is approximately 200 microamps, ranging from 0 uA to
- 50800 uA.
-
-Example:
-
-max30102@57 {
- compatible = "maxim,max30102";
- reg = <0x57>;
- maxim,red-led-current-microamp = <7000>;
- maxim,ir-led-current-microamp = <7000>;
- interrupt-parent = <&gpio1>;
- interrupts = <16 2>;
-};
diff --git a/dts/Bindings/iio/health/maxim,max30100.yaml b/dts/Bindings/iio/health/maxim,max30100.yaml
new file mode 100644
index 0000000000..64b8626370
--- /dev/null
+++ b/dts/Bindings/iio/health/maxim,max30100.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/health/maxim,max30100.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX30100 heart rate and pulse oximeter sensor
+
+maintainers:
+ - Matt Ranostay <matt.ranostay@konsulko.com>
+
+properties:
+ compatible:
+ const: maxim,max30100
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+ description: Connected to ADC_RDY pin.
+
+ maxim,led-current-microamp:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 2
+ maxItems: 2
+ description: |
+ LED current whilst the engine is running. First indexed value is
+ the configuration for the RED LED, and second value is for the IR LED.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ heart-rate@57 {
+ compatible = "maxim,max30100";
+ reg = <0x57>;
+ maxim,led-current-microamp = <24000 50000>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <16 2>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/health/maxim,max30102.yaml b/dts/Bindings/iio/health/maxim,max30102.yaml
new file mode 100644
index 0000000000..c13c10c8d6
--- /dev/null
+++ b/dts/Bindings/iio/health/maxim,max30102.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/health/maxim,max30102.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX30102 heart rate and pulse oximeter and MAX30105 particle-sensor
+
+maintainers:
+ - Matt Ranostay <matt.ranostay@konsulko.com>
+
+properties:
+ compatible:
+ enum:
+ - maxim,max30102
+ - maxim,max30105
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+ description: Connected to ADC_RDY pin.
+
+ maxim,red-led-current-microamp:
+ description: RED LED current. Each step is approximately 200 microamps.
+ minimum: 0
+ maximum: 50800
+
+ maxim,ir-led-current-microamp:
+ description: IR LED current. Each step is approximately 200 microamps.
+ minimum: 0
+ maximum: 50800
+
+ maxim,green-led-current-microamp:
+ description: Green LED current. Each step is approximately 200 microamps.
+ minimum: 0
+ maximum: 50800
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: maxim,max30100
+ then:
+ properties:
+ maxim,green-led-current-microamp: false
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ heart-rate@57 {
+ compatible = "maxim,max30102";
+ reg = <0x57>;
+ maxim,red-led-current-microamp = <7000>;
+ maxim,ir-led-current-microamp = <7000>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <16 2>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/health/ti,afe4403.yaml b/dts/Bindings/iio/health/ti,afe4403.yaml
new file mode 100644
index 0000000000..d861526c5c
--- /dev/null
+++ b/dts/Bindings/iio/health/ti,afe4403.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/health/ti,afe4403.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments AFE4403 Heart rate and Pulse Oximeter
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+properties:
+ compatible:
+ const: ti,afe4403
+
+ reg:
+ maxItems: 1
+
+ tx-supply:
+ description: Supply to transmitting LEDs.
+
+ interrupts:
+ maxItems: 1
+ description: Connected to ADC_RDY pin.
+
+ reset-gpios: true
+
+ spi-max-frequency: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ heart_mon@0 {
+ compatible = "ti,afe4403";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ tx-supply = <&vbat>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <28 IRQ_TYPE_EDGE_RISING>;
+ reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/health/ti,afe4404.yaml b/dts/Bindings/iio/health/ti,afe4404.yaml
new file mode 100644
index 0000000000..3b4d6c48b8
--- /dev/null
+++ b/dts/Bindings/iio/health/ti,afe4404.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/health/ti,afe4404.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments AFE4404 Heart rate and Pulse Oximeter
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+properties:
+ compatible:
+ const: ti,afe4403
+
+ reg:
+ maxItems: 1
+
+ tx-supply:
+ description: Supply to transmitting LEDs.
+
+ interrupts:
+ maxItems: 1
+ description: Connected to ADC_RDY pin.
+
+ reset-gpios: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ heart_mon@58 {
+ compatible = "ti,afe4404";
+ reg = <0x58>;
+ tx-supply = <&vbat>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <28 IRQ_TYPE_EDGE_RISING>;
+ reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/humidity/dht11.txt b/dts/Bindings/iio/humidity/dht11.txt
deleted file mode 100644
index ecc24c199f..0000000000
--- a/dts/Bindings/iio/humidity/dht11.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* DHT11 humidity/temperature sensor (and compatibles like DHT22)
-
-Required properties:
- - compatible: Should be "dht11"
- - gpios: Should specify the GPIO connected to the sensor's data
- line, see "gpios property" in
- Documentation/devicetree/bindings/gpio/gpio.txt.
-
-Example:
-
-humidity_sensor {
- compatible = "dht11";
- gpios = <&gpio0 6 0>;
-}
diff --git a/dts/Bindings/iio/humidity/dht11.yaml b/dts/Bindings/iio/humidity/dht11.yaml
new file mode 100644
index 0000000000..2247481d02
--- /dev/null
+++ b/dts/Bindings/iio/humidity/dht11.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/humidity/dht11.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: DHT11 humidity + temperature sensor
+
+maintainers:
+ - Harald Geyer <harald@ccbib.org>
+
+description: |
+ A simple and low cost module providing a non standard single GPIO based
+ interface. It is believed the part is made by aosong but don't have
+ absolute confirmation of this, or what the aosong part number is.
+
+properties:
+ compatible:
+ const: dht11
+
+ reg:
+ maxItems: 1
+
+ gpios:
+ maxItems: 1
+ description:
+ Single, interrupt capable, GPIO used to communicate with the device.
+
+required:
+ - compatible
+ - gpios
+
+additionalProperties: false
+
+examples:
+ - |
+ humidity_sensor {
+ compatible = "dht11";
+ gpios = <&gpio0 6 0>;
+ };
+...
diff --git a/dts/Bindings/iio/humidity/hdc100x.txt b/dts/Bindings/iio/humidity/hdc100x.txt
deleted file mode 100644
index c52333bdfd..0000000000
--- a/dts/Bindings/iio/humidity/hdc100x.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-* HDC100x temperature + humidity sensors
-
-Required properties:
- - compatible: Should contain one of the following:
- ti,hdc1000
- ti,hdc1008
- ti,hdc1010
- ti,hdc1050
- ti,hdc1080
- - reg: i2c address of the sensor
-
-Example:
-
-hdc100x@40 {
- compatible = "ti,hdc1000";
- reg = <0x40>;
-};
diff --git a/dts/Bindings/iio/humidity/hts221.txt b/dts/Bindings/iio/humidity/hts221.txt
deleted file mode 100644
index 84d0293722..0000000000
--- a/dts/Bindings/iio/humidity/hts221.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-* HTS221 STM humidity + temperature sensor
-
-Required properties:
-- compatible: should be "st,hts221"
-- reg: i2c address of the sensor / spi cs line
-
-Optional properties:
-- drive-open-drain: the interrupt/data ready line will be configured
- as open drain, which is useful if several sensors share the same
- interrupt line. This is a boolean property.
- If the requested interrupt is configured as IRQ_TYPE_LEVEL_HIGH or
- IRQ_TYPE_EDGE_RISING a pull-down resistor is needed to drive the line
- when it is not active, whereas a pull-up one is needed when interrupt
- line is configured as IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_EDGE_FALLING.
- Refer to pinctrl/pinctrl-bindings.txt for the property description.
-- interrupts: interrupt mapping for IRQ. It should be configured with
- flags IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_RISING, IRQ_TYPE_LEVEL_LOW or
- IRQ_TYPE_EDGE_FALLING.
-
- Refer to interrupt-controller/interrupts.txt for generic interrupt
- client node bindings.
-
-Example:
-
-hts221@5f {
- compatible = "st,hts221";
- reg = <0x5f>;
- interrupt-parent = <&gpio0>;
- interrupts = <0 IRQ_TYPE_EDGE_RISING>;
-};
diff --git a/dts/Bindings/iio/humidity/htu21.txt b/dts/Bindings/iio/humidity/htu21.txt
deleted file mode 100644
index 97d79636f7..0000000000
--- a/dts/Bindings/iio/humidity/htu21.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-*HTU21 - Measurement-Specialties htu21 temperature & humidity sensor and humidity part of MS8607 sensor
-
-Required properties:
-
- - compatible: should be "meas,htu21" or "meas,ms8607-humidity"
- - reg: I2C address of the sensor
-
-Example:
-
-htu21@40 {
- compatible = "meas,htu21";
- reg = <0x40>;
-};
diff --git a/dts/Bindings/iio/humidity/st,hts221.yaml b/dts/Bindings/iio/humidity/st,hts221.yaml
new file mode 100644
index 0000000000..598473df74
--- /dev/null
+++ b/dts/Bindings/iio/humidity/st,hts221.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/humidity/st,hts221.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HTS221 STM humidity + temperature sensor
+
+maintainers:
+ - Lorenzo Bianconi <lorenzo@kernel.org>
+
+description: |
+ Humidity and temperature sensor with I2C interface and data ready
+ interrupt.
+
+properties:
+ compatible:
+ const: st,hts221
+
+ reg:
+ maxItems: 1
+
+ drive-open-drain:
+ type: boolean
+ description:
+ The interrupt/data ready line will be configured as open drain, which
+ is useful if several sensors share the same interrupt line.
+
+ vdd-supply: true
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hts221@5f {
+ compatible = "st,hts221";
+ reg = <0x5f>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/humidity/ti,hdc2010.yaml b/dts/Bindings/iio/humidity/ti,hdc2010.yaml
index 7037f82ec7..88384b69f9 100644
--- a/dts/Bindings/iio/humidity/ti,hdc2010.yaml
+++ b/dts/Bindings/iio/humidity/ti,hdc2010.yaml
@@ -22,8 +22,7 @@ properties:
- ti,hdc2010
- ti,hdc2080
- vdd-supply:
- maxItems: 1
+ vdd-supply: true
reg:
maxItems: 1
diff --git a/dts/Bindings/iio/iio-bindings.txt b/dts/Bindings/iio/iio-bindings.txt
deleted file mode 100644
index aa63cac732..0000000000
--- a/dts/Bindings/iio/iio-bindings.txt
+++ /dev/null
@@ -1,102 +0,0 @@
-This binding is derived from clock bindings, and based on suggestions
-from Lars-Peter Clausen [1].
-
-Sources of IIO channels can be represented by any node in the device
-tree. Those nodes are designated as IIO providers. IIO consumer
-nodes use a phandle and IIO specifier pair to connect IIO provider
-outputs to IIO inputs. Similar to the gpio specifiers, an IIO
-specifier is an array of one or more cells identifying the IIO
-output on a device. The length of an IIO specifier is defined by the
-value of a #io-channel-cells property in the IIO provider node.
-
-[1] https://marc.info/?l=linux-iio&m=135902119507483&w=2
-
-==IIO providers==
-
-Required properties:
-#io-channel-cells: Number of cells in an IIO specifier; Typically 0 for nodes
- with a single IIO output and 1 for nodes with multiple
- IIO outputs.
-
-Optional properties:
-label: A symbolic name for the device.
-
-
-Example for a simple configuration with no trigger:
-
- adc: voltage-sensor@35 {
- compatible = "maxim,max1139";
- reg = <0x35>;
- #io-channel-cells = <1>;
- label = "voltage_feedback_group1";
- };
-
-Example for a configuration with trigger:
-
- adc@35 {
- compatible = "some-vendor,some-adc";
- reg = <0x35>;
-
- adc1: iio-device@0 {
- #io-channel-cells = <1>;
- /* other properties */
- };
- adc2: iio-device@1 {
- #io-channel-cells = <1>;
- /* other properties */
- };
- };
-
-==IIO consumers==
-
-Required properties:
-io-channels: List of phandle and IIO specifier pairs, one pair
- for each IIO input to the device. Note: if the
- IIO provider specifies '0' for #io-channel-cells,
- then only the phandle portion of the pair will appear.
-
-Optional properties:
-io-channel-names:
- List of IIO input name strings sorted in the same
- order as the io-channels property. Consumers drivers
- will use io-channel-names to match IIO input names
- with IIO specifiers.
-io-channel-ranges:
- Empty property indicating that child nodes can inherit named
- IIO channels from this node. Useful for bus nodes to provide
- and IIO channel to their children.
-
-For example:
-
- device {
- io-channels = <&adc 1>, <&ref 0>;
- io-channel-names = "vcc", "vdd";
- };
-
-This represents a device with two IIO inputs, named "vcc" and "vdd".
-The vcc channel is connected to output 1 of the &adc device, and the
-vdd channel is connected to output 0 of the &ref device.
-
-==Example==
-
- adc: max1139@35 {
- compatible = "maxim,max1139";
- reg = <0x35>;
- #io-channel-cells = <1>;
- };
-
- ...
-
- iio-hwmon {
- compatible = "iio-hwmon";
- io-channels = <&adc 0>, <&adc 1>, <&adc 2>,
- <&adc 3>, <&adc 4>, <&adc 5>,
- <&adc 6>, <&adc 7>, <&adc 8>,
- <&adc 9>;
- };
-
- some_consumer {
- compatible = "some-consumer";
- io-channels = <&adc 10>, <&adc 11>;
- io-channel-names = "adc1", "adc2";
- };
diff --git a/dts/Bindings/iio/impedance-analyzer/ad5933.txt b/dts/Bindings/iio/impedance-analyzer/ad5933.txt
deleted file mode 100644
index 5ff38728ff..0000000000
--- a/dts/Bindings/iio/impedance-analyzer/ad5933.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-Analog Devices AD5933/AD5934 Impedance Converter, Network Analyzer
-
-https://www.analog.com/media/en/technical-documentation/data-sheets/AD5933.pdf
-https://www.analog.com/media/en/technical-documentation/data-sheets/AD5934.pdf
-
-Required properties:
- - compatible : should be one of
- "adi,ad5933"
- "adi,ad5934"
- - reg : the I2C address.
- - vdd-supply : The regulator supply for DVDD, AVDD1 and AVDD2 when they
- are connected together.
-
-Optional properties:
-- clocks : external clock reference.
-- clock-names : must be "mclk" if clocks is set.
-
-Example for a I2C device node:
-
- impedance-analyzer@0d {
- compatible = "adi,adxl345";
- reg = <0x0d>;
- vdd-supply = <&vdd_supply>;
- clocks = <&ref_clk>;
- clock-names = "mclk";
- };
diff --git a/dts/Bindings/iio/impedance-analyzer/adi,ad5933.yaml b/dts/Bindings/iio/impedance-analyzer/adi,ad5933.yaml
new file mode 100644
index 0000000000..2ad043554b
--- /dev/null
+++ b/dts/Bindings/iio/impedance-analyzer/adi,ad5933.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/impedance-analyzer/adi,ad5933.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD5933/AD5934 Impedance Converter, Network Analyzer
+
+maintainers:
+ - Marcelo Schmitt <marcelo.schmitt1@gmail.com>
+ - Gabriel Capella <gabriel@capella.pro>
+
+description: |
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD5933.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD5934.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,ad5933
+ - adi,ad5934
+
+ reg:
+ maxItems: 1
+
+ vdd-supply:
+ description: |
+ The regulator supply for DVDD, AVDD1 and AVDD2 when they
+ are connected together. Used to calculate voltage scaling of measurement
+ channels.
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: mclk
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - vdd-supply
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ impedance-analyzer@d {
+ compatible = "adi,ad5933";
+ reg = <0x0d>;
+ vdd-supply = <&vdd_supply>;
+ clocks = <&ref_clk>;
+ clock-names = "mclk";
+ };
+ };
+...
diff --git a/dts/Bindings/iio/imu/adi,adis16480.txt b/dts/Bindings/iio/imu/adi,adis16480.txt
deleted file mode 100644
index cd903a1d88..0000000000
--- a/dts/Bindings/iio/imu/adi,adis16480.txt
+++ /dev/null
@@ -1,86 +0,0 @@
-
-Analog Devices ADIS16480 and similar IMUs
-
-Required properties for the ADIS16480:
-
-- compatible: Must be one of
- * "adi,adis16375"
- * "adi,adis16480"
- * "adi,adis16485"
- * "adi,adis16488"
- * "adi,adis16490"
- * "adi,adis16495-1"
- * "adi,adis16495-2"
- * "adi,adis16495-3"
- * "adi,adis16497-1"
- * "adi,adis16497-2"
- * "adi,adis16497-3"
-- reg: SPI chip select number for the device
-- spi-max-frequency: Max SPI frequency to use
- see: Documentation/devicetree/bindings/spi/spi-bus.txt
-- spi-cpha: See Documentation/devicetree/bindings/spi/spi-bus.txt
-- spi-cpol: See Documentation/devicetree/bindings/spi/spi-bus.txt
-- interrupts: interrupt mapping for IRQ, accepted values are:
- * IRQF_TRIGGER_RISING
- * IRQF_TRIGGER_FALLING
-
-Optional properties:
-
-- interrupt-names: Data ready line selection. Valid values are:
- * DIO1
- * DIO2
- * DIO3
- * DIO4
- If this field is left empty, DIO1 is assigned as default data ready
- signal.
-- reset-gpios: must be the device tree identifier of the RESET pin. As the line
- is active low, it should be marked GPIO_ACTIVE_LOW.
-- clocks: phandle to the external clock. Should be set according to
- "clock-names".
- If this field is left empty together with the "clock-names" field, then
- the internal clock is used.
-- clock-names: The name of the external clock to be used. Valid values are:
- * sync: In sync mode, the internal clock is disabled and the frequency
- of the external clock signal establishes therate of data
- collection and processing. See Fig 14 and 15 in the datasheet.
- The clock-frequency must be:
- * 3000 to 4500 Hz for adis1649x devices.
- * 700 to 2400 Hz for adis1648x devices.
- * pps: In Pulse Per Second (PPS) Mode, the rate of data collection and
- production is equal to the product of the external clock
- frequency and the scale factor in the SYNC_SCALE register, see
- Table 154 in the datasheet.
- The clock-frequency must be:
- * 1 to 128 Hz for adis1649x devices.
- * This mode is not supported by adis1648x devices.
- If this field is left empty together with the "clocks" field, then the
- internal clock is used.
-- adi,ext-clk-pin: The DIOx line to be used as an external clock input.
- Valid values are:
- * DIO1
- * DIO2
- * DIO3
- * DIO4
- Each DIOx pin supports only one function at a time (data ready line
- selection or external clock input). When a single pin has two
- two assignments, the enable bit for the lower priority function
- automatically resets to zero (disabling the lower priority function).
- Data ready has highest priority.
- If this field is left empty, DIO2 is assigned as default external clock
- input pin.
-
-Example:
-
- imu@0 {
- compatible = "adi,adis16495-1";
- reg = <0>;
- spi-max-frequency = <3200000>;
- spi-cpol;
- spi-cpha;
- interrupts = <25 IRQF_TRIGGER_FALLING>;
- interrupt-parent = <&gpio>;
- interrupt-names = "DIO2";
- clocks = <&adis16495_sync>;
- clock-names = "sync";
- adi,ext-clk-pin = "DIO1";
- };
diff --git a/dts/Bindings/iio/imu/adi,adis16480.yaml b/dts/Bindings/iio/imu/adi,adis16480.yaml
new file mode 100644
index 0000000000..5dbe24be99
--- /dev/null
+++ b/dts/Bindings/iio/imu/adi,adis16480.yaml
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/imu/adi,adis16480.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices ADIS16480 and similar IMUs
+
+maintainers:
+ - Alexandru Ardelean <alexandru.ardelean@analog.com>
+
+properties:
+ compatible:
+ enum:
+ - adi,adis16375
+ - adi,adis16480
+ - adi,adis16485
+ - adi,adis16488
+ - adi,adis16490
+ - adi,adis16495-1
+ - adi,adis16495-2
+ - adi,adis16495-3
+ - adi,adis16497-1
+ - adi,adis16497-2
+ - adi,adis16497-3
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+ description: |
+ Accepted interrupt types are:
+ * IRQ_TYPE_EDGE_RISING
+ * IRQ_TYPE_EDGE_FALLING
+
+ interrupt-names:
+ minItems: 1
+ maxItems: 2
+ description:
+ Default if not supplied is DIO1.
+ items:
+ enum:
+ - DIO1
+ - DIO2
+ - DIO3
+ - DIO4
+
+ spi-max-frequency: true
+
+ spi-cpha: true
+ spi-cpol: true
+
+ reset-gpios:
+ maxItems: 1
+ description: Connected to RESET pin which is active low.
+
+ clocks:
+ maxItems: 1
+ description: If not provided, then the internal clock is used.
+
+ clock-names:
+ description: |
+ sync: In sync mode, the internal clock is disabled and the frequency
+ of the external clock signal establishes therate of data
+ collection and processing. See Fig 14 and 15 in the datasheet.
+ The clock-frequency must be:
+ * 3000 to 4500 Hz for adis1649x devices.
+ * 700 to 2400 Hz for adis1648x devices.
+ pps: In Pulse Per Second (PPS) Mode, the rate of data collection and
+ production is equal to the product of the external clock
+ frequency and the scale factor in the SYNC_SCALE register, see
+ Table 154 in the datasheet.
+ The clock-frequency must be:
+ * 1 to 128 Hz for adis1649x devices.
+ * This mode is not supported by adis1648x devices.
+ enum:
+ - sync
+ - pps
+
+ adi,ext-clk-pin:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: |
+ The DIOx line to be used as an external clock input.
+ Each DIOx pin supports only one function at a time (data ready line
+ selection or external clock input). When a single pin has two
+ two assignments, the enable bit for the lower priority function
+ automatically resets to zero (disabling the lower priority function).
+ Data ready has highest priority.
+ If not provided then DIO2 is assigned as default external clock
+ input pin.
+ enum:
+ - DIO1
+ - DIO2
+ - DIO3
+ - DIO4
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - spi-cpha
+ - spi-cpol
+ - spi-max-frequency
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ imu@0 {
+ compatible = "adi,adis16495-1";
+ reg = <0>;
+ spi-max-frequency = <3200000>;
+ spi-cpol;
+ spi-cpha;
+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpio>;
+ interrupt-names = "DIO2";
+ clocks = <&adis16495_sync>;
+ clock-names = "sync";
+ adi,ext-clk-pin = "DIO1";
+ };
+ };
+...
diff --git a/dts/Bindings/iio/imu/st,lsm6dsx.yaml b/dts/Bindings/iio/imu/st,lsm6dsx.yaml
new file mode 100644
index 0000000000..d9b3213318
--- /dev/null
+++ b/dts/Bindings/iio/imu/st,lsm6dsx.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/imu/st,lsm6dsx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STM 6-axis (acc + gyro) IMU Mems sensors
+
+maintainers:
+ - Lorenzo Bianconi <lorenzo@kernel.org>
+
+description:
+ Devices have both I2C and SPI interfaces.
+
+properties:
+ compatible:
+ enum:
+ - st,lsm6ds3
+ - st,lsm6ds3h
+ - st,lsm6dsl
+ - st,lsm6dsm
+ - st,ism330dlc
+ - st,lsm6dso
+ - st,asm330lhh
+ - st,lsm6dsox
+ - st,lsm6dsr
+ - st,lsm6ds3tr-c
+ - st,ism330dhcx
+ - st,lsm9ds1-imu
+ - st,lsm6ds0
+ - st,lsm6dsrx
+ - st,lsm6dst
+ - st,lsm6dsop
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+ description:
+ Supports up to 2 interrupt lines via the INT1 and INT2 pins.
+
+ spi-max-frequency: true
+
+ vdd-supply:
+ description: if defined provides VDD power to the sensor.
+
+ vddio-supply:
+ description: if defined provides VDD IO power to the sensor.
+
+ st,drdy-int-pin:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: |
+ The pin on the package that will be used to signal data ready
+ enum:
+ - 1
+ - 2
+
+ st,pullups:
+ type: boolean
+ description: enable/disable internal i2c controller pullup resistors.
+
+ drive-open-drain:
+ type: boolean
+ description:
+ The interrupt/data ready line will be configured as open drain, which
+ is useful if several sensors share the same interrupt line.
+
+ wakeup-source:
+ $ref: /schemas/types.yaml#/definitions/flag
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ imu@6b {
+ compatible = "st,lsm6dsm";
+ reg = <0x6b>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/imu/st_lsm6dsx.txt b/dts/Bindings/iio/imu/st_lsm6dsx.txt
deleted file mode 100644
index cef4bc16fc..0000000000
--- a/dts/Bindings/iio/imu/st_lsm6dsx.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-* ST_LSM6DSx driver for STM 6-axis (acc + gyro) imu Mems sensors
-
-Required properties:
-- compatible: must be one of:
- "st,lsm6ds3"
- "st,lsm6ds3h"
- "st,lsm6dsl"
- "st,lsm6dsm"
- "st,ism330dlc"
- "st,lsm6dso"
- "st,asm330lhh"
- "st,lsm6dsox"
- "st,lsm6dsr"
- "st,lsm6ds3tr-c"
- "st,ism330dhcx"
- "st,lsm9ds1-imu"
- "st,lsm6ds0"
- "st,lsm6dsrx"
-- reg: i2c address of the sensor / spi cs line
-
-Optional properties:
-- st,drdy-int-pin: the pin on the package that will be used to signal
- "data ready" (valid values: 1 or 2).
-- st,pullups : enable/disable internal i2c controller pullup resistors.
-- drive-open-drain: the interrupt/data ready line will be configured
- as open drain, which is useful if several sensors share the same
- interrupt line. This is a boolean property.
- (This binding is taken from pinctrl/pinctrl-bindings.txt)
- If the requested interrupt is configured as IRQ_TYPE_LEVEL_HIGH or
- IRQ_TYPE_EDGE_RISING a pull-down resistor is needed to drive the line
- when it is not active, whereas a pull-up one is needed when interrupt
- line is configured as IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_EDGE_FALLING.
-- interrupts: interrupt mapping for IRQ. It should be configured with
- flags IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_RISING, IRQ_TYPE_LEVEL_LOW or
- IRQ_TYPE_EDGE_FALLING.
-- wakeup-source: Enables wake up of host system on event.
-
- Refer to interrupt-controller/interrupts.txt for generic interrupt
- client node bindings.
-
-Example:
-
-lsm6dsm@6b {
- compatible = "st,lsm6dsm";
- reg = <0x6b>;
- interrupt-parent = <&gpio0>;
- interrupts = <0 IRQ_TYPE_EDGE_RISING>;
-};
diff --git a/dts/Bindings/iio/light/apds9300.txt b/dts/Bindings/iio/light/apds9300.txt
deleted file mode 100644
index 3aa6db3ee9..0000000000
--- a/dts/Bindings/iio/light/apds9300.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-* Avago APDS9300 ambient light sensor
-
-https://www.avagotech.com/docs/AV02-1077EN
-
-Required properties:
-
- - compatible : should be "avago,apds9300"
- - reg : the I2C address of the sensor
-
-Optional properties:
-
- - interrupts : interrupt mapping for GPIO IRQ
-
-Example:
-
-apds9300@39 {
- compatible = "avago,apds9300";
- reg = <0x39>;
- interrupt-parent = <&gpio2>;
- interrupts = <29 8>;
-};
diff --git a/dts/Bindings/iio/light/apds9960.txt b/dts/Bindings/iio/light/apds9960.txt
deleted file mode 100644
index c53ddb81c4..0000000000
--- a/dts/Bindings/iio/light/apds9960.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-* Avago APDS9960 gesture/RGB/ALS/proximity sensor
-
-https://www.avagotech.com/docs/AV02-4191EN
-
-Required properties:
-
- - compatible: must be "avago,apds9960"
- - reg: the I2c address of the sensor
- - interrupts : the sole interrupt generated by the device
-
- Refer to interrupt-controller/interrupts.txt for generic interrupt client
- node bindings.
-
-Example:
-
-apds9960@39 {
- compatible = "avago,apds9960";
- reg = <0x39>;
- interrupt-parent = <&gpio1>;
- interrupts = <16 1>;
-};
diff --git a/dts/Bindings/iio/light/avago,apds9300.yaml b/dts/Bindings/iio/light/avago,apds9300.yaml
new file mode 100644
index 0000000000..206af44f2c
--- /dev/null
+++ b/dts/Bindings/iio/light/avago,apds9300.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/light/avago,apds9300.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Avago APDS9300 ambient light sensor
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+description: |
+ Datasheet at https://www.avagotech.com/docs/AV02-1077EN
+
+properties:
+ compatible:
+ const: avago,apds9300
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ light-sensor@39 {
+ compatible = "avago,apds9300";
+ reg = <0x39>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <29 8>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/light/avago,apds9960.yaml b/dts/Bindings/iio/light/avago,apds9960.yaml
new file mode 100644
index 0000000000..f06e0fda56
--- /dev/null
+++ b/dts/Bindings/iio/light/avago,apds9960.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/light/avago,apds9960.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Avago APDS9960 gesture/RGB/ALS/proximity sensor
+
+maintainers:
+ - Matt Ranostay <matt.ranostay@konsulko.com>
+
+description: |
+ Datasheet at https://www.avagotech.com/docs/AV02-4191EN
+
+properties:
+ compatible:
+ const: avago,apds9960
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ light-sensor@39 {
+ compatible = "avago,apds9960";
+ reg = <0x39>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <16 1>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/light/capella,cm3605.yaml b/dts/Bindings/iio/light/capella,cm3605.yaml
new file mode 100644
index 0000000000..27972938b6
--- /dev/null
+++ b/dts/Bindings/iio/light/capella,cm3605.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/light/capella,cm3605.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title:
+ Capella Microsystems CM3605 Ambient Light and Short Distance Proximity Sensor
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+ - Kevin Tsai <ktsai@capellamicro.com>
+
+description: |
+ The CM3605 is an entirely analog part. However, it requires quite a bit of
+ software logic to interface a host operating system.
+
+ This ALS and proximity sensor was one of the very first deployed in mobile
+ handsets, notably it is used in the very first Nexus One Android phone from
+ 2010.
+
+properties:
+ compatible:
+ const: capella,cm3605
+
+ aset-gpios:
+ maxItems: 1
+ description:
+ ASET line (drive low to activate the ALS, should be flagged
+ GPIO_ACTIVE_LOW)
+
+ interrupts:
+ maxItems: 1
+ description:
+ Connected to the POUT (proximity sensor out) line. The edge
+ detection must be set to IRQ_TYPE_EDGE_BOTH so as to detect
+ movements toward and away from the proximity sensor.
+
+ io-channels:
+ maxItems: 1
+ description:
+ ADC channel used for converting the voltage from AOUT to a digital
+ representation.
+
+ io-channel-names:
+ const: aout
+
+ vdd-supply: true
+
+ capella,aset-resistance-ohms:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [50000, 100000, 300000, 600000]
+ description: >
+ Sensitivity calibration resistance. Note that calibration curves
+ are only provided for specific allowed values. Default: 100 kOhms.
+
+required:
+ - compatible
+ - aset-gpios
+ - interrupts
+ - io-channels
+ - io-channel-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ light-sensor {
+ compatible = "capella,cm3605";
+ vdd-supply = <&foo_reg>;
+ aset-gpios = <&foo_gpio 1 GPIO_ACTIVE_LOW>;
+ capella,aset-resistance-ohms = <100000>;
+ interrupts = <1 IRQ_TYPE_EDGE_BOTH>;
+ io-channels = <&adc 0x01>;
+ io-channel-names = "aout";
+ };
+...
diff --git a/dts/Bindings/iio/light/capella,cm36651.yaml b/dts/Bindings/iio/light/capella,cm36651.yaml
new file mode 100644
index 0000000000..446d94f3a8
--- /dev/null
+++ b/dts/Bindings/iio/light/capella,cm36651.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/light/capella,cm36651.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Capella CM36651 I2C Proximity and Color Light sensor
+
+maintainers:
+ - Beomho Seo <beomho.seo@samsung.com>
+
+properties:
+ compatible:
+ const: capella,cm36651
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ vled-supply:
+ description: |
+ Supply for the IR_LED which is part of the cm36651 for proximity detection.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - vled-supply
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ light-sensor@18 {
+ compatible = "capella,cm36651";
+ reg = <0x18>;
+ interrupt-parent = <&gpx0>;
+ interrupts = <2 0>;
+ vled-supply = <&ps_als_reg>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/light/cm3605.txt b/dts/Bindings/iio/light/cm3605.txt
deleted file mode 100644
index 56331a79f9..0000000000
--- a/dts/Bindings/iio/light/cm3605.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-Capella Microsystems CM3605
-Ambient Light and Short Distance Proximity Sensor
-
-The CM3605 is an entirely analog part which however require quite a bit of
-software logic to interface a host operating system.
-
-This ALS and proximity sensor was one of the very first deployed in mobile
-handsets, notably it is used in the very first Nexus One Android phone from
-2010.
-
-Required properties:
-- compatible: must be: "capella,cm3605"
-- aset-gpios: GPIO line controlling the ASET line (drive low
- to activate the ALS, should be flagged GPIO_ACTIVE_LOW)
-- interrupts: the IRQ line (such as a GPIO) that is connected to
- the POUT (proximity sensor out) line. The edge detection must
- be set to IRQ_TYPE_EDGE_BOTH so as to detect movements toward
- and away from the proximity sensor.
-- io-channels: the ADC channel used for converting the voltage from
- AOUT to a digital representation.
-- io-channel-names: must be "aout"
-
-Optional properties:
-- vdd-supply: regulator supplying VDD power to the component.
-- capella,aset-resistance-ohms: the sensitivity calibration resistance,
- in Ohms. Valid values are: 50000, 100000, 300000 and 600000,
- as these are the resistance values that we are supplied with
- calibration curves for. If not supplied, 100 kOhm will be assumed
- but it is strongly recommended to supply this.
-
-Example:
-
-cm3605 {
- compatible = "capella,cm3605";
- vdd-supply = <&foo_reg>;
- aset-gpios = <&foo_gpio 1 GPIO_ACTIVE_LOW>;
- capella,aset-resistance-ohms = <100000>;
- interrupts = <1 IRQ_TYPE_EDGE_BOTH>;
- io-channels = <&adc 0x01>;
- io-channel-names = "aout";
-};
diff --git a/dts/Bindings/iio/light/cm36651.txt b/dts/Bindings/iio/light/cm36651.txt
deleted file mode 100644
index c03e19db45..0000000000
--- a/dts/Bindings/iio/light/cm36651.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-* Capella CM36651 I2C Proximity and Color Light sensor
-
-Required properties:
-- compatible: must be "capella,cm36651"
-- reg: the I2C address of the device
-- interrupts: interrupt-specifier for the sole interrupt
- generated by the device
-- vled-supply: regulator for the IR LED. IR_LED is a part
- of the cm36651 for proximity detection.
- As covered in ../../regulator/regulator.txt
-
-Example:
-
- i2c_cm36651: i2c-gpio {
- /* ... */
-
- cm36651@18 {
- compatible = "capella,cm36651";
- reg = <0x18>;
- interrupt-parent = <&gpx0>;
- interrupts = <2 0>;
- vled-supply = <&ps_als_reg>;
- };
-
- /* ... */
- };
diff --git a/dts/Bindings/iio/light/gp2ap020a00f.txt b/dts/Bindings/iio/light/gp2ap020a00f.txt
deleted file mode 100644
index 9231c82317..0000000000
--- a/dts/Bindings/iio/light/gp2ap020a00f.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-* Sharp GP2AP020A00F I2C Proximity/ALS sensor
-
-The proximity detector sensor requires power supply
-for its built-in led. It is also defined by this binding.
-
-Required properties:
-
- - compatible : should be "sharp,gp2ap020a00f"
- - reg : the I2C slave address of the light sensor
- - interrupts : interrupt specifier for the sole interrupt generated
- by the device
- - vled-supply : VLED power supply, as covered in ../regulator/regulator.txt
-
-Example:
-
-gp2ap020a00f@39 {
- compatible = "sharp,gp2ap020a00f";
- reg = <0x39>;
- interrupts = <2 0>;
- vled-supply = <...>;
-};
diff --git a/dts/Bindings/iio/light/max44009.txt b/dts/Bindings/iio/light/max44009.txt
deleted file mode 100644
index 4a98848e35..0000000000
--- a/dts/Bindings/iio/light/max44009.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-* MAX44009 Ambient Light Sensor
-
-Required properties:
-
-- compatible: should be "maxim,max44009"
-- reg: the I2C address of the device (default is <0x4a>)
-
-Optional properties:
-
-- interrupts: interrupt mapping for GPIO IRQ. Should be configured with
- IRQ_TYPE_EDGE_FALLING.
-
-Refer to interrupt-controller/interrupts.txt for generic interrupt client
-node bindings.
-
-Example:
-
-light-sensor@4a {
- compatible = "maxim,max44009";
- reg = <0x4a>;
-
- interrupt-parent = <&gpio1>;
- interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
-};
diff --git a/dts/Bindings/iio/light/maxim,max44009.yaml b/dts/Bindings/iio/light/maxim,max44009.yaml
new file mode 100644
index 0000000000..5911bd93bc
--- /dev/null
+++ b/dts/Bindings/iio/light/maxim,max44009.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/light/maxim,max44009.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MAX44009 Ambient Light Sensor
+
+maintainers:
+ - Robert Eshleman <bobbyeshleman@gmail.com>
+
+properties:
+ compatible:
+ const: maxim,max44009
+
+ reg:
+ maxItems: 1
+ description: Default address is 0x4a
+
+ interrupts:
+ maxItems: 1
+ description: Should be configured with type IRQ_TYPE_EDGE_FALLING
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ light-sensor@4a {
+ compatible = "maxim,max44009";
+ reg = <0x4a>;
+
+ interrupt-parent = <&gpio1>;
+ interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/light/opt3001.txt b/dts/Bindings/iio/light/opt3001.txt
deleted file mode 100644
index 9e6f2998e7..0000000000
--- a/dts/Bindings/iio/light/opt3001.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-* Texas Instruments OPT3001 Ambient Light Sensor
-
-The driver supports interrupt-driven and interrupt-less operation, depending
-on whether an interrupt property has been populated into the DT. Note that
-the optional generation of IIO events on rising/falling light threshold changes
-requires the use of interrupts. Without interrupts, only the simple reading
-of the current light value is supported through the IIO API.
-
-https://www.ti.com/product/opt3001
-
-Required properties:
- - compatible: should be "ti,opt3001"
- - reg: the I2C address of the sensor
-
-Optional properties:
- - interrupts: interrupt mapping for GPIO IRQ (configure for falling edge)
-
-Example:
-
-opt3001@44 {
- compatible = "ti,opt3001";
- reg = <0x44>;
- interrupt-parent = <&gpio1>;
- interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
-};
diff --git a/dts/Bindings/iio/light/renesas,isl29501.txt b/dts/Bindings/iio/light/renesas,isl29501.txt
deleted file mode 100644
index 46957997fe..0000000000
--- a/dts/Bindings/iio/light/renesas,isl29501.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-* ISL29501 Time-of-flight sensor.
-
-Required properties:
-
- - compatible : should be "renesas,isl29501"
- - reg : the I2C address of the sensor
-
-Example:
-
-isl29501@57 {
- compatible = "renesas,isl29501";
- reg = <0x57>;
-};
diff --git a/dts/Bindings/iio/light/sharp,gp2ap020a00f.yaml b/dts/Bindings/iio/light/sharp,gp2ap020a00f.yaml
new file mode 100644
index 0000000000..3fabf1f576
--- /dev/null
+++ b/dts/Bindings/iio/light/sharp,gp2ap020a00f.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/light/sharp,gp2ap020a00f.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sharp GP2AP020A00F I2C Proximity/ALS sensor
+
+maintainers:
+ - Kyungmin Park <kyungmin.park@samsung.com>
+
+description: |
+ The proximity detector sensor requires power supply for its built-in led.
+
+properties:
+ compatible:
+ const: sharp,gp2ap020a00f
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ vled-supply: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - vled-supply
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ light-sensor@39 {
+ compatible = "sharp,gp2ap020a00f";
+ reg = <0x39>;
+ interrupts = <2 0>;
+ vled-supply = <&als_reg>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/light/st,uvis25.yaml b/dts/Bindings/iio/light/st,uvis25.yaml
new file mode 100644
index 0000000000..c86e5e1d13
--- /dev/null
+++ b/dts/Bindings/iio/light/st,uvis25.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/light/st,uvis25.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ST UVIS25 uv sensor
+
+maintainers:
+ - Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
+
+properties:
+ compatible:
+ const: st,uvis25
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ uv-sensor@47 {
+ compatible = "st,uvis25";
+ reg = <0x47>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/light/st,vl6180.yaml b/dts/Bindings/iio/light/st,vl6180.yaml
new file mode 100644
index 0000000000..27c36ab799
--- /dev/null
+++ b/dts/Bindings/iio/light/st,vl6180.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/light/st,vl6180.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicro VL6180 ALS, range and proximity sensor
+
+maintainers:
+ - Manivannan Sadhasivam <manivannanece23@gmail.com>
+ - Peter Meerwald-Stadler <pmeerw@pmeerw.net>
+
+description: |
+ Proximity sensing module incorporating time of flight sensor
+ Datasheet at https://www.st.com/resource/en/datasheet/vl6180x.pdf
+
+properties:
+ compatible:
+ const: st,vl6180
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ proximity@29 {
+ compatible = "st,vl6180";
+ reg = <0x29>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/light/ti,opt3001.yaml b/dts/Bindings/iio/light/ti,opt3001.yaml
new file mode 100644
index 0000000000..441e9343fc
--- /dev/null
+++ b/dts/Bindings/iio/light/ti,opt3001.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/light/ti,opt3001.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments OPT3001 Ambient Light Sensor
+
+maintainers:
+ - Andreas Dannenberg <dannenberg@ti.com>
+
+description: |
+ The device supports interrupt-driven and interrupt-less operation, depending
+ on whether an interrupt property has been populated into the DT.
+
+properties:
+ compatible:
+ const: ti,opt3001
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+ description: Should be configured with type IRQ_TYPE_EDGE_FALLING
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ light-sensor@44 {
+ compatible = "ti,opt3001";
+ reg = <0x44>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/light/upisemi,us5182.yaml b/dts/Bindings/iio/light/upisemi,us5182.yaml
new file mode 100644
index 0000000000..de5882cb33
--- /dev/null
+++ b/dts/Bindings/iio/light/upisemi,us5182.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/light/upisemi,us5182.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UPISEMI us5182d I2C ALS and Proximity sensor
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+properties:
+ compatible:
+ const: upisemi,asd5182
+
+ reg:
+ maxItems: 1
+
+ upsemi,glass-coef:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ glass attenuation factor - compensation factor of resolution 1000
+ for material transmittance.
+ default: 1000
+
+ upisemi,dark-ths:
+ $ref: /schemas/types.yaml#/definitions/uint16-array
+ minItems: 8
+ maxItems: 8
+ description:
+ 16-bit thresholds (adc counts) corresponding to every scale.
+
+ upisemi,upper-dark-gain:
+ $ref: /schemas/types.yaml#/definitions/uint8
+ description: |
+ 8-bit dark gain compensation factor(4 int and 4 fractional bits - Q4.4)
+ applied when light > threshold.
+ default: 0
+
+ upisemi,lower-dark-gain:
+ $ref: /schemas/types.yaml#/definitions/uint8
+ description: |
+ 8-bit dark gain compensation factor(4 int and 4 fractional bits - Q4.4)
+ applied when light < threshold.
+ default: 0x16
+
+ upisemi,continuous:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: |
+ This chip has two power modes: one-shot (chip takes one measurement and
+ then shuts itself down) and continuous (chip takes continuous
+ measurements). The one-shot mode is more power-friendly but the
+ continuous mode may be more reliable. If this property is specified
+ the continuous mode will be used instead of the default one-shot one for
+ raw reads.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ light-sensor@39 {
+ compatible = "upisemi,usd5182";
+ reg = <0x39>;
+ upisemi,glass-coef = < 1000 >;
+ upisemi,dark-ths = /bits/ 16 <170 200 512 512 800 2000 4000 8000>;
+ upisemi,upper-dark-gain = /bits/ 8 <0x00>;
+ upisemi,lower-dark-gain = /bits/ 8 <0x16>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/light/us5182d.txt b/dts/Bindings/iio/light/us5182d.txt
deleted file mode 100644
index a61979997f..0000000000
--- a/dts/Bindings/iio/light/us5182d.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-* UPISEMI us5182d I2C ALS and Proximity sensor
-
-Required properties:
-- compatible: must be "upisemi,usd5182"
-- reg: the I2C address of the device
-
-Optional properties:
-- upisemi,glass-coef: glass attenuation factor - compensation factor of
- resolution 1000 for material transmittance.
-
-- upisemi,dark-ths: array of 8 elements containing 16-bit thresholds (adc
- counts) corresponding to every scale.
-
-- upisemi,upper-dark-gain: 8-bit dark gain compensation factor(4 int and 4
- fractional bits - Q4.4) applied when light > threshold
-
-- upisemi,lower-dark-gain: 8-bit dark gain compensation factor(4 int and 4
- fractional bits - Q4.4) applied when light < threshold
-
-- upisemi,continuous: This chip has two power modes: one-shot (chip takes one
- measurement and then shuts itself down) and continuous (
- chip takes continuous measurements). The one-shot mode is
- more power-friendly but the continuous mode may be more
- reliable. If this property is specified the continuous
- mode will be used instead of the default one-shot one for
- raw reads.
-
-If the optional properties are not specified these factors will default to the
-values in the below example.
-The glass-coef defaults to no compensation for the covering material.
-The threshold array defaults to experimental values that work with US5182D
-sensor on evaluation board - roughly between 12-32 lux.
-There will be no dark-gain compensation by default when ALS > thresh
-(0 * dark-gain), and a 1.35 compensation factor when ALS < thresh.
-
-Example:
-
- usd5182@39 {
- compatible = "upisemi,usd5182";
- reg = <0x39>;
- upisemi,glass-coef = < 1000 >;
- upisemi,dark-ths = /bits/ 16 <170 200 512 512 800 2000 4000 8000>;
- upisemi,upper-dark-gain = /bits/ 8 <0x00>;
- upisemi,lower-dark-gain = /bits/ 8 <0x16>;
- };
diff --git a/dts/Bindings/iio/light/uvis25.txt b/dts/Bindings/iio/light/uvis25.txt
deleted file mode 100644
index 043c139d91..0000000000
--- a/dts/Bindings/iio/light/uvis25.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-* ST UVIS25 uv sensor
-
-Required properties:
-- compatible: should be "st,uvis25"
-- reg: i2c address of the sensor / spi cs line
-
-Optional properties:
-- interrupts: interrupt mapping for IRQ. It should be configured with
- flags IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_RISING, IRQ_TYPE_LEVEL_LOW or
- IRQ_TYPE_EDGE_FALLING.
-
- Refer to interrupt-controller/interrupts.txt for generic interrupt
- client node bindings.
-
-Example:
-
-uvis25@47 {
- compatible = "st,uvis25";
- reg = <0x47>;
- interrupt-parent = <&gpio0>;
- interrupts = <0 IRQ_TYPE_EDGE_RISING>;
-};
diff --git a/dts/Bindings/iio/light/vcnl4035.txt b/dts/Bindings/iio/light/vcnl4035.txt
deleted file mode 100644
index c07c7f0525..0000000000
--- a/dts/Bindings/iio/light/vcnl4035.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-VISHAY VCNL4035 - Ambient Light and proximity sensor
-
-Link to datasheet: https://www.vishay.com/docs/84251/vcnl4035x01.pdf
-
-Required properties:
-
- -compatible: should be "vishay,vcnl4035"
- -reg: I2C address of the sensor, should be 0x60
- -interrupts: interrupt mapping for GPIO IRQ (level active low)
-
-Example:
-
-light-sensor@60 {
- compatible = "vishay,vcnl4035";
- reg = <0x60>;
- interrupt-parent = <&gpio4>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
-};
diff --git a/dts/Bindings/iio/light/vishay,vcnl4035.yaml b/dts/Bindings/iio/light/vishay,vcnl4035.yaml
new file mode 100644
index 0000000000..2c57ff05de
--- /dev/null
+++ b/dts/Bindings/iio/light/vishay,vcnl4035.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/light/vishay,vcnl4035.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: VISHAY VCNL4035 ambient Light and proximity sensor
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+description: |
+ Datasheet at https://www.vishay.com/docs/84251/vcnl4035x01.pdf
+
+properties:
+ compatible:
+ const: vishay,vcnl4035
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ light-sensor@60 {
+ compatible = "vishay,vcnl4035";
+ reg = <0x60>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/light/vl6180.txt b/dts/Bindings/iio/light/vl6180.txt
deleted file mode 100644
index fb9137d85d..0000000000
--- a/dts/Bindings/iio/light/vl6180.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-STMicro VL6180 - ALS, range and proximity sensor
-
-Link to datasheet: https://www.st.com/resource/en/datasheet/vl6180x.pdf
-
-Required properties:
-
- -compatible: should be "st,vl6180"
- -reg: the I2C address of the sensor
-
-Example:
-
-vl6180@29 {
- compatible = "st,vl6180";
- reg = <0x29>;
-};
diff --git a/dts/Bindings/iio/magnetometer/ak8974.txt b/dts/Bindings/iio/magnetometer/ak8974.txt
deleted file mode 100644
index 7f06eff3b5..0000000000
--- a/dts/Bindings/iio/magnetometer/ak8974.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-* Asahi Kasei AK8974 magnetometer sensor
-
-Required properties:
-
-- compatible:
- * "asahi-kasei,ak8974"
- * "alps,hscdtd008a"
-- reg : the I2C address of the magnetometer
-
-Optional properties:
-
-- avdd-supply: regulator supply for the analog voltage
- (see regulator/regulator.txt)
-- dvdd-supply: regulator supply for the digital voltage
- (see regulator/regulator.txt)
-- interrupts: data ready (DRDY) and interrupt (INT1) lines
- from the chip, the DRDY interrupt must be placed first.
- The interrupts can be triggered on rising or falling
- edges alike.
-- mount-matrix: an optional 3x3 mounting rotation matrix
-
-Example:
-
-ak8974@f {
- compatible = "asahi-kasei,ak8974";
- reg = <0x0f>;
- avdd-supply = <&foo_reg>;
- dvdd-supply = <&bar_reg>;
- interrupts = <0 IRQ_TYPE_EDGE_RISING>,
- <1 IRQ_TYPE_EDGE_RISING>;
-};
diff --git a/dts/Bindings/iio/magnetometer/asahi-kasei,ak8974.yaml b/dts/Bindings/iio/magnetometer/asahi-kasei,ak8974.yaml
new file mode 100644
index 0000000000..cefb70def1
--- /dev/null
+++ b/dts/Bindings/iio/magnetometer/asahi-kasei,ak8974.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/magnetometer/asahi-kasei,ak8974.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Asahi Kasei AK8974 magnetometer sensor
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+properties:
+ compatible:
+ enum:
+ - alps,hscdtd008a
+ - asahi-kasei,ak8974
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+ description: |
+ Data ready (DRDY) and interrupt (INT1) lines from the chip. The DRDY
+ interrupt must be placed first. The interrupts can be triggered on
+ rising or falling edges.
+
+ avdd-supply: true
+
+ dvdd-supply: true
+
+ mount-matrix: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ magnetometer@f {
+ compatible = "asahi-kasei,ak8974";
+ reg = <0x0f>;
+ avdd-supply = <&foo_reg>;
+ dvdd-supply = <&bar_reg>;
+ interrupts = <0 IRQ_TYPE_EDGE_RISING>,
+ <1 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/magnetometer/bmc150_magn.txt b/dts/Bindings/iio/magnetometer/bmc150_magn.txt
deleted file mode 100644
index 22912e43b6..0000000000
--- a/dts/Bindings/iio/magnetometer/bmc150_magn.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-* Bosch BMC150 magnetometer sensor
-
-http://ae-bst.resource.bosch.com/media/products/dokumente/bmc150/BST-BMC150-DS000-04.pdf
-
-Required properties:
-
- - compatible : should be one of:
- "bosch,bmc150_magn"
- "bosch,bmc156_magn"
- "bosch,bmm150"
- "bosch,bmm150_magn" (DEPRECATED, use bosch,bmm150)
- - reg : the I2C address of the magnetometer
-
-Optional properties:
-
- - interrupts : interrupt mapping for GPIO IRQ
-
-Example:
-
-bmc150_magn@12 {
- compatible = "bosch,bmc150_magn";
- reg = <0x12>;
- interrupt-parent = <&gpio1>;
- interrupts = <0 1>;
-};
diff --git a/dts/Bindings/iio/magnetometer/bosch,bmc150_magn.yaml b/dts/Bindings/iio/magnetometer/bosch,bmc150_magn.yaml
new file mode 100644
index 0000000000..cdef7aeba7
--- /dev/null
+++ b/dts/Bindings/iio/magnetometer/bosch,bmc150_magn.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/magnetometer/bosch,bmc150_magn.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bosch BMC150 magnetometer sensor
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+description: |
+ Supports a range of parts, some of which form part of a multi die
+ package that also contains other sensors. The interface is independent
+ however, so a separate driver is used to support the magnetometer part.
+ Datasheet at:
+ http://ae-bst.resource.bosch.com/media/products/dokumente/bmc150/BST-BMC150-DS000-04.pdf
+
+properties:
+ compatible:
+ description:
+ Note the bmm150_magn is a deprecated compatible as this part contains only
+ a magnetometer.
+ enum:
+ - bosch,bmc150_magn
+ - bosch,bmc156_magn
+ - bosch,bmm150
+ - bosch,bmm150_magn
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ magnetometer@12 {
+ compatible = "bosch,bmc150_magn";
+ reg = <0x12>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <0 1>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/magnetometer/fsl,mag3110.yaml b/dts/Bindings/iio/magnetometer/fsl,mag3110.yaml
new file mode 100644
index 0000000000..6b54d32323
--- /dev/null
+++ b/dts/Bindings/iio/magnetometer/fsl,mag3110.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/magnetometer/fsl,mag3110.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale MAG3110 magnetometer sensor
+
+maintainers:
+ - Anson Huang <Anson.Huang@nxp.com>
+
+properties:
+ compatible:
+ const: fsl,mag3110
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ vdd-supply: true
+
+ vddio-supply: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ magnetometer@e {
+ compatible = "fsl,mag3110";
+ reg = <0x0e>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3_mag3110_int>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <16 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/magnetometer/hmc5843.txt b/dts/Bindings/iio/magnetometer/hmc5843.txt
deleted file mode 100644
index 8e191eef01..0000000000
--- a/dts/Bindings/iio/magnetometer/hmc5843.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-* Honeywell HMC5843 magnetometer sensor
-
-Required properties:
-
- - compatible : should be "honeywell,hmc5843"
- Other models which are supported with driver are:
- "honeywell,hmc5883"
- "honeywell,hmc5883l"
- "honeywell,hmc5983"
- - reg : the I2C address of the magnetometer - typically 0x1e
-
-Optional properties:
-
- - gpios : should be device tree identifier of the magnetometer DRDY pin
-
-Example:
-
-hmc5843@1e {
- compatible = "honeywell,hmc5843"
- reg = <0x1e>;
-};
diff --git a/dts/Bindings/iio/magnetometer/honeywell,hmc5843.yaml b/dts/Bindings/iio/magnetometer/honeywell,hmc5843.yaml
new file mode 100644
index 0000000000..5e778c9858
--- /dev/null
+++ b/dts/Bindings/iio/magnetometer/honeywell,hmc5843.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/magnetometer/honeywell,hmc5843.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Honeywell HMC5843 magnetometer sensor
+
+maintainers:
+ - Neil Brown <neilb@suse.de>
+
+properties:
+ compatible:
+ enum:
+ - honeywell,hmc5843
+ - honeywell,hmc5883
+ - honeywell,hmc5883l
+ - honeywell,hmc5983
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ magnetometer@1e {
+ compatible = "honeywell,hmc5843";
+ reg = <0x1e>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/magnetometer/mag3110.txt b/dts/Bindings/iio/magnetometer/mag3110.txt
deleted file mode 100644
index bdd40bcaaa..0000000000
--- a/dts/Bindings/iio/magnetometer/mag3110.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-* FREESCALE MAG3110 magnetometer sensor
-
-Required properties:
-
- - compatible : should be "fsl,mag3110"
- - reg : the I2C address of the magnetometer
-
-Optional properties:
-
- - interrupts: the sole interrupt generated by the device
-
- Refer to interrupt-controller/interrupts.txt for generic interrupt client
- node bindings.
-
- - vdd-supply: phandle to the regulator that provides power to the sensor.
- - vddio-supply: phandle to the regulator that provides power to the sensor's IO.
-
-Example:
-
-magnetometer@e {
- compatible = "fsl,mag3110";
- reg = <0x0e>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3_mag3110_int>;
- interrupt-parent = <&gpio3>;
- interrupts = <16 IRQ_TYPE_EDGE_RISING>;
-};
diff --git a/dts/Bindings/iio/magnetometer/mmc35240.txt b/dts/Bindings/iio/magnetometer/mmc35240.txt
deleted file mode 100644
index a01235c7fa..0000000000
--- a/dts/Bindings/iio/magnetometer/mmc35240.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-* MEMSIC MMC35240 magnetometer sensor
-
-Required properties:
-
- - compatible : should be "memsic,mmc35240"
- - reg : the I2C address of the magnetometer
-
-Example:
-
-mmc35240@30 {
- compatible = "memsic,mmc35240";
- reg = <0x30>;
-};
diff --git a/dts/Bindings/iio/magnetometer/pni,rm3100.txt b/dts/Bindings/iio/magnetometer/pni,rm3100.txt
deleted file mode 100644
index 497c932e9e..0000000000
--- a/dts/Bindings/iio/magnetometer/pni,rm3100.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-* PNI RM3100 3-axis magnetometer sensor
-
-Required properties:
-
-- compatible : should be "pni,rm3100"
-- reg : the I2C address or SPI chip select number of the sensor.
-
-Optional properties:
-
-- interrupts: data ready (DRDY) from the chip.
- The interrupts can be triggered on level high.
-
-Example:
-
-rm3100: rm3100@20 {
- compatible = "pni,rm3100";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
-};
diff --git a/dts/Bindings/iio/magnetometer/pni,rm3100.yaml b/dts/Bindings/iio/magnetometer/pni,rm3100.yaml
new file mode 100644
index 0000000000..a845cdd23e
--- /dev/null
+++ b/dts/Bindings/iio/magnetometer/pni,rm3100.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/magnetometer/pni,rm3100.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PNI RM3100 3-axis magnetometer sensor
+
+maintainers:
+ - Song Qiang <songqiang1304521@gmail.com>
+
+properties:
+ compatible:
+ const: pni,rm3100
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ magnetometer@20 {
+ compatible = "pni,rm3100";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/potentiometer/ad5272.txt b/dts/Bindings/iio/potentiometer/ad5272.txt
deleted file mode 100644
index f9b2eef946..0000000000
--- a/dts/Bindings/iio/potentiometer/ad5272.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-* Analog Devices AD5272 digital potentiometer
-
-The node for this device must be a child node of a I2C controller, hence
-all mandatory properties for your controller must be specified. See directory:
-
- Documentation/devicetree/bindings/i2c
-
-for more details.
-
-Required properties:
- - compatible: Must be one of the following, depending on the model:
- adi,ad5272-020
- adi,ad5272-050
- adi,ad5272-100
- adi,ad5274-020
- adi,ad5274-100
-
-Optional properties:
- - reset-gpios: GPIO specification for the RESET input. This is an
- active low signal to the AD5272.
-
-Example:
-ad5272: potentiometer@2f {
- reg = <0x2F>;
- compatible = "adi,ad5272-020";
- reset-gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>;
-};
diff --git a/dts/Bindings/iio/potentiometer/adi,ad5272.yaml b/dts/Bindings/iio/potentiometer/adi,ad5272.yaml
new file mode 100644
index 0000000000..1aee9f9be9
--- /dev/null
+++ b/dts/Bindings/iio/potentiometer/adi,ad5272.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/potentiometer/adi,ad5272.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD5272 digital potentiometer
+
+maintainers:
+ - Phil Reid <preid@electromag.com.au>
+
+description: |
+ Datasheet: https://www.analog.com/en/products/ad5272.html
+
+properties:
+ compatible:
+ enum:
+ - adi,ad5272-020
+ - adi,ad5272-050
+ - adi,ad5272-100
+ - adi,ad5274-020
+ - adi,ad5274-100
+
+ reg:
+ maxItems: 1
+
+ reset-gpios:
+ description:
+ Active low signal to the AD5272 RESET input.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ potentiometer@2f {
+ compatible = "adi,ad5272-020";
+ reg = <0x2F>;
+ reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/potentiometer/ds1803.txt b/dts/Bindings/iio/potentiometer/ds1803.txt
deleted file mode 100644
index df77bf5526..0000000000
--- a/dts/Bindings/iio/potentiometer/ds1803.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-* Maxim Integrated DS1803 digital potentiometer driver
-
-The node for this driver must be a child node of a I2C controller, hence
-all mandatory properties for your controller must be specified. See directory:
-
- Documentation/devicetree/bindings/i2c
-
-for more details.
-
-Required properties:
- - compatible: Must be one of the following, depending on the
- model:
- "maxim,ds1803-010",
- "maxim,ds1803-050",
- "maxim,ds1803-100"
-
-Example:
-ds1803: ds1803@1 {
- reg = <0x28>;
- compatible = "maxim,ds1803-010";
-};
diff --git a/dts/Bindings/iio/potentiometer/max5481.txt b/dts/Bindings/iio/potentiometer/max5481.txt
deleted file mode 100644
index 6a91b106e0..0000000000
--- a/dts/Bindings/iio/potentiometer/max5481.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-* Maxim Linear-Taper Digital Potentiometer MAX5481-MAX5484
-
-The node for this driver must be a child node of a SPI controller, hence
-all mandatory properties described in
-
- Documentation/devicetree/bindings/spi/spi-bus.txt
-
-must be specified.
-
-Required properties:
- - compatible: Must be one of the following, depending on the
- model:
- "maxim,max5481"
- "maxim,max5482"
- "maxim,max5483"
- "maxim,max5484"
-
-Example:
-max548x: max548x@0 {
- compatible = "maxim,max5482";
- spi-max-frequency = <7000000>;
- reg = <0>; /* chip-select */
-};
diff --git a/dts/Bindings/iio/potentiometer/mcp41010.txt b/dts/Bindings/iio/potentiometer/mcp41010.txt
deleted file mode 100644
index 4f245e8469..0000000000
--- a/dts/Bindings/iio/potentiometer/mcp41010.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-* Microchip MCP41010/41050/41100/42010/42050/42100 Digital Potentiometer
-
-Datasheet publicly available at:
-https://ww1.microchip.com/downloads/en/devicedoc/11195c.pdf
-
-The node for this driver must be a child node of a SPI controller, hence
-all mandatory properties described in
-
- Documentation/devicetree/bindings/spi/spi-bus.txt
-
-must be specified.
-
-Required properties:
- - compatible: Must be one of the following, depending on the
- model:
- "microchip,mcp41010"
- "microchip,mcp41050"
- "microchip,mcp41100"
- "microchip,mcp42010"
- "microchip,mcp42050"
- "microchip,mcp42100"
-
-Example:
-potentiometer@0 {
- compatible = "microchip,mcp41010";
- reg = <0>;
- spi-max-frequency = <500000>;
-};
diff --git a/dts/Bindings/iio/potentiometer/mcp4131.txt b/dts/Bindings/iio/potentiometer/mcp4131.txt
deleted file mode 100644
index 3ccba16f70..0000000000
--- a/dts/Bindings/iio/potentiometer/mcp4131.txt
+++ /dev/null
@@ -1,84 +0,0 @@
-* Microchip MCP413X/414X/415X/416X/423X/424X/425X/426X Digital Potentiometer
- driver
-
-The node for this driver must be a child node of a SPI controller, hence
-all mandatory properties described in
-
- Documentation/devicetree/bindings/spi/spi-bus.txt
-
-must be specified.
-
-Required properties:
- - compatible: Must be one of the following, depending on the
- model:
- "microchip,mcp4131-502"
- "microchip,mcp4131-103"
- "microchip,mcp4131-503"
- "microchip,mcp4131-104"
- "microchip,mcp4132-502"
- "microchip,mcp4132-103"
- "microchip,mcp4132-503"
- "microchip,mcp4132-104"
- "microchip,mcp4141-502"
- "microchip,mcp4141-103"
- "microchip,mcp4141-503"
- "microchip,mcp4141-104"
- "microchip,mcp4142-502"
- "microchip,mcp4142-103"
- "microchip,mcp4142-503"
- "microchip,mcp4142-104"
- "microchip,mcp4151-502"
- "microchip,mcp4151-103"
- "microchip,mcp4151-503"
- "microchip,mcp4151-104"
- "microchip,mcp4152-502"
- "microchip,mcp4152-103"
- "microchip,mcp4152-503"
- "microchip,mcp4152-104"
- "microchip,mcp4161-502"
- "microchip,mcp4161-103"
- "microchip,mcp4161-503"
- "microchip,mcp4161-104"
- "microchip,mcp4162-502"
- "microchip,mcp4162-103"
- "microchip,mcp4162-503"
- "microchip,mcp4162-104"
- "microchip,mcp4231-502"
- "microchip,mcp4231-103"
- "microchip,mcp4231-503"
- "microchip,mcp4231-104"
- "microchip,mcp4232-502"
- "microchip,mcp4232-103"
- "microchip,mcp4232-503"
- "microchip,mcp4232-104"
- "microchip,mcp4241-502"
- "microchip,mcp4241-103"
- "microchip,mcp4241-503"
- "microchip,mcp4241-104"
- "microchip,mcp4242-502"
- "microchip,mcp4242-103"
- "microchip,mcp4242-503"
- "microchip,mcp4242-104"
- "microchip,mcp4251-502"
- "microchip,mcp4251-103"
- "microchip,mcp4251-503"
- "microchip,mcp4251-104"
- "microchip,mcp4252-502"
- "microchip,mcp4252-103"
- "microchip,mcp4252-503"
- "microchip,mcp4252-104"
- "microchip,mcp4261-502"
- "microchip,mcp4261-103"
- "microchip,mcp4261-503"
- "microchip,mcp4261-104"
- "microchip,mcp4262-502"
- "microchip,mcp4262-103"
- "microchip,mcp4262-503"
- "microchip,mcp4262-104"
-
-Example:
-mcp4131: mcp4131@0 {
- compatible = "mcp4131-502";
- reg = <0>;
- spi-max-frequency = <500000>;
-};
diff --git a/dts/Bindings/iio/potentiometer/microchip,mcp41010.yaml b/dts/Bindings/iio/potentiometer/microchip,mcp41010.yaml
new file mode 100644
index 0000000000..567697d996
--- /dev/null
+++ b/dts/Bindings/iio/potentiometer/microchip,mcp41010.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/potentiometer/microchip,mcp41010.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MCP41010/41050/41100/42010/42050/42100 Digital Potentiometer
+
+maintainers:
+ - Chris Coffey <cmc@babblebit.net>
+
+description: |
+ Datasheet: https://ww1.microchip.com/downloads/en/devicedoc/11195c.pdf
+
+properties:
+ compatible:
+ enum:
+ - microchip,mcp41010
+ - microchip,mcp41050
+ - microchip,mcp41100
+ - microchip,mcp42010
+ - microchip,mcp42050
+ - microchip,mcp42100
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ potentiometer@0 {
+ compatible = "microchip,mcp41010";
+ reg = <0>;
+ spi-max-frequency = <500000>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/potentiometer/microchip,mcp4131.yaml b/dts/Bindings/iio/potentiometer/microchip,mcp4131.yaml
new file mode 100644
index 0000000000..945a2d644d
--- /dev/null
+++ b/dts/Bindings/iio/potentiometer/microchip,mcp4131.yaml
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/potentiometer/microchip,mcp4131.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MCP413X/414X/415X/416X/423X/424X/425X/426X Digital Potentiometer
+
+maintainers:
+ - Slawomir Stepien <sst@poczta.fm>
+
+properties:
+ compatible:
+ enum:
+ - microchip,mcp4131-103
+ - microchip,mcp4131-104
+ - microchip,mcp4131-502
+ - microchip,mcp4131-503
+ - microchip,mcp4132-103
+ - microchip,mcp4132-104
+ - microchip,mcp4132-502
+ - microchip,mcp4132-503
+ - microchip,mcp4141-103
+ - microchip,mcp4141-104
+ - microchip,mcp4141-502
+ - microchip,mcp4141-503
+ - microchip,mcp4142-103
+ - microchip,mcp4142-104
+ - microchip,mcp4142-502
+ - microchip,mcp4142-503
+ - microchip,mcp4151-103
+ - microchip,mcp4151-104
+ - microchip,mcp4151-502
+ - microchip,mcp4151-503
+ - microchip,mcp4152-103
+ - microchip,mcp4152-104
+ - microchip,mcp4152-502
+ - microchip,mcp4152-503
+ - microchip,mcp4161-103
+ - microchip,mcp4161-104
+ - microchip,mcp4161-502
+ - microchip,mcp4161-503
+ - microchip,mcp4162-103
+ - microchip,mcp4162-104
+ - microchip,mcp4162-502
+ - microchip,mcp4162-503
+ - microchip,mcp4231-103
+ - microchip,mcp4231-104
+ - microchip,mcp4231-502
+ - microchip,mcp4231-503
+ - microchip,mcp4232-103
+ - microchip,mcp4232-104
+ - microchip,mcp4232-502
+ - microchip,mcp4232-503
+ - microchip,mcp4241-103
+ - microchip,mcp4241-104
+ - microchip,mcp4241-502
+ - microchip,mcp4241-503
+ - microchip,mcp4242-103
+ - microchip,mcp4242-104
+ - microchip,mcp4242-502
+ - microchip,mcp4242-503
+ - microchip,mcp4251-103
+ - microchip,mcp4251-104
+ - microchip,mcp4251-502
+ - microchip,mcp4251-503
+ - microchip,mcp4252-103
+ - microchip,mcp4252-104
+ - microchip,mcp4252-502
+ - microchip,mcp4252-503
+ - microchip,mcp4261-103
+ - microchip,mcp4261-104
+ - microchip,mcp4261-502
+ - microchip,mcp4261-503
+ - microchip,mcp4262-103
+ - microchip,mcp4262-104
+ - microchip,mcp4262-502
+ - microchip,mcp4262-503
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ potentiometer@0 {
+ compatible = "mcp4131-502";
+ reg = <0>;
+ spi-max-frequency = <500000>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/potentiometer/microchip,mcp4531.yaml b/dts/Bindings/iio/potentiometer/microchip,mcp4531.yaml
new file mode 100644
index 0000000000..5c4b9b9181
--- /dev/null
+++ b/dts/Bindings/iio/potentiometer/microchip,mcp4531.yaml
@@ -0,0 +1,116 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/potentiometer/microchip,mcp4531.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip mcp4531 and similar potentiometers.
+
+maintainers:
+ - Peter Rosin <peda@axentia.se>
+
+description: |
+ Family of I2C digital potentiometer
+ Datasheets at:
+ * volatile https://ww1.microchip.com/downloads/en/DeviceDoc/22096b.pdf
+ * non-volatile https://ww1.microchip.com/downloads/en/DeviceDoc/22107B.pdf
+ Part numbers as follows: mcp4ABC-XXX where
+ A = 5 (1 wiper), 6 (2 wipers)
+ B = 3 (7-bit, volatile), 4 (7-bit, non-volatile),
+ 5 (8-bit, volatile), 6 (8-bit, non-volatile),
+ C: 1 (potentiometer), 2 (rheostat)
+ XXX = 502 (5 kOhms), 103 (10 kOhms), 503 (50 kOhms), 104 (100 kOhms)
+
+properties:
+ compatible:
+ enum:
+ # Ordering reflects part number + range, so 502 < 103 etc
+ - microchip,mcp4531-502
+ - microchip,mcp4531-103
+ - microchip,mcp4531-503
+ - microchip,mcp4531-104
+ - microchip,mcp4532-502
+ - microchip,mcp4532-103
+ - microchip,mcp4532-503
+ - microchip,mcp4532-104
+ - microchip,mcp4541-502
+ - microchip,mcp4541-103
+ - microchip,mcp4541-503
+ - microchip,mcp4541-104
+ - microchip,mcp4542-502
+ - microchip,mcp4542-103
+ - microchip,mcp4542-503
+ - microchip,mcp4542-104
+ - microchip,mcp4551-502
+ - microchip,mcp4551-103
+ - microchip,mcp4551-503
+ - microchip,mcp4551-104
+ - microchip,mcp4552-502
+ - microchip,mcp4552-103
+ - microchip,mcp4552-503
+ - microchip,mcp4552-104
+ - microchip,mcp4561-502
+ - microchip,mcp4561-103
+ - microchip,mcp4561-503
+ - microchip,mcp4561-104
+ - microchip,mcp4562-502
+ - microchip,mcp4562-103
+ - microchip,mcp4562-503
+ - microchip,mcp4562-104
+ - microchip,mcp4631-502
+ - microchip,mcp4631-103
+ - microchip,mcp4631-503
+ - microchip,mcp4631-104
+ - microchip,mcp4632-502
+ - microchip,mcp4632-103
+ - microchip,mcp4632-503
+ - microchip,mcp4632-104
+ - microchip,mcp4641-502
+ - microchip,mcp4641-103
+ - microchip,mcp4641-503
+ - microchip,mcp4641-104
+ - microchip,mcp4642-502
+ - microchip,mcp4642-103
+ - microchip,mcp4642-503
+ - microchip,mcp4642-104
+ - microchip,mcp4651-502
+ - microchip,mcp4651-103
+ - microchip,mcp4651-503
+ - microchip,mcp4651-104
+ - microchip,mcp4652-502
+ - microchip,mcp4652-103
+ - microchip,mcp4652-503
+ - microchip,mcp4652-104
+ - microchip,mcp4661-502
+ - microchip,mcp4661-103
+ - microchip,mcp4661-503
+ - microchip,mcp4661-104
+ - microchip,mcp4662-502
+ - microchip,mcp4662-103
+ - microchip,mcp4662-503
+ - microchip,mcp4662-104
+
+ reg:
+ maxItems: 1
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dpot: dpot@28 {
+ compatible = "microchip,mcp4651-104";
+ reg = <0x28>;
+ #io-channel-cells = <1>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/potentiostat/lmp91000.txt b/dts/Bindings/iio/potentiostat/lmp91000.txt
deleted file mode 100644
index f3ab02b0dd..0000000000
--- a/dts/Bindings/iio/potentiostat/lmp91000.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-* Texas Instruments LMP91000 series of potentiostats
-
-LMP91000: https://www.ti.com/lit/ds/symlink/lmp91000.pdf
-LMP91002: https://www.ti.com/lit/ds/symlink/lmp91002.pdf
-
-Required properties:
-
- - compatible: should be one of the following:
- "ti,lmp91000"
- "ti,lmp91002"
- - reg: the I2C address of the device
- - io-channels: the phandle of the iio provider
-
- - ti,external-tia-resistor: if the property ti,tia-gain-ohm is not defined this
- needs to be set to signal that an external resistor value is being used.
-
-Optional properties:
-
- - ti,tia-gain-ohm: ohm value of the internal resistor for the transimpedance
- amplifier. Must be 2750, 3500, 7000, 14000, 35000, 120000, or 350000 ohms.
-
- - ti,rload-ohm: ohm value of the internal resistor load applied to the gas
- sensor. Must be 10, 33, 50, or 100 (default) ohms.
-
-Example:
-
-lmp91000@48 {
- compatible = "ti,lmp91000";
- reg = <0x48>;
- ti,tia-gain-ohm = <7500>;
- ti,rload = <100>;
- io-channels = <&adc>;
-};
diff --git a/dts/Bindings/iio/potentiostat/ti,lmp91000.yaml b/dts/Bindings/iio/potentiostat/ti,lmp91000.yaml
new file mode 100644
index 0000000000..e4b5d890e8
--- /dev/null
+++ b/dts/Bindings/iio/potentiostat/ti,lmp91000.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/potentiostat/ti,lmp91000.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments LMP91000 series of potentiostats with I2C control
+
+maintainers:
+ - Matt Ranostay <matt.ranostay@konsulko.com>
+
+description: |
+ Typically used as a signal conditioner for chemical sensors.
+ LMP91000: https://www.ti.com/lit/ds/symlink/lmp91000.pdf
+ LMP91002: https://www.ti.com/lit/ds/symlink/lmp91002.pdf
+
+properties:
+ compatible:
+ enum:
+ - ti,lmp91000
+ - ti,lmp91002
+
+ reg:
+ maxItems: 1
+
+ io-channels:
+ maxItems: 1
+
+ ti,external-tia-resistor:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ If the property ti,tia-gain-ohm is not defined this needs to be set to
+ signal that an external resistor value is being used.
+
+ ti,tia-gain-ohm:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [2750, 3500, 7000, 14000, 35000, 120000, 350000]
+ description:
+ Internal resistor for the transimpedance amplifier.
+
+ ti,rload-ohm:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [10, 33, 50, 100]
+ description:
+ Internal resistor load applied to the gas sensor.
+ Default 100 Ohms.
+
+required:
+ - compatible
+ - reg
+ - io-channels
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ lmp91000@48 {
+ compatible = "ti,lmp91000";
+ reg = <0x48>;
+ ti,tia-gain-ohm = <7000>;
+ ti,rload-ohm = <100>;
+ io-channels = <&adc>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/pressure/hoperf,hp03.yaml b/dts/Bindings/iio/pressure/hoperf,hp03.yaml
new file mode 100644
index 0000000000..69a3759e23
--- /dev/null
+++ b/dts/Bindings/iio/pressure/hoperf,hp03.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/pressure/hoperf,hp03.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HopeRF HP03 digital pressure/temperature sensors
+
+maintainers:
+ - Marek Vasut <marex@denx.de>
+
+description: |
+ Digital pressure and temperature sensor with an I2C interface.
+
+properties:
+ compatible:
+ const: hoperf,hp03
+
+ reg:
+ maxItems: 1
+
+ xclr-gpios:
+ description:
+ The XCLR pin is a reset of the ADC in the chip, it must be pulled
+ HI before the conversion and readout of the value from the ADC
+ registers and pulled LO afterward.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pressure@77 {
+ compatible = "hoperf,hp03";
+ reg = <0x77>;
+ xclr-gpios = <&portc 0 0x0>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/pressure/hp03.txt b/dts/Bindings/iio/pressure/hp03.txt
deleted file mode 100644
index 831dbee7a5..0000000000
--- a/dts/Bindings/iio/pressure/hp03.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-HopeRF HP03 digital pressure/temperature sensors
-
-Required properties:
-- compatible: must be "hoperf,hp03"
-- xclr-gpio: must be device tree identifier of the XCLR pin.
- The XCLR pin is a reset of the ADC in the chip,
- it must be pulled HI before the conversion and
- readout of the value from the ADC registers and
- pulled LO afterward.
-
-Example:
-
-hp03@77 {
- compatible = "hoperf,hp03";
- reg = <0x77>;
- xclr-gpio = <&portc 0 0x0>;
-};
diff --git a/dts/Bindings/iio/pressure/meas,ms5611.yaml b/dts/Bindings/iio/pressure/meas,ms5611.yaml
new file mode 100644
index 0000000000..4f06707450
--- /dev/null
+++ b/dts/Bindings/iio/pressure/meas,ms5611.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/pressure/meas,ms5611.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Measurement Specialities ms5611 and similar pressure sensors
+
+maintainers:
+ - Tomasz Duszynski <tduszyns@gmail.com>
+
+description: |
+ Pressure sensors from MEAS Switzerland with SPI and I2C bus interfaces.
+
+properties:
+ compatible:
+ enum:
+ - meas,ms5607
+ - meas,ms5611
+
+ reg:
+ maxItems: 1
+
+ vdd-supply: true
+
+ spi-max-frequency:
+ maximum: 20000000
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pressure@77 {
+ compatible = "meas,ms5607";
+ reg = <0x77>;
+ vdd-supply = <&ldo_3v3_gnss>;
+ };
+ };
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pressure@0 {
+ compatible = "meas,ms5611";
+ reg = <0>;
+ vdd-supply = <&ldo_3v3_gnss>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/pressure/ms5611.txt b/dts/Bindings/iio/pressure/ms5611.txt
deleted file mode 100644
index 17bca866c0..0000000000
--- a/dts/Bindings/iio/pressure/ms5611.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-MEAS ms5611 family pressure sensors
-
-Pressure sensors from MEAS Switzerland with SPI and I2C bus interfaces.
-
-Required properties:
-- compatible: "meas,ms5611" or "meas,ms5607"
-- reg: the I2C address or SPI chip select the device will respond to
-
-Optional properties:
-- vdd-supply: an optional regulator that needs to be on to provide VDD
- power to the sensor.
-
-Example:
-
-ms5607@77 {
- compatible = "meas,ms5607";
- reg = <0x77>;
- vdd-supply = <&ldo_3v3_gnss>;
-};
diff --git a/dts/Bindings/iio/pressure/ms5637.txt b/dts/Bindings/iio/pressure/ms5637.txt
deleted file mode 100644
index 1f43ffa068..0000000000
--- a/dts/Bindings/iio/pressure/ms5637.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-* MS5637 - Measurement-Specialties MS5637, MS5805, MS5837 and MS8607 pressure & temperature sensor
-
-Required properties:
-
- -compatible: should be one of the following
- meas,ms5637
- meas,ms5805
- meas,ms5837
- meas,ms8607-temppressure
- -reg: I2C address of the sensor
-
-Example:
-
-ms5637@76 {
- compatible = "meas,ms5637";
- reg = <0x76>;
-};
diff --git a/dts/Bindings/iio/pressure/murata,zpa2326.yaml b/dts/Bindings/iio/pressure/murata,zpa2326.yaml
new file mode 100644
index 0000000000..d6103be034
--- /dev/null
+++ b/dts/Bindings/iio/pressure/murata,zpa2326.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/pressure/murata,zpa2326.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Murata ZPA2326 pressure sensor
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+description: |
+ Pressure sensor from Murata with SPI and I2C bus interfaces.
+
+
+properties:
+ compatible:
+ const: murata,zpa2326
+
+ reg:
+ maxItems: 1
+
+ vdd-supply: true
+ vref-supply: true
+
+ interrupts:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 1000000
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pressure@5c {
+ compatible = "murata,zpa2326";
+ reg = <0x5c>;
+ interrupt-parent = <&gpio>;
+ interrupts = <12>;
+ vdd-supply = <&ldo_1v8_gnss>;
+ };
+ };
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pressure@0 {
+ compatible = "murata,zpa2326";
+ reg = <0>;
+ spi-max-frequency = <500000>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/pressure/zpa2326.txt b/dts/Bindings/iio/pressure/zpa2326.txt
deleted file mode 100644
index a36ab3e0c3..0000000000
--- a/dts/Bindings/iio/pressure/zpa2326.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-Murata ZPA2326 pressure sensor
-
-Pressure sensor from Murata with SPI and I2C bus interfaces.
-
-Required properties:
-- compatible: "murata,zpa2326"
-- reg: the I2C address or SPI chip select the device will respond to
-
-Recommended properties for SPI bus usage:
-- spi-max-frequency: maximum SPI bus frequency as documented in
- Documentation/devicetree/bindings/spi/spi-bus.txt
-
-Optional properties:
-- vref-supply: an optional regulator that needs to be on to provide VREF
- power to the sensor
-- vdd-supply: an optional regulator that needs to be on to provide VDD
- power to the sensor
-- interrupts: interrupt mapping for IRQ as documented in
- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
-
-Example:
-
-zpa2326@5c {
- compatible = "murata,zpa2326";
- reg = <0x5c>;
- interrupt-parent = <&gpio>;
- interrupts = <12>;
- vdd-supply = <&ldo_1v8_gnss>;
-};
diff --git a/dts/Bindings/iio/proximity/ams,as3935.yaml b/dts/Bindings/iio/proximity/ams,as3935.yaml
new file mode 100644
index 0000000000..7fcba5d6d5
--- /dev/null
+++ b/dts/Bindings/iio/proximity/ams,as3935.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/proximity/ams,as3935.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Austrian Microsystems AS3935 Franklin lightning sensor
+
+maintainers:
+ - Matt Ranostay <matt.ranostay@konsulko.com>
+
+description:
+ This lightening distance sensor uses an I2C or SPI interface. The
+ binding currently only covers the SPI option.
+
+properties:
+ compatible:
+ const: ams,as3935
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 2000000
+
+ spi-cpha: true
+
+ interrupts:
+ maxItems: 1
+
+ ams,tuning-capacitor-pf:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Calibration tuning capacitor stepping value. This will require using
+ the calibration data from the manufacturer.
+ minimum: 0
+ maximum: 120
+
+ ams,nflwdth:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Set the noise and watchdog threshold register on startup. This will
+ need to set according to the noise from the MCU board, and possibly
+ the local environment. Refer to the datasheet for the threshold settings.
+
+required:
+ - compatible
+ - reg
+ - spi-cpha
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lightning@0 {
+ compatible = "ams,as3935";
+ reg = <0>;
+ spi-max-frequency = <400000>;
+ spi-cpha;
+ interrupt-parent = <&gpio1>;
+ interrupts = <16 1>;
+ ams,tuning-capacitor-pf = <80>;
+ ams,nflwdth = <0x44>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/proximity/as3935.txt b/dts/Bindings/iio/proximity/as3935.txt
deleted file mode 100644
index 849115585d..0000000000
--- a/dts/Bindings/iio/proximity/as3935.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-Austrian Microsystems AS3935 Franklin lightning sensor device driver
-
-Required properties:
- - compatible: must be "ams,as3935"
- - reg: SPI chip select number for the device
- - spi-max-frequency: specifies maximum SPI clock frequency
- - spi-cpha: SPI Mode 1. Refer to spi/spi-bus.txt for generic SPI
- slave node bindings.
- - interrupts : the sole interrupt generated by the device
-
- Refer to interrupt-controller/interrupts.txt for generic
- interrupt client node bindings.
-
-Optional properties:
- - ams,tuning-capacitor-pf: Calibration tuning capacitor stepping
- value 0 - 120pF. This will require using the calibration data from
- the manufacturer.
- - ams,nflwdth: Set the noise and watchdog threshold register on
- startup. This will need to set according to the noise from the
- MCU board, and possibly the local environment. Refer to the
- datasheet for the threshold settings.
-
-Example:
-
-as3935@0 {
- compatible = "ams,as3935";
- reg = <0>;
- spi-max-frequency = <400000>;
- spi-cpha;
- interrupt-parent = <&gpio1>;
- interrupts = <16 1>;
- ams,tuning-capacitor-pf = <80>;
- ams,nflwdth = <0x44>;
-};
diff --git a/dts/Bindings/iio/proximity/semtech,sx9310.yaml b/dts/Bindings/iio/proximity/semtech,sx9310.yaml
index 5739074d35..5de0bb2180 100644
--- a/dts/Bindings/iio/proximity/semtech,sx9310.yaml
+++ b/dts/Bindings/iio/proximity/semtech,sx9310.yaml
@@ -40,6 +40,63 @@ properties:
"#io-channel-cells":
const: 1
+ semtech,cs0-ground:
+ description: Indicates the CS0 sensor is connected to ground.
+ type: boolean
+
+ semtech,combined-sensors:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ List of which sensors are combined and represented by CS3.
+ Possible values are -
+ 3 - CS3 (internal)
+ 0 1 - CS0 + CS1
+ 1 2 - CS1 + CS2 (default)
+ 0 1 2 3 - CS0 + CS1 + CS2 + CS3
+ items:
+ enum: [ 0, 1, 2, 3 ]
+ minItems: 1
+ maxItems: 4
+
+ semtech,resolution:
+ description:
+ Capacitance measure resolution. Refer to datasheet for more details.
+ enum:
+ - coarsest
+ - very-coarse
+ - coarse
+ - medium-coarse
+ - medium
+ - fine
+ - very-fine
+ - finest
+
+ semtech,startup-sensor:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ default: 0
+ description:
+ Sensor used for start-up proximity detection. The combined
+ sensor is represented by the value 3. This is used for initial
+ compensation.
+
+ semtech,proxraw-strength:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 2, 4, 8]
+ default: 2
+ description:
+ PROXRAW filter strength. A value of 0 represents off, and other values
+ represent 1-1/N.
+
+ semtech,avg-pos-strength:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 16, 64, 128, 256, 512, 1024, 4294967295]
+ default: 16
+ description:
+ Average positive filter strength. A value of 0 represents off and
+ UINT_MAX (4294967295) represents infinite. Other values
+ represent 1-1/N.
+
required:
- compatible
- reg
@@ -61,5 +118,11 @@ examples:
vdd-supply = <&pp3300_a>;
svdd-supply = <&pp1800_prox>;
#io-channel-cells = <1>;
+ semtech,cs0-ground;
+ semtech,combined-sensors = <1 2 3>;
+ semtech,resolution = "fine";
+ semtech,startup-sensor = <1>;
+ semtech,proxraw-strength = <2>;
+ semtech,avg-pos-strength = <64>;
};
};
diff --git a/dts/Bindings/iio/proximity/semtech,sx9500.yaml b/dts/Bindings/iio/proximity/semtech,sx9500.yaml
new file mode 100644
index 0000000000..66dd015068
--- /dev/null
+++ b/dts/Bindings/iio/proximity/semtech,sx9500.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/proximity/semtech,sx9500.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Semtech's SX9500 capacitive proximity button device
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+properties:
+ compatible:
+ const: semtech,sx9500
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ reset-gpios:
+ description:
+ GPIO connected to the active low reset pin.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ proximity@28 {
+ compatible = "semtech,sx9500";
+ reg = <0x28>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/proximity/st,vl53l0x.yaml b/dts/Bindings/iio/proximity/st,vl53l0x.yaml
new file mode 100644
index 0000000000..656460d9d8
--- /dev/null
+++ b/dts/Bindings/iio/proximity/st,vl53l0x.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/proximity/st,vl53l0x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ST VL53L0X ToF ranging sensor
+
+maintainers:
+ - Song Qiang <songqiang1304521@gmail.com>
+
+properties:
+ compatible:
+ const: st,vl53l0x
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ proximity@29 {
+ compatible = "st,vl53l0x";
+ reg = <0x29>;
+ interrupt-parent = <&gpio>;
+ interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/proximity/sx9500.txt b/dts/Bindings/iio/proximity/sx9500.txt
deleted file mode 100644
index c54455db3b..0000000000
--- a/dts/Bindings/iio/proximity/sx9500.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-Semtech's SX9500 capacitive proximity button device driver
-
-Required properties:
- - compatible: must be "semtech,sx9500"
- - reg: i2c address where to find the device
- - interrupts : the sole interrupt generated by the device
-
- Refer to interrupt-controller/interrupts.txt for generic
- interrupt client node bindings.
-
-Optional properties:
- - reset-gpios: Reference to the GPIO connected to the device's active
- low reset pin.
-
-Example:
-
-sx9500@28 {
- compatible = "semtech,sx9500";
- reg = <0x28>;
- interrupt-parent = <&gpio2>;
- interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
-};
diff --git a/dts/Bindings/iio/proximity/vl53l0x.txt b/dts/Bindings/iio/proximity/vl53l0x.txt
deleted file mode 100644
index dfe00eb961..0000000000
--- a/dts/Bindings/iio/proximity/vl53l0x.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-ST VL53L0X ToF ranging sensor
-
-Required properties:
- - compatible: must be "st,vl53l0x"
- - reg: i2c address where to find the device
-
-Optional properties:
- - interrupts: Interrupt for notifying that new measurement is ready.
- If no interrupt is specified, polling is used.
-
-Example:
-
-vl53l0x@29 {
- compatible = "st,vl53l0x";
- reg = <0x29>;
- interrupt-parent = <&gpio>;
- interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
-};
diff --git a/dts/Bindings/iio/resolver/ad2s90.txt b/dts/Bindings/iio/resolver/ad2s90.txt
deleted file mode 100644
index 477d41fa64..0000000000
--- a/dts/Bindings/iio/resolver/ad2s90.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-Analog Devices AD2S90 Resolver-to-Digital Converter
-
-https://www.analog.com/en/products/ad2s90.html
-
-Required properties:
- - compatible: should be "adi,ad2s90"
- - reg: SPI chip select number for the device
- - spi-max-frequency: set maximum clock frequency, must be 830000
- - spi-cpol and spi-cpha:
- Either SPI mode (0,0) or (1,1) must be used, so specify none or both of
- spi-cpha, spi-cpol.
-
-See for more details:
- Documentation/devicetree/bindings/spi/spi-bus.txt
-
-Note about max frequency:
- Chip's max frequency, as specified in its datasheet, is 2Mhz. But a 600ns
- delay is expected between the application of a logic LO to CS and the
- application of SCLK, as also specified. And since the delay is not
- implemented in the spi code, to satisfy it, SCLK's period should be at most
- 2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which gives
- roughly 830000Hz.
-
-Example:
-resolver@0 {
- compatible = "adi,ad2s90";
- reg = <0>;
- spi-max-frequency = <830000>;
- spi-cpol;
- spi-cpha;
-};
diff --git a/dts/Bindings/iio/resolver/adi,ad2s90.yaml b/dts/Bindings/iio/resolver/adi,ad2s90.yaml
new file mode 100644
index 0000000000..81e4bdfc17
--- /dev/null
+++ b/dts/Bindings/iio/resolver/adi,ad2s90.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/resolver/adi,ad2s90.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD2S90 Resolver-to-Digital Converter
+
+maintainers:
+ - Matheus Tavares <matheus.bernardino@usp.br>
+
+description: |
+ Datasheet: https://www.analog.com/en/products/ad2s90.html
+
+properties:
+ compatible:
+ const: adi,ad2s90
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 830000
+ description: |
+ Chip's max frequency, as specified in its datasheet, is 2Mhz. But a 600ns
+ delay is expected between the application of a logic LO to CS and the
+ application of SCLK, as also specified. And since the delay is not
+ implemented in the spi code, to satisfy it, SCLK's period should be at
+ most 2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which gives
+ roughly 830000Hz.
+
+ spi-cpol: true
+
+ spi-cpha: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+dependencies:
+ spi-cpol: [ spi-cpha ]
+ spi-cpha: [ spi-cpol ]
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ resolver@0 {
+ compatible = "adi,ad2s90";
+ reg = <0>;
+ spi-max-frequency = <830000>;
+ spi-cpol;
+ spi-cpha;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/samsung,sensorhub-rinato.yaml b/dts/Bindings/iio/samsung,sensorhub-rinato.yaml
new file mode 100644
index 0000000000..a88b3b14d6
--- /dev/null
+++ b/dts/Bindings/iio/samsung,sensorhub-rinato.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/samsung,sensorhub-rinato.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Sensorhub driver
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+description: |
+ Sensorhub is a MCU which manages several sensors and also plays the role
+ of a virtual sensor device.
+
+properties:
+ compatible:
+ enum:
+ - samsung,sensorhub-rinato
+ - samsung,sensorhub-thermostat
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ ap-mcu-gpios:
+ maxItems: 1
+ description:
+ Application Processor to sensorhub line - used during communication
+
+ mcu-ap-gpios:
+ maxItems: 1
+ description:
+ Sensorhub to Application Processor - used during communication
+
+ mcu-reset-gpios:
+ maxItems: 1
+ description:
+ Reset the sensorhub.
+
+ spi-max-frequency: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - ap-mcu-gpios
+ - mcu-ap-gpios
+ - mcu-reset-gpios
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sensorhub@0 {
+ compatible = "samsung,sensorhub-rinato";
+ reg = <0>;
+ spi-max-frequency = <5000000>;
+ interrupt-parent = <&gpx0>;
+ interrupts = <2 0>;
+ ap-mcu-gpios = <&gpx0 0 0>;
+ mcu-ap-gpios = <&gpx0 4 0>;
+ mcu-reset-gpios = <&gpx0 5 0>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/sensorhub.txt b/dts/Bindings/iio/sensorhub.txt
deleted file mode 100644
index b6ac0457d4..0000000000
--- a/dts/Bindings/iio/sensorhub.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-Samsung Sensorhub driver
-
-Sensorhub is a MCU which manages several sensors and also plays the role
-of a virtual sensor device.
-
-Required properties:
-- compatible: "samsung,sensorhub-rinato" or "samsung,sensorhub-thermostat"
-- spi-max-frequency: max SPI clock frequency
-- interrupts: communication interrupt
-- ap-mcu-gpios: [out] ap to sensorhub line - used during communication
-- mcu-ap-gpios: [in] sensorhub to ap - used during communication
-- mcu-reset-gpios: [out] sensorhub reset
-
-Example:
-
- shub_spi: shub {
- compatible = "samsung,sensorhub-rinato";
- spi-max-frequency = <5000000>;
- interrupt-parent = <&gpx0>;
- interrupts = <2 0>;
- ap-mcu-gpios = <&gpx0 0 0>;
- mcu-ap-gpios = <&gpx0 4 0>;
- mcu-reset-gpios = <&gpx0 5 0>;
- };
diff --git a/dts/Bindings/iio/st,st-sensors.yaml b/dts/Bindings/iio/st,st-sensors.yaml
new file mode 100644
index 0000000000..db291a9390
--- /dev/null
+++ b/dts/Bindings/iio/st,st-sensors.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/st,st-sensors.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics MEMS sensors
+
+description: |
+ Note that whilst this covers many STMicro MEMs sensors, some more complex
+ IMUs need their own bindings.
+ The STMicroelectronics sensor devices are pretty straight-forward I2C or
+ SPI devices, all sharing the same device tree descriptions no matter what
+ type of sensor it is.
+
+maintainers:
+ - Denis Ciocca <denis.ciocca@st.com>
+
+properties:
+ compatible:
+ description: |
+ Some values are deprecated.
+ st,lis3lv02d (deprecated, use st,lis3lv02dl-accel)
+ st,lis302dl-spi (deprecated, use st,lis3lv02dl-accel)
+ enum:
+ # Accelerometers
+ - st,lis3lv02d
+ - st,lis302dl-spi
+ - st,lis3lv02dl-accel
+ - st,lsm303dlh-accel
+ - st,lsm303dlhc-accel
+ - st,lis3dh-accel
+ - st,lsm330d-accel
+ - st,lsm330dl-accel
+ - st,lsm330dlc-accel
+ - st,lis331dl-accel
+ - st,lis331dlh-accel
+ - st,lsm303dl-accel
+ - st,lsm303dlm-accel
+ - st,lsm330-accel
+ - st,lsm303agr-accel
+ - st,lis2dh12-accel
+ - st,h3lis331dl-accel
+ - st,lng2dm-accel
+ - st,lis3l02dq
+ - st,lis2dw12
+ - st,lis3dhh
+ - st,lis3de
+ - st,lis2de12
+ - st,lis2hh12
+ # Gyroscopes
+ - st,l3g4200d-gyro
+ - st,lsm330d-gyro
+ - st,lsm330dl-gyro
+ - st,lsm330dlc-gyro
+ - st,l3gd20-gyro
+ - st,l3gd20h-gyro
+ - st,l3g4is-gyro
+ - st,lsm330-gyro
+ - st,lsm9ds0-gyro
+ # Magnetometers
+ - st,lsm303agr-magn
+ - st,lsm303dlh-magn
+ - st,lsm303dlhc-magn
+ - st,lsm303dlm-magn
+ - st,lis3mdl-magn
+ - st,lis2mdl
+ - st,lsm9ds1-magn
+ # Pressure sensors
+ - st,lps001wp-press
+ - st,lps25h-press
+ - st,lps331ap-press
+ - st,lps22hb-press
+ - st,lps33hw
+ - st,lps35hw
+ - st,lps22hh
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+
+ vdd-supply: true
+ vddio-supply: true
+
+ st,drdy-int-pin:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Some sensors have multiple possible pins via which they can provide
+ a data ready interrupt. This selects which one.
+ enum:
+ - 1
+ - 2
+
+ drive-open-drain:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: |
+ The interrupt/data ready line will be configured as open drain, which
+ is useful if several sensors share the same interrupt line.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ accelerometer@1d {
+ compatible = "st,lis3lv02dl-accel";
+ reg = <0x1d>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <18 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-0 = <&lis3lv02dl_nhk_mode>;
+ pinctrl-names = "default";
+ };
+ };
+...
diff --git a/dts/Bindings/iio/st-sensors.txt b/dts/Bindings/iio/st-sensors.txt
deleted file mode 100644
index 3213599c50..0000000000
--- a/dts/Bindings/iio/st-sensors.txt
+++ /dev/null
@@ -1,82 +0,0 @@
-STMicroelectronics MEMS sensors
-
-The STMicroelectronics sensor devices are pretty straight-forward I2C or
-SPI devices, all sharing the same device tree descriptions no matter what
-type of sensor it is.
-
-Required properties:
-- compatible: see the list of valid compatible strings below
-- reg: the I2C or SPI address the device will respond to
-
-Optional properties:
-- vdd-supply: an optional regulator that needs to be on to provide VDD
- power to the sensor.
-- vddio-supply: an optional regulator that needs to be on to provide the
- VDD IO power to the sensor.
-- st,drdy-int-pin: the pin on the package that will be used to signal
- "data ready" (valid values: 1 or 2). This property is not configurable
- on all sensors.
-- drive-open-drain: the interrupt/data ready line will be configured
- as open drain, which is useful if several sensors share the same
- interrupt line. (This binding is taken from pinctrl/pinctrl-bindings.txt)
- This is a boolean property.
-
-Sensors may also have applicable pin control settings, those use the
-standard bindings from pinctrl/pinctrl-bindings.txt.
-
-Valid compatible strings:
-
-Accelerometers:
-- st,lis3lv02d (deprecated, use st,lis3lv02dl-accel)
-- st,lis302dl-spi (deprecated, use st,lis3lv02dl-accel)
-- st,lis3lv02dl-accel
-- st,lsm303dlh-accel
-- st,lsm303dlhc-accel
-- st,lis3dh-accel
-- st,lsm330d-accel
-- st,lsm330dl-accel
-- st,lsm330dlc-accel
-- st,lis331dl-accel
-- st,lis331dlh-accel
-- st,lsm303dl-accel
-- st,lsm303dlm-accel
-- st,lsm330-accel
-- st,lsm303agr-accel
-- st,lis2dh12-accel
-- st,h3lis331dl-accel
-- st,lng2dm-accel
-- st,lis3l02dq
-- st,lis2dw12
-- st,lis3dhh
-- st,lis3de
-- st,lis2de12
-- st,lis2hh12
-
-Gyroscopes:
-- st,l3g4200d-gyro
-- st,lsm330d-gyro
-- st,lsm330dl-gyro
-- st,lsm330dlc-gyro
-- st,l3gd20-gyro
-- st,l3gd20h-gyro
-- st,l3g4is-gyro
-- st,lsm330-gyro
-- st,lsm9ds0-gyro
-
-Magnetometers:
-- st,lsm303agr-magn
-- st,lsm303dlh-magn
-- st,lsm303dlhc-magn
-- st,lsm303dlm-magn
-- st,lis3mdl-magn
-- st,lis2mdl
-- st,lsm9ds1-magn
-
-Pressure sensors:
-- st,lps001wp-press
-- st,lps25h-press
-- st,lps331ap-press
-- st,lps22hb-press
-- st,lps33hw
-- st,lps35hw
-- st,lps22hh
diff --git a/dts/Bindings/iio/temperature/max31856.txt b/dts/Bindings/iio/temperature/max31856.txt
deleted file mode 100644
index 06ab43bb4d..0000000000
--- a/dts/Bindings/iio/temperature/max31856.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-Maxim MAX31856 thermocouple support
-
-https://datasheets.maximintegrated.com/en/ds/MAX31856.pdf
-
-Optional property:
- - thermocouple-type: Type of thermocouple (THERMOCOUPLE_TYPE_K if
- omitted). Supported types are B, E, J, K, N, R, S, T.
-
-Required properties:
- - compatible: must be "maxim,max31856"
- - reg: SPI chip select number for the device
- - spi-max-frequency: As per datasheet max. supported freq is 5000000
- - spi-cpha: must be defined for max31856 to enable SPI mode 1
-
- Refer to spi/spi-bus.txt for generic SPI slave bindings.
-
- Example:
- temp-sensor@0 {
- compatible = "maxim,max31856";
- reg = <0>;
- spi-max-frequency = <5000000>;
- spi-cpha;
- thermocouple-type = <THERMOCOUPLE_TYPE_K>;
- };
diff --git a/dts/Bindings/iio/temperature/maxim,max31855k.yaml b/dts/Bindings/iio/temperature/maxim,max31855k.yaml
new file mode 100644
index 0000000000..9969bac66a
--- /dev/null
+++ b/dts/Bindings/iio/temperature/maxim,max31855k.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/temperature/maxim,max31855k.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX31855 and similar thermocouples
+
+maintainers:
+ - Matt Ranostay <matt.ranostay@konsulko.com>
+
+description: |
+ https://datasheets.maximintegrated.com/en/ds/MAX6675.pdf
+ https://datasheets.maximintegrated.com/en/ds/MAX31855.pdf
+
+properties:
+ compatible:
+ description:
+ The generic maxim,max31855 compatible is deprecated in favour of
+ the thermocouple type specific variants.
+ enum:
+ - maxim,max6675
+ - maxim,max31855
+ - maxim,max31855k
+ - maxim,max31855j
+ - maxim,max31855n
+ - maxim,max31855s
+ - maxim,max31855t
+ - maxim,max31855e
+ - maxim,max31855r
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency: true
+ spi-cpha: true
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - maxim,max6675
+ then:
+ required:
+ - spi-cpha
+ else:
+ properties:
+ spi-cpha: false
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ temp-sensor@0 {
+ compatible = "maxim,max31855k";
+ reg = <0>;
+ spi-max-frequency = <4300000>;
+ };
+ temp-sensor@1 {
+ compatible = "maxim,max6675";
+ reg = <1>;
+ spi-max-frequency = <4300000>;
+ spi-cpha;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/temperature/maxim,max31856.yaml b/dts/Bindings/iio/temperature/maxim,max31856.yaml
new file mode 100644
index 0000000000..873b347666
--- /dev/null
+++ b/dts/Bindings/iio/temperature/maxim,max31856.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/temperature/maxim,max31856.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX31856 thermocouple support
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+description: |
+ https://datasheets.maximintegrated.com/en/ds/MAX31856.pdf
+
+properties:
+ compatible:
+ const: maxim,max31856
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency: true
+ spi-cpha: true
+
+ thermocouple-type:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Type of thermocouple (THERMOCOUPLE_TYPE_K if omitted).
+ Use defines in dt-bindings/iio/temperature/thermocouple.h.
+ Supported types are B, E, J, K, N, R, S, T.
+
+required:
+ - compatible
+ - reg
+ - spi-cpha
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/iio/temperature/thermocouple.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ temp-sensor@0 {
+ compatible = "maxim,max31856";
+ reg = <0>;
+ spi-max-frequency = <5000000>;
+ spi-cpha;
+ thermocouple-type = <THERMOCOUPLE_TYPE_K>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/temperature/maxim_thermocouple.txt b/dts/Bindings/iio/temperature/maxim_thermocouple.txt
deleted file mode 100644
index bb85cd0e03..0000000000
--- a/dts/Bindings/iio/temperature/maxim_thermocouple.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-Maxim thermocouple support
-
-* https://datasheets.maximintegrated.com/en/ds/MAX6675.pdf
-* https://datasheets.maximintegrated.com/en/ds/MAX31855.pdf
-
-Required properties:
-
- - compatible: must be "maxim,max6675" or one of the following:
- "maxim,max31855k", "maxim,max31855j", "maxim,max31855n",
- "maxim,max31855s", "maxim,max31855t", "maxim,max31855e",
- "maxim,max31855r"; the generic "max,max31855" is deprecated.
- - reg: SPI chip select number for the device
- - spi-max-frequency: must be 4300000
- - spi-cpha: must be defined for max6675 to enable SPI mode 1
-
- Refer to spi/spi-bus.txt for generic SPI slave bindings.
-
-Example:
-
- max31855@0 {
- compatible = "maxim,max31855k";
- reg = <0>;
- spi-max-frequency = <4300000>;
- };
diff --git a/dts/Bindings/iio/temperature/melexis,mlx90614.yaml b/dts/Bindings/iio/temperature/melexis,mlx90614.yaml
new file mode 100644
index 0000000000..d6965a0c1c
--- /dev/null
+++ b/dts/Bindings/iio/temperature/melexis,mlx90614.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/temperature/melexis,mlx90614.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Melexis MLX90614 contactless IR temperature sensor
+
+maintainers:
+ - Peter Meerwald <pmeerw@pmeerw.net>
+ - Crt Mori <cmo@melexis.com>
+
+description: |
+ http://melexis.com/Infrared-Thermometer-Sensors/Infrared-Thermometer-Sensors/MLX90614-615.aspx
+
+properties:
+ compatible:
+ const: melexis,mlx90614
+
+ reg:
+ maxItems: 1
+
+ wakeup-gpios:
+ description:
+ GPIO connected to the SDA line to hold low in order to wake up the
+ device. In normal operation, the GPIO is set as input and will
+ not interfere in I2C communication. There is no need for a GPIO
+ driving the SCL line. If no GPIO is given, power management is disabled.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ temp-sensor@5a {
+ compatible = "melexis,mlx90614";
+ reg = <0x5a>;
+ wakeup-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/temperature/melexis,mlx90632.yaml b/dts/Bindings/iio/temperature/melexis,mlx90632.yaml
new file mode 100644
index 0000000000..b547ddcd54
--- /dev/null
+++ b/dts/Bindings/iio/temperature/melexis,mlx90632.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/temperature/melexis,mlx90632.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Melexis MLX90632 contactless Infra Red temperature sensor
+
+maintainers:
+ - Crt Mori <cmo@melexis.com>
+
+description: |
+ https://www.melexis.com/en/documents/documentation/datasheets/datasheet-mlx90632
+
+ There are various applications for the Infra Red contactless temperature
+ sensor and MLX90632 is most suitable for consumer applications where
+ measured object temperature is in range between -20 to 200 degrees
+ Celsius with relative error of measurement below 1 degree Celsius in
+ object temperature range for industrial applications. Since it can
+ operate and measure ambient temperature in range of -20 to 85 degrees
+ Celsius it is suitable also for outdoor use.
+
+ Be aware that electronics surrounding the sensor can increase ambient
+ temperature. MLX90632 can be calibrated to reduce the housing effect via
+ already existing EEPROM parameters.
+
+ Since measured object emissivity effects Infra Red energy emitted,
+ emissivity should be set before requesting the object temperature.
+
+properties:
+ compatible:
+ const: melexis,mlx90632
+
+ reg:
+ maxItems: 1
+ description: Default is 0x3a, but can be reprogrammed.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ temp-sensor@3a {
+ compatible = "melexis,mlx90632";
+ reg = <0x3a>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/temperature/mlx90614.txt b/dts/Bindings/iio/temperature/mlx90614.txt
deleted file mode 100644
index 9be57b0360..0000000000
--- a/dts/Bindings/iio/temperature/mlx90614.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-* Melexis MLX90614 contactless IR temperature sensor
-
-http://melexis.com/Infrared-Thermometer-Sensors/Infrared-Thermometer-Sensors/MLX90614-615.aspx
-
-Required properties:
-
- - compatible: should be "melexis,mlx90614"
- - reg: the I2C address of the sensor
-
-Optional properties:
-
- - wakeup-gpios: device tree identifier of the GPIO connected to the SDA line
- to hold low in order to wake up the device. In normal operation, the
- GPIO is set as input and will not interfere in I2C communication. There
- is no need for a GPIO driving the SCL line. If no GPIO is given, power
- management is disabled.
-
-Example:
-
-mlx90614@5a {
- compatible = "melexis,mlx90614";
- reg = <0x5a>;
- wakeup-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
-};
diff --git a/dts/Bindings/iio/temperature/mlx90632.txt b/dts/Bindings/iio/temperature/mlx90632.txt
deleted file mode 100644
index 0b05812001..0000000000
--- a/dts/Bindings/iio/temperature/mlx90632.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-* Melexis MLX90632 contactless Infra Red temperature sensor
-
-Link to datasheet: https://www.melexis.com/en/documents/documentation/datasheets/datasheet-mlx90632
-
-There are various applications for the Infra Red contactless temperature sensor
-and MLX90632 is most suitable for consumer applications where measured object
-temperature is in range between -20 to 200 degrees Celsius with relative error
-of measurement below 1 degree Celsius in object temperature range for
-industrial applications. Since it can operate and measure ambient temperature
-in range of -20 to 85 degrees Celsius it is suitable also for outdoor use.
-
-Be aware that electronics surrounding the sensor can increase ambient
-temperature. MLX90632 can be calibrated to reduce the housing effect via
-already existing EEPROM parameters.
-
-Since measured object emissivity effects Infra Red energy emitted, emissivity
-should be set before requesting the object temperature.
-
-Required properties:
- - compatible: should be "melexis,mlx90632"
- - reg: the I2C address of the sensor (default 0x3a)
-
-Example:
-
-mlx90632@3a {
- compatible = "melexis,mlx90632";
- reg = <0x3a>;
-};
diff --git a/dts/Bindings/iio/temperature/temperature-bindings.txt b/dts/Bindings/iio/temperature/temperature-bindings.txt
deleted file mode 100644
index 8f339cab74..0000000000
--- a/dts/Bindings/iio/temperature/temperature-bindings.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-If the temperature sensor device can be configured to use some specific
-thermocouple type, you can use the defined types provided in the file
-"include/dt-bindings/iio/temperature/thermocouple.h".
-
-Property:
-thermocouple-type: A single cell representing the type of the thermocouple
- used by the device.
diff --git a/dts/Bindings/iio/temperature/ti,tmp007.yaml b/dts/Bindings/iio/temperature/ti,tmp007.yaml
new file mode 100644
index 0000000000..3c2b7189fa
--- /dev/null
+++ b/dts/Bindings/iio/temperature/ti,tmp007.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/temperature/ti,tmp007.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: IR thermopile sensor with integrated math engine
+
+maintainers:
+ - Manivannan Sadhasivam <manivannanece23@gmail.com>
+
+description: |
+ http://www.ti.com/lit/ds/symlink/tmp007.pdf
+
+properties:
+ compatible:
+ const: ti,tmp007
+
+ reg:
+ description: |
+ The I2C address of the sensor (changeable via ADR pins)
+ ------------------------------
+ |ADR1 | ADR0 | Device Address|
+ ------------------------------
+ 0 0 0x40
+ 0 1 0x41
+ 0 SDA 0x42
+ 0 SCL 0x43
+ 1 0 0x44
+ 1 1 0x45
+ 1 SDA 0x46
+ 1 SCL 0x47
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ temp-sensor@40 {
+ compatible = "ti,tmp007";
+ reg = <0x40>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <5 0x08>;
+ };
+ };
+...
diff --git a/dts/Bindings/iio/temperature/tmp007.txt b/dts/Bindings/iio/temperature/tmp007.txt
deleted file mode 100644
index da0af234a3..0000000000
--- a/dts/Bindings/iio/temperature/tmp007.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-* TI TMP007 - IR thermopile sensor with integrated math engine
-
-Link to datasheet: http://www.ti.com/lit/ds/symlink/tmp007.pdf
-
-Required properties:
-
- - compatible: should be "ti,tmp007"
- - reg: the I2C address of the sensor (changeable via ADR pins)
- ------------------------------
- |ADR1 | ADR0 | Device Address|
- ------------------------------
- 0 0 0x40
- 0 1 0x41
- 0 SDA 0x42
- 0 SCL 0x43
- 1 0 0x44
- 1 1 0x45
- 1 SDA 0x46
- 1 SCL 0x47
-
-Optional properties:
-
- - interrupts: interrupt mapping for GPIO IRQ (level active low)
-
-Example:
-
-tmp007@40 {
- compatible = "ti,tmp007";
- reg = <0x40>;
- interrupt-parent = <&gpio0>;
- interrupts = <5 0x08>;
-};
-
diff --git a/dts/Bindings/iio/temperature/tsys01.txt b/dts/Bindings/iio/temperature/tsys01.txt
deleted file mode 100644
index 0d5cc5595d..0000000000
--- a/dts/Bindings/iio/temperature/tsys01.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-* TSYS01 - Measurement Specialties temperature sensor
-
-Required properties:
-
- - compatible: should be "meas,tsys01"
- - reg: I2C address of the sensor (changeable via CSB pin)
-
- ------------------------
- | CSB | Device Address |
- ------------------------
- 1 0x76
- 0 0x77
-
-Example:
-
-tsys01@76 {
- compatible = "meas,tsys01";
- reg = <0x76>;
-};
diff --git a/dts/Bindings/input/ariel-pwrbutton.yaml b/dts/Bindings/input/ariel-pwrbutton.yaml
new file mode 100644
index 0000000000..b4ad829d73
--- /dev/null
+++ b/dts/Bindings/input/ariel-pwrbutton.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/ariel-pwrbutton.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Dell Wyse 3020 a.k.a. "Ariel" Power Button
+
+maintainers:
+ - Lubomir Rintel <lkundrak@v3.sk>
+
+description: |
+ The ENE Embedded Controller on the Ariel board has an interface to the
+ SPI bus that is capable of sending keyboard and mouse data. A single
+ power button is attached to it. This binding describes this
+ configuration.
+
+allOf:
+ - $ref: input.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: dell,wyse-ariel-ec-input
+ - const: ene,kb3930-input
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ spi-max-frequency: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-button@0 {
+ compatible = "dell,wyse-ariel-ec-input", "ene,kb3930-input";
+ reg = <0>;
+ interrupt-parent = <&gpio>;
+ interrupts = <60 IRQ_TYPE_EDGE_RISING>;
+ spi-max-frequency = <33000000>;
+ };
+ };
diff --git a/dts/Bindings/input/atmel,maxtouch.txt b/dts/Bindings/input/atmel,maxtouch.txt
deleted file mode 100644
index c88919480d..0000000000
--- a/dts/Bindings/input/atmel,maxtouch.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-Atmel maXTouch touchscreen/touchpad
-
-Required properties:
-- compatible:
- atmel,maxtouch
-
- The following compatibles have been used in various products but are
- deprecated:
- atmel,qt602240_ts
- atmel,atmel_mxt_ts
- atmel,atmel_mxt_tp
- atmel,mXT224
-
-- reg: The I2C address of the device
-
-- interrupts: The sink for the touchpad's IRQ output
- See ../interrupt-controller/interrupts.txt
-
-Optional properties for main touchpad device:
-
-- linux,gpio-keymap: When enabled, the SPT_GPIOPWN_T19 object sends messages
- on GPIO bit changes. An array of up to 8 entries can be provided
- indicating the Linux keycode mapped to each bit of the status byte,
- starting at the LSB. Linux keycodes are defined in
- <dt-bindings/input/input.h>.
-
- Note: the numbering of the GPIOs and the bit they start at varies between
- maXTouch devices. You must either refer to the documentation, or
- experiment to determine which bit corresponds to which input. Use
- KEY_RESERVED for unused padding values.
-
-- reset-gpios: GPIO specifier for the touchscreen's reset pin (active low)
-
-Example:
-
- touch@4b {
- compatible = "atmel,maxtouch";
- reg = <0x4b>;
- interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_LOW>;
- };
diff --git a/dts/Bindings/input/atmel,maxtouch.yaml b/dts/Bindings/input/atmel,maxtouch.yaml
new file mode 100644
index 0000000000..8c6418f76e
--- /dev/null
+++ b/dts/Bindings/input/atmel,maxtouch.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/atmel,maxtouch.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Atmel maXTouch touchscreen/touchpad
+
+maintainers:
+ - Nick Dyer <nick@shmanahar.org>
+ - Linus Walleij <linus.walleij@linaro.org>
+
+description: |
+ Atmel maXTouch touchscreen or touchpads such as the mXT244
+ and similar devices.
+
+properties:
+ compatible:
+ const: atmel,maxtouch
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ vdda-supply:
+ description:
+ Optional regulator for the AVDD analog voltage.
+
+ vdd-supply:
+ description:
+ Optional regulator for the VDD digital voltage.
+
+ reset-gpios:
+ maxItems: 1
+ description:
+ Optional GPIO specifier for the touchscreen's reset pin
+ (active low). The line must be flagged with
+ GPIO_ACTIVE_LOW.
+
+ linux,gpio-keymap:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ When enabled, the SPT_GPIOPWN_T19 object sends messages
+ on GPIO bit changes. An array of up to 8 entries can be provided
+ indicating the Linux keycode mapped to each bit of the status byte,
+ starting at the LSB. Linux keycodes are defined in
+ <dt-bindings/input/input.h>.
+
+ Note: the numbering of the GPIOs and the bit they start at varies
+ between maXTouch devices. You must either refer to the documentation,
+ or experiment to determine which bit corresponds to which input. Use
+ KEY_RESERVED for unused padding values.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ reg = <0x4a>;
+ interrupt-parent = <&gpio>;
+ interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+ vdda-supply = <&ab8500_ldo_aux2_reg>;
+ vdd-supply = <&ab8500_ldo_aux5_reg>;
+ };
+ };
+
+...
diff --git a/dts/Bindings/input/cypress,tm2-touchkey.txt b/dts/Bindings/input/cypress,tm2-touchkey.txt
deleted file mode 100644
index 921172f689..0000000000
--- a/dts/Bindings/input/cypress,tm2-touchkey.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-Samsung tm2-touchkey
-
-Required properties:
-- compatible:
- * "cypress,tm2-touchkey" - for the touchkey found on the tm2 board
- * "cypress,midas-touchkey" - for the touchkey found on midas boards
- * "cypress,aries-touchkey" - for the touchkey found on aries boards
- * "coreriver,tc360-touchkey" - for the Coreriver TouchCore 360 touchkey
-- reg: I2C address of the chip.
-- interrupts: interrupt to which the chip is connected (see interrupt
- binding[0]).
-- vcc-supply : internal regulator output. 1.8V
-- vdd-supply : power supply for IC 3.3V
-
-Optional properties:
-- linux,keycodes: array of keycodes (max 4), default KEY_PHONE and KEY_BACK
-
-[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
-
-Example:
- &i2c0 {
- /* ... */
-
- touchkey@20 {
- compatible = "cypress,tm2-touchkey";
- reg = <0x20>;
- interrupt-parent = <&gpa3>;
- interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
- vcc-supply=<&ldo32_reg>;
- vdd-supply=<&ldo33_reg>;
- linux,keycodes = <KEY_PHONE KEY_BACK>;
- };
- };
diff --git a/dts/Bindings/input/cypress,tm2-touchkey.yaml b/dts/Bindings/input/cypress,tm2-touchkey.yaml
new file mode 100644
index 0000000000..52dca8b640
--- /dev/null
+++ b/dts/Bindings/input/cypress,tm2-touchkey.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/cypress,tm2-touchkey.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung TM2 touch key controller
+
+maintainers:
+ - Stephan Gerhold <stephan@gerhold.net>
+
+description: |
+ Touch key controllers similar to the TM2 can be found in a wide range of
+ Samsung devices. They are implemented using many different MCUs, but use
+ a similar I2C protocol.
+
+allOf:
+ - $ref: input.yaml#
+
+properties:
+ compatible:
+ enum:
+ - cypress,tm2-touchkey
+ - cypress,midas-touchkey
+ - cypress,aries-touchkey
+ - coreriver,tc360-touchkey
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ vdd-supply:
+ description: Optional regulator for LED voltage, 3.3V.
+
+ vcc-supply:
+ description: Optional regulator for MCU, 1.8V-3.3V (depending on MCU).
+
+ vddio-supply:
+ description: |
+ Optional regulator that provides digital I/O voltage,
+ e.g. for pulling up the interrupt line or the I2C pins.
+
+ linux,keycodes:
+ minItems: 1
+ maxItems: 4
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/input/input.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchkey@20 {
+ compatible = "cypress,tm2-touchkey";
+ reg = <0x20>;
+ interrupt-parent = <&gpa3>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ vcc-supply = <&ldo32_reg>;
+ vdd-supply = <&ldo33_reg>;
+ linux,keycodes = <KEY_MENU KEY_BACK>;
+ };
+ };
diff --git a/dts/Bindings/input/dlg,da7280.txt b/dts/Bindings/input/dlg,da7280.txt
new file mode 100644
index 0000000000..96ee5d50e1
--- /dev/null
+++ b/dts/Bindings/input/dlg,da7280.txt
@@ -0,0 +1,108 @@
+Dialog Semiconductor DA7280 Haptics bindings
+
+Required properties:
+- compatible: Should be "dlg,da7280".
+- reg: Specifies the I2C slave address.
+
+- interrupt-parent : Specifies the phandle of the interrupt controller to
+ which the IRQs from DA7280 are delivered to.
+
+- dlg,actuator-type: Set Actuator type. it should be one of:
+ "LRA" - Linear Resonance Actuator type.
+ "ERM-bar" - Bar type Eccentric Rotating Mass.
+ "ERM-coin" - Coin type Eccentric Rotating Mass.
+
+- dlg,const-op-mode: Haptic operation mode for FF_CONSTANT.
+ Possible values:
+ 1 - Direct register override(DRO) mode triggered by i2c(default),
+ 2 - PWM data source mode controlled by PWM duty,
+- dlg,periodic-op-mode: Haptic operation mode for FF_PERIODIC.
+ Possible values:
+ 1 - Register triggered waveform memory(RTWM) mode, the pattern
+ assigned to the PS_SEQ_ID played as much times as PS_SEQ_LOOP,
+ 2 - Edge triggered waveform memory(ETWM) mode, external GPI(N)
+ control are required to enable/disable and it needs to keep
+ device enabled by sending magnitude (X > 0),
+ the pattern is assigned to the GPI(N)_SEQUENCE_ID below.
+ The default value is 1 for both of the operation modes.
+ For more details, please see the datasheet.
+
+- dlg,nom-microvolt: Nominal actuator voltage rating.
+ Valid values: 0 - 6000000.
+- dlg,abs-max-microvolt: Absolute actuator maximum voltage rating.
+ Valid values: 0 - 6000000.
+- dlg,imax-microamp: Actuator max current rating.
+ Valid values: 0 - 252000.
+ Default: 130000.
+- dlg,impd-micro-ohms: the impedance of the actuator in micro ohms.
+ Valid values: 0 - 1500000000.
+
+Optional properties:
+- pwms : phandle to the physical PWM(Pulse Width Modulation) device.
+ PWM properties should be named "pwms". And number of cell is different
+ for each pwm device.
+ (See Documentation/devicetree/bindings/pwm/pwm.txt
+ for further information relating to pwm properties)
+
+- dlg,ps-seq-id: the PS_SEQ_ID(pattern ID in waveform memory inside chip)
+ to play back when RTWM-MODE is enabled.
+ Valid range: 0 - 15.
+- dlg,ps-seq-loop: the PS_SEQ_LOOP, Number of times the pre-stored sequence
+ pointed to by PS_SEQ_ID or GPI(N)_SEQUENCE_ID is repeated.
+ Valid range: 0 - 15.
+- dlg,gpiN-seq-id: the GPI(N)_SEQUENCE_ID, pattern to play
+ when gpi0 is triggered, 'N' must be 0 - 2.
+ Valid range: 0 - 15.
+- dlg,gpiN-mode: the pattern mode which can select either
+ "Single-pattern" or "Multi-pattern", 'N' must be 0 - 2.
+- dlg,gpiN-polarity: gpiN polarity which can be chosen among
+ "Rising-edge", "Falling-edge" and "Both-edge",
+ 'N' must be 0 - 2
+ Haptic will work by this edge option in case of ETWM mode.
+
+- dlg,resonant-freq-hz: use in case of LRA.
+ the frequency range: 50 - 300.
+ Default: 205.
+
+- dlg,bemf-sens-enable: Enable for internal loop computations.
+- dlg,freq-track-enable: Enable for resonant frequency tracking.
+- dlg,acc-enable: Enable for active acceleration.
+- dlg,rapid-stop-enable: Enable for rapid stop.
+- dlg,amp-pid-enable: Enable for the amplitude PID.
+- dlg,mem-array: Customized waveform memory(patterns) data downloaded to
+ the device during initialization. This is an array of 100 values(u8).
+
+For further information, see device datasheet.
+
+======
+
+Example:
+
+ haptics: da7280-haptics@4a {
+ compatible = "dlg,da7280";
+ reg = <0x4a>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ dlg,actuator-type = "LRA";
+ dlg,dlg,const-op-mode = <1>;
+ dlg,dlg,periodic-op-mode = <1>;
+ dlg,nom-microvolt = <2000000>;
+ dlg,abs-max-microvolt = <2000000>;
+ dlg,imax-microamp = <170000>;
+ dlg,resonant-freq-hz = <180>;
+ dlg,impd-micro-ohms = <10500000>;
+ dlg,freq-track-enable;
+ dlg,rapid-stop-enable;
+ dlg,mem-array = <
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ >;
+ };
diff --git a/dts/Bindings/input/fsl,mpr121-touchkey.yaml b/dts/Bindings/input/fsl,mpr121-touchkey.yaml
index 378a85c09d..878464f128 100644
--- a/dts/Bindings/input/fsl,mpr121-touchkey.yaml
+++ b/dts/Bindings/input/fsl,mpr121-touchkey.yaml
@@ -31,8 +31,7 @@ properties:
interrupts:
maxItems: 1
- vdd-supply:
- maxItems: 1
+ vdd-supply: true
linux,keycodes:
minItems: 1
diff --git a/dts/Bindings/input/gpio-keys.yaml b/dts/Bindings/input/gpio-keys.yaml
index 6966ab009f..060a309ff8 100644
--- a/dts/Bindings/input/gpio-keys.yaml
+++ b/dts/Bindings/input/gpio-keys.yaml
@@ -34,13 +34,13 @@ patternProperties:
linux,code:
description: Key / Axis code to emit.
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
linux,input-type:
description:
Specify event type this button/key generates. If not specified defaults to
<1> == EV_KEY.
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
default: 1
@@ -56,12 +56,12 @@ patternProperties:
linux,input-value = <0xffffffff>; /* -1 */
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
debounce-interval:
description:
Debouncing interval time in milliseconds. If not specified defaults to 5.
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
default: 5
@@ -79,7 +79,7 @@ patternProperties:
EV_ACT_ANY - both asserted and deasserted
EV_ACT_ASSERTED - asserted
EV_ACT_DEASSERTED - deasserted
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2]
linux,can-disable:
@@ -118,7 +118,7 @@ then:
poll-interval:
description:
Poll interval time in milliseconds
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
required:
- poll-interval
diff --git a/dts/Bindings/input/sprd,sc27xx-vibra.txt b/dts/Bindings/input/sprd,sc27xx-vibra.txt
deleted file mode 100644
index f2ec0d4f2d..0000000000
--- a/dts/Bindings/input/sprd,sc27xx-vibra.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-Spreadtrum SC27xx PMIC Vibrator
-
-Required properties:
-- compatible: should be "sprd,sc2731-vibrator".
-- reg: address of vibrator control register.
-
-Example :
-
- sc2731_pmic: pmic@0 {
- compatible = "sprd,sc2731";
- reg = <0>;
- spi-max-frequency = <26000000>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- vibrator@eb4 {
- compatible = "sprd,sc2731-vibrator";
- reg = <0xeb4>;
- };
- };
diff --git a/dts/Bindings/input/sprd,sc27xx-vibrator.yaml b/dts/Bindings/input/sprd,sc27xx-vibrator.yaml
new file mode 100644
index 0000000000..5d67fc8ebc
--- /dev/null
+++ b/dts/Bindings/input/sprd,sc27xx-vibrator.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2020 Unisoc Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/sprd,sc27xx-vibrator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Spreadtrum SC27xx PMIC Vibrator Device Tree Bindings
+
+maintainers:
+ - Orson Zhai <orsonzhai@gmail.com>
+ - Baolin Wang <baolin.wang7@gmail.com>
+ - Chunyan Zhang <zhang.lyra@gmail.com>
+
+properties:
+ compatible:
+ enum:
+ - sprd,sc2721-vibrator
+ - sprd,sc2730-vibrator
+ - sprd,sc2731-vibrator
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ sc2731_pmic: pmic@0 {
+ compatible = "sprd,sc2731";
+ reg = <0 0>;
+ spi-max-frequency = <26000000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vibrator@eb4 {
+ compatible = "sprd,sc2731-vibrator";
+ reg = <0xeb4>;
+ };
+ };
diff --git a/dts/Bindings/input/touchscreen/edt-ft5x06.yaml b/dts/Bindings/input/touchscreen/edt-ft5x06.yaml
index 4ce109476a..bfc3a8b5e1 100644
--- a/dts/Bindings/input/touchscreen/edt-ft5x06.yaml
+++ b/dts/Bindings/input/touchscreen/edt-ft5x06.yaml
@@ -55,8 +55,7 @@ properties:
wakeup-source: true
- vcc-supply:
- maxItems: 1
+ vcc-supply: true
gain:
description: Allows setting the sensitivity in the range from 0 to 31.
diff --git a/dts/Bindings/input/touchscreen/ektf2127.txt b/dts/Bindings/input/touchscreen/ektf2127.txt
index 94c4fc6449..5eef5e7d6a 100644
--- a/dts/Bindings/input/touchscreen/ektf2127.txt
+++ b/dts/Bindings/input/touchscreen/ektf2127.txt
@@ -1,7 +1,7 @@
* Elan eKTF2127 I2C touchscreen controller
Required properties:
- - compatible : "elan,ektf2127"
+ - compatible : "elan,ektf2127" or "elan,ektf2132"
- reg : I2C slave address of the chip (0x40)
- interrupts : interrupt specification for the ektf2127 interrupt
- power-gpios : GPIO specification for the pin connected to the
diff --git a/dts/Bindings/interrupt-controller/arm,gic.yaml b/dts/Bindings/interrupt-controller/arm,gic.yaml
index 06889963df..ba282f4c9f 100644
--- a/dts/Bindings/interrupt-controller/arm,gic.yaml
+++ b/dts/Bindings/interrupt-controller/arm,gic.yaml
@@ -35,7 +35,6 @@ properties:
- arm,gic-400
- arm,pl390
- arm,tc11mp-gic
- - nvidia,tegra210-agic
- qcom,msm-8660-qgic
- qcom,msm-qgic2
@@ -53,6 +52,14 @@ properties:
- const: brcm,brahma-b15-gic
- const: arm,cortex-a15-gic
+ - oneOf:
+ - const: nvidia,tegra210-agic
+ - items:
+ - enum:
+ - nvidia,tegra186-agic
+ - nvidia,tegra194-agic
+ - const: nvidia,tegra210-agic
+
interrupt-controller: true
"#address-cells":
diff --git a/dts/Bindings/interrupt-controller/fsl,ls-extirq.txt b/dts/Bindings/interrupt-controller/fsl,ls-extirq.txt
index f0ad7801e8..4d47df1a5c 100644
--- a/dts/Bindings/interrupt-controller/fsl,ls-extirq.txt
+++ b/dts/Bindings/interrupt-controller/fsl,ls-extirq.txt
@@ -1,6 +1,7 @@
* Freescale Layerscape external IRQs
-Some Layerscape SOCs (LS1021A, LS1043A, LS1046A) support inverting
+Some Layerscape SOCs (LS1021A, LS1043A, LS1046A
+LS1088A, LS208xA, LX216xA) support inverting
the polarity of certain external interrupt lines.
The device node must be a child of the node representing the
@@ -8,12 +9,15 @@ Supplemental Configuration Unit (SCFG).
Required properties:
- compatible: should be "fsl,<soc-name>-extirq", e.g. "fsl,ls1021a-extirq".
+ "fsl,ls1043a-extirq": for LS1043A, LS1046A.
+ "fsl,ls1088a-extirq": for LS1088A, LS208xA, LX216xA.
- #interrupt-cells: Must be 2. The first element is the index of the
external interrupt line. The second element is the trigger type.
- #address-cells: Must be 0.
- interrupt-controller: Identifies the node as an interrupt controller
- reg: Specifies the Interrupt Polarity Control Register (INTPCR) in
- the SCFG.
+ the SCFG or the External Interrupt Control Register (IRQCR) in
+ the ISC.
- interrupt-map: Specifies the mapping from external interrupts to GIC
interrupts.
- interrupt-map-mask: Must be <0xffffffff 0>.
diff --git a/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
deleted file mode 100644
index f5baeccb68..0000000000
--- a/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Microsemi Ocelot SoC ICPU Interrupt Controller
-
-Required properties:
-
-- compatible : should be "mscc,ocelot-icpu-intr"
-- reg : Specifies base physical address and size of the registers.
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
- interrupt source. The value shall be 1.
-- interrupts : Specifies the CPU interrupt the controller is connected to.
-
-Example:
-
- intc: interrupt-controller@70000070 {
- compatible = "mscc,ocelot-icpu-intr";
- reg = <0x70000070 0x70>;
- #interrupt-cells = <1>;
- interrupt-controller;
- interrupt-parent = <&cpuintc>;
- interrupts = <2>;
- };
diff --git a/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml b/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
new file mode 100644
index 0000000000..27b798bfe2
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Microsemi Ocelot SoC ICPU Interrupt Controller
+
+maintainers:
+ - Alexandre Belloni <alexandre.belloni@bootlin.com>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+description: |
+ the Microsemi Ocelot interrupt controller that is part of the
+ ICPU. It is connected directly to the MIPS core interrupt
+ controller.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mscc,jaguar2-icpu-intr
+ - mscc,luton-icpu-intr
+ - mscc,ocelot-icpu-intr
+ - mscc,serval-icpu-intr
+
+
+ '#interrupt-cells':
+ const: 1
+
+ '#address-cells':
+ const: 0
+
+ interrupt-controller: true
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - '#interrupt-cells'
+ - '#address-cells'
+ - interrupt-controller
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ intc: interrupt-controller@70000070 {
+ compatible = "mscc,ocelot-icpu-intr";
+ reg = <0x70000070 0x70>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+...
diff --git a/dts/Bindings/interrupt-controller/mti,gic.yaml b/dts/Bindings/interrupt-controller/mti,gic.yaml
index 039e08af98..91bb3c2307 100644
--- a/dts/Bindings/interrupt-controller/mti,gic.yaml
+++ b/dts/Bindings/interrupt-controller/mti,gic.yaml
@@ -42,7 +42,7 @@ properties:
Specifies the list of CPU interrupt vectors to which the GIC may not
route interrupts. This property is ignored if the CPU is started in EIC
mode.
- $ref: /schemas/types.yaml#definitions/uint32-array
+ $ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 6
uniqueItems: true
@@ -56,7 +56,7 @@ properties:
It accepts two values: the 1st is the starting interrupt and the 2nd is
the size of the reserved range. If not specified, the driver will
allocate the last (2 * number of VPEs in the system).
- $ref: /schemas/types.yaml#definitions/uint32-array
+ $ref: /schemas/types.yaml#/definitions/uint32-array
items:
- minimum: 0
maximum: 254
diff --git a/dts/Bindings/interrupt-controller/ti,pruss-intc.yaml b/dts/Bindings/interrupt-controller/ti,pruss-intc.yaml
index 1c4c009ded..c2ce215501 100644
--- a/dts/Bindings/interrupt-controller/ti,pruss-intc.yaml
+++ b/dts/Bindings/interrupt-controller/ti,pruss-intc.yaml
@@ -80,7 +80,7 @@ properties:
mapping is provided.
ti,irqs-reserved:
- $ref: /schemas/types.yaml#definitions/uint8
+ $ref: /schemas/types.yaml#/definitions/uint8
description: |
Bitmask of host interrupts between 0 and 7 (corresponding to PRUSS INTC
output interrupts 2 through 9) that are not connected to the Arm interrupt
diff --git a/dts/Bindings/interrupt-controller/ti,sci-inta.yaml b/dts/Bindings/interrupt-controller/ti,sci-inta.yaml
index b5af120114..3d89668573 100644
--- a/dts/Bindings/interrupt-controller/ti,sci-inta.yaml
+++ b/dts/Bindings/interrupt-controller/ti,sci-inta.yaml
@@ -76,7 +76,7 @@ properties:
"limit" specifies the limit for translation
ti,unmapped-event-sources:
- $ref: /schemas/types.yaml#definitions/phandle-array
+ $ref: /schemas/types.yaml#/definitions/phandle-array
description:
Array of phandles to DMA controllers where the unmapped events originate.
diff --git a/dts/Bindings/iommu/arm,smmu.yaml b/dts/Bindings/iommu/arm,smmu.yaml
index 503160a7b9..3b63f2ae24 100644
--- a/dts/Bindings/iommu/arm,smmu.yaml
+++ b/dts/Bindings/iommu/arm,smmu.yaml
@@ -28,8 +28,6 @@ properties:
- enum:
- qcom,msm8996-smmu-v2
- qcom,msm8998-smmu-v2
- - qcom,sc7180-smmu-v2
- - qcom,sdm845-smmu-v2
- const: qcom,smmu-v2
- description: Qcom SoCs implementing "arm,mmu-500"
@@ -40,6 +38,13 @@ properties:
- qcom,sm8150-smmu-500
- qcom,sm8250-smmu-500
- const: arm,mmu-500
+ - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
+ items:
+ - enum:
+ - qcom,sc7180-smmu-v2
+ - qcom,sdm845-smmu-v2
+ - const: qcom,adreno-smmu
+ - const: qcom,smmu-v2
- description: Marvell SoCs implementing "arm,mmu-500"
items:
- const: marvell,ap806-smmu-500
diff --git a/dts/Bindings/leds/backlight/common.yaml b/dts/Bindings/leds/backlight/common.yaml
index bc817f77d2..702ba350d8 100644
--- a/dts/Bindings/leds/backlight/common.yaml
+++ b/dts/Bindings/leds/backlight/common.yaml
@@ -22,7 +22,7 @@ properties:
The default brightness that should be applied to the LED by the operating
system on start-up. The brightness should not exceed the brightness the
LED can provide.
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
max-brightness:
description:
@@ -31,6 +31,6 @@ properties:
on the brightness apart from what the driver says, as it could happen
that a LED can be made so bright that it gets damaged or causes damage
due to restrictions in a specific system, such as mounting conditions.
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
additionalProperties: true
diff --git a/dts/Bindings/leds/common.yaml b/dts/Bindings/leds/common.yaml
index f1211e7045..b1f363747a 100644
--- a/dts/Bindings/leds/common.yaml
+++ b/dts/Bindings/leds/common.yaml
@@ -27,21 +27,21 @@ properties:
List of device current outputs the LED is connected to. The outputs are
identified by the numbers that must be defined in the LED device binding
documentation.
- $ref: /schemas/types.yaml#definitions/uint32-array
+ $ref: /schemas/types.yaml#/definitions/uint32-array
function:
description:
LED function. Use one of the LED_FUNCTION_* prefixed definitions
from the header include/dt-bindings/leds/common.h. If there is no
matching LED_FUNCTION available, add a new one.
- $ref: /schemas/types.yaml#definitions/string
+ $ref: /schemas/types.yaml#/definitions/string
color:
description:
Color of the LED. Use one of the LED_COLOR_ID_* prefixed definitions from
the header include/dt-bindings/leds/common.h. If there is no matching
LED_COLOR_ID available, add a new one.
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 9
@@ -49,7 +49,7 @@ properties:
description:
Integer to be used when more than one instance of the same function is
needed, differing only with an ordinal number.
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
label:
description:
@@ -66,7 +66,7 @@ properties:
produced where the LED momentarily turns off (or on). The "keep" setting
will keep the LED at whatever its current state is, without producing a
glitch.
- $ref: /schemas/types.yaml#definitions/string
+ $ref: /schemas/types.yaml#/definitions/string
enum:
- on
- off
@@ -77,7 +77,7 @@ properties:
description:
This parameter, if present, is a string defining the trigger assigned to
the LED.
- $ref: /schemas/types.yaml#definitions/string
+ $ref: /schemas/types.yaml#/definitions/string
enum:
# LED will act as a back-light, controlled by the framebuffer system
@@ -109,7 +109,7 @@ properties:
brightness and duration (in ms). The exact format is
described in:
Documentation/devicetree/bindings/leds/leds-trigger-pattern.txt
- $ref: /schemas/types.yaml#definitions/uint32-matrix
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
minItems: 2
maxItems: 2
@@ -143,7 +143,7 @@ properties:
the device tree and be referenced by a phandle and a set of phandle
arguments. A length of arguments should be specified by the
#trigger-source-cells property in the source node.
- $ref: /schemas/types.yaml#definitions/phandle-array
+ $ref: /schemas/types.yaml#/definitions/phandle-array
# Required properties for flash LED child nodes:
flash-max-microamp:
diff --git a/dts/Bindings/leds/leds-lp55xx.yaml b/dts/Bindings/leds/leds-lp55xx.yaml
index 58e974793a..f552cd143d 100644
--- a/dts/Bindings/leds/leds-lp55xx.yaml
+++ b/dts/Bindings/leds/leds-lp55xx.yaml
@@ -35,7 +35,7 @@ properties:
description: I2C slave address
clock-mode:
- $ref: /schemas/types.yaml#definitions/uint8
+ $ref: /schemas/types.yaml#/definitions/uint8
description: |
Input clock mode
enum:
@@ -49,7 +49,7 @@ properties:
GPIO attached to the chip's enable pin
pwr-sel:
- $ref: /schemas/types.yaml#definitions/uint8
+ $ref: /schemas/types.yaml#/definitions/uint8
description: |
LP8501 specific property. Power selection for output channels.
enum:
@@ -70,14 +70,14 @@ patternProperties:
$ref: common.yaml#
properties:
led-cur:
- $ref: /schemas/types.yaml#definitions/uint8
+ $ref: /schemas/types.yaml#/definitions/uint8
description: |
Current setting at each LED channel (mA x10, 0 if LED is not connected)
minimum: 0
maximum: 255
max-cur:
- $ref: /schemas/types.yaml#definitions/uint8
+ $ref: /schemas/types.yaml#/definitions/uint8
description: Maximun current at each LED channel.
reg:
@@ -97,7 +97,7 @@ patternProperties:
- 8 # LED output D9
chan-name:
- $ref: /schemas/types.yaml#definitions/string
+ $ref: /schemas/types.yaml#/definitions/string
description: name of channel
required:
diff --git a/dts/Bindings/leds/leds-pwm.txt b/dts/Bindings/leds/leds-pwm.txt
deleted file mode 100644
index 6c6583c35f..0000000000
--- a/dts/Bindings/leds/leds-pwm.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-LED connected to PWM
-
-Required properties:
-- compatible : should be "pwm-leds".
-
-Each LED is represented as a sub-node of the pwm-leds device. Each
-node's name represents the name of the corresponding LED.
-
-LED sub-node properties:
-- pwms : PWM property to point to the PWM device (phandle)/port (id) and to
- specify the period time to be used: <&phandle id period_ns>;
-- pwm-names : (optional) Name to be used by the PWM subsystem for the PWM device
- For the pwms and pwm-names property please refer to:
- Documentation/devicetree/bindings/pwm/pwm.txt
-- max-brightness : Maximum brightness possible for the LED
-- active-low : (optional) For PWMs where the LED is wired to supply
- rather than ground.
-- label : (optional)
- see Documentation/devicetree/bindings/leds/common.txt
-- linux,default-trigger : (optional)
- see Documentation/devicetree/bindings/leds/common.txt
-
-Example:
-
-twl_pwm: pwm {
- /* provides two PWMs (id 0, 1 for PWM1 and PWM2) */
- compatible = "ti,twl6030-pwm";
- #pwm-cells = <2>;
-};
-
-twl_pwmled: pwmled {
- /* provides one PWM (id 0 for Charing indicator LED) */
- compatible = "ti,twl6030-pwmled";
- #pwm-cells = <2>;
-};
-
-pwmleds {
- compatible = "pwm-leds";
- kpad {
- label = "omap4::keypad";
- pwms = <&twl_pwm 0 7812500>;
- max-brightness = <127>;
- };
-
- charging {
- label = "omap4:green:chrg";
- pwms = <&twl_pwmled 0 7812500>;
- max-brightness = <255>;
- };
-};
diff --git a/dts/Bindings/leds/leds-pwm.yaml b/dts/Bindings/leds/leds-pwm.yaml
new file mode 100644
index 0000000000..fe4d5fd259
--- /dev/null
+++ b/dts/Bindings/leds/leds-pwm.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/leds-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LEDs connected to PWM
+
+maintainers:
+ - Pavel Machek <pavel@ucw.cz>
+
+description:
+ Each LED is represented as a sub-node of the pwm-leds device. Each
+ node's name represents the name of the corresponding LED.
+
+properties:
+ compatible:
+ const: pwm-leds
+
+patternProperties:
+ "^led(-[0-9a-f]+)?$":
+ type: object
+
+ $ref: common.yaml#
+
+ properties:
+ pwms:
+ maxItems: 1
+
+ pwm-names: true
+
+ max-brightness:
+ description:
+ Maximum brightness possible for the LED
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ active-low:
+ description:
+ For PWMs where the LED is wired to supply rather than ground.
+ type: boolean
+
+ required:
+ - pwms
+ - max-brightness
+
+additionalProperties: false
+
+examples:
+ - |
+
+ #include <dt-bindings/leds/common.h>
+
+ led-controller {
+ compatible = "pwm-leds";
+
+ led-1 {
+ label = "omap4::keypad";
+ pwms = <&twl_pwm 0 7812500>;
+ max-brightness = <127>;
+ };
+
+ led-2 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_CHARGING;
+ pwms = <&twl_pwmled 0 7812500>;
+ max-brightness = <255>;
+ };
+ };
+
+...
diff --git a/dts/Bindings/mailbox/arm,mhu.yaml b/dts/Bindings/mailbox/arm,mhu.yaml
index d43791a2dd..d07eb00b97 100644
--- a/dts/Bindings/mailbox/arm,mhu.yaml
+++ b/dts/Bindings/mailbox/arm,mhu.yaml
@@ -61,7 +61,6 @@ properties:
- description: low-priority non-secure
- description: high-priority non-secure
- description: Secure
- maxItems: 3
clocks:
maxItems: 1
diff --git a/dts/Bindings/mailbox/arm,mhuv2.yaml b/dts/Bindings/mailbox/arm,mhuv2.yaml
new file mode 100644
index 0000000000..6608545ea6
--- /dev/null
+++ b/dts/Bindings/mailbox/arm,mhuv2.yaml
@@ -0,0 +1,209 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/arm,mhuv2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM MHUv2 Mailbox Controller
+
+maintainers:
+ - Tushar Khandelwal <tushar.khandelwal@arm.com>
+ - Viresh Kumar <viresh.kumar@linaro.org>
+
+description: |
+ The Arm Message Handling Unit (MHU) Version 2 is a mailbox controller that has
+ between 1 and 124 channel windows (each 32-bit wide) to provide unidirectional
+ communication with remote processor(s), where the number of channel windows
+ are implementation dependent.
+
+ Given the unidirectional nature of the controller, an MHUv2 mailbox may only
+ be written to or read from. If a pair of MHU controllers is implemented
+ between two processing elements to provide bidirectional communication, these
+ must be specified as two separate mailboxes.
+
+ If the interrupts property is present in device tree node, then its treated as
+ a "receiver" mailbox, otherwise a "sender".
+
+ An MHU controller must be specified along with the supported transport
+ protocols. The transport protocols determine the method of data transmission
+ as well as the number of provided mailbox channels.
+
+ Following are the possible transport protocols.
+
+ - Data-transfer: Each transfer is made of one or more words, using one or more
+ channel windows.
+
+ - Doorbell: Each transfer is made up of single bit flag, using any one of the
+ bits in a channel window. A channel window can support up to 32 doorbells
+ and the entire window shall be used in doorbell protocol. Optionally, data
+ may be transmitted through a shared memory region, wherein the MHU is used
+ strictly as an interrupt generation mechanism but that is out of the scope
+ of these bindings.
+
+# We need a select here so we don't match all nodes with 'arm,primecell'
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - arm,mhuv2-tx
+ - arm,mhuv2-rx
+ required:
+ - compatible
+
+properties:
+ compatible:
+ oneOf:
+ - description: Sender mode
+ items:
+ - const: arm,mhuv2-tx
+ - const: arm,primecell
+
+ - description: Receiver-mode
+ items:
+ - const: arm,mhuv2-rx
+ - const: arm,primecell
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: |
+ The MHUv2 controller always implements an interrupt in the "receiver"
+ mode, while the interrupt in the "sender" mode was not available in the
+ version MHUv2.0, but the later versions do have it.
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ maxItems: 1
+
+ arm,mhuv2-protocols:
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ description: |
+ The MHUv2 controller may contain up to 124 channel windows (each 32-bit
+ wide). The hardware and the DT bindings allows any combination of those to
+ be used for various transport protocols.
+
+ This property allows a platform to describe how these channel windows are
+ used in various transport protocols. The entries in this property shall be
+ present as an array of tuples, where each tuple describes details about
+ one of the transport protocol being implemented over some channel
+ window(s).
+
+ The first field of a tuple signifies the transfer protocol, 0 is reserved
+ for doorbell protocol, and 1 is reserved for data-transfer protocol.
+ Using any other value in the first field of a tuple makes it invalid.
+
+ The second field of a tuple signifies the number of channel windows where
+ the protocol would be used and should be set to a non zero value. For
+ doorbell protocol this field signifies the number of 32-bit channel
+ windows that implement the doorbell protocol. For data-transfer protocol,
+ this field signifies the number of 32-bit channel windows that implement
+ the data-transfer protocol.
+
+ The total number of channel windows specified here shouldn't be more than
+ the ones implemented by the platform, though one can specify lesser number
+ of windows here than what the platform implements.
+
+ mhu: mailbox@2b1f0000 {
+ ...
+
+ arm,mhuv2-protocols = <0 2>, <1 1>, <1 5>, <1 7>;
+ }
+
+ The above example defines the protocols of an ARM MHUv2 mailbox
+ controller, where a total of 15 channel windows are used. The first two
+ windows are used in doorbell protocol (64 doorbells), followed by 1, 5 and
+ 7 windows (separately) used in data-transfer protocol.
+
+ minItems: 1
+ maxItems: 124
+ items:
+ items:
+ - enum: [ 0, 1 ]
+ - minimum: 0
+ maximum: 124
+
+
+ '#mbox-cells':
+ description: |
+ It is always set to 2. The first argument in the consumers 'mboxes'
+ property represents the channel window group, which may be used in
+ doorbell, or data-transfer protocol, and the second argument (only
+ relevant in doorbell protocol, should be 0 otherwise) represents the
+ doorbell number within the 32 bit wide channel window.
+
+ From the example given above for arm,mhuv2-protocols, here is how a client
+ node can reference them.
+
+ mboxes = <&mhu 0 5>; // Channel Window Group 0, doorbell 5.
+ mboxes = <&mhu 1 7>; // Channel Window Group 1, doorbell 7.
+ mboxes = <&mhu 2 0>; // Channel Window Group 2, data transfer protocol with 1 window.
+ mboxes = <&mhu 3 0>; // Channel Window Group 3, data transfer protocol with 5 windows.
+ mboxes = <&mhu 4 0>; // Channel Window Group 4, data transfer protocol with 7 windows.
+
+ const: 2
+
+if:
+ # Interrupt is compulsory for receiver
+ properties:
+ compatible:
+ contains:
+ const: arm,mhuv2-rx
+then:
+ required:
+ - interrupts
+
+required:
+ - compatible
+ - reg
+ - '#mbox-cells'
+ - arm,mhuv2-protocols
+
+additionalProperties: false
+
+examples:
+ # Multiple transport protocols implemented by the mailbox controllers
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ mhu_tx: mailbox@2b1f0000 {
+ #mbox-cells = <2>;
+ compatible = "arm,mhuv2-tx", "arm,primecell";
+ reg = <0 0x2b1f0000 0 0x1000>;
+ clocks = <&clock 0>;
+ clock-names = "apb_pclk";
+ interrupts = <0 45 4>;
+ arm,mhuv2-protocols = <1 5>, <1 2>, <1 5>, <1 7>, <0 2>;
+ };
+
+ mhu_rx: mailbox@2b1f1000 {
+ #mbox-cells = <2>;
+ compatible = "arm,mhuv2-rx", "arm,primecell";
+ reg = <0 0x2b1f1000 0 0x1000>;
+ clocks = <&clock 0>;
+ clock-names = "apb_pclk";
+ interrupts = <0 46 4>;
+ arm,mhuv2-protocols = <1 1>, <1 7>, <0 2>;
+ };
+
+ mhu_client: scb@2e000000 {
+ compatible = "fujitsu,mb86s70-scb-1.0";
+ reg = <0 0x2e000000 0 0x4000>;
+
+ mboxes =
+ //data-transfer protocol with 5 windows, mhu-tx
+ <&mhu_tx 2 0>,
+ //data-transfer protocol with 7 windows, mhu-tx
+ <&mhu_tx 3 0>,
+ //doorbell protocol channel 4, doorbell 27, mhu-tx
+ <&mhu_tx 4 27>,
+ //data-transfer protocol with 1 window, mhu-rx
+ <&mhu_rx 0 0>;
+ };
+ };
diff --git a/dts/Bindings/media/allwinner,sun4i-a10-video-engine.yaml b/dts/Bindings/media/allwinner,sun4i-a10-video-engine.yaml
index 4cc1a670c9..2f7058f776 100644
--- a/dts/Bindings/media/allwinner,sun4i-a10-video-engine.yaml
+++ b/dts/Bindings/media/allwinner,sun4i-a10-video-engine.yaml
@@ -18,6 +18,8 @@ properties:
- allwinner,sun7i-a20-video-engine
- allwinner,sun8i-a33-video-engine
- allwinner,sun8i-h3-video-engine
+ - allwinner,sun8i-v3s-video-engine
+ - allwinner,sun8i-r40-video-engine
- allwinner,sun50i-a64-video-engine
- allwinner,sun50i-h5-video-engine
- allwinner,sun50i-h6-video-engine
diff --git a/dts/Bindings/media/amlogic,axg-ge2d.yaml b/dts/Bindings/media/amlogic,axg-ge2d.yaml
new file mode 100644
index 0000000000..bee93bd847
--- /dev/null
+++ b/dts/Bindings/media/amlogic,axg-ge2d.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2020 BayLibre, SAS
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/media/amlogic,axg-ge2d.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic GE2D Acceleration Unit
+
+maintainers:
+ - Neil Armstrong <narmstrong@baylibre.com>
+
+properties:
+ compatible:
+ enum:
+ - amlogic,axg-ge2d
+
+ interrupts:
+ minItems: 1
+
+ reg:
+ minItems: 1
+
+ resets:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ ge2d: ge2d@ff940000 {
+ compatible = "amlogic,axg-ge2d";
+ reg = <0xff940000 0x10000>;
+ interrupts = <150>;
+ clocks = <&clk_ge2d>;
+ resets = <&reset_ge2d>;
+ };
diff --git a/dts/Bindings/media/coda.txt b/dts/Bindings/media/coda.txt
deleted file mode 100644
index 90eb74cc19..0000000000
--- a/dts/Bindings/media/coda.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-Chips&Media Coda multi-standard codec IP
-========================================
-
-Coda codec IPs are present in i.MX SoCs in various versions,
-called VPU (Video Processing Unit).
-
-Required properties:
-- compatible : should be "fsl,<chip>-src" for i.MX SoCs:
- (a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27
- (b) "fsl,imx51-vpu" for CodaHx4 present in i.MX51
- (c) "fsl,imx53-vpu" for CODA7541 present in i.MX53
- (d) "fsl,imx6q-vpu" for CODA960 present in i.MX6q
-- reg: should be register base and length as documented in the
- SoC reference manual
-- interrupts : Should contain the VPU interrupt. For CODA960,
- a second interrupt is needed for the MJPEG unit.
-- clocks : Should contain the ahb and per clocks, in the order
- determined by the clock-names property.
-- clock-names : Should be "ahb", "per"
-- iram : phandle pointing to the SRAM device node
-
-Example:
-
-vpu: vpu@63ff4000 {
- compatible = "fsl,imx53-vpu";
- reg = <0x63ff4000 0x1000>;
- interrupts = <9>;
- clocks = <&clks 63>, <&clks 63>;
- clock-names = "ahb", "per";
- iram = <&ocram>;
-};
diff --git a/dts/Bindings/media/coda.yaml b/dts/Bindings/media/coda.yaml
new file mode 100644
index 0000000000..36781ee461
--- /dev/null
+++ b/dts/Bindings/media/coda.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/coda.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Chips&Media Coda multi-standard codec IP
+
+maintainers:
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |-
+ Coda codec IPs are present in i.MX SoCs in various versions,
+ called VPU (Video Processing Unit).
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: fsl,imx27-vpu
+ - const: cnm,codadx6
+ - items:
+ - const: fsl,imx51-vpu
+ - const: cnm,codahx4
+ - items:
+ - const: fsl,imx53-vpu
+ - const: cnm,coda7541
+ - items:
+ - enum:
+ - fsl,imx6dl-vpu
+ - fsl,imx6q-vpu
+ - const: cnm,coda960
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: PER clock
+ - description: AHB interface clock
+
+ clock-names:
+ items:
+ - const: per
+ - const: ahb
+
+ interrupts:
+ minItems: 1
+ items:
+ - description: BIT processor interrupt
+ - description: JPEG unit interrupt
+
+ interrupt-names:
+ minItems: 1
+ items:
+ - const: bit
+ - const: jpeg
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ iram:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle pointing to the SRAM device node
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: cnm,coda960
+ then:
+ properties:
+ interrupts:
+ minItems: 2
+
+ interrupt-names:
+ minItems: 2
+ else:
+ properties:
+ interrupts:
+ maxItems: 1
+
+ power-domains: false
+
+examples:
+ - |
+ vpu: video-codec@63ff4000 {
+ compatible = "fsl,imx53-vpu", "cnm,coda7541";
+ reg = <0x63ff4000 0x1000>;
+ interrupts = <9>;
+ clocks = <&clks 63>, <&clks 63>;
+ clock-names = "per", "ahb";
+ iram = <&ocram>;
+ };
diff --git a/dts/Bindings/media/i2c/adv7604.txt b/dts/Bindings/media/i2c/adv7604.txt
deleted file mode 100644
index b3e688b77a..0000000000
--- a/dts/Bindings/media/i2c/adv7604.txt
+++ /dev/null
@@ -1,88 +0,0 @@
-* Analog Devices ADV7604/11/12 video decoder with HDMI receiver
-
-The ADV7604 and ADV7611/12 are multiformat video decoders with an integrated
-HDMI receiver. The ADV7604 has four multiplexed HDMI inputs and one analog
-input, and the ADV7611 has one HDMI input and no analog input. The 7612 is
-similar to the 7611 but has 2 HDMI inputs.
-
-These device tree bindings support the ADV7611/12 only at the moment.
-
-Required Properties:
-
- - compatible: Must contain one of the following
- - "adi,adv7611" for the ADV7611
- - "adi,adv7612" for the ADV7612
-
- - reg: I2C slave addresses
- The ADV76xx has up to thirteen 256-byte maps that can be accessed via the
- main I2C ports. Each map has it own I2C address and acts as a standard
- slave device on the I2C bus. The main address is mandatory, others are
- optional and revert to defaults if not specified.
-
- - hpd-gpios: References to the GPIOs that control the HDMI hot-plug
- detection pins, one per HDMI input. The active flag indicates the GPIO
- level that enables hot-plug detection.
-
-The device node must contain one 'port' child node per device input and output
-port, in accordance with the video interface bindings defined in
-Documentation/devicetree/bindings/media/video-interfaces.txt. The port nodes
-are numbered as follows.
-
- Port ADV7611 ADV7612
-------------------------------------------------------------
- HDMI 0 0, 1
- Digital output 1 2
-
-The digital output port node must contain at least one endpoint.
-
-Optional Properties:
-
- - reset-gpios: Reference to the GPIO connected to the device's reset pin.
- - default-input: Select which input is selected after reset.
- - reg-names : Names of maps with programmable addresses.
- It can contain any map needing a non-default address.
- Possible maps names are :
- "main", "avlink", "cec", "infoframe", "esdp", "dpp", "afe",
- "rep", "edid", "hdmi", "test", "cp", "vdp"
-
-Optional Endpoint Properties:
-
- The following three properties are defined in video-interfaces.txt and are
- valid for source endpoints only.
-
- - hsync-active: Horizontal synchronization polarity. Defaults to active low.
- - vsync-active: Vertical synchronization polarity. Defaults to active low.
- - pclk-sample: Pixel clock polarity. Defaults to output on the falling edge.
-
- If none of hsync-active, vsync-active and pclk-sample is specified the
- endpoint will use embedded BT.656 synchronization.
-
-Example:
-
- hdmi_receiver@4c {
- compatible = "adi,adv7611";
- /*
- * The edid page will be accessible @ 0x66 on the I2C bus. All
- * other maps will retain their default addresses.
- */
- reg = <0x4c>, <0x66>;
- reg-names = "main", "edid";
-
- reset-gpios = <&ioexp 0 GPIO_ACTIVE_LOW>;
- hpd-gpios = <&ioexp 2 GPIO_ACTIVE_HIGH>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- default-input = <0>;
-
- port@0 {
- reg = <0>;
- };
- port@1 {
- reg = <1>;
- hdmi_in: endpoint {
- remote-endpoint = <&ccdc_in>;
- };
- };
- };
diff --git a/dts/Bindings/media/i2c/adv7604.yaml b/dts/Bindings/media/i2c/adv7604.yaml
new file mode 100644
index 0000000000..407baddfaa
--- /dev/null
+++ b/dts/Bindings/media/i2c/adv7604.yaml
@@ -0,0 +1,178 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/adv7604.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices ADV7604/11/12 video decoder with HDMI receiver
+
+maintainers:
+ - Hans Verkuil <hverkuil-cisco@xs4all.nl>
+
+description:
+ The ADV7604 and ADV7611/12 are multiformat video decoders with an integrated
+ HDMI receiver. The ADV7604 has four multiplexed HDMI inputs and one analog
+ input, and the ADV7611 has one HDMI input and no analog input. The 7612 is
+ similar to the 7611 but has 2 HDMI inputs.
+
+ These device tree bindings support the ADV7611/12 only at the moment.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - adi,adv7611
+ - adi,adv7612
+
+ reg:
+ minItems: 1
+ maxItems: 13
+
+ reg-names:
+ minItems: 1
+ maxItems: 13
+ items:
+ - const: main
+ - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
+ - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
+ - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
+ - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
+ - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
+ - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
+ - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
+ - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
+ - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
+ - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
+ - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
+ - enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
+
+ interrupts:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+
+ hpd-gpios:
+ minItems: 1
+ description:
+ References to the GPIOs that control the HDMI hot-plug detection pins,
+ one per HDMI input. The active flag indicates the GPIO level that
+ enables hot-plug detection.
+
+ default-input:
+ maxItems: 1
+ description:
+ Select which input is selected after reset.
+
+ ports:
+ type: object
+ description:
+ A node containing input and output port nodes with endpoint definitions
+ as documented in
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: adi,adv7611
+ then:
+ properties:
+ ports:
+ properties:
+ '#address-cells':
+ const: 1
+ '#size-cells':
+ const: 0
+ port@0:
+ type: object
+ description: Input port
+ port@1:
+ type: object
+ description: Output port
+
+ required:
+ - port@1
+
+ additionalProperties: false
+
+ required:
+ - ports
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: adi,adv7612
+ then:
+ properties:
+ ports:
+ properties:
+ '#address-cells':
+ const: 1
+ '#size-cells':
+ const: 0
+ port@2:
+ type: object
+ description: Output port
+
+ patternProperties:
+ "^port@[0-1]$":
+ type: object
+ description: Input port
+
+ required:
+ - port@2
+
+ additionalProperties: false
+
+ required:
+ - ports
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_receiver@4c {
+ compatible = "adi,adv7611";
+ /*
+ * The edid page will be accessible @ 0x66 on the I2C bus. All
+ * other maps will retain their default addresses.
+ */
+ reg = <0x4c>, <0x66>;
+ reg-names = "main", "edid";
+
+ reset-gpios = <&ioexp 0 GPIO_ACTIVE_LOW>;
+ hpd-gpios = <&ioexp 2 GPIO_ACTIVE_HIGH>;
+ default-input = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ hdmi_in: endpoint {
+ remote-endpoint = <&ccdc_in>;
+ };
+ };
+ };
+
+
+ };
+ };
diff --git a/dts/Bindings/media/i2c/aptina,mt9v111.txt b/dts/Bindings/media/i2c/aptina,mt9v111.txt
deleted file mode 100644
index bd896e9f67..0000000000
--- a/dts/Bindings/media/i2c/aptina,mt9v111.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-* Aptina MT9V111 CMOS sensor
-----------------------------
-
-The Aptina MT9V111 is a 1/4-Inch VGA-format digital image sensor with a core
-based on Aptina MT9V011 sensor and an integrated Image Flow Processor (IFP).
-
-The sensor has an active pixel array of 640x480 pixels and can output a number
-of image resolution and formats controllable through a simple two-wires
-interface.
-
-Required properties:
---------------------
-
-- compatible: shall be "aptina,mt9v111".
-- clocks: reference to the system clock input provider.
-
-Optional properties:
---------------------
-
-- enable-gpios: output enable signal, pin name "OE#". Active low.
-- standby-gpios: low power state control signal, pin name "STANDBY".
- Active high.
-- reset-gpios: chip reset signal, pin name "RESET#". Active low.
-
-The device node must contain one 'port' child node with one 'endpoint' child
-sub-node for its digital output video port, in accordance with the video
-interface bindings defined in:
-Documentation/devicetree/bindings/media/video-interfaces.txt
-
-Example:
---------
-
- &i2c1 {
- camera@48 {
- compatible = "aptina,mt9v111";
- reg = <0x48>;
-
- clocks = <&camera_clk>;
-
- port {
- mt9v111_out: endpoint {
- remote-endpoint = <&ceu_in>;
- };
- };
- };
- };
diff --git a/dts/Bindings/media/i2c/aptina,mt9v111.yaml b/dts/Bindings/media/i2c/aptina,mt9v111.yaml
new file mode 100644
index 0000000000..ff9546e95d
--- /dev/null
+++ b/dts/Bindings/media/i2c/aptina,mt9v111.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/aptina,mt9v111.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Aptina MT9V111 CMOS sensor
+
+maintainers:
+ - Jacopo Mondi <jacopo@jmondi.org>
+
+description: |
+ The Aptina MT9V111 is a 1/4-Inch VGA-format digital image sensor with a core
+ based on Aptina MT9V011 sensor and an integrated Image Flow Processor (IFP).
+
+ The sensor has an active pixel array of 640x480 pixels and can output a number
+ of image resolutions and formats controllable through a simple two-wires
+ interface.
+
+properties:
+ compatible:
+ const: aptina,mt9v111
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ enable-gpios:
+ description: Enable signal, pin name "OE#". Active low.
+ maxItems: 1
+
+ standby-gpios:
+ description: |
+ Low power state control signal, pin name "STANDBY". Active high.
+ maxItems: 1
+
+ reset-gpios:
+ description: Chip reset signal, pin name "RESET#". Active low.
+ maxItems: 1
+
+ port:
+ type: object
+ description: |
+ Output video port. See ../video-interfaces.txt.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera@48 {
+ compatible = "aptina,mt9v111";
+ reg = <0x48>;
+ clocks = <&camera_clk>;
+
+ port {
+ mt9v111_out: endpoint {
+ remote-endpoint = <&ceu_in>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/media/i2c/maxim,max9286.yaml b/dts/Bindings/media/i2c/maxim,max9286.yaml
index 9ea827092f..68ee8c7d9e 100644
--- a/dts/Bindings/media/i2c/maxim,max9286.yaml
+++ b/dts/Bindings/media/i2c/maxim,max9286.yaml
@@ -40,7 +40,6 @@ properties:
poc-supply:
description: Regulator providing Power over Coax to the cameras
- maxItems: 1
enable-gpios:
description: GPIO connected to the \#PWDN pin with inverted polarity
diff --git a/dts/Bindings/media/i2c/mipi-ccs.yaml b/dts/Bindings/media/i2c/mipi-ccs.yaml
new file mode 100644
index 0000000000..bb3528315f
--- /dev/null
+++ b/dts/Bindings/media/i2c/mipi-ccs.yaml
@@ -0,0 +1,133 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2014--2020 Intel Corporation
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/mipi-ccs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MIPI CCS, SMIA++ and SMIA compliant camera sensors
+
+maintainers:
+ - Sakari Ailus <sakari.ailus@linux.intel.com>
+
+description:
+
+ CCS (Camera Command Set) is a raw Bayer camera sensor standard defined by the
+ MIPI Alliance; see
+ <URL:https://www.mipi.org/specifications/camera-command-set>.
+
+ SMIA (Standard Mobile Imaging Architecture) is an image sensor standard
+ defined jointly by Nokia and ST. SMIA++, defined by Nokia, is an extension of
+ that.
+
+ More detailed documentation can be found in
+ Documentation/devicetree/bindings/media/video-interfaces.txt .
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mipi-ccs-1.1
+ - const: mipi-ccs
+ - items:
+ - const: mipi-ccs-1.0
+ - const: mipi-ccs
+ - const: nokia,smia
+
+ reg:
+ maxItems: 1
+
+ vana-supply:
+ description: Analogue voltage supply (VANA), sensor dependent.
+
+ vcore-supply:
+ description: Core voltage supply (VCore), sensor dependent.
+
+ vio-supply:
+ description: I/O voltage supply (VIO), sensor dependent.
+
+ clocks:
+ description: External clock to the sensor.
+ maxItems: 1
+
+ clock-frequency:
+ description: Frequency of the external clock to the sensor in Hz.
+
+ reset-gpios:
+ description: Reset GPIO. Also commonly called XSHUTDOWN in hardware
+ documentation.
+ maxItems: 1
+
+ flash-leds:
+ description: Flash LED phandles. See ../video-interfaces.txt for details.
+
+ lens-focus:
+ description: Lens focus controller phandles. See ../video-interfaces.txt
+ for details.
+
+ rotation:
+ description: Rotation of the sensor. See ../video-interfaces.txt for
+ details.
+ enum: [ 0, 180 ]
+
+ port:
+ type: object
+ properties:
+ endpoint:
+ type: object
+ properties:
+ link-frequencies:
+ $ref: /schemas/types.yaml#/definitions/uint64-array
+ description: List of allowed data link frequencies.
+ data-lanes:
+ minItems: 1
+ maxItems: 8
+ bus-type:
+ description: The type of the data bus.
+ oneOf:
+ - const: 1 # CSI-2 C-PHY
+ - const: 3 # CCP2
+ - const: 4 # CSI-2 D-PHY
+
+ required:
+ - link-frequencies
+ - data-lanes
+ - bus-type
+
+required:
+ - compatible
+ - reg
+ - clock-frequency
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clock-frequency = <400000>;
+
+ camera-sensor@10 {
+ compatible = "mipi-ccs-1.0", "mipi-ccs";
+ reg = <0x10>;
+ reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
+ vana-supply = <&vaux3>;
+ clocks = <&omap3_isp 0>;
+ clock-frequency = <9600000>;
+ port {
+ ccs_ep: endpoint {
+ data-lanes = <1 2>;
+ remote-endpoint = <&csi2a_ep>;
+ link-frequencies = /bits/ 64 <199200000 210000000
+ 499200000>;
+ bus-type = <4>;
+ };
+ };
+ };
+ };
+...
diff --git a/dts/Bindings/media/i2c/nokia,smia.txt b/dts/Bindings/media/i2c/nokia,smia.txt
deleted file mode 100644
index 10ece81080..0000000000
--- a/dts/Bindings/media/i2c/nokia,smia.txt
+++ /dev/null
@@ -1,66 +0,0 @@
-SMIA/SMIA++ sensor
-
-SMIA (Standard Mobile Imaging Architecture) is an image sensor standard
-defined jointly by Nokia and ST. SMIA++, defined by Nokia, is an extension
-of that. These definitions are valid for both types of sensors.
-
-More detailed documentation can be found in
-Documentation/devicetree/bindings/media/video-interfaces.txt .
-
-The device node should contain a "port" node which may contain one or more
-endpoint nodes, in accordance with video interface bindings defined in
-Documentation/devicetree/bindings/media/video-interfaces.txt .
-
-Mandatory properties
---------------------
-
-- compatible: "nokia,smia"
-- reg: I2C address (0x10, or an alternative address)
-- vana-supply: Analogue voltage supply (VANA), typically 2,8 volts (sensor
- dependent).
-- clocks: External clock to the sensor
-- clock-frequency: Frequency of the external clock to the sensor
-- link-frequencies: List of allowed data link frequencies. An array of
- 64-bit elements.
-
-
-Optional properties
--------------------
-
-- reset-gpios: XSHUTDOWN GPIO
-- flash-leds: See ../video-interfaces.txt
-- lens-focus: See ../video-interfaces.txt
-- rotation: Integer property; valid values are 0 (sensor mounted upright)
- and 180 (sensor mounted upside down). See
- ../video-interfaces.txt .
-
-
-Endpoint node mandatory properties
-----------------------------------
-
-- data-lanes: <1..n>
-
-
-Example
--------
-
-&i2c2 {
- clock-frequency = <400000>;
-
- camera-sensor@10 {
- compatible = "nokia,smia";
- reg = <0x10>;
- reset-gpios = <&gpio3 20 0>;
- vana-supply = <&vaux3>;
- clocks = <&omap3_isp 0>;
- clock-frequency = <9600000>;
- nokia,nvm-size = <512>; /* 8 * 64 */
- link-frequencies = /bits/ 64 <199200000 210000000 499200000>;
- port {
- smiapp_ep: endpoint {
- data-lanes = <1 2>;
- remote-endpoint = <&csi2a_ep>;
- };
- };
- };
-};
diff --git a/dts/Bindings/media/i2c/ov2680.txt b/dts/Bindings/media/i2c/ov2680.txt
deleted file mode 100644
index 11e925ed9d..0000000000
--- a/dts/Bindings/media/i2c/ov2680.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-* Omnivision OV2680 MIPI CSI-2 sensor
-
-Required Properties:
-- compatible: should be "ovti,ov2680".
-- clocks: reference to the xvclk input clock.
-- clock-names: should be "xvclk".
-- DOVDD-supply: Digital I/O voltage supply.
-- DVDD-supply: Digital core voltage supply.
-- AVDD-supply: Analog voltage supply.
-
-Optional Properties:
-- reset-gpios: reference to the GPIO connected to the powerdown/reset pin,
- if any. This is an active low signal to the OV2680.
-
-The device node must contain one 'port' child node for its digital output
-video port, and this port must have a single endpoint in accordance with
- the video interface bindings defined in
-Documentation/devicetree/bindings/media/video-interfaces.txt.
-
-Endpoint node required properties for CSI-2 connection are:
-- remote-endpoint: a phandle to the bus receiver's endpoint node.
-- clock-lanes: should be set to <0> (clock lane on hardware lane 0).
-- data-lanes: should be set to <1> (one CSI-2 lane supported).
-
-Example:
-
-&i2c2 {
- ov2680: camera-sensor@36 {
- compatible = "ovti,ov2680";
- reg = <0x36>;
- clocks = <&osc>;
- clock-names = "xvclk";
- reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
- DOVDD-supply = <&sw2_reg>;
- DVDD-supply = <&sw2_reg>;
- AVDD-supply = <&reg_peri_3p15v>;
-
- port {
- ov2680_to_mipi: endpoint {
- remote-endpoint = <&mipi_from_sensor>;
- clock-lanes = <0>;
- data-lanes = <1>;
- };
- };
- };
-};
diff --git a/dts/Bindings/media/i2c/ov772x.txt b/dts/Bindings/media/i2c/ov772x.txt
deleted file mode 100644
index 0b3ede5b8e..0000000000
--- a/dts/Bindings/media/i2c/ov772x.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-* Omnivision OV7720/OV7725 CMOS sensor
-
-The Omnivision OV7720/OV7725 sensor supports multiple resolutions output,
-such as VGA, QVGA, and any size scaling down from CIF to 40x30. It also can
-support the YUV422, RGB565/555/444, GRB422 or raw RGB output formats.
-
-Required Properties:
-- compatible: shall be one of
- "ovti,ov7720"
- "ovti,ov7725"
-- clocks: reference to the xclk input clock.
-
-Optional Properties:
-- reset-gpios: reference to the GPIO connected to the RSTB pin which is
- active low, if any.
-- powerdown-gpios: reference to the GPIO connected to the PWDN pin which is
- active high, if any.
-
-The device node shall contain one 'port' child node with one child 'endpoint'
-subnode for its digital output video port, in accordance with the video
-interface bindings defined in Documentation/devicetree/bindings/media/
-video-interfaces.txt.
-
-Example:
-
-&i2c0 {
- ov772x: camera@21 {
- compatible = "ovti,ov7725";
- reg = <0x21>;
- reset-gpios = <&axi_gpio_0 0 GPIO_ACTIVE_LOW>;
- powerdown-gpios = <&axi_gpio_0 1 GPIO_ACTIVE_LOW>;
- clocks = <&xclk>;
-
- port {
- ov772x_0: endpoint {
- remote-endpoint = <&vcap1_in0>;
- };
- };
- };
-};
diff --git a/dts/Bindings/media/i2c/ovti,ov02a10.yaml b/dts/Bindings/media/i2c/ovti,ov02a10.yaml
new file mode 100644
index 0000000000..1c3879ec41
--- /dev/null
+++ b/dts/Bindings/media/i2c/ovti,ov02a10.yaml
@@ -0,0 +1,159 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/ovti,ov02a10.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Omnivision OV02A10 CMOS Sensor Device Tree Bindings
+
+maintainers:
+ - Dongchun Zhu <dongchun.zhu@mediatek.com>
+
+description: |-
+ The Omnivision OV02A10 is a low-cost, high performance, 1/5-inch, 2 megapixel
+ image sensor, which is the latest production derived from Omnivision's CMOS
+ image sensor technology. Ihis chip supports high frame rate speeds up to 30fps
+ @ 1600x1200 (UXGA) resolution transferred over a 1-lane MIPI interface. The
+ sensor output is available via CSI-2 serial data output.
+
+properties:
+ compatible:
+ const: ovti,ov02a10
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ description:
+ External clock for the sensor.
+ items:
+ - const: eclk
+
+ clock-frequency:
+ description:
+ Frequency of the eclk clock in Hz.
+
+ dovdd-supply:
+ description:
+ Definition of the regulator used as Digital I/O voltage supply.
+
+ avdd-supply:
+ description:
+ Definition of the regulator used as Analog voltage supply.
+
+ dvdd-supply:
+ description:
+ Definition of the regulator used as Digital core voltage supply.
+
+ powerdown-gpios:
+ description:
+ Must be the device tree identifier of the GPIO connected to the
+ PD_PAD pin. This pin is used to place the OV02A10 into standby mode
+ or shutdown mode. As the line needs to be high for the powerdown mode
+ to be active, it should be marked GPIO_ACTIVE_HIGH.
+ maxItems: 1
+
+ reset-gpios:
+ description:
+ Must be the device tree identifier of the GPIO connected to the
+ RST_PD pin. If specified, it will be asserted during driver probe.
+ As the line needs to be low for the reset to be active, it should be
+ marked GPIO_ACTIVE_LOW.
+ maxItems: 1
+
+ rotation:
+ description:
+ Definition of the sensor's placement.
+ allOf:
+ - $ref: "/schemas/types.yaml#/definitions/uint32"
+ - enum:
+ - 0 # Sensor Mounted Upright
+ - 180 # Sensor Mounted Upside Down
+ default: 0
+
+ # See ../video-interfaces.txt for details
+ port:
+ type: object
+ additionalProperties: false
+ description:
+ Output port node, single endpoint describing the CSI-2 transmitter.
+
+ properties:
+ endpoint:
+ type: object
+ additionalProperties: false
+
+ properties:
+ link-frequencies: true
+ ovti,mipi-clock-voltage:
+ allOf:
+ - $ref: "/schemas/types.yaml#/definitions/uint32"
+ description:
+ Definition of MIPI clock voltage unit. This entry corresponds to
+ the link speed defined by the 'link-frequencies' property.
+ If present, the value shall be in the range of 0-4.
+ default: 4
+ remote-endpoint: true
+
+ required:
+ - link-frequencies
+ - remote-endpoint
+
+ required:
+ - endpoint
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - clock-frequency
+ - dovdd-supply
+ - avdd-supply
+ - dvdd-supply
+ - powerdown-gpios
+ - reset-gpios
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ov02a10: camera-sensor@3d {
+ compatible = "ovti,ov02a10";
+ reg = <0x3d>;
+
+ powerdown-gpios = <&pio 107 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 109 GPIO_ACTIVE_LOW>;
+
+ clocks = <&ov02a10_clk>;
+ clock-names = "eclk";
+ clock-frequency = <24000000>;
+
+ rotation = <180>;
+
+ dovdd-supply = <&ov02a10_dovdd>;
+ avdd-supply = <&ov02a10_avdd>;
+ dvdd-supply = <&ov02a10_dvdd>;
+
+ port {
+ wcam_out: endpoint {
+ link-frequencies = /bits/ 64 <390000000>;
+ ovti,mipi-clock-voltage = <3>;
+ remote-endpoint = <&mipi_in_wcam>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/media/i2c/ovti,ov2680.yaml b/dts/Bindings/media/i2c/ovti,ov2680.yaml
new file mode 100644
index 0000000000..43bf749807
--- /dev/null
+++ b/dts/Bindings/media/i2c/ovti,ov2680.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/ovti,ov2680.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Omnivision OV2680 CMOS Sensor
+
+maintainers:
+ - Rui Miguel Silva <rmfrfs@gmail.com>
+
+description: |-
+ The OV2680 color sensor is a low voltage, high performance 1/5 inch UXGA (2
+ megapixel) CMOS image sensor that provides a single-chip UXGA (1600 x 1200)
+ camera. It provides full-frame, sub-sampled, or windowed 10-bit images in
+ various formats via the control of the Serial Camera Control Bus (SCCB)
+ interface. The OV2680 has an image array capable of operating at up to 30
+ frames per second (fps) in UXGA resolution.
+
+properties:
+ compatible:
+ const: ovti,ov2680
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: xvclk
+
+ reset-gpios:
+ description:
+ The phandle and specifier for the GPIO that controls sensor reset.
+ This corresponds to the hardware pin XSHUTDOWN which is physically
+ active low.
+ maxItems: 1
+
+ dovdd-supply:
+ description:
+ Definition of the regulator used as interface power supply.
+
+ avdd-supply:
+ description:
+ Definition of the regulator used as analog power supply.
+
+ dvdd-supply:
+ description:
+ Definition of the regulator used as digital power supply.
+
+ port:
+ type: object
+ description:
+ A node containing an output port node with an endpoint definition
+ as documented in
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - dovdd-supply
+ - avdd-supply
+ - dvdd-supply
+ - reset-gpios
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ov2680: camera-sensor@36 {
+ compatible = "ovti,ov2680";
+ reg = <0x36>;
+ clocks = <&osc>;
+ clock-names = "xvclk";
+ reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+
+ dovdd-supply = <&sw2_reg>;
+ dvdd-supply = <&sw2_reg>;
+ avdd-supply = <&reg_peri_3p15v>;
+
+ port {
+ ov2680_to_mipi: endpoint {
+ remote-endpoint = <&mipi_from_sensor>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/media/i2c/ovti,ov772x.yaml b/dts/Bindings/media/i2c/ovti,ov772x.yaml
new file mode 100644
index 0000000000..6866c2cdac
--- /dev/null
+++ b/dts/Bindings/media/i2c/ovti,ov772x.yaml
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/ovti,ov772x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Omnivision OV7720/OV7725 CMOS sensor
+
+maintainers:
+ - Jacopo Mondi <jacopo@jmondi.org>
+
+description: |
+ The Omnivision OV7720/OV7725 sensor supports multiple resolutions output,
+ such as VGA, QVGA, and any size scaling down from CIF to 40x30. It also can
+ support the YUV422, RGB565/555/444, GRB422 or raw RGB output formats.
+
+properties:
+ compatible:
+ enum:
+ - ovti,ov7720
+ - ovti,ov7725
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ reset-gpios:
+ description: |
+ Reference to the GPIO connected to the RSTB pin which is active low.
+ maxItems: 1
+
+ powerdown-gpios:
+ description: |
+ Reference to the GPIO connected to the PWDN pin which is active high.
+ maxItems: 1
+
+ port:
+ type: object
+ description: |
+ Video output port. See ../video-interfaces.txt.
+
+ properties:
+ endpoint:
+ type: object
+
+ properties:
+ bus-type:
+ enum: [5, 6]
+
+ bus-width:
+ enum: [8, 10]
+ default: 10
+
+ data-shift:
+ enum: [0, 2]
+ default: 0
+
+ hsync-active:
+ enum: [0, 1]
+ default: 1
+
+ vsync-active:
+ enum: [0, 1]
+ default: 1
+
+ pclk-sample:
+ enum: [0, 1]
+ default: 1
+
+ allOf:
+ - if:
+ properties:
+ bus-type:
+ const: 6
+ then:
+ properties:
+ hsync-active: false
+ vsync-active: false
+
+ - if:
+ properties:
+ bus-width:
+ const: 10
+ then:
+ properties:
+ data-shift:
+ const: 0
+
+ required:
+ - bus-type
+
+ unevaluatedProperties: false
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ov772x: camera@21 {
+ compatible = "ovti,ov7725";
+ reg = <0x21>;
+ reset-gpios = <&axi_gpio_0 0 GPIO_ACTIVE_LOW>;
+ powerdown-gpios = <&axi_gpio_0 1 GPIO_ACTIVE_LOW>;
+ clocks = <&xclk>;
+
+ port {
+ ov772x_0: endpoint {
+ bus-type = <5>;
+ vsync-active = <0>;
+ hsync-active = <0>;
+ pclk-sample = <0>;
+ bus-width = <8>;
+ data-shift = <0>;
+ remote-endpoint = <&vcap1_in0>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/media/i2c/sony,imx214.txt b/dts/Bindings/media/i2c/sony,imx214.txt
deleted file mode 100644
index f11f28a5fd..0000000000
--- a/dts/Bindings/media/i2c/sony,imx214.txt
+++ /dev/null
@@ -1,53 +0,0 @@
-* Sony 1/3.06-Inch 13.13Mp CMOS Digital Image Sensor
-
-The Sony imx214 is a 1/3.06-inch CMOS active pixel digital image sensor with
-an active array size of 4224H x 3200V. It is programmable through an I2C
-interface.
-Image data is sent through MIPI CSI-2, through 2 or 4 lanes at a maximum
-throughput of 1.2Gbps/lane.
-
-
-Required Properties:
-- compatible: Shall be "sony,imx214".
-- reg: I2C bus address of the device. Depending on how the sensor is wired,
- it shall be <0x10> or <0x1a>;
-- enable-gpios: GPIO descriptor for the enable pin.
-- vdddo-supply: Chip digital IO regulator (1.8V).
-- vdda-supply: Chip analog regulator (2.7V).
-- vddd-supply: Chip digital core regulator (1.12V).
-- clocks: Reference to the xclk clock.
-- clock-frequency: Frequency of the xclk clock.
-
-Optional Properties:
-- flash-leds: See ../video-interfaces.txt
-- lens-focus: See ../video-interfaces.txt
-
-The imx214 device node shall contain one 'port' child node with
-an 'endpoint' subnode. For further reading on port node refer to
-Documentation/devicetree/bindings/media/video-interfaces.txt.
-
-Required Properties on endpoint:
-- data-lanes: check ../video-interfaces.txt
-- link-frequencies: check ../video-interfaces.txt
-- remote-endpoint: check ../video-interfaces.txt
-
-Example:
-
- camera-sensor@1a {
- compatible = "sony,imx214";
- reg = <0x1a>;
- vdddo-supply = <&pm8994_lvs1>;
- vddd-supply = <&camera_vddd_1v12>;
- vdda-supply = <&pm8994_l17>;
- lens-focus = <&ad5820>;
- enable-gpios = <&msmgpio 25 GPIO_ACTIVE_HIGH>;
- clocks = <&mmcc CAMSS_MCLK0_CLK>;
- clock-frequency = <24000000>;
- port {
- imx214_ep: endpoint {
- data-lanes = <1 2 3 4>;
- link-frequencies = /bits/ 64 <480000000>;
- remote-endpoint = <&csiphy0_ep>;
- };
- };
- };
diff --git a/dts/Bindings/media/i2c/sony,imx214.yaml b/dts/Bindings/media/i2c/sony,imx214.yaml
new file mode 100644
index 0000000000..eb12526a46
--- /dev/null
+++ b/dts/Bindings/media/i2c/sony,imx214.yaml
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/sony,imx214.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sony 1/3.06-Inch 13.13MP CMOS Digital Image Sensor
+
+maintainers:
+ - Ricardo Ribalda <ribalda@kernel.org>
+
+description: |
+ The Sony IMX214 is a 1/3.06-inch CMOS active pixel digital image sensor with
+ an active array size of 4224H x 3200V. It is programmable through an I2C
+ interface. Image data is sent through MIPI CSI-2, through 2 or 4 lanes at a
+ maximum throughput of 1.2Gbps/lane.
+
+properties:
+ compatible:
+ const: sony,imx214
+
+ reg:
+ enum:
+ - 0x10
+ - 0x1a
+
+ clocks:
+ description: Reference to the xclk clock.
+ maxItems: 1
+
+ clock-frequency:
+ description: Frequency of the xclk clock in Hz.
+
+ enable-gpios:
+ description: GPIO descriptor for the enable pin.
+ maxItems: 1
+
+ vdddo-supply:
+ description: Chip digital IO regulator (1.8V).
+
+ vdda-supply:
+ description: Chip analog regulator (2.7V).
+
+ vddd-supply:
+ description: Chip digital core regulator (1.12V).
+
+ flash-leds:
+ description: See ../video-interfaces.txt
+
+ lens-focus:
+ description: See ../video-interfaces.txt
+
+ port:
+ type: object
+ description: |
+ Video output port. See ../video-interfaces.txt.
+
+ properties:
+ endpoint:
+ type: object
+
+ properties:
+ data-lanes:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: See ../video-interfaces.txt
+ anyOf:
+ - items:
+ - const: 1
+ - const: 2
+ - items:
+ - const: 1
+ - const: 2
+ - const: 3
+ - const: 4
+
+ link-frequencies:
+ $ref: /schemas/types.yaml#/definitions/uint64-array
+ description: See ../video-interfaces.txt
+
+ required:
+ - data-lanes
+ - link-frequencies
+
+ unevaluatedProperties: false
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-frequency
+ - enable-gpios
+ - vdddo-supply
+ - vdda-supply
+ - vddd-supply
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera-sensor@1a {
+ compatible = "sony,imx214";
+ reg = <0x1a>;
+ vdddo-supply = <&pm8994_lvs1>;
+ vddd-supply = <&camera_vddd_1v12>;
+ vdda-supply = <&pm8994_l17>;
+ lens-focus = <&ad5820>;
+ enable-gpios = <&msmgpio 25 GPIO_ACTIVE_HIGH>;
+ clocks = <&camera_clk>;
+ clock-frequency = <24000000>;
+
+ port {
+ imx214_ep: endpoint {
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <480000000>;
+ remote-endpoint = <&csiphy0_ep>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/media/i2c/sony,imx274.yaml b/dts/Bindings/media/i2c/sony,imx274.yaml
index f697e1a20b..a66acb20d5 100644
--- a/dts/Bindings/media/i2c/sony,imx274.yaml
+++ b/dts/Bindings/media/i2c/sony,imx274.yaml
@@ -33,15 +33,12 @@ properties:
vana-supply:
description: Sensor 2.8 V analog supply.
- maxItems: 1
vdig-supply:
description: Sensor 1.8 V digital core supply.
- maxItems: 1
vddl-supply:
description: Sensor digital IO 1.2 V supply.
- maxItems: 1
port:
type: object
diff --git a/dts/Bindings/media/imx7-csi.txt b/dts/Bindings/media/imx7-csi.txt
deleted file mode 100644
index d80ceefa0c..0000000000
--- a/dts/Bindings/media/imx7-csi.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-Freescale i.MX7 CMOS Sensor Interface
-=====================================
-
-csi node
---------
-
-This is device node for the CMOS Sensor Interface (CSI) which enables the chip
-to connect directly to external CMOS image sensors.
-
-Required properties:
-
-- compatible : "fsl,imx7-csi" or "fsl,imx6ul-csi";
-- reg : base address and length of the register set for the device;
-- interrupts : should contain CSI interrupt;
-- clocks : list of clock specifiers, see
- Documentation/devicetree/bindings/clock/clock-bindings.txt for details;
-- clock-names : must contain "mclk";
-
-The device node shall contain one 'port' child node with one child 'endpoint'
-node, according to the bindings defined in:
-Documentation/devicetree/bindings/media/video-interfaces.txt.
-
-In the following example a remote endpoint is a video multiplexer.
-
-example:
-
- csi: csi@30710000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- compatible = "fsl,imx7-csi";
- reg = <0x30710000 0x10000>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_CSI_MCLK_ROOT_CLK>;
- clock-names = "mclk";
-
- port {
- csi_from_csi_mux: endpoint {
- remote-endpoint = <&csi_mux_to_csi>;
- };
- };
- };
diff --git a/dts/Bindings/media/imx7-mipi-csi2.txt b/dts/Bindings/media/imx7-mipi-csi2.txt
deleted file mode 100644
index 71fd74ed3e..0000000000
--- a/dts/Bindings/media/imx7-mipi-csi2.txt
+++ /dev/null
@@ -1,90 +0,0 @@
-Freescale i.MX7 Mipi CSI2
-=========================
-
-mipi_csi2 node
---------------
-
-This is the device node for the MIPI CSI-2 receiver core in i.MX7 SoC. It is
-compatible with previous version of Samsung D-phy.
-
-Required properties:
-
-- compatible : "fsl,imx7-mipi-csi2";
-- reg : base address and length of the register set for the device;
-- interrupts : should contain MIPI CSIS interrupt;
-- clocks : list of clock specifiers, see
- Documentation/devicetree/bindings/clock/clock-bindings.txt for details;
-- clock-names : must contain "pclk", "wrap" and "phy" entries, matching
- entries in the clock property;
-- power-domains : a phandle to the power domain, see
- Documentation/devicetree/bindings/power/power_domain.txt for details.
-- reset-names : should include following entry "mrst";
-- resets : a list of phandle, should contain reset entry of
- reset-names;
-- phy-supply : from the generic phy bindings, a phandle to a regulator that
- provides power to MIPI CSIS core;
-
-Optional properties:
-
-- clock-frequency : The IP's main (system bus) clock frequency in Hz, default
- value when this property is not specified is 166 MHz;
-- fsl,csis-hs-settle : differential receiver (HS-RX) settle time;
-
-The device node should contain two 'port' child nodes with one child 'endpoint'
-node, according to the bindings defined in:
- Documentation/devicetree/bindings/ media/video-interfaces.txt.
- The following are properties specific to those nodes.
-
-port node
----------
-
-- reg : (required) can take the values 0 or 1, where 0 shall be
- related to the sink port and port 1 shall be the source
- one;
-
-endpoint node
--------------
-
-- data-lanes : (required) an array specifying active physical MIPI-CSI2
- data input lanes and their mapping to logical lanes; this
- shall only be applied to port 0 (sink port), the array's
- content is unused only its length is meaningful,
- in this case the maximum length supported is 2;
-
-example:
-
- mipi_csi: mipi-csi@30750000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- compatible = "fsl,imx7-mipi-csi2";
- reg = <0x30750000 0x10000>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_IPG_ROOT_CLK>,
- <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
- <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
- clock-names = "pclk", "wrap", "phy";
- clock-frequency = <166000000>;
- power-domains = <&pgc_mipi_phy>;
- phy-supply = <&reg_1p0d>;
- resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
- reset-names = "mrst";
- fsl,csis-hs-settle = <3>;
-
- port@0 {
- reg = <0>;
-
- mipi_from_sensor: endpoint {
- remote-endpoint = <&ov2680_to_mipi>;
- data-lanes = <1>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- mipi_vc0_to_csi_mux: endpoint {
- remote-endpoint = <&csi_mux_from_mipi_vc0>;
- };
- };
- };
diff --git a/dts/Bindings/media/nxp,imx7-csi.yaml b/dts/Bindings/media/nxp,imx7-csi.yaml
new file mode 100644
index 0000000000..4e81a47e60
--- /dev/null
+++ b/dts/Bindings/media/nxp,imx7-csi.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/nxp,imx7-csi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: i.MX7 CMOS Sensor Interface
+
+maintainers:
+ - Rui Miguel Silva <rmfrfs@gmail.com>
+
+description: |
+ This is device node for the CMOS Sensor Interface (CSI) which enables the
+ chip to connect directly to external CMOS image sensors.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx7-csi
+ - fsl,imx6ul-csi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: mclk
+
+ port:
+ type: object
+ description:
+ A node containing input port nodes with endpoint definitions as documented
+ in Documentation/devicetree/bindings/media/video-interfaces.txt
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx7d-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ csi: csi@30710000 {
+ compatible = "fsl,imx7-csi";
+ reg = <0x30710000 0x10000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_CSI_MCLK_ROOT_CLK>;
+ clock-names = "mclk";
+
+ port {
+ csi_from_csi_mux: endpoint {
+ remote-endpoint = <&csi_mux_to_csi>;
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/media/nxp,imx7-mipi-csi2.yaml b/dts/Bindings/media/nxp,imx7-mipi-csi2.yaml
new file mode 100644
index 0000000000..0668332959
--- /dev/null
+++ b/dts/Bindings/media/nxp,imx7-mipi-csi2.yaml
@@ -0,0 +1,173 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/nxp,imx7-mipi-csi2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX7 Mipi CSI2
+
+maintainers:
+ - Rui Miguel Silva <rmfrfs@gmail.com>
+
+description: |
+ This is the device node for the MIPI CSI-2 receiver core in i.MX7 soc. It is
+ compatible with previous version of samsung d-phy.
+
+properties:
+ compatible:
+ const: fsl,imx7-mipi-csi2
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 3
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: pclk
+ - const: wrap
+ - const: phy
+
+ power-domains:
+ maxItems: 1
+
+ phy-supply:
+ description:
+ Phandle to a regulator that provides power to the PHY. This
+ regulator will be managed during the PHY power on/off sequence.
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: mrst
+
+ clock-frequency:
+ description:
+ The IP main (system bus) clock frequency in Hertz
+ default: 166000000
+
+ fsl,csis-hs-settle:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Differential receiver (HS-RX) settle time
+
+ ports:
+ type: object
+ description:
+ A node containing input and output port nodes with endpoint definitions
+ as documented in
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+
+ properties:
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ port@0:
+ type: object
+ description:
+ Input port node, single endpoint describing the CSI-2 transmitter.
+
+ properties:
+ reg:
+ const: 0
+
+ endpoint:
+ type: object
+
+ properties:
+ data-lanes:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: See ../video-interfaces.txt
+ oneOf:
+ - items:
+ - const: 1
+ - items:
+ - const: 1
+ - const: 2
+
+ remote-endpoint: true
+
+ required:
+ - data-lanes
+ - remote-endpoint
+
+ additionalProperties: false
+
+ additionalProperties: false
+
+ port@1:
+ type: object
+ description:
+ Output port node
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+ - phy-supply
+ - resets
+ - reset-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx7d-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/reset/imx7-reset.h>
+
+ mipi_csi: mipi-csi@30750000 {
+ compatible = "fsl,imx7-mipi-csi2";
+ reg = <0x30750000 0x10000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+ <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
+ <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
+ clock-names = "pclk", "wrap", "phy";
+ clock-frequency = <166000000>;
+
+ power-domains = <&pgc_mipi_phy>;
+ phy-supply = <&reg_1p0d>;
+ resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
+ reset-names = "mrst";
+ fsl,csis-hs-settle = <3>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mipi_from_sensor: endpoint {
+ remote-endpoint = <&ov2680_to_mipi>;
+ data-lanes = <1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_vc0_to_csi_mux: endpoint {
+ remote-endpoint = <&csi_mux_from_mipi_vc0>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/Bindings/media/qcom,camss.txt b/dts/Bindings/media/qcom,camss.txt
index 09eb6ed991..498234629e 100644
--- a/dts/Bindings/media/qcom,camss.txt
+++ b/dts/Bindings/media/qcom,camss.txt
@@ -8,6 +8,7 @@ Qualcomm Camera Subsystem
Definition: Should contain one of:
- "qcom,msm8916-camss"
- "qcom,msm8996-camss"
+ - "qcom,sdm660-camss"
- reg:
Usage: required
Value type: <prop-encoded-array>
@@ -64,30 +65,36 @@ Qualcomm Camera Subsystem
Value type: <stringlist>
Definition: Should contain the following entries:
- "top_ahb"
+ - "throttle_axi" (660 only)
- "ispif_ahb"
- "csiphy0_timer"
- "csiphy1_timer"
- "csiphy2_timer" (8996 only)
+ - "csiphy_ahb2crif" (660 only)
- "csi0_ahb"
- "csi0"
- "csi0_phy"
- "csi0_pix"
- "csi0_rdi"
+ - "cphy_csid0" (660 only)
- "csi1_ahb"
- "csi1"
- "csi1_phy"
- "csi1_pix"
- "csi1_rdi"
+ - "cphy_csid1" (660 only)
- "csi2_ahb" (8996 only)
- "csi2" (8996 only)
- "csi2_phy" (8996 only)
- "csi2_pix" (8996 only)
- "csi2_rdi" (8996 only)
+ - "cphy_csid2" (660 only)
- "csi3_ahb" (8996 only)
- "csi3" (8996 only)
- "csi3_phy" (8996 only)
- "csi3_pix" (8996 only)
- "csi3_rdi" (8996 only)
+ - "cphy_csid3" (660 only)
- "ahb"
- "vfe0"
- "csi_vfe0"
diff --git a/dts/Bindings/media/rc.yaml b/dts/Bindings/media/rc.yaml
index 8ad2cba5f6..946441b4e1 100644
--- a/dts/Bindings/media/rc.yaml
+++ b/dts/Bindings/media/rc.yaml
@@ -83,6 +83,7 @@ properties:
- rc-it913x-v2
- rc-kaiomy
- rc-khadas
+ - rc-khamsin
- rc-kworld-315u
- rc-kworld-pc150u
- rc-kworld-plus-tv-analog
@@ -102,6 +103,7 @@ properties:
- rc-npgtech
- rc-odroid
- rc-pctv-sedna
+ - rc-pine64
- rc-pinnacle-color
- rc-pinnacle-grey
- rc-pinnacle-pctv-hd
diff --git a/dts/Bindings/media/rockchip-isp1.yaml b/dts/Bindings/media/rockchip-isp1.yaml
new file mode 100644
index 0000000000..2004c054ed
--- /dev/null
+++ b/dts/Bindings/media/rockchip-isp1.yaml
@@ -0,0 +1,215 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/rockchip-isp1.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SoC Image Signal Processing unit v1
+
+maintainers:
+ - Helen Koike <helen.koike@collabora.com>
+
+description: |
+ Rockchip ISP1 is the Camera interface for the Rockchip series of SoCs
+ which contains image processing, scaling, and compression functions.
+
+properties:
+ compatible:
+ const: rockchip,rk3399-cif-isp
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 3
+ items:
+ # isp0 and isp1
+ - description: ISP clock
+ - description: ISP AXI clock
+ - description: ISP AHB clock
+ # only for isp1
+ - description: ISP Pixel clock
+
+ clock-names:
+ minItems: 3
+ items:
+ # isp0 and isp1
+ - const: isp
+ - const: aclk
+ - const: hclk
+ # only for isp1
+ - const: pclk_isp
+
+ iommus:
+ maxItems: 1
+
+ phys:
+ maxItems: 1
+ description: phandle for the PHY port
+
+ phy-names:
+ const: dphy
+
+ power-domains:
+ maxItems: 1
+
+ # See ./video-interfaces.txt for details
+ ports:
+ type: object
+ additionalProperties: false
+
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ port@0:
+ type: object
+ description: connection point for sensors at MIPI-DPHY RX0
+ additionalProperties: false
+
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ reg:
+ const: 0
+
+ patternProperties:
+ endpoint:
+ type: object
+ additionalProperties: false
+
+ properties:
+ reg:
+ maxItems: 1
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ remote-endpoint: true
+
+ required:
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+
+ required:
+ - "#address-cells"
+ - "#size-cells"
+ - port@0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - iommus
+ - phys
+ - phy-names
+ - power-domains
+ - ports
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3399-cif-isp
+then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 4
+ clock-names:
+ minItems: 3
+ maxItems: 4
+
+additionalProperties: false
+
+examples:
+ - |
+
+ #include <dt-bindings/clock/rk3399-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/rk3399-power.h>
+
+ parent0: parent {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ isp0: isp0@ff910000 {
+ compatible = "rockchip,rk3399-cif-isp";
+ reg = <0x0 0xff910000 0x0 0x4000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_ISP0>,
+ <&cru ACLK_ISP0_WRAPPER>,
+ <&cru HCLK_ISP0_WRAPPER>;
+ clock-names = "isp", "aclk", "hclk";
+ iommus = <&isp0_mmu>;
+ phys = <&dphy>;
+ phy-names = "dphy";
+ power-domains = <&power RK3399_PD_ISP0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_in_wcam: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&wcam_out>;
+ data-lanes = <1 2>;
+ };
+
+ mipi_in_ucam: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&ucam_out>;
+ data-lanes = <1>;
+ };
+ };
+ };
+ };
+
+ i2c7: i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ wcam: camera@36 {
+ compatible = "ovti,ov5695";
+ reg = <0x36>;
+
+ port {
+ wcam_out: endpoint {
+ remote-endpoint = <&mipi_in_wcam>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
+ ucam: camera@3c {
+ compatible = "ovti,ov2685";
+ reg = <0x3c>;
+
+ port {
+ ucam_out: endpoint {
+ remote-endpoint = <&mipi_in_ucam>;
+ data-lanes = <1>;
+ };
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/media/st,stm32-dcmi.yaml b/dts/Bindings/media/st,stm32-dcmi.yaml
index 3fe778cb5c..c18574bb3e 100644
--- a/dts/Bindings/media/st,stm32-dcmi.yaml
+++ b/dts/Bindings/media/st,stm32-dcmi.yaml
@@ -44,6 +44,43 @@ properties:
bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
+ properties:
+ endpoint:
+ type: object
+
+ properties:
+ bus-type:
+ enum: [5, 6]
+ default: 5
+
+ bus-width:
+ enum: [8, 10, 12, 14]
+ default: 8
+
+ remote-endpoint: true
+
+ allOf:
+ - if:
+ properties:
+ bus-type:
+ const: 6
+
+ then:
+ properties:
+ hsync-active: false
+ vsync-active: false
+ bus-width:
+ enum: [8]
+
+ required:
+ - remote-endpoint
+ - bus-type
+ - pclk-sample
+
+ unevaluatedProperties: false
+
+ additionalProperties: false
+
required:
- compatible
- reg
@@ -75,6 +112,7 @@ examples:
port {
dcmi_0: endpoint {
remote-endpoint = <&ov5640_0>;
+ bus-type = <5>;
bus-width = <8>;
hsync-active = <0>;
vsync-active = <0>;
diff --git a/dts/Bindings/memory-controllers/mediatek,smi-common.txt b/dts/Bindings/memory-controllers/mediatek,smi-common.txt
deleted file mode 100644
index dbafffe3f4..0000000000
--- a/dts/Bindings/memory-controllers/mediatek,smi-common.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-SMI (Smart Multimedia Interface) Common
-
-The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
-
-Mediatek SMI have two generations of HW architecture, here is the list
-which generation the SoCs use:
-generation 1: mt2701 and mt7623.
-generation 2: mt2712, mt6779, mt8167, mt8173 and mt8183.
-
-There's slight differences between the two SMI, for generation 2, the
-register which control the iommu port is at each larb's register base. But
-for generation 1, the register is at smi ao base(smi always on register
-base). Besides that, the smi async clock should be prepared and enabled for
-SMI generation 1 to transform the smi clock into emi clock domain, but that is
-not needed for SMI generation 2.
-
-Required properties:
-- compatible : must be one of :
- "mediatek,mt2701-smi-common"
- "mediatek,mt2712-smi-common"
- "mediatek,mt6779-smi-common"
- "mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
- "mediatek,mt8167-smi-common"
- "mediatek,mt8173-smi-common"
- "mediatek,mt8183-smi-common"
-- reg : the register and size of the SMI block.
-- power-domains : a phandle to the power domain of this local arbiter.
-- clocks : Must contain an entry for each entry in clock-names.
-- clock-names : must contain 3 entries for generation 1 smi HW and 2 entries
- for generation 2 smi HW as follows:
- - "apb" : Advanced Peripheral Bus clock, It's the clock for setting
- the register.
- - "smi" : It's the clock for transfer data and command.
- They may be the same if both source clocks are the same.
- - "async" : asynchronous clock, it help transform the smi clock into the emi
- clock domain, this clock is only needed by generation 1 smi HW.
- and these 2 option clocks for generation 2 smi HW:
- - "gals0": the path0 clock of GALS(Global Async Local Sync).
- - "gals1": the path1 clock of GALS(Global Async Local Sync).
- Here is the list which has this GALS: mt6779 and mt8183.
-
-Example:
- smi_common: smi@14022000 {
- compatible = "mediatek,mt8173-smi-common";
- reg = <0 0x14022000 0 0x1000>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_SMI_COMMON>,
- <&mmsys CLK_MM_SMI_COMMON>;
- clock-names = "apb", "smi";
- };
diff --git a/dts/Bindings/memory-controllers/mediatek,smi-common.yaml b/dts/Bindings/memory-controllers/mediatek,smi-common.yaml
new file mode 100644
index 0000000000..a08a323409
--- /dev/null
+++ b/dts/Bindings/memory-controllers/mediatek,smi-common.yaml
@@ -0,0 +1,142 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SMI (Smart Multimedia Interface) Common
+
+maintainers:
+ - Yong Wu <yong.wu@mediatek.com>
+
+description: |
+ The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
+
+ MediaTek SMI have two generations of HW architecture, here is the list
+ which generation the SoCs use:
+ generation 1: mt2701 and mt7623.
+ generation 2: mt2712, mt6779, mt8167, mt8173, mt8183 and mt8192.
+
+ There's slight differences between the two SMI, for generation 2, the
+ register which control the iommu port is at each larb's register base. But
+ for generation 1, the register is at smi ao base(smi always on register
+ base). Besides that, the smi async clock should be prepared and enabled for
+ SMI generation 1 to transform the smi clock into emi clock domain, but that is
+ not needed for SMI generation 2.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - mediatek,mt2701-smi-common
+ - mediatek,mt2712-smi-common
+ - mediatek,mt6779-smi-common
+ - mediatek,mt8167-smi-common
+ - mediatek,mt8173-smi-common
+ - mediatek,mt8183-smi-common
+ - mediatek,mt8192-smi-common
+
+ - description: for mt7623
+ items:
+ - const: mediatek,mt7623-smi-common
+ - const: mediatek,mt2701-smi-common
+
+ reg:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ description: |
+ apb and smi are mandatory. the async is only for generation 1 smi HW.
+ gals(global async local sync) also is optional, see below.
+ minItems: 2
+ maxItems: 4
+ items:
+ - description: apb is Advanced Peripheral Bus clock, It's the clock for
+ setting the register.
+ - description: smi is the clock for transfer data and command.
+ - description: async is asynchronous clock, it help transform the smi
+ clock into the emi clock domain.
+ - description: gals0 is the path0 clock of gals.
+ - description: gals1 is the path1 clock of gals.
+
+ clock-names:
+ minItems: 2
+ maxItems: 4
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - clocks
+ - clock-names
+
+allOf:
+ - if: # only for gen1 HW
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mediatek,mt2701-smi-common
+ then:
+ properties:
+ clock:
+ items:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: apb
+ - const: smi
+ - const: async
+
+ - if: # for gen2 HW that have gals
+ properties:
+ compatible:
+ enum:
+ - mediatek,mt6779-smi-common
+ - mediatek,mt8183-smi-common
+ - mediatek,mt8192-smi-common
+
+ then:
+ properties:
+ clock:
+ items:
+ minItems: 4
+ maxItems: 4
+ clock-names:
+ items:
+ - const: apb
+ - const: smi
+ - const: gals0
+ - const: gals1
+
+ else: # for gen2 HW that don't have gals
+ properties:
+ clock:
+ items:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: apb
+ - const: smi
+
+additionalProperties: false
+
+examples:
+ - |+
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+
+ smi_common: smi@14022000 {
+ compatible = "mediatek,mt8173-smi-common";
+ reg = <0x14022000 0x1000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_COMMON>;
+ clock-names = "apb", "smi";
+ };
diff --git a/dts/Bindings/memory-controllers/mediatek,smi-larb.txt b/dts/Bindings/memory-controllers/mediatek,smi-larb.txt
deleted file mode 100644
index 0c5de12b54..0000000000
--- a/dts/Bindings/memory-controllers/mediatek,smi-larb.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-SMI (Smart Multimedia Interface) Local Arbiter
-
-The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
-
-Required properties:
-- compatible : must be one of :
- "mediatek,mt2701-smi-larb"
- "mediatek,mt2712-smi-larb"
- "mediatek,mt6779-smi-larb"
- "mediatek,mt7623-smi-larb", "mediatek,mt2701-smi-larb"
- "mediatek,mt8167-smi-larb"
- "mediatek,mt8173-smi-larb"
- "mediatek,mt8183-smi-larb"
-- reg : the register and size of this local arbiter.
-- mediatek,smi : a phandle to the smi_common node.
-- power-domains : a phandle to the power domain of this local arbiter.
-- clocks : Must contain an entry for each entry in clock-names.
-- clock-names: must contain 2 entries, as follows:
- - "apb" : Advanced Peripheral Bus clock, It's the clock for setting
- the register.
- - "smi" : It's the clock for transfer data and command.
- and this optional clock name:
- - "gals": the clock for GALS(Global Async Local Sync).
- Here is the list which has this GALS: mt8183.
-
-Required property for mt2701, mt2712, mt6779, mt7623 and mt8167:
-- mediatek,larb-id :the hardware id of this larb.
-
-Example:
- larb1: larb@16010000 {
- compatible = "mediatek,mt8173-smi-larb";
- reg = <0 0x16010000 0 0x1000>;
- mediatek,smi = <&smi_common>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
- clocks = <&vdecsys CLK_VDEC_CKEN>,
- <&vdecsys CLK_VDEC_LARB_CKEN>;
- clock-names = "apb", "smi";
- };
-
-Example for mt2701:
- larb0: larb@14010000 {
- compatible = "mediatek,mt2701-smi-larb";
- reg = <0 0x14010000 0 0x1000>;
- mediatek,smi = <&smi_common>;
- mediatek,larb-id = <0>;
- clocks = <&mmsys CLK_MM_SMI_LARB0>,
- <&mmsys CLK_MM_SMI_LARB0>;
- clock-names = "apb", "smi";
- power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
- };
diff --git a/dts/Bindings/memory-controllers/mediatek,smi-larb.yaml b/dts/Bindings/memory-controllers/mediatek,smi-larb.yaml
new file mode 100644
index 0000000000..7ed7839ff0
--- /dev/null
+++ b/dts/Bindings/memory-controllers/mediatek,smi-larb.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-larb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SMI (Smart Multimedia Interface) Local Arbiter
+
+maintainers:
+ - Yong Wu <yong.wu@mediatek.com>
+
+description: |
+ The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - mediatek,mt2701-smi-larb
+ - mediatek,mt2712-smi-larb
+ - mediatek,mt6779-smi-larb
+ - mediatek,mt8167-smi-larb
+ - mediatek,mt8173-smi-larb
+ - mediatek,mt8183-smi-larb
+ - mediatek,mt8192-smi-larb
+
+ - description: for mt7623
+ items:
+ - const: mediatek,mt7623-smi-larb
+ - const: mediatek,mt2701-smi-larb
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description: |
+ apb and smi are mandatory. gals(global async local sync) is optional.
+ minItems: 2
+ maxItems: 3
+ items:
+ - description: apb is Advanced Peripheral Bus clock, It's the clock for
+ setting the register.
+ - description: smi is the clock for transfer data and command.
+ - description: the clock for gals.
+
+ clock-names:
+ minItems: 2
+ maxItems: 3
+
+ power-domains:
+ maxItems: 1
+
+ mediatek,smi:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: a phandle to the smi_common node.
+
+ mediatek,larb-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 31
+ description: the hardware id of this larb. It's only required when this
+ hardward id is not consecutive from its M4U point of view.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - power-domains
+
+allOf:
+ - if: # HW has gals
+ properties:
+ compatible:
+ enum:
+ - mediatek,mt8183-smi-larb
+
+ then:
+ properties:
+ clock:
+ items:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: apb
+ - const: smi
+ - const: gals
+
+ else:
+ properties:
+ clock:
+ items:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: apb
+ - const: smi
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mediatek,mt2701-smi-larb
+ - mediatek,mt2712-smi-larb
+ - mediatek,mt6779-smi-larb
+ - mediatek,mt8167-smi-larb
+ - mediatek,mt8192-smi-larb
+
+ then:
+ required:
+ - mediatek,larb-id
+
+additionalProperties: false
+
+examples:
+ - |+
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+
+ larb1: larb@16010000 {
+ compatible = "mediatek,mt8173-smi-larb";
+ reg = <0x16010000 0x1000>;
+ mediatek,smi = <&smi_common>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
+ clocks = <&vdecsys CLK_VDEC_CKEN>,
+ <&vdecsys CLK_VDEC_LARB_CKEN>;
+ clock-names = "apb", "smi";
+ };
diff --git a/dts/Bindings/memory-controllers/nvidia,tegra124-emc.yaml b/dts/Bindings/memory-controllers/nvidia,tegra124-emc.yaml
index 278549f9e0..09bde65e19 100644
--- a/dts/Bindings/memory-controllers/nvidia,tegra124-emc.yaml
+++ b/dts/Bindings/memory-controllers/nvidia,tegra124-emc.yaml
@@ -29,11 +29,23 @@ properties:
items:
- const: emc
+ "#interconnect-cells":
+ const: 0
+
nvidia,memory-controller:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle of the memory controller node
+ core-supply:
+ description:
+ Phandle of voltage regulator of the SoC "core" power domain.
+
+ operating-points-v2:
+ description:
+ Should contain freqs and voltages and opp-supported-hw property, which
+ is a bitfield indicating SoC speedo ID mask.
+
patternProperties:
"^emc-timings-[0-9]+$":
type: object
@@ -327,6 +339,8 @@ required:
- clocks
- clock-names
- nvidia,memory-controller
+ - "#interconnect-cells"
+ - operating-points-v2
additionalProperties: false
@@ -345,6 +359,7 @@ examples:
#iommu-cells = <1>;
#reset-cells = <1>;
+ #interconnect-cells = <1>;
};
external-memory-controller@7001b000 {
@@ -354,6 +369,10 @@ examples:
clock-names = "emc";
nvidia,memory-controller = <&mc>;
+ operating-points-v2 = <&dvfs_opp_table>;
+ core-supply = <&vdd_core>;
+
+ #interconnect-cells = <0>;
emc-timings-0 {
nvidia,ram-code = <3>;
diff --git a/dts/Bindings/memory-controllers/nvidia,tegra124-mc.yaml b/dts/Bindings/memory-controllers/nvidia,tegra124-mc.yaml
index 84d0339505..7b18b4d11e 100644
--- a/dts/Bindings/memory-controllers/nvidia,tegra124-mc.yaml
+++ b/dts/Bindings/memory-controllers/nvidia,tegra124-mc.yaml
@@ -40,6 +40,9 @@ properties:
"#iommu-cells":
const: 1
+ "#interconnect-cells":
+ const: 1
+
patternProperties:
"^emc-timings-[0-9]+$":
type: object
@@ -104,6 +107,7 @@ required:
- clock-names
- "#reset-cells"
- "#iommu-cells"
+ - "#interconnect-cells"
additionalProperties: false
@@ -119,6 +123,7 @@ examples:
#iommu-cells = <1>;
#reset-cells = <1>;
+ #interconnect-cells = <1>;
emc-timings-3 {
nvidia,ram-code = <3>;
diff --git a/dts/Bindings/memory-controllers/nvidia,tegra20-emc.txt b/dts/Bindings/memory-controllers/nvidia,tegra20-emc.txt
index add9536764..cc443fcf4b 100644
--- a/dts/Bindings/memory-controllers/nvidia,tegra20-emc.txt
+++ b/dts/Bindings/memory-controllers/nvidia,tegra20-emc.txt
@@ -12,18 +12,44 @@ Properties:
irrespective of ram-code configuration.
- interrupts : Should contain EMC General interrupt.
- clocks : Should contain EMC clock.
+- nvidia,memory-controller : Phandle of the Memory Controller node.
+- #interconnect-cells : Should be 0.
+- operating-points-v2: See ../bindings/opp/opp.txt for details.
+
+For each opp entry in 'operating-points-v2' table:
+- opp-supported-hw: One bitfield indicating SoC process ID mask
+
+ A bitwise AND is performed against this value and if any bit
+ matches, the OPP gets enabled.
+
+Optional properties:
+- core-supply: Phandle of voltage regulator of the SoC "core" power domain.
Child device nodes describe the memory settings for different configurations and clock rates.
Example:
+ opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp@36000000 {
+ opp-microvolt = <950000 950000 1300000>;
+ opp-hz = /bits/ 64 <36000000>;
+ };
+ ...
+ };
+
memory-controller@7000f400 {
#address-cells = < 1 >;
#size-cells = < 0 >;
+ #interconnect-cells = <0>;
compatible = "nvidia,tegra20-emc";
- reg = <0x7000f4000 0x200>;
+ reg = <0x7000f400 0x400>;
interrupts = <0 78 0x04>;
clocks = <&tegra_car TEGRA20_CLK_EMC>;
+ nvidia,memory-controller = <&mc>;
+ core-supply = <&core_vdd_reg>;
+ operating-points-v2 = <&opp_table>;
}
diff --git a/dts/Bindings/memory-controllers/nvidia,tegra20-mc.txt b/dts/Bindings/memory-controllers/nvidia,tegra20-mc.txt
index e55328237d..739b7c6f2e 100644
--- a/dts/Bindings/memory-controllers/nvidia,tegra20-mc.txt
+++ b/dts/Bindings/memory-controllers/nvidia,tegra20-mc.txt
@@ -16,6 +16,8 @@ Required properties:
IOMMU specifier needed to encode an address. GART supports only a single
address space that is shared by all devices, therefore no additional
information needed for the address encoding.
+- #interconnect-cells : Should be 1. This cell represents memory client.
+ The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h>.
Example:
mc: memory-controller@7000f000 {
@@ -27,6 +29,7 @@ Example:
interrupts = <GIC_SPI 77 0x04>;
#reset-cells = <1>;
#iommu-cells = <0>;
+ #interconnect-cells = <1>;
};
video-codec@6001a000 {
diff --git a/dts/Bindings/memory-controllers/nvidia,tegra30-emc.yaml b/dts/Bindings/memory-controllers/nvidia,tegra30-emc.yaml
index 112bae2fcb..0a2e2c0d0f 100644
--- a/dts/Bindings/memory-controllers/nvidia,tegra30-emc.yaml
+++ b/dts/Bindings/memory-controllers/nvidia,tegra30-emc.yaml
@@ -31,11 +31,23 @@ properties:
interrupts:
maxItems: 1
+ "#interconnect-cells":
+ const: 0
+
nvidia,memory-controller:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle of the Memory Controller node.
+ core-supply:
+ description:
+ Phandle of voltage regulator of the SoC "core" power domain.
+
+ operating-points-v2:
+ description:
+ Should contain freqs and voltages and opp-supported-hw property, which
+ is a bitfield indicating SoC speedo ID mask.
+
patternProperties:
"^emc-timings-[0-9]+$":
type: object
@@ -214,6 +226,8 @@ required:
- interrupts
- clocks
- nvidia,memory-controller
+ - "#interconnect-cells"
+ - operating-points-v2
additionalProperties: false
@@ -226,6 +240,10 @@ examples:
clocks = <&tegra_car 57>;
nvidia,memory-controller = <&mc>;
+ operating-points-v2 = <&dvfs_opp_table>;
+ core-supply = <&vdd_core>;
+
+ #interconnect-cells = <0>;
emc-timings-1 {
nvidia,ram-code = <1>;
diff --git a/dts/Bindings/memory-controllers/nvidia,tegra30-mc.yaml b/dts/Bindings/memory-controllers/nvidia,tegra30-mc.yaml
index 84fd57bcf0..5436e6d420 100644
--- a/dts/Bindings/memory-controllers/nvidia,tegra30-mc.yaml
+++ b/dts/Bindings/memory-controllers/nvidia,tegra30-mc.yaml
@@ -57,6 +57,9 @@ properties:
"#iommu-cells":
const: 1
+ "#interconnect-cells":
+ const: 1
+
patternProperties:
"^emc-timings-[0-9]+$":
type: object
@@ -120,6 +123,7 @@ required:
- clock-names
- "#reset-cells"
- "#iommu-cells"
+ - "#interconnect-cells"
additionalProperties: false
@@ -135,6 +139,7 @@ examples:
#iommu-cells = <1>;
#reset-cells = <1>;
+ #interconnect-cells = <1>;
emc-timings-1 {
nvidia,ram-code = <1>;
diff --git a/dts/Bindings/mfd/aspeed-lpc.txt b/dts/Bindings/mfd/aspeed-lpc.txt
index a92acf1dd4..d0a38ba8b9 100644
--- a/dts/Bindings/mfd/aspeed-lpc.txt
+++ b/dts/Bindings/mfd/aspeed-lpc.txt
@@ -46,6 +46,7 @@ Required properties
- compatible: One of:
"aspeed,ast2400-lpc", "simple-mfd"
"aspeed,ast2500-lpc", "simple-mfd"
+ "aspeed,ast2600-lpc", "simple-mfd"
- reg: contains the physical address and length values of the Aspeed
LPC memory region.
@@ -64,6 +65,7 @@ BMC Node
- compatible: One of:
"aspeed,ast2400-lpc-bmc"
"aspeed,ast2500-lpc-bmc"
+ "aspeed,ast2600-lpc-bmc"
- reg: contains the physical address and length values of the
H8S/2168-compatible LPC controller memory region
@@ -74,6 +76,7 @@ Host Node
- compatible: One of:
"aspeed,ast2400-lpc-host", "simple-mfd", "syscon"
"aspeed,ast2500-lpc-host", "simple-mfd", "syscon"
+ "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"
- reg: contains the address and length values of the host-related
register space for the Aspeed LPC controller
@@ -128,6 +131,7 @@ Required properties:
- compatible: One of:
"aspeed,ast2400-lpc-ctrl";
"aspeed,ast2500-lpc-ctrl";
+ "aspeed,ast2600-lpc-ctrl";
- reg: contains offset/length values of the host interface controller
memory regions
@@ -168,6 +172,7 @@ Required properties:
- compatible: One of:
"aspeed,ast2400-lhc";
"aspeed,ast2500-lhc";
+ "aspeed,ast2600-lhc";
- reg: contains offset/length values of the LHC memory regions. In the
AST2400 and AST2500 there are two regions.
@@ -187,7 +192,8 @@ state of the LPC bus. Some systems may chose to modify this configuration.
Required properties:
- - compatible: "aspeed,ast2500-lpc-reset" or
+ - compatible: "aspeed,ast2600-lpc-reset" or
+ "aspeed,ast2500-lpc-reset"
"aspeed,ast2400-lpc-reset"
- reg: offset and length of the IP in the LHC memory region
- #reset-controller indicates the number of reset cells expected
diff --git a/dts/Bindings/mfd/aspeed-scu.txt b/dts/Bindings/mfd/aspeed-scu.txt
index 4d92c0bb66..857ee33f73 100644
--- a/dts/Bindings/mfd/aspeed-scu.txt
+++ b/dts/Bindings/mfd/aspeed-scu.txt
@@ -20,3 +20,29 @@ syscon: syscon@1e6e2000 {
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+Silicon ID
+-----------------
+
+Families have unique hardware silicon identifiers within the SoC.
+
+Required properties:
+
+ - compatible: "aspeed,silicon-id" or:
+ "aspeed,ast2400-silicon-id" or
+ "aspeed,ast2500-silicon-id" or
+ "aspeed,ast2600-silicon-id"
+
+ - reg: offset and length of the silicon id information
+ optionally, a second offset and length describes the unique chip id
+
+ The reg should be the unique silicon id register, and
+ not backwards compatible one in eg. the 2600.
+
+Example:
+
+
+silicon-id@7c {
+ compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id";
+ reg = <0x7c 0x4 0x150 0x8>;
+};
diff --git a/dts/Bindings/mfd/rohm,bd71837-pmic.yaml b/dts/Bindings/mfd/rohm,bd71837-pmic.yaml
index 65018a019e..3bfdd33702 100644
--- a/dts/Bindings/mfd/rohm,bd71837-pmic.yaml
+++ b/dts/Bindings/mfd/rohm,bd71837-pmic.yaml
@@ -32,9 +32,15 @@ properties:
clocks:
maxItems: 1
+ clock-names:
+ const: osc
+
"#clock-cells":
const: 0
+ clock-output-names:
+ const: pmic_clk
+
# The BD718x7 supports two different HW states as reset target states. States
# are called as SNVS and READY. At READY state all the PMIC power outputs go
# down and OTP is reload. At the SNVS state all other logic and external
diff --git a/dts/Bindings/mfd/st,stm32-timers.yaml b/dts/Bindings/mfd/st,stm32-timers.yaml
index f212fc6e16..0f16c8864a 100644
--- a/dts/Bindings/mfd/st,stm32-timers.yaml
+++ b/dts/Bindings/mfd/st,stm32-timers.yaml
@@ -131,7 +131,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/stm32mp1-clks.h>
- timers2: timers@40000000 {
+ timers2: timer@40000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
@@ -149,9 +149,9 @@ examples:
#pwm-cells = <3>;
st,breakinput = <0 1 5>;
};
- timer@0 {
+ timer@1 {
compatible = "st,stm32-timer-trigger";
- reg = <0>;
+ reg = <1>;
};
counter {
compatible = "st,stm32-timer-counter";
diff --git a/dts/Bindings/mfd/st,stmfx.yaml b/dts/Bindings/mfd/st,stmfx.yaml
index 888ab4b5df..19e9afb385 100644
--- a/dts/Bindings/mfd/st,stmfx.yaml
+++ b/dts/Bindings/mfd/st,stmfx.yaml
@@ -26,8 +26,7 @@ properties:
drive-open-drain: true
- vdd-supply:
- maxItems: 1
+ vdd-supply: true
pinctrl:
type: object
diff --git a/dts/Bindings/mfd/syscon.yaml b/dts/Bindings/mfd/syscon.yaml
index 8f4764a9ed..f14ae6da00 100644
--- a/dts/Bindings/mfd/syscon.yaml
+++ b/dts/Bindings/mfd/syscon.yaml
@@ -44,6 +44,10 @@ properties:
- hisilicon,peri-subctrl
- microchip,sparx5-cpu-syscon
- mstar,msc313-pmsleep
+ - rockchip,px30-qos
+ - rockchip,rk3066-qos
+ - rockchip,rk3288-qos
+ - rockchip,rk3399-qos
- samsung,exynos3-sysreg
- samsung,exynos4-sysreg
- samsung,exynos5-sysreg
diff --git a/dts/Bindings/mips/mscc.txt b/dts/Bindings/mips/mscc.txt
index bc817e9846..cc916eaeed 100644
--- a/dts/Bindings/mips/mscc.txt
+++ b/dts/Bindings/mips/mscc.txt
@@ -4,7 +4,7 @@ Boards with a SoC of the Microsemi MIPS family shall have the following
properties:
Required properties:
-- compatible: "mscc,ocelot"
+- compatible: "mscc,ocelot", "mscc,luton", "mscc,serval" or "mscc,jr2"
* Other peripherals:
diff --git a/dts/Bindings/misc/fsl,dpaa2-console.txt b/dts/Bindings/misc/fsl,dpaa2-console.txt
deleted file mode 100644
index 1442ba5d2d..0000000000
--- a/dts/Bindings/misc/fsl,dpaa2-console.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-DPAA2 console support
-
-Required properties:
-
- - compatible
- Value type: <string>
- Definition: Must be "fsl,dpaa2-console".
- - reg
- Value type: <prop-encoded-array>
- Definition: A standard property. Specifies the region where the MCFBA
- (MC firmware base address) register can be found.
diff --git a/dts/Bindings/misc/fsl,dpaa2-console.yaml b/dts/Bindings/misc/fsl,dpaa2-console.yaml
new file mode 100644
index 0000000000..271a3eafc0
--- /dev/null
+++ b/dts/Bindings/misc/fsl,dpaa2-console.yaml
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2020 NXP
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/fsl,dpaa2-console.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: DPAA2 console support
+
+maintainers:
+ - Laurentiu Tudor <laurentiu.tudor@nxp.com>
+
+properties:
+ compatible:
+ const: "fsl,dpaa2-console"
+
+ reg:
+ description: A standard property. Specifies the region where the MCFBA
+ (MC firmware base address) register can be found.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
diff --git a/dts/Bindings/mmc/arasan,sdhci.yaml b/dts/Bindings/mmc/arasan,sdhci.yaml
index 0753289fba..37a5fe7b26 100644
--- a/dts/Bindings/mmc/arasan,sdhci.yaml
+++ b/dts/Bindings/mmc/arasan,sdhci.yaml
@@ -147,7 +147,7 @@ properties:
xlnx,mio-bank:
$ref: /schemas/types.yaml#/definitions/uint32
- enum: [0, 2]
+ enum: [0, 1, 2]
default: 0
description:
The MIO bank number in which the command and data lines are configured.
diff --git a/dts/Bindings/mmc/fsl-imx-esdhc.yaml b/dts/Bindings/mmc/fsl-imx-esdhc.yaml
index e71d13c2d1..802c9df237 100644
--- a/dts/Bindings/mmc/fsl-imx-esdhc.yaml
+++ b/dts/Bindings/mmc/fsl-imx-esdhc.yaml
@@ -39,6 +39,7 @@ properties:
- fsl,imx8mn-usdhc
- fsl,imx8mp-usdhc
- fsl,imx8mq-usdhc
+ - fsl,imx8qm-usdhc
- fsl,imx8qxp-usdhc
- const: fsl,imx7d-usdhc
diff --git a/dts/Bindings/mmc/mtk-sd.txt b/dts/Bindings/mmc/mtk-sd.txt
deleted file mode 100644
index 26a8f320a1..0000000000
--- a/dts/Bindings/mmc/mtk-sd.txt
+++ /dev/null
@@ -1,75 +0,0 @@
-* MTK MMC controller
-
-The MTK MSDC can act as a MMC controller
-to support MMC, SD, and SDIO types of memory cards.
-
-This file documents differences between the core properties in mmc.txt
-and the properties used by the msdc driver.
-
-Required properties:
-- compatible: value should be either of the following.
- "mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
- "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
- "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183
- "mediatek,mt8516-mmc": for mmc host ip compatible with mt8516
- "mediatek,mt6779-mmc": for mmc host ip compatible with mt6779
- "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
- "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
- "mediatek,mt7622-mmc": for MT7622 SoC
- "mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC
- "mediatek,mt7620-mmc", for MT7621 SoC (and others)
-
-- reg: physical base address of the controller and length
-- interrupts: Should contain MSDC interrupt number
-- clocks: Should contain phandle for the clock feeding the MMC controller
-- clock-names: Should contain the following:
- "source" - source clock (required)
- "hclk" - HCLK which used for host (required)
- "source_cg" - independent source clock gate (required for MT2712)
- "bus_clk" - bus clock used for internal register access (required for MT2712 MSDC0/3)
-- pinctrl-names: should be "default", "state_uhs"
-- pinctrl-0: should contain default/high speed pin ctrl
-- pinctrl-1: should contain uhs mode pin ctrl
-- vmmc-supply: power to the Core
-- vqmmc-supply: power to the IO
-
-Optional properties:
-- assigned-clocks: PLL of the source clock
-- assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock
-- hs400-ds-delay: HS400 DS delay setting
-- mediatek,hs200-cmd-int-delay: HS200 command internal delay setting.
- This field has total 32 stages.
- The value is an integer from 0 to 31.
-- mediatek,hs400-cmd-int-delay: HS400 command internal delay setting
- This field has total 32 stages.
- The value is an integer from 0 to 31.
-- mediatek,hs400-cmd-resp-sel-rising: HS400 command response sample selection
- If present,HS400 command responses are sampled on rising edges.
- If not present,HS400 command responses are sampled on falling edges.
-- mediatek,latch-ck: Some SoCs do not support enhance_rx, need set correct latch-ck to avoid data crc
- error caused by stop clock(fifo full)
- Valid range = [0:0x7]. if not present, default value is 0.
- applied to compatible "mediatek,mt2701-mmc".
-- resets: Phandle and reset specifier pair to softreset line of MSDC IP.
-- reset-names: Should be "hrst".
-
-Examples:
-mmc0: mmc@11230000 {
- compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc";
- reg = <0 0x11230000 0 0x108>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
- vmmc-supply = <&mt6397_vemc_3v3_reg>;
- vqmmc-supply = <&mt6397_vio18_reg>;
- clocks = <&pericfg CLK_PERI_MSDC30_0>,
- <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
- clock-names = "source", "hclk";
- pinctrl-names = "default", "state_uhs";
- pinctrl-0 = <&mmc0_pins_default>;
- pinctrl-1 = <&mmc0_pins_uhs>;
- assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
- hs400-ds-delay = <0x14015>;
- mediatek,hs200-cmd-int-delay = <26>;
- mediatek,hs400-cmd-int-delay = <14>;
- mediatek,hs400-cmd-resp-sel-rising;
-};
diff --git a/dts/Bindings/mmc/mtk-sd.yaml b/dts/Bindings/mmc/mtk-sd.yaml
new file mode 100644
index 0000000000..01630b0ece
--- /dev/null
+++ b/dts/Bindings/mmc/mtk-sd.yaml
@@ -0,0 +1,176 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MTK MSDC Storage Host Controller Binding
+
+maintainers:
+ - Chaotian Jing <chaotian.jing@mediatek.com>
+ - Wenbin Mei <wenbin.mei@mediatek.com>
+
+allOf:
+ - $ref: mmc-controller.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - mediatek,mt2701-mmc
+ - mediatek,mt2712-mmc
+ - mediatek,mt6779-mmc
+ - mediatek,mt7620-mmc
+ - mediatek,mt7622-mmc
+ - mediatek,mt8135-mmc
+ - mediatek,mt8173-mmc
+ - mediatek,mt8183-mmc
+ - mediatek,mt8516-mmc
+ - items:
+ - const: mediatek,mt7623-mmc
+ - const: mediatek,mt2701-mmc
+ - items:
+ - const: mediatek,mt8192-mmc
+ - const: mediatek,mt8183-mmc
+
+ clocks:
+ description:
+ Should contain phandle for the clock feeding the MMC controller.
+ minItems: 2
+ maxItems: 8
+ items:
+ - description: source clock (required).
+ - description: HCLK which used for host (required).
+ - description: independent source clock gate (required for MT2712).
+ - description: bus clock used for internal register access (required for MT2712 MSDC0/3).
+ - description: msdc subsys clock gate (required for MT8192).
+ - description: peripheral bus clock gate (required for MT8192).
+ - description: AXI bus clock gate (required for MT8192).
+ - description: AHB bus clock gate (required for MT8192).
+
+ clock-names:
+ minItems: 2
+ maxItems: 8
+ items:
+ - const: source
+ - const: hclk
+ - const: source_cg
+ - const: bus_clk
+ - const: sys_cg
+ - const: pclk_cg
+ - const: axi_cg
+ - const: ahb_cg
+
+ pinctrl-names:
+ items:
+ - const: default
+ - const: state_uhs
+
+ pinctrl-0:
+ description:
+ should contain default/high speed pin ctrl.
+ maxItems: 1
+
+ pinctrl-1:
+ description:
+ should contain uhs mode pin ctrl.
+ maxItems: 1
+
+ assigned-clocks:
+ description:
+ PLL of the source clock.
+ maxItems: 1
+
+ assigned-clock-parents:
+ description:
+ parent of source clock, used for HS400 mode to get 400Mhz source clock.
+ maxItems: 1
+
+ hs400-ds-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ HS400 DS delay setting.
+ minimum: 0
+ maximum: 0xffffffff
+
+ mediatek,hs200-cmd-int-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ HS200 command internal delay setting.
+ This field has total 32 stages.
+ The value is an integer from 0 to 31.
+ minimum: 0
+ maximum: 31
+
+ mediatek,hs400-cmd-int-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ HS400 command internal delay setting.
+ This field has total 32 stages.
+ The value is an integer from 0 to 31.
+ minimum: 0
+ maximum: 31
+
+ mediatek,hs400-cmd-resp-sel-rising:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ HS400 command response sample selection.
+ If present, HS400 command responses are sampled on rising edges.
+ If not present, HS400 command responses are sampled on falling edges.
+
+ mediatek,latch-ck:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
+ data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
+ if not present, default value is 0.
+ applied to compatible "mediatek,mt2701-mmc".
+ minimum: 0
+ maximum: 7
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: hrst
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - pinctrl-names
+ - pinctrl-0
+ - pinctrl-1
+ - vmmc-supply
+ - vqmmc-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8173-clk.h>
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8173-mmc";
+ reg = <0x11230000 0x1000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
+ vmmc-supply = <&mt6397_vemc_3v3_reg>;
+ vqmmc-supply = <&mt6397_vio18_reg>;
+ clocks = <&pericfg CLK_PERI_MSDC30_0>,
+ <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
+ clock-names = "source", "hclk";
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_default>;
+ pinctrl-1 = <&mmc0_pins_uhs>;
+ assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
+ hs400-ds-delay = <0x14015>;
+ mediatek,hs200-cmd-int-delay = <26>;
+ mediatek,hs400-cmd-int-delay = <14>;
+ mediatek,hs400-cmd-resp-sel-rising;
+ };
+
+...
diff --git a/dts/Bindings/mmc/owl-mmc.yaml b/dts/Bindings/mmc/owl-mmc.yaml
index b6ab527087..b0d81ebe0f 100644
--- a/dts/Bindings/mmc/owl-mmc.yaml
+++ b/dts/Bindings/mmc/owl-mmc.yaml
@@ -17,7 +17,9 @@ properties:
oneOf:
- const: actions,owl-mmc
- items:
- - const: actions,s700-mmc
+ - enum:
+ - actions,s500-mmc
+ - actions,s700-mmc
- const: actions,owl-mmc
reg:
diff --git a/dts/Bindings/mtd/gpmi-nand.yaml b/dts/Bindings/mtd/gpmi-nand.yaml
index 28ff8c5818..9d764e654e 100644
--- a/dts/Bindings/mtd/gpmi-nand.yaml
+++ b/dts/Bindings/mtd/gpmi-nand.yaml
@@ -9,9 +9,6 @@ title: Freescale General-Purpose Media Interface (GPMI) binding
maintainers:
- Han Xu <han.xu@nxp.com>
-allOf:
- - $ref: "nand-controller.yaml"
-
description: |
The GPMI nand controller provides an interface to control the NAND
flash chips. The device tree may optionally contain sub-nodes
@@ -58,22 +55,10 @@ properties:
clocks:
minItems: 1
maxItems: 5
- items:
- - description: SoC gpmi io clock
- - description: SoC gpmi apb clock
- - description: SoC gpmi bch clock
- - description: SoC gpmi bch apb clock
- - description: SoC per1 bch clock
clock-names:
minItems: 1
maxItems: 5
- items:
- - const: gpmi_io
- - const: gpmi_apb
- - const: gpmi_bch
- - const: gpmi_bch_apb
- - const: per1_bch
fsl,use-minimum-ecc:
type: boolean
@@ -107,6 +92,67 @@ required:
unevaluatedProperties: false
+allOf:
+ - $ref: "nand-controller.yaml"
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx23-gpmi-nand
+ - fsl,imx28-gpmi-nand
+ then:
+ properties:
+ clocks:
+ items:
+ - description: SoC gpmi io clock
+ clock-names:
+ items:
+ - const: gpmi_io
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx6q-gpmi-nand
+ - fsl,imx6sx-gpmi-nand
+ then:
+ properties:
+ clocks:
+ items:
+ - description: SoC gpmi io clock
+ - description: SoC gpmi apb clock
+ - description: SoC gpmi bch clock
+ - description: SoC gpmi bch apb clock
+ - description: SoC per1 bch clock
+ clock-names:
+ items:
+ - const: gpmi_io
+ - const: gpmi_apb
+ - const: gpmi_bch
+ - const: gpmi_bch_apb
+ - const: per1_bch
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx7d-gpmi-nand
+ then:
+ properties:
+ clocks:
+ items:
+ - description: SoC gpmi io clock
+ - description: SoC gpmi bch apb clock
+ clock-names:
+ minItems: 2
+ maxItems: 2
+ items:
+ - const: gpmi_io
+ - const: gpmi_bch_apb
+
examples:
- |
nand-controller@8000c000 {
diff --git a/dts/Bindings/mtd/intel,lgm-nand.yaml b/dts/Bindings/mtd/intel,lgm-nand.yaml
new file mode 100644
index 0000000000..30e0c66ab0
--- /dev/null
+++ b/dts/Bindings/mtd/intel,lgm-nand.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/intel,lgm-nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel LGM SoC NAND Controller Device Tree Bindings
+
+allOf:
+ - $ref: "nand-controller.yaml"
+
+maintainers:
+ - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
+
+properties:
+ compatible:
+ const: intel,lgm-nand
+
+ reg:
+ maxItems: 6
+
+ reg-names:
+ items:
+ - const: ebunand
+ - const: hsnand
+ - const: nand_cs0
+ - const: nand_cs1
+ - const: addr_sel0
+ - const: addr_sel1
+
+ clocks:
+ maxItems: 1
+
+ dmas:
+ maxItems: 2
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+patternProperties:
+ "^nand@[a-f0-9]+$":
+ type: object
+ properties:
+ reg:
+ minimum: 0
+ maximum: 7
+
+ nand-ecc-mode: true
+
+ nand-ecc-algo:
+ const: hw
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - dmas
+ - dma-names
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ nand-controller@e0f00000 {
+ compatible = "intel,lgm-nand";
+ reg = <0xe0f00000 0x100>,
+ <0xe1000000 0x300>,
+ <0xe1400000 0x8000>,
+ <0xe1c00000 0x1000>,
+ <0x17400000 0x4>,
+ <0x17c00000 0x4>;
+ reg-names = "ebunand", "hsnand", "nand_cs0", "nand_cs1",
+ "addr_sel0", "addr_sel1";
+ clocks = <&cgu0 125>;
+ dmas = <&dma0 8>, <&dma0 9>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-mode = "hw";
+ };
+ };
+
+...
diff --git a/dts/Bindings/mtd/nand-controller.yaml b/dts/Bindings/mtd/nand-controller.yaml
index b29050fd74..d0e422f4b3 100644
--- a/dts/Bindings/mtd/nand-controller.yaml
+++ b/dts/Bindings/mtd/nand-controller.yaml
@@ -46,15 +46,6 @@ patternProperties:
description:
Contains the native Ready/Busy IDs.
- nand-ecc-mode:
- description:
- Desired ECC engine, either hardware (most of the time
- embedded in the NAND controller) or software correction
- (Linux will handle the calculations). soft_bch is deprecated
- and should be replaced by soft and nand-ecc-algo.
- $ref: /schemas/types.yaml#/definitions/string
- enum: [none, soft, hw, hw_syndrome, hw_oob_first, on-die]
-
nand-ecc-engine:
allOf:
- $ref: /schemas/types.yaml#/definitions/phandle
@@ -171,7 +162,7 @@ examples:
nand@0 {
reg = <0>;
- nand-ecc-mode = "soft";
+ nand-use-soft-ecc-engine;
nand-ecc-algo = "bch";
/* controller specific properties */
diff --git a/dts/Bindings/mtd/partition.txt b/dts/Bindings/mtd/partition.txt
index 4a39698221..ead90e8274 100644
--- a/dts/Bindings/mtd/partition.txt
+++ b/dts/Bindings/mtd/partition.txt
@@ -24,137 +24,10 @@ another partitioning method.
Available bindings are listed in the "partitions" subdirectory.
-Fixed Partitions
-================
-
-Partitions can be represented by sub-nodes of a flash device. This can be used
-on platforms which have strong conventions about which portions of a flash are
-used for what purposes, but which don't use an on-flash partition table such
-as RedBoot.
-
-The partition table should be a subnode of the flash node and should be named
-'partitions'. This node should have the following property:
-- compatible : (required) must be "fixed-partitions"
-Partitions are then defined in subnodes of the partitions node.
+Deprecated: partitions defined in flash node
+============================================
For backwards compatibility partitions as direct subnodes of the flash device are
supported. This use is discouraged.
NOTE: also for backwards compatibility, direct subnodes that have a compatible
string are not considered partitions, as they may be used for other bindings.
-
-#address-cells & #size-cells must both be present in the partitions subnode of the
-flash device. There are two valid values for both:
-<1>: for partitions that require a single 32-bit cell to represent their
- size/address (aka the value is below 4 GiB)
-<2>: for partitions that require two 32-bit cells to represent their
- size/address (aka the value is 4 GiB or greater).
-
-Required properties:
-- reg : The partition's offset and size within the flash
-
-Optional properties:
-- label : The label / name for this partition. If omitted, the label is taken
- from the node name (excluding the unit address).
-- read-only : This parameter, if present, is a hint to Linux that this
- partition should only be mounted read-only. This is usually used for flash
- partitions containing early-boot firmware images or data which should not be
- clobbered.
-- lock : Do not unlock the partition at initialization time (not supported on
- all devices)
-- slc-mode: This parameter, if present, allows one to emulate SLC mode on a
- partition attached to an MLC NAND thus making this partition immune to
- paired-pages corruptions
-
-Examples:
-
-
-flash@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0000000 0x100000>;
- read-only;
- };
-
- uimage@100000 {
- reg = <0x0100000 0x200000>;
- };
- };
-};
-
-flash@1 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <2>;
-
- /* a 4 GiB partition */
- partition@0 {
- label = "filesystem";
- reg = <0x00000000 0x1 0x00000000>;
- };
- };
-};
-
-flash@2 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <2>;
- #size-cells = <2>;
-
- /* an 8 GiB partition */
- partition@0 {
- label = "filesystem #1";
- reg = <0x0 0x00000000 0x2 0x00000000>;
- };
-
- /* a 4 GiB partition */
- partition@200000000 {
- label = "filesystem #2";
- reg = <0x2 0x00000000 0x1 0x00000000>;
- };
- };
-};
-
-flash@3 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "bootloader";
- reg = <0x000000 0x100000>;
- read-only;
- };
-
- firmware@100000 {
- label = "firmware";
- reg = <0x100000 0xe00000>;
- compatible = "brcm,trx";
- };
-
- calibration@f00000 {
- label = "calibration";
- reg = <0xf00000 0x100000>;
- compatible = "fixed-partitions";
- ranges = <0 0xf00000 0x100000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "wifi0";
- reg = <0x000000 0x080000>;
- };
-
- partition@80000 {
- label = "wifi1";
- reg = <0x080000 0x080000>;
- };
- };
- };
-};
diff --git a/dts/Bindings/mtd/partitions/fixed-partitions.yaml b/dts/Bindings/mtd/partitions/fixed-partitions.yaml
new file mode 100644
index 0000000000..6d4a3450e0
--- /dev/null
+++ b/dts/Bindings/mtd/partitions/fixed-partitions.yaml
@@ -0,0 +1,152 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/partitions/fixed-partitions.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Fixed partitions
+
+description: |
+ This binding can be used on platforms which have strong conventions about
+ which portions of a flash are used for what purposes, but which don't use an
+ on-flash partition table such as RedBoot.
+
+ The partition table should be a node named "partitions". Partitions are then
+ defined as subnodes.
+
+maintainers:
+ - Rafał Miłecki <rafal@milecki.pl>
+
+properties:
+ compatible:
+ const: fixed-partitions
+
+ "#address-cells": true
+
+ "#size-cells": true
+
+patternProperties:
+ "@[0-9a-f]+$":
+ description: node describing a single flash partition
+ type: object
+
+ properties:
+ reg:
+ description: partition's offset and size within the flash
+ maxItems: 1
+
+ label:
+ description: The label / name for this partition. If omitted, the label
+ is taken from the node name (excluding the unit address).
+
+ read-only:
+ description: This parameter, if present, is a hint that this partition
+ should only be mounted read-only. This is usually used for flash
+ partitions containing early-boot firmware images or data which should
+ not be clobbered.
+ type: boolean
+
+ lock:
+ description: Do not unlock the partition at initialization time (not
+ supported on all devices)
+ type: boolean
+
+ slc-mode:
+ description: This parameter, if present, allows one to emulate SLC mode
+ on a partition attached to an MLC NAND thus making this partition
+ immune to paired-pages corruptions
+ type: boolean
+
+ required:
+ - reg
+
+required:
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: true
+
+examples:
+ - |
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x100000>;
+ read-only;
+ };
+
+ uimage@100000 {
+ reg = <0x0100000 0x200000>;
+ };
+ };
+ - |
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <2>;
+
+ /* a 4 GiB partition */
+ partition@0 {
+ label = "filesystem";
+ reg = <0x00000000 0x1 0x00000000>;
+ };
+ };
+ - |
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /* an 8 GiB partition */
+ partition@0 {
+ label = "filesystem #1";
+ reg = <0x0 0x00000000 0x2 0x00000000>;
+ };
+
+ /* a 4 GiB partition */
+ partition@200000000 {
+ label = "filesystem #2";
+ reg = <0x2 0x00000000 0x1 0x00000000>;
+ };
+ };
+ - |
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bootloader";
+ reg = <0x000000 0x100000>;
+ read-only;
+ };
+
+ firmware@100000 {
+ compatible = "brcm,trx";
+ label = "firmware";
+ reg = <0x100000 0xe00000>;
+ };
+
+ calibration@f00000 {
+ compatible = "fixed-partitions";
+ label = "calibration";
+ reg = <0xf00000 0x100000>;
+ ranges = <0 0xf00000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "wifi0";
+ reg = <0x000000 0x080000>;
+ };
+
+ partition@80000 {
+ label = "wifi1";
+ reg = <0x080000 0x080000>;
+ };
+ };
+ };
diff --git a/dts/Bindings/mtd/qcom_nandc.txt b/dts/Bindings/mtd/qcom_nandc.txt
index 5c2fba4b30..5647913d88 100644
--- a/dts/Bindings/mtd/qcom_nandc.txt
+++ b/dts/Bindings/mtd/qcom_nandc.txt
@@ -6,8 +6,12 @@ Required properties:
SoC and it uses ADM DMA
* "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
IPQ4019 SoC and it uses BAM DMA
+ * "qcom,ipq6018-nand" - for QPIC NAND controller v1.5.0 being used in
+ IPQ6018 SoC and it uses BAM DMA
* "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
IPQ8074 SoC and it uses BAM DMA
+ * "qcom,sdx55-nand" - for QPIC NAND controller v2.0.0 being used in
+ SDX55 SoC and it uses BAM DMA
- reg: MMIO address range
- clocks: must contain core clock and always on clock
diff --git a/dts/Bindings/mtd/rockchip,nand-controller.yaml b/dts/Bindings/mtd/rockchip,nand-controller.yaml
new file mode 100644
index 0000000000..0922536b18
--- /dev/null
+++ b/dts/Bindings/mtd/rockchip,nand-controller.yaml
@@ -0,0 +1,161 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/rockchip,nand-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SoCs NAND FLASH Controller (NFC)
+
+allOf:
+ - $ref: "nand-controller.yaml#"
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ compatible:
+ oneOf:
+ - const: rockchip,px30-nfc
+ - const: rockchip,rk2928-nfc
+ - const: rockchip,rv1108-nfc
+ - items:
+ - const: rockchip,rk3036-nfc
+ - const: rockchip,rk2928-nfc
+ - items:
+ - const: rockchip,rk3308-nfc
+ - const: rockchip,rv1108-nfc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ items:
+ - description: Bus Clock
+ - description: Module Clock
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: ahb
+ - const: nfc
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-rates:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+patternProperties:
+ "^nand@[0-7]$":
+ type: object
+ properties:
+ reg:
+ minimum: 0
+ maximum: 7
+
+ nand-ecc-mode:
+ const: hw
+
+ nand-ecc-step-size:
+ const: 1024
+
+ nand-ecc-strength:
+ enum: [16, 24, 40, 60, 70]
+ description: |
+ The ECC configurations that can be supported are as follows.
+ NFC v600 ECC 16, 24, 40, 60
+ RK2928, RK3066, RK3188
+
+ NFC v622 ECC 16, 24, 40, 60
+ RK3036, RK3128
+
+ NFC v800 ECC 16
+ RK3308, RV1108
+
+ NFC v900 ECC 16, 40, 60, 70
+ RK3326, PX30
+
+ nand-bus-width:
+ const: 8
+
+ rockchip,boot-blks:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 2
+ default: 16
+ description:
+ The NFC driver need this information to select ECC
+ algorithms supported by the boot ROM.
+ Only used in combination with 'nand-is-boot-medium'.
+
+ rockchip,boot-ecc-strength:
+ enum: [16, 24, 40, 60, 70]
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ If specified it indicates that a different BCH/ECC setting is
+ supported by the boot ROM.
+ NFC v600 ECC 16, 24
+ RK2928, RK3066, RK3188
+
+ NFC v622 ECC 16, 24, 40, 60
+ RK3036, RK3128
+
+ NFC v800 ECC 16
+ RK3308, RV1108
+
+ NFC v900 ECC 16, 70
+ RK3326, PX30
+
+ Only used in combination with 'nand-is-boot-medium'.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3308-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ nfc: nand-controller@ff4b0000 {
+ compatible = "rockchip,rk3308-nfc",
+ "rockchip,rv1108-nfc";
+ reg = <0xff4b0000 0x4000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
+ clock-names = "ahb", "nfc";
+ assigned-clocks = <&clks SCLK_NANDC>;
+ assigned-clock-rates = <150000000>;
+
+ pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
+ &flash_rdn &flash_rdy &flash_wrn>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+ label = "rk-nand";
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-step-size = <1024>;
+ nand-ecc-strength = <16>;
+ nand-is-boot-medium;
+ rockchip,boot-blks = <8>;
+ rockchip,boot-ecc-strength = <16>;
+ };
+ };
+
+...
diff --git a/dts/Bindings/net/allwinner,sun8i-a83t-emac.yaml b/dts/Bindings/net/allwinner,sun8i-a83t-emac.yaml
index c7c9ad4e3f..7f2578d48e 100644
--- a/dts/Bindings/net/allwinner,sun8i-a83t-emac.yaml
+++ b/dts/Bindings/net/allwinner,sun8i-a83t-emac.yaml
@@ -38,7 +38,7 @@ properties:
const: stmmaceth
syscon:
- $ref: /schemas/types.yaml#definitions/phandle
+ $ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the device containing the EMAC or GMAC clock
register
@@ -114,7 +114,7 @@ allOf:
then:
properties:
allwinner,leds-active-low:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
EPHY LEDs are active low.
@@ -126,7 +126,7 @@ allOf:
const: allwinner,sun8i-h3-mdio-mux
mdio-parent-bus:
- $ref: /schemas/types.yaml#definitions/phandle
+ $ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to EMAC MDIO.
diff --git a/dts/Bindings/net/amlogic,meson-dwmac.yaml b/dts/Bindings/net/amlogic,meson-dwmac.yaml
index 6b057b117a..1f133f4a29 100644
--- a/dts/Bindings/net/amlogic,meson-dwmac.yaml
+++ b/dts/Bindings/net/amlogic,meson-dwmac.yaml
@@ -60,7 +60,7 @@ allOf:
- const: timing-adjustment
amlogic,tx-delay-ns:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description:
The internal RGMII TX clock delay (provided by this driver) in
nanoseconds. Allowed values are 0ns, 2ns, 4ns, 6ns.
diff --git a/dts/Bindings/net/can/fsl,flexcan.yaml b/dts/Bindings/net/can/fsl,flexcan.yaml
index 13875eab2e..0d2df30f19 100644
--- a/dts/Bindings/net/can/fsl,flexcan.yaml
+++ b/dts/Bindings/net/can/fsl,flexcan.yaml
@@ -57,6 +57,7 @@ properties:
- const: per
clock-frequency:
+ $ref: /schemas/types.yaml#/definitions/uint32
description: |
The oscillator frequency driving the flexcan device, filled in by the
boot loader. This property should only be used the used operating system
@@ -99,7 +100,7 @@ properties:
by default.
0: clock source 0 (oscillator clock)
1: clock source 1 (peripheral clock)
- $ref: /schemas/types.yaml#/definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint8
default: 1
minimum: 0
maximum: 1
@@ -124,7 +125,7 @@ examples:
interrupts = <48 0x2>;
interrupt-parent = <&mpic>;
clock-frequency = <200000000>;
- fsl,clk-source = <0>;
+ fsl,clk-source = /bits/ 8 <0>;
};
- |
#include <dt-bindings/interrupt-controller/irq.h>
diff --git a/dts/Bindings/net/dsa/b53.txt b/dts/Bindings/net/dsa/b53.txt
deleted file mode 100644
index f1487a751b..0000000000
--- a/dts/Bindings/net/dsa/b53.txt
+++ /dev/null
@@ -1,149 +0,0 @@
-Broadcom BCM53xx Ethernet switches
-==================================
-
-Required properties:
-
-- compatible: For external switch chips, compatible string must be exactly one
- of: "brcm,bcm5325"
- "brcm,bcm53115"
- "brcm,bcm53125"
- "brcm,bcm53128"
- "brcm,bcm5365"
- "brcm,bcm5395"
- "brcm,bcm5389"
- "brcm,bcm5397"
- "brcm,bcm5398"
-
- For the BCM11360 SoC, must be:
- "brcm,bcm11360-srab" and the mandatory "brcm,cygnus-srab" string
-
- For the BCM5310x SoCs with an integrated switch, must be one of:
- "brcm,bcm53010-srab"
- "brcm,bcm53011-srab"
- "brcm,bcm53012-srab"
- "brcm,bcm53018-srab"
- "brcm,bcm53019-srab" and the mandatory "brcm,bcm5301x-srab" string
-
- For the BCM5831X/BCM1140x SoCs with an integrated switch, must be one of:
- "brcm,bcm11404-srab"
- "brcm,bcm11407-srab"
- "brcm,bcm11409-srab"
- "brcm,bcm58310-srab"
- "brcm,bcm58311-srab"
- "brcm,bcm58313-srab" and the mandatory "brcm,omega-srab" string
-
- For the BCM585xx/586XX/88312 SoCs with an integrated switch, must be one of:
- "brcm,bcm58522-srab"
- "brcm,bcm58523-srab"
- "brcm,bcm58525-srab"
- "brcm,bcm58622-srab"
- "brcm,bcm58623-srab"
- "brcm,bcm58625-srab"
- "brcm,bcm88312-srab" and the mandatory "brcm,nsp-srab string
-
- For the BCM63xx/33xx SoCs with an integrated switch, must be one of:
- "brcm,bcm3384-switch"
- "brcm,bcm6328-switch"
- "brcm,bcm6368-switch" and the mandatory "brcm,bcm63xx-switch"
-
-Required properties for BCM585xx/586xx/88312 SoCs:
-
- - reg: a total of 3 register base addresses, the first one must be the
- Switch Register Access block base, the second is the port 5/4 mux
- configuration register and the third one is the SGMII configuration
- and status register base address.
-
- - interrupts: a total of 13 interrupts must be specified, in the following
- order: port 0-5, 7-8 link status change, then the integrated PHY interrupt,
- then the timestamping interrupt and the sleep timer interrupts for ports
- 5,7,8.
-
-Optional properties for BCM585xx/586xx/88312 SoCs:
-
- - reg-names: a total of 3 names matching the 3 base register address, must
- be in the following order:
- "srab"
- "mux_config"
- "sgmii_config"
-
- - interrupt-names: a total of 13 names matching the 13 interrupts specified
- must be in the following order:
- "link_state_p0"
- "link_state_p1"
- "link_state_p2"
- "link_state_p3"
- "link_state_p4"
- "link_state_p5"
- "link_state_p7"
- "link_state_p8"
- "phy"
- "ts"
- "imp_sleep_timer_p5"
- "imp_sleep_timer_p7"
- "imp_sleep_timer_p8"
-
-See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
-required and optional properties.
-
-Examples:
-
-Ethernet switch connected via MDIO to the host, CPU port wired to eth0:
-
- eth0: ethernet@10001000 {
- compatible = "brcm,unimac";
- reg = <0x10001000 0x1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- mdio0: mdio@10000000 {
- compatible = "brcm,unimac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- switch0: ethernet-switch@1e {
- compatible = "brcm,bcm53125";
- reg = <30>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port0@0 {
- reg = <0>;
- label = "lan1";
- };
-
- port1@1 {
- reg = <1>;
- label = "lan2";
- };
-
- port5@5 {
- reg = <5>;
- label = "cable-modem";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- phy-mode = "rgmii-txid";
- };
-
- port8@8 {
- reg = <8>;
- label = "cpu";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- phy-mode = "rgmii-txid";
- ethernet = <&eth0>;
- };
- };
- };
- };
diff --git a/dts/Bindings/net/dsa/brcm,b53.yaml b/dts/Bindings/net/dsa/brcm,b53.yaml
new file mode 100644
index 0000000000..c3c938893a
--- /dev/null
+++ b/dts/Bindings/net/dsa/brcm,b53.yaml
@@ -0,0 +1,249 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/brcm,b53.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM53xx Ethernet switches
+
+allOf:
+ - $ref: dsa.yaml#
+
+maintainers:
+ - Florian Fainelli <f.fainelli@gmail.com>
+
+description:
+ Broadcom BCM53xx Ethernet switches
+
+properties:
+ compatible:
+ oneOf:
+ - const: brcm,bcm5325
+ - const: brcm,bcm53115
+ - const: brcm,bcm53125
+ - const: brcm,bcm53128
+ - const: brcm,bcm5365
+ - const: brcm,bcm5395
+ - const: brcm,bcm5389
+ - const: brcm,bcm5397
+ - const: brcm,bcm5398
+ - items:
+ - const: brcm,bcm11360-srab
+ - const: brcm,cygnus-srab
+ - items:
+ - enum:
+ - brcm,bcm53010-srab
+ - brcm,bcm53011-srab
+ - brcm,bcm53012-srab
+ - brcm,bcm53018-srab
+ - brcm,bcm53019-srab
+ - const: brcm,bcm5301x-srab
+ - items:
+ - enum:
+ - brcm,bcm11404-srab
+ - brcm,bcm11407-srab
+ - brcm,bcm11409-srab
+ - brcm,bcm58310-srab
+ - brcm,bcm58311-srab
+ - brcm,bcm58313-srab
+ - const: brcm,omega-srab
+ - items:
+ - enum:
+ - brcm,bcm58522-srab
+ - brcm,bcm58523-srab
+ - brcm,bcm58525-srab
+ - brcm,bcm58622-srab
+ - brcm,bcm58623-srab
+ - brcm,bcm58625-srab
+ - brcm,bcm88312-srab
+ - const: brcm,nsp-srab
+ - items:
+ - enum:
+ - brcm,bcm3384-switch
+ - brcm,bcm6328-switch
+ - brcm,bcm6368-switch
+ - const: brcm,bcm63xx-switch
+
+required:
+ - compatible
+ - reg
+
+# BCM585xx/586xx/88312 SoCs
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - brcm,bcm58522-srab
+ - brcm,bcm58523-srab
+ - brcm,bcm58525-srab
+ - brcm,bcm58622-srab
+ - brcm,bcm58623-srab
+ - brcm,bcm58625-srab
+ - brcm,bcm88312-srab
+then:
+ properties:
+ reg:
+ minItems: 3
+ maxItems: 3
+ reg-names:
+ items:
+ - const: srab
+ - const: mux_config
+ - const: sgmii_config
+ interrupts:
+ minItems: 13
+ maxItems: 13
+ interrupt-names:
+ items:
+ - const: link_state_p0
+ - const: link_state_p1
+ - const: link_state_p2
+ - const: link_state_p3
+ - const: link_state_p4
+ - const: link_state_p5
+ - const: link_state_p7
+ - const: link_state_p8
+ - const: phy
+ - const: ts
+ - const: imp_sleep_timer_p5
+ - const: imp_sleep_timer_p7
+ - const: imp_sleep_timer_p8
+ required:
+ - interrupts
+else:
+ properties:
+ reg:
+ maxItems: 1
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-switch@1e {
+ compatible = "brcm,bcm53125";
+ reg = <30>;
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cable-modem";
+ phy-mode = "rgmii-txid";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@8 {
+ reg = <8>;
+ label = "cpu";
+ phy-mode = "rgmii-txid";
+ ethernet = <&eth0>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+ };
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ axi {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ switch@36000 {
+ compatible = "brcm,bcm58623-srab", "brcm,nsp-srab";
+ reg = <0x36000 0x1000>,
+ <0x3f308 0x8>,
+ <0x3f410 0xc>;
+ reg-names = "srab", "mux_config", "sgmii_config";
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "link_state_p0",
+ "link_state_p1",
+ "link_state_p2",
+ "link_state_p3",
+ "link_state_p4",
+ "link_state_p5",
+ "link_state_p7",
+ "link_state_p8",
+ "phy",
+ "ts",
+ "imp_sleep_timer_p5",
+ "imp_sleep_timer_p7",
+ "imp_sleep_timer_p8";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ label = "port0";
+ reg = <0>;
+ };
+
+ port@1 {
+ label = "port1";
+ reg = <1>;
+ };
+
+ port@2 {
+ label = "port2";
+ reg = <2>;
+ };
+
+ port@3 {
+ label = "port3";
+ reg = <3>;
+ };
+
+ port@4 {
+ label = "port4";
+ reg = <4>;
+ };
+
+ port@8 {
+ ethernet = <&amac2>;
+ label = "cpu";
+ reg = <8>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/net/dsa/dsa.yaml b/dts/Bindings/net/dsa/dsa.yaml
index a765ceba28..8a3494db4d 100644
--- a/dts/Bindings/net/dsa/dsa.yaml
+++ b/dts/Bindings/net/dsa/dsa.yaml
@@ -20,7 +20,7 @@ select: false
properties:
$nodename:
- pattern: "^switch(@.*)?$"
+ pattern: "^(ethernet-)?switch(@.*)?$"
dsa,member:
minItems: 2
@@ -54,7 +54,7 @@ patternProperties:
description:
Describes the label associated with this port, which will become
the netdev name
- $ref: /schemas/types.yaml#definitions/string
+ $ref: /schemas/types.yaml#/definitions/string
link:
description:
@@ -62,13 +62,13 @@ patternProperties:
port is used as the outgoing port towards the phandle ports. The
full routing information must be given, not just the one hop
routes to neighbouring switches
- $ref: /schemas/types.yaml#definitions/phandle-array
+ $ref: /schemas/types.yaml#/definitions/phandle-array
ethernet:
description:
Should be a phandle to a valid Ethernet device node. This host
device is what the switch port is connected to
- $ref: /schemas/types.yaml#definitions/phandle
+ $ref: /schemas/types.yaml#/definitions/phandle
phy-handle: true
@@ -78,6 +78,10 @@ patternProperties:
mac-address: true
+ sfp: true
+
+ managed: true
+
required:
- reg
diff --git a/dts/Bindings/net/dsa/hirschmann,hellcreek.yaml b/dts/Bindings/net/dsa/hirschmann,hellcreek.yaml
new file mode 100644
index 0000000000..5592f58fa6
--- /dev/null
+++ b/dts/Bindings/net/dsa/hirschmann,hellcreek.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/hirschmann,hellcreek.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hirschmann Hellcreek TSN Switch Device Tree Bindings
+
+allOf:
+ - $ref: dsa.yaml#
+
+maintainers:
+ - Andrew Lunn <andrew@lunn.ch>
+ - Florian Fainelli <f.fainelli@gmail.com>
+ - Vivien Didelot <vivien.didelot@gmail.com>
+ - Kurt Kanzenbach <kurt@linutronix.de>
+
+description:
+ The Hellcreek TSN Switch IP is a 802.1Q Ethernet compliant switch. It supports
+ the Precision Time Protocol, Hardware Timestamping as well the Time Aware
+ Shaper.
+
+properties:
+ compatible:
+ items:
+ - const: hirschmann,hellcreek-de1soc-r1
+
+ reg:
+ description:
+ The physical base address and size of TSN and PTP memory base
+ minItems: 2
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: tsn
+ - const: ptp
+
+ leds:
+ type: object
+ properties:
+ '#address-cells':
+ const: 1
+ '#size-cells':
+ const: 0
+
+ patternProperties:
+ "^led@[01]$":
+ type: object
+ description: Hellcreek leds
+ $ref: ../../leds/common.yaml#
+
+ properties:
+ reg:
+ items:
+ - enum: [0, 1]
+ description: Led number
+
+ label: true
+
+ default-state: true
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - ethernet-ports
+ - leds
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ switch0: switch@ff240000 {
+ compatible = "hirschmann,hellcreek-de1soc-r1";
+ reg = <0xff240000 0x1000>,
+ <0xff250000 0x1000>;
+ reg-names = "tsn", "ptp";
+ dsa,member = <0 0>;
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan0";
+ phy-handle = <&phy1>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan1";
+ phy-handle = <&phy2>;
+ };
+ };
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ label = "sync_good";
+ default-state = "on";
+ };
+
+ led@1 {
+ reg = <1>;
+ label = "is_gm";
+ default-state = "off";
+ };
+ };
+ };
diff --git a/dts/Bindings/net/dsa/ksz.txt b/dts/Bindings/net/dsa/ksz.txt
deleted file mode 100644
index 95e91e8415..0000000000
--- a/dts/Bindings/net/dsa/ksz.txt
+++ /dev/null
@@ -1,125 +0,0 @@
-Microchip KSZ Series Ethernet switches
-==================================
-
-Required properties:
-
-- compatible: For external switch chips, compatible string must be exactly one
- of the following:
- - "microchip,ksz8765"
- - "microchip,ksz8794"
- - "microchip,ksz8795"
- - "microchip,ksz9477"
- - "microchip,ksz9897"
- - "microchip,ksz9896"
- - "microchip,ksz9567"
- - "microchip,ksz8565"
- - "microchip,ksz9893"
- - "microchip,ksz9563"
- - "microchip,ksz8563"
-
-Optional properties:
-
-- reset-gpios : Should be a gpio specifier for a reset line
-- microchip,synclko-125 : Set if the output SYNCLKO frequency should be set to
- 125MHz instead of 25MHz.
-
-See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
-required and optional properties.
-
-Examples:
-
-Ethernet switch connected via SPI to the host, CPU port wired to eth0:
-
- eth0: ethernet@10001000 {
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- spi1: spi@f8008000 {
- pinctrl-0 = <&pinctrl_spi_ksz>;
- cs-gpios = <&pioC 25 0>;
- id = <1>;
-
- ksz9477: ksz9477@0 {
- compatible = "microchip,ksz9477";
- reg = <0>;
-
- spi-max-frequency = <44000000>;
- spi-cpha;
- spi-cpol;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- label = "lan1";
- };
- port@1 {
- reg = <1>;
- label = "lan2";
- };
- port@2 {
- reg = <2>;
- label = "lan3";
- };
- port@3 {
- reg = <3>;
- label = "lan4";
- };
- port@4 {
- reg = <4>;
- label = "lan5";
- };
- port@5 {
- reg = <5>;
- label = "cpu";
- ethernet = <&eth0>;
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
- };
- ksz8565: ksz8565@0 {
- compatible = "microchip,ksz8565";
- reg = <0>;
-
- spi-max-frequency = <44000000>;
- spi-cpha;
- spi-cpol;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- label = "lan1";
- };
- port@1 {
- reg = <1>;
- label = "lan2";
- };
- port@2 {
- reg = <2>;
- label = "lan3";
- };
- port@3 {
- reg = <3>;
- label = "lan4";
- };
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&eth0>;
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
- };
- };
diff --git a/dts/Bindings/net/dsa/microchip,ksz.yaml b/dts/Bindings/net/dsa/microchip,ksz.yaml
new file mode 100644
index 0000000000..9f7d131bbc
--- /dev/null
+++ b/dts/Bindings/net/dsa/microchip,ksz.yaml
@@ -0,0 +1,148 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/microchip,ksz.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip KSZ Series Ethernet switches
+
+maintainers:
+ - Marek Vasut <marex@denx.de>
+ - Woojung Huh <Woojung.Huh@microchip.com>
+
+allOf:
+ - $ref: dsa.yaml#
+
+properties:
+ # See Documentation/devicetree/bindings/net/dsa/dsa.yaml for a list of additional
+ # required and optional properties.
+ compatible:
+ enum:
+ - microchip,ksz8765
+ - microchip,ksz8794
+ - microchip,ksz8795
+ - microchip,ksz9477
+ - microchip,ksz9897
+ - microchip,ksz9896
+ - microchip,ksz9567
+ - microchip,ksz8565
+ - microchip,ksz9893
+ - microchip,ksz9563
+ - microchip,ksz8563
+
+ reset-gpios:
+ description:
+ Should be a gpio specifier for a reset line.
+ maxItems: 1
+
+ microchip,synclko-125:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Set if the output SYNCLKO frequency should be set to 125MHz instead of 25MHz.
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ // Ethernet switch connected via SPI to the host, CPU port wired to eth0:
+ eth0 {
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ spi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-0 = <&pinctrl_spi_ksz>;
+ cs-gpios = <&pioC 25 0>;
+ id = <1>;
+
+ ksz9477: switch@0 {
+ compatible = "microchip,ksz9477";
+ reg = <0>;
+ reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+
+ spi-max-frequency = <44000000>;
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ };
+ port@4 {
+ reg = <4>;
+ label = "lan5";
+ };
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&eth0>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+
+ ksz8565: switch@1 {
+ compatible = "microchip,ksz8565";
+ reg = <1>;
+
+ spi-max-frequency = <44000000>;
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ };
+ port@6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <&eth0>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+ };
+...
diff --git a/dts/Bindings/net/ethernet-controller.yaml b/dts/Bindings/net/ethernet-controller.yaml
index fdf7098172..0965f6515f 100644
--- a/dts/Bindings/net/ethernet-controller.yaml
+++ b/dts/Bindings/net/ethernet-controller.yaml
@@ -16,7 +16,7 @@ properties:
local-mac-address:
description:
Specifies the MAC address that was assigned to the network device.
- $ref: /schemas/types.yaml#definitions/uint8-array
+ $ref: /schemas/types.yaml#/definitions/uint8-array
items:
- minItems: 6
maxItems: 6
@@ -27,20 +27,20 @@ properties:
program; should be used in cases where the MAC address assigned
to the device by the boot program is different from the
local-mac-address property.
- $ref: /schemas/types.yaml#definitions/uint8-array
+ $ref: /schemas/types.yaml#/definitions/uint8-array
items:
- minItems: 6
maxItems: 6
max-frame-size:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description:
Maximum transfer unit (IEEE defined MTU), rather than the
maximum frame size (there\'s contradiction in the Devicetree
Specification).
max-speed:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description:
Specifies maximum speed in Mbit/s supported by the device.
@@ -95,12 +95,13 @@ properties:
# 10GBASE-KR, XFI, SFI
- 10gbase-kr
- usxgmii
+ - 10gbase-r
phy-mode:
$ref: "#/properties/phy-connection-type"
phy-handle:
- $ref: /schemas/types.yaml#definitions/phandle
+ $ref: /schemas/types.yaml#/definitions/phandle
description:
Specifies a reference to a node representing a PHY device.
@@ -113,7 +114,7 @@ properties:
deprecated: true
rx-fifo-depth:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description:
The size of the controller\'s receive fifo in bytes. This is used
for components that can have configurable receive fifo sizes,
@@ -128,12 +129,12 @@ properties:
If this property is present then the MAC applies the RX delay.
sfp:
- $ref: /schemas/types.yaml#definitions/phandle
+ $ref: /schemas/types.yaml#/definitions/phandle
description:
Specifies a reference to a node representing a SFP cage.
tx-fifo-depth:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description:
The size of the controller\'s transmit fifo in bytes. This
is used for components that can have configurable fifo sizes.
@@ -149,7 +150,7 @@ properties:
description:
Specifies the PHY management type. If auto is set and fixed-link
is not specified, it uses MDIO for management.
- $ref: /schemas/types.yaml#definitions/string
+ $ref: /schemas/types.yaml#/definitions/string
default: auto
enum:
- auto
@@ -197,17 +198,17 @@ properties:
speed:
description:
Link speed.
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
enum: [10, 100, 1000]
full-duplex:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
Indicates that full-duplex is used. When absent, half
duplex is assumed.
asym-pause:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
Indicates that asym_pause should be enabled.
diff --git a/dts/Bindings/net/ethernet-phy.yaml b/dts/Bindings/net/ethernet-phy.yaml
index 6dd72faebd..2766fe45bb 100644
--- a/dts/Bindings/net/ethernet-phy.yaml
+++ b/dts/Bindings/net/ethernet-phy.yaml
@@ -78,57 +78,57 @@ properties:
Maximum PHY supported speed in Mbits / seconds.
broken-turn-around:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
If set, indicates the PHY device does not correctly release
the turn around line low at end of the control phase of the
MDIO transaction.
enet-phy-lane-swap:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
If set, indicates the PHY will swap the TX/RX lanes to
compensate for the board being designed with the lanes
swapped.
eee-broken-100tx:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
Mark the corresponding energy efficient ethernet mode as
broken and request the ethernet to stop advertising it.
eee-broken-1000t:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
Mark the corresponding energy efficient ethernet mode as
broken and request the ethernet to stop advertising it.
eee-broken-10gt:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
Mark the corresponding energy efficient ethernet mode as
broken and request the ethernet to stop advertising it.
eee-broken-1000kx:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
Mark the corresponding energy efficient ethernet mode as
broken and request the ethernet to stop advertising it.
eee-broken-10gkx4:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
Mark the corresponding energy efficient ethernet mode as
broken and request the ethernet to stop advertising it.
eee-broken-10gkr:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
Mark the corresponding energy efficient ethernet mode as
broken and request the ethernet to stop advertising it.
phy-is-integrated:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
If set, indicates that the PHY is integrated into the same
physical package as the Ethernet MAC. If needed, muxers
@@ -158,7 +158,7 @@ properties:
this property is missing the delay will be skipped.
sfp:
- $ref: /schemas/types.yaml#definitions/phandle
+ $ref: /schemas/types.yaml#/definitions/phandle
description:
Specifies a reference to a node representing a SFP cage.
diff --git a/dts/Bindings/net/fsl,qoriq-mc-dpmac.yaml b/dts/Bindings/net/fsl,qoriq-mc-dpmac.yaml
new file mode 100644
index 0000000000..7f620a71a9
--- /dev/null
+++ b/dts/Bindings/net/fsl,qoriq-mc-dpmac.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/fsl,qoriq-mc-dpmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: DPAA2 MAC bindings
+
+maintainers:
+ - Ioana Ciornei <ioana.ciornei@nxp.com>
+
+description:
+ This binding represents the DPAA2 MAC objects found on the fsl-mc bus and
+ located under the 'dpmacs' node for the fsl-mc bus DTS node.
+
+allOf:
+ - $ref: "ethernet-controller.yaml#"
+
+properties:
+ compatible:
+ const: fsl,qoriq-mc-dpmac
+
+ reg:
+ maxItems: 1
+ description: The DPMAC number
+
+ phy-handle: true
+
+ phy-connection-type: true
+
+ phy-mode: true
+
+ pcs-handle:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ A reference to a node representing a PCS PHY device found on
+ the internal MDIO bus.
+
+ managed: true
+
+required:
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ dpmacs {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet@4 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x4>;
+ phy-handle = <&mdio1_phy6>;
+ phy-connection-type = "qsgmii";
+ managed = "in-band-status";
+ pcs-handle = <&pcs3_1>;
+ };
+ };
diff --git a/dts/Bindings/net/ftgmac100.txt b/dts/Bindings/net/ftgmac100.txt
index f878c11034..29234021f6 100644
--- a/dts/Bindings/net/ftgmac100.txt
+++ b/dts/Bindings/net/ftgmac100.txt
@@ -15,6 +15,7 @@ Required properties:
- interrupts: Should contain ethernet controller interrupt
Optional properties:
+- phy-handle: See ethernet.txt file in the same directory.
- phy-mode: See ethernet.txt file in the same directory. If the property is
absent, "rgmii" is assumed. Supported values are "rgmii*" and "rmii" for
aspeed parts. Other (unknown) parts will accept any value.
@@ -32,6 +33,9 @@ Optional properties:
- "MACCLK": The MAC IP clock
- "RCLK": Clock gate for the RMII RCLK
+Optional subnodes:
+- mdio: See mdio.txt file in the same directory.
+
Example:
mac0: ethernet@1e660000 {
@@ -40,3 +44,24 @@ Example:
interrupts = <2>;
use-ncsi;
};
+
+Example with phy-handle:
+
+ mac1: ethernet@1e680000 {
+ compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
+ reg = <0x1e680000 0x180>;
+ interrupts = <2>;
+
+ phy-handle = <&phy>;
+ phy-mode = "rgmii";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+ };
diff --git a/dts/Bindings/net/macb.txt b/dts/Bindings/net/macb.txt
index 0b61a90f15..a4d547efc3 100644
--- a/dts/Bindings/net/macb.txt
+++ b/dts/Bindings/net/macb.txt
@@ -7,8 +7,6 @@ Required properties:
Use "cdns,sam9x60-macb" for Microchip sam9x60 SoC.
Use "cdns,np4-macb" for NP4 SoC devices.
Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb".
- Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on
- the Cadence GEM, or the generic form: "cdns,gem".
Use "atmel,sama5d2-gem" for the GEM IP (10/100) available on Atmel sama5d2 SoCs.
Use "atmel,sama5d3-macb" for the 10/100Mbit IP available on Atmel sama5d3 SoCs.
Use "atmel,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs.
@@ -16,6 +14,8 @@ Required properties:
Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC.
Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
Use "sifive,fu540-c000-gem" for SiFive FU540-C000 SoC.
+ Use "microchip,sama7g5-emac" for Microchip SAMA7G5 ethernet interface.
+ Use "microchip,sama7g5-gem" for Microchip SAMA7G5 gigabit ethernet interface.
Or the generic form: "cdns,emac".
- reg: Address and length of the register set for the device
For "sifive,fu540-c000-gem", second range is required to specify the
diff --git a/dts/Bindings/net/mdio.yaml b/dts/Bindings/net/mdio.yaml
index e811e0fd85..08e15fb158 100644
--- a/dts/Bindings/net/mdio.yaml
+++ b/dts/Bindings/net/mdio.yaml
@@ -70,7 +70,7 @@ patternProperties:
The ID number for the device.
broken-turn-around:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
If set, indicates the MDIO device does not correctly release
the turn around line low at end of the control phase of the
diff --git a/dts/Bindings/net/mediatek,star-emac.yaml b/dts/Bindings/net/mediatek,star-emac.yaml
index 0bbd598704..e6a5ff2082 100644
--- a/dts/Bindings/net/mediatek,star-emac.yaml
+++ b/dts/Bindings/net/mediatek,star-emac.yaml
@@ -42,7 +42,7 @@ properties:
- const: trans
mediatek,pericfg:
- $ref: /schemas/types.yaml#definitions/phandle
+ $ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the device containing the PERICFG register range. This is used
to control the MII mode.
diff --git a/dts/Bindings/net/nfc/nxp-nci.txt b/dts/Bindings/net/nfc/nxp-nci.txt
index 9e4dc510a4..285a37c2f1 100644
--- a/dts/Bindings/net/nfc/nxp-nci.txt
+++ b/dts/Bindings/net/nfc/nxp-nci.txt
@@ -6,11 +6,11 @@ Required properties:
- reg: address on the bus
- interrupts: GPIO interrupt to which the chip is connected
- enable-gpios: Output GPIO pin used for enabling/disabling the chip
-- firmware-gpios: Output GPIO pin used to enter firmware download mode
Optional SoC Specific Properties:
- pinctrl-names: Contains only one value - "default".
- pintctrl-0: Specifies the pin control groups used for this controller.
+- firmware-gpios: Output GPIO pin used to enter firmware download mode
Example (for ARM-based BeagleBone with NPC100 NFC controller on I2C2):
diff --git a/dts/Bindings/net/nfc/samsung,s3fwrn5.yaml b/dts/Bindings/net/nfc/samsung,s3fwrn5.yaml
index cb0b8a5602..477066e2b8 100644
--- a/dts/Bindings/net/nfc/samsung,s3fwrn5.yaml
+++ b/dts/Bindings/net/nfc/samsung,s3fwrn5.yaml
@@ -12,7 +12,9 @@ maintainers:
properties:
compatible:
- const: samsung,s3fwrn5-i2c
+ enum:
+ - samsung,s3fwrn5-i2c
+ - samsung,s3fwrn82
en-gpios:
maxItems: 1
@@ -47,10 +49,19 @@ additionalProperties: false
required:
- compatible
- en-gpios
- - interrupts
- - reg
- wake-gpios
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,s3fwrn5-i2c
+ then:
+ required:
+ - interrupts
+ - reg
+
examples:
- |
#include <dt-bindings/gpio/gpio.h>
@@ -65,9 +76,23 @@ examples:
reg = <0x27>;
interrupt-parent = <&gpa1>;
- interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <3 IRQ_TYPE_EDGE_RISING>;
en-gpios = <&gpf1 4 GPIO_ACTIVE_HIGH>;
wake-gpios = <&gpj0 2 GPIO_ACTIVE_HIGH>;
};
};
+ # UART example on Raspberry Pi
+ - |
+ uart0 {
+ status = "okay";
+
+ nfc {
+ compatible = "samsung,s3fwrn82";
+
+ en-gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+
+ status = "okay";
+ };
+ };
diff --git a/dts/Bindings/net/qcom,ipa.yaml b/dts/Bindings/net/qcom,ipa.yaml
index 4d8464b267..8a2d126446 100644
--- a/dts/Bindings/net/qcom,ipa.yaml
+++ b/dts/Bindings/net/qcom,ipa.yaml
@@ -114,14 +114,13 @@ properties:
validating firwmare used by the GSI.
modem-remoteproc:
- $ref: /schemas/types.yaml#definitions/phandle
+ $ref: /schemas/types.yaml#/definitions/phandle
description:
This defines the phandle to the remoteproc node representing
the modem subsystem. This is requied so the IPA driver can
receive and act on notifications of modem up/down events.
memory-region:
- $ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
description:
If present, a phandle for a reserved memory area that holds
diff --git a/dts/Bindings/net/snps,dwmac.yaml b/dts/Bindings/net/snps,dwmac.yaml
index 11a6fdb657..b2f6083f55 100644
--- a/dts/Bindings/net/snps,dwmac.yaml
+++ b/dts/Bindings/net/snps,dwmac.yaml
@@ -126,7 +126,7 @@ properties:
in a different mode than the PHY in order to function.
snps,axi-config:
- $ref: /schemas/types.yaml#definitions/phandle
+ $ref: /schemas/types.yaml#/definitions/phandle
description:
AXI BUS Mode parameters. Phandle to a node that can contain the
following properties
@@ -141,7 +141,7 @@ properties:
* snps,rb, rebuild INCRx Burst
snps,mtl-rx-config:
- $ref: /schemas/types.yaml#definitions/phandle
+ $ref: /schemas/types.yaml#/definitions/phandle
description:
Multiple RX Queues parameters. Phandle to a node that can
contain the following properties
@@ -164,7 +164,7 @@ properties:
* snps,priority, RX queue priority (Range 0x0 to 0xF)
snps,mtl-tx-config:
- $ref: /schemas/types.yaml#definitions/phandle
+ $ref: /schemas/types.yaml#/definitions/phandle
description:
Multiple TX Queues parameters. Phandle to a node that can
contain the following properties
@@ -198,7 +198,7 @@ properties:
snps,reset-active-low:
deprecated: true
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
Indicates that the PHY Reset is active low
@@ -208,55 +208,55 @@ properties:
Triplet of delays. The 1st cell is reset pre-delay in micro
seconds. The 2nd cell is reset pulse in micro seconds. The 3rd
cell is reset post-delay in micro seconds.
- $ref: /schemas/types.yaml#definitions/uint32-array
+ $ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 3
maxItems: 3
snps,aal:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
Use Address-Aligned Beats
snps,fixed-burst:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
Program the DMA to use the fixed burst mode
snps,mixed-burst:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
Program the DMA to use the mixed burst mode
snps,force_thresh_dma_mode:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
Force DMA to use the threshold mode for both tx and rx
snps,force_sf_dma_mode:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
Force DMA to use the Store and Forward mode for both tx and
rx. This flag is ignored if force_thresh_dma_mode is set.
snps,en-tx-lpi-clockgating:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
Enable gating of the MAC TX clock during TX low-power mode
snps,multicast-filter-bins:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description:
Number of multicast filter hash bins supported by this device
instance
snps,perfect-filter-entries:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description:
Number of perfect filter entries supported by this device
instance
snps,ps-speed:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description:
Port selection speed that can be passed to the core when PCS
is supported. For example, this is used in case of SGMII and
@@ -307,25 +307,25 @@ allOf:
snps,pbl:
description:
Programmable Burst Length (tx and rx)
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
enum: [2, 4, 8]
snps,txpbl:
description:
Tx Programmable Burst Length. If set, DMA tx will use this
value rather than snps,pbl.
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
enum: [2, 4, 8]
snps,rxpbl:
description:
Rx Programmable Burst Length. If set, DMA rx will use this
value rather than snps,pbl.
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
enum: [2, 4, 8]
snps,no-pbl-x8:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
Don\'t multiply the pbl/txpbl/rxpbl values by 8. For core
rev < 3.50, don\'t multiply the values by 4.
@@ -351,7 +351,7 @@ allOf:
then:
properties:
snps,tso:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
Enables the TSO feature otherwise it will be managed by
MAC HW capability register.
diff --git a/dts/Bindings/net/socionext,uniphier-ave4.yaml b/dts/Bindings/net/socionext,uniphier-ave4.yaml
index cbacc04fc9..8a03a24a20 100644
--- a/dts/Bindings/net/socionext,uniphier-ave4.yaml
+++ b/dts/Bindings/net/socionext,uniphier-ave4.yaml
@@ -64,7 +64,7 @@ properties:
- const: ether # for others
socionext,syscon-phy-mode:
- $ref: /schemas/types.yaml#definitions/phandle-array
+ $ref: /schemas/types.yaml#/definitions/phandle-array
description:
A phandle to syscon with one argument that configures phy mode.
The argument is the ID of MAC instance.
diff --git a/dts/Bindings/net/ti,cpsw-switch.yaml b/dts/Bindings/net/ti,cpsw-switch.yaml
index dadeb8f811..07a00f53ad 100644
--- a/dts/Bindings/net/ti,cpsw-switch.yaml
+++ b/dts/Bindings/net/ti,cpsw-switch.yaml
@@ -70,7 +70,7 @@ properties:
pinctrl-names: true
syscon:
- $ref: /schemas/types.yaml#definitions/phandle
+ $ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the system control device node which provides access to
efuse IO range with MAC addresses
diff --git a/dts/Bindings/net/ti,dp83867.yaml b/dts/Bindings/net/ti,dp83867.yaml
index 4050a36086..047d757e8d 100644
--- a/dts/Bindings/net/ti,dp83867.yaml
+++ b/dts/Bindings/net/ti,dp83867.yaml
@@ -47,31 +47,31 @@ properties:
takes precedence.
tx-fifo-depth:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description: |
Transmitt FIFO depth see dt-bindings/net/ti-dp83867.h for values
rx-fifo-depth:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description: |
Receive FIFO depth see dt-bindings/net/ti-dp83867.h for values
ti,clk-output-sel:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description: |
Muxing option for CLK_OUT pin. See dt-bindings/net/ti-dp83867.h
for applicable values. The CLK_OUT pin can also be disabled by this
property. When omitted, the PHY's default will be left as is.
ti,rx-internal-delay:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description: |
RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
for applicable values. Required only if interface type is
PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID.
ti,tx-internal-delay:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description: |
RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
for applicable values. Required only if interface type is
@@ -101,7 +101,7 @@ properties:
ti,fifo-depth:
deprecated: true
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description: |
Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h for applicable
values.
diff --git a/dts/Bindings/net/ti,dp83869.yaml b/dts/Bindings/net/ti,dp83869.yaml
index c3235f08e3..70a1209cb1 100644
--- a/dts/Bindings/net/ti,dp83869.yaml
+++ b/dts/Bindings/net/ti,dp83869.yaml
@@ -44,22 +44,22 @@ properties:
to a maximum value (70 ohms).
tx-fifo-depth:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description: |
Transmitt FIFO depth see dt-bindings/net/ti-dp83869.h for values
rx-fifo-depth:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description: |
Receive FIFO depth see dt-bindings/net/ti-dp83869.h for values
ti,clk-output-sel:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description: |
Muxing option for CLK_OUT pin see dt-bindings/net/ti-dp83869.h for values.
ti,op-mode:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description: |
Operational mode for the PHY. If this is not set then the operational
mode is set by the straps. see dt-bindings/net/ti-dp83869.h for values
diff --git a/dts/Bindings/net/ti,k3-am654-cpsw-nuss.yaml b/dts/Bindings/net/ti,k3-am654-cpsw-nuss.yaml
index 227270cbf8..c47b58f3e3 100644
--- a/dts/Bindings/net/ti,k3-am654-cpsw-nuss.yaml
+++ b/dts/Bindings/net/ti,k3-am654-cpsw-nuss.yaml
@@ -119,12 +119,12 @@ properties:
description: label associated with this port
ti,mac-only:
- $ref: /schemas/types.yaml#definitions/flag
+ $ref: /schemas/types.yaml#/definitions/flag
description:
Specifies the port works in mac-only mode.
ti,syscon-efuse:
- $ref: /schemas/types.yaml#definitions/phandle-array
+ $ref: /schemas/types.yaml#/definitions/phandle-array
description:
Phandle to the system control device node which provides access
to efuse IO range with MAC addresses
diff --git a/dts/Bindings/net/wireless/qcom,ath11k.yaml b/dts/Bindings/net/wireless/qcom,ath11k.yaml
index 4b365c9d93..85c2f699d6 100644
--- a/dts/Bindings/net/wireless/qcom,ath11k.yaml
+++ b/dts/Bindings/net/wireless/qcom,ath11k.yaml
@@ -136,7 +136,7 @@ properties:
- const: tcl2host-status-ring
qcom,rproc:
- $ref: /schemas/types.yaml#definitions/phandle
+ $ref: /schemas/types.yaml#/definitions/phandle
description:
DT entry of q6v5-wcss remoteproc driver.
Phandle to a node that can contain the following properties
@@ -144,6 +144,12 @@ properties:
* reg
* reg-names
+ qcom,ath11k-calibration-variant:
+ $ref: /schemas/types.yaml#/definitions/string
+ description:
+ string to uniquely identify variant of the calibration data in the
+ board-2.bin for designs with colliding bus and device specific ids
+
required:
- compatible
- reg
diff --git a/dts/Bindings/nvmem/mtk-efuse.txt b/dts/Bindings/nvmem/mtk-efuse.txt
index 0668c45a15..ef93c3b954 100644
--- a/dts/Bindings/nvmem/mtk-efuse.txt
+++ b/dts/Bindings/nvmem/mtk-efuse.txt
@@ -7,6 +7,7 @@ Required properties:
"mediatek,mt7622-efuse", "mediatek,efuse": for MT7622
"mediatek,mt7623-efuse", "mediatek,efuse": for MT7623
"mediatek,mt8173-efuse" or "mediatek,efuse": for MT8173
+ "mediatek,mt8516-efuse", "mediatek,efuse": for MT8516
- reg: Should contain registers location and length
= Data cells =
diff --git a/dts/Bindings/nvmem/qcom,qfprom.yaml b/dts/Bindings/nvmem/qcom,qfprom.yaml
index 1a18b6bab3..992777c90a 100644
--- a/dts/Bindings/nvmem/qcom,qfprom.yaml
+++ b/dts/Bindings/nvmem/qcom,qfprom.yaml
@@ -14,7 +14,18 @@ allOf:
properties:
compatible:
- const: qcom,qfprom
+ items:
+ - enum:
+ - qcom,apq8064-qfprom
+ - qcom,apq8084-qfprom
+ - qcom,msm8974-qfprom
+ - qcom,msm8916-qfprom
+ - qcom,msm8996-qfprom
+ - qcom,msm8998-qfprom
+ - qcom,qcs404-qfprom
+ - qcom,sc7180-qfprom
+ - qcom,sdm845-qfprom
+ - const: qcom,qfprom
reg:
# If the QFPROM is read-only OS image then only the corrected region
@@ -60,7 +71,7 @@ examples:
#size-cells = <2>;
efuse@784000 {
- compatible = "qcom,qfprom";
+ compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
reg = <0 0x00784000 0 0x8ff>,
<0 0x00780000 0 0x7a0>,
<0 0x00782000 0 0x100>,
@@ -85,7 +96,7 @@ examples:
#size-cells = <2>;
efuse@784000 {
- compatible = "qcom,qfprom";
+ compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
reg = <0 0x00784000 0 0x8ff>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/dts/Bindings/opp/opp.txt b/dts/Bindings/opp/opp.txt
index 9847dfeeff..08b3da4736 100644
--- a/dts/Bindings/opp/opp.txt
+++ b/dts/Bindings/opp/opp.txt
@@ -65,7 +65,9 @@ Required properties:
- OPP nodes: One or more OPP nodes describing voltage-current-frequency
combinations. Their name isn't significant but their phandle can be used to
- reference an OPP.
+ reference an OPP. These are mandatory except for the case where the OPP table
+ is present only to indicate dependency between devices using the opp-shared
+ property.
Optional properties:
- opp-shared: Indicates that device nodes using this OPP Table Node's phandle
@@ -568,3 +570,53 @@ Example 6: opp-microvolt-<name>, opp-microamp-<name>:
};
};
};
+
+Example 7: Single cluster Quad-core ARM cortex A53, OPP points from firmware,
+distinct clock controls but two sets of clock/voltage/current lines.
+
+/ {
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x100>;
+ next-level-cache = <&A53_L2>;
+ clocks = <&dvfs_controller 0>;
+ operating-points-v2 = <&cpu_opp0_table>;
+ };
+ cpu@1 {
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x101>;
+ next-level-cache = <&A53_L2>;
+ clocks = <&dvfs_controller 1>;
+ operating-points-v2 = <&cpu_opp0_table>;
+ };
+ cpu@2 {
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x102>;
+ next-level-cache = <&A53_L2>;
+ clocks = <&dvfs_controller 2>;
+ operating-points-v2 = <&cpu_opp1_table>;
+ };
+ cpu@3 {
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x103>;
+ next-level-cache = <&A53_L2>;
+ clocks = <&dvfs_controller 3>;
+ operating-points-v2 = <&cpu_opp1_table>;
+ };
+
+ };
+
+ cpu_opp0_table: opp0_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+ };
+
+ cpu_opp1_table: opp1_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+ };
+};
diff --git a/dts/Bindings/pci/cdns-pcie-ep.yaml b/dts/Bindings/pci/cdns-pcie-ep.yaml
index 60b8baf299..21e8a88490 100644
--- a/dts/Bindings/pci/cdns-pcie-ep.yaml
+++ b/dts/Bindings/pci/cdns-pcie-ep.yaml
@@ -20,7 +20,4 @@ properties:
maximum: 32
default: 32
-required:
- - cdns,max-outbound-regions
-
additionalProperties: true
diff --git a/dts/Bindings/pci/qcom,pcie.txt b/dts/Bindings/pci/qcom,pcie.txt
index 02bc81bb8b..3b55310390 100644
--- a/dts/Bindings/pci/qcom,pcie.txt
+++ b/dts/Bindings/pci/qcom,pcie.txt
@@ -13,6 +13,7 @@
- "qcom,pcie-ipq8074" for ipq8074
- "qcom,pcie-qcs404" for qcs404
- "qcom,pcie-sdm845" for sdm845
+ - "qcom,pcie-sm8250" for sm8250
- reg:
Usage: required
@@ -27,6 +28,7 @@
- "dbi" DesignWare PCIe registers
- "elbi" External local bus interface registers
- "config" PCIe configuration space
+ - "atu" ATU address space (optional)
- device_type:
Usage: required
@@ -131,7 +133,7 @@
- "slave_bus" AXI Slave clock
-clock-names:
- Usage: required for sdm845
+ Usage: required for sdm845 and sm8250
Value type: <stringlist>
Definition: Should contain the following entries
- "aux" Auxiliary clock
@@ -206,7 +208,7 @@
- "ahb" AHB reset
- reset-names:
- Usage: required for sdm845
+ Usage: required for sdm845 and sm8250
Value type: <stringlist>
Definition: Should contain the following entries
- "pci" PCIe core reset
diff --git a/dts/Bindings/pci/rcar-pci-ep.yaml b/dts/Bindings/pci/rcar-pci-ep.yaml
index 84eeb7fe6e..295840cf61 100644
--- a/dts/Bindings/pci/rcar-pci-ep.yaml
+++ b/dts/Bindings/pci/rcar-pci-ep.yaml
@@ -32,6 +32,10 @@ properties:
- const: memory2
- const: memory3
+ interrupts:
+ minItems: 3
+ maxItems: 3
+
power-domains:
maxItems: 1
@@ -53,6 +57,7 @@ required:
- compatible
- reg
- reg-names
+ - interrupts
- resets
- power-domains
- clocks
@@ -64,6 +69,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a774c0-sysc.h>
pcie0_ep: pcie-ep@fe000000 {
@@ -75,6 +81,9 @@ examples:
<0x30000000 0x8000000>,
<0x38000000 0x8000000>;
reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
resets = <&cpg 319>;
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
clocks = <&cpg CPG_MOD 319>;
diff --git a/dts/Bindings/pci/rcar-pci-host.yaml b/dts/Bindings/pci/rcar-pci-host.yaml
new file mode 100644
index 0000000000..4a2bcc0158
--- /dev/null
+++ b/dts/Bindings/pci/rcar-pci-host.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Renesas Electronics Corp.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/rcar-pci-host.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car PCIe Host
+
+maintainers:
+ - Marek Vasut <marek.vasut+renesas@gmail.com>
+ - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+
+allOf:
+ - $ref: pci-bus.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - renesas,pcie-r8a7742 # RZ/G1H
+ - renesas,pcie-r8a7743 # RZ/G1M
+ - renesas,pcie-r8a7744 # RZ/G1N
+ - renesas,pcie-r8a7790 # R-Car H2
+ - renesas,pcie-r8a7791 # R-Car M2-W
+ - renesas,pcie-r8a7793 # R-Car M2-N
+ - const: renesas,pcie-rcar-gen2 # R-Car Gen2 and RZ/G1
+ - items:
+ - enum:
+ - renesas,pcie-r8a774a1 # RZ/G2M
+ - renesas,pcie-r8a774b1 # RZ/G2N
+ - renesas,pcie-r8a774c0 # RZ/G2E
+ - renesas,pcie-r8a774e1 # RZ/G2H
+ - renesas,pcie-r8a7795 # R-Car H3
+ - renesas,pcie-r8a7796 # R-Car M3-W
+ - renesas,pcie-r8a77961 # R-Car M3-W+
+ - renesas,pcie-r8a77965 # R-Car M3-N
+ - renesas,pcie-r8a77980 # R-Car V3H
+ - renesas,pcie-r8a77990 # R-Car E3
+ - const: renesas,pcie-rcar-gen3 # R-Car Gen3 and RZ/G2
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 3
+ maxItems: 3
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: pcie
+ - const: pcie_bus
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ const: pcie
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+ - resets
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7791-sysc.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
+ reg = <0 0xfe000000 0 0x80000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
+ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
+ <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
+ <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>,
+ <0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
+ };
+ };
diff --git a/dts/Bindings/pci/rcar-pci.txt b/dts/Bindings/pci/rcar-pci.txt
deleted file mode 100644
index 14d307deff..0000000000
--- a/dts/Bindings/pci/rcar-pci.txt
+++ /dev/null
@@ -1,72 +0,0 @@
-* Renesas R-Car PCIe interface
-
-Required properties:
-compatible: "renesas,pcie-r8a7742" for the R8A7742 SoC;
- "renesas,pcie-r8a7743" for the R8A7743 SoC;
- "renesas,pcie-r8a7744" for the R8A7744 SoC;
- "renesas,pcie-r8a774a1" for the R8A774A1 SoC;
- "renesas,pcie-r8a774b1" for the R8A774B1 SoC;
- "renesas,pcie-r8a774c0" for the R8A774C0 SoC;
- "renesas,pcie-r8a7779" for the R8A7779 SoC;
- "renesas,pcie-r8a7790" for the R8A7790 SoC;
- "renesas,pcie-r8a7791" for the R8A7791 SoC;
- "renesas,pcie-r8a7793" for the R8A7793 SoC;
- "renesas,pcie-r8a7795" for the R8A7795 SoC;
- "renesas,pcie-r8a7796" for the R8A77960 SoC;
- "renesas,pcie-r8a77961" for the R8A77961 SoC;
- "renesas,pcie-r8a77980" for the R8A77980 SoC;
- "renesas,pcie-r8a77990" for the R8A77990 SoC;
- "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or
- RZ/G1 compatible device.
- "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 or
- RZ/G2 compatible device.
-
- When compatible with the generic version, nodes must list the
- SoC-specific version corresponding to the platform first
- followed by the generic version.
-
-- reg: base address and length of the PCIe controller registers.
-- #address-cells: set to <3>
-- #size-cells: set to <2>
-- bus-range: PCI bus numbers covered
-- device_type: set to "pci"
-- ranges: ranges for the PCI memory and I/O regions.
-- dma-ranges: ranges for the inbound memory regions.
-- interrupts: two interrupt sources for MSI interrupts, followed by interrupt
- source for hardware related interrupts (e.g. link speed change).
-- #interrupt-cells: set to <1>
-- interrupt-map-mask and interrupt-map: standard PCI properties
- to define the mapping of the PCIe interface to interrupt numbers.
-- clocks: from common clock binding: clock specifiers for the PCIe controller
- and PCIe bus clocks.
-- clock-names: from common clock binding: should be "pcie" and "pcie_bus".
-
-Optional properties:
-- phys: from common PHY binding: PHY phandle and specifier (only make sense
- for R-Car gen3 SoCs where the PCIe PHYs have their own register blocks).
-- phy-names: from common PHY binding: should be "pcie".
-
-Example:
-
-SoC-specific DT Entry:
-
- pcie: pcie@fe000000 {
- compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
- reg = <0 0xfe000000 0 0x80000>;
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x00 0xff>;
- device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
- 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
- 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
- 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000
- 0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
- interrupts = <0 116 4>, <0 117 4>, <0 118 4>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 116 4>;
- clocks = <&mstp3_clks R8A7791_CLK_PCIE>, <&pcie_bus_clk>;
- clock-names = "pcie", "pcie_bus";
- };
diff --git a/dts/Bindings/pci/samsung,exynos-pcie.yaml b/dts/Bindings/pci/samsung,exynos-pcie.yaml
new file mode 100644
index 0000000000..1810bf7223
--- /dev/null
+++ b/dts/Bindings/pci/samsung,exynos-pcie.yaml
@@ -0,0 +1,119 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series PCIe Host Controller Device Tree Bindings
+
+maintainers:
+ - Marek Szyprowski <m.szyprowski@samsung.com>
+ - Jaehoon Chung <jh80.chung@samsung.com>
+
+description: |+
+ Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
+ PCIe IP and thus inherits all the common properties defined in
+ designware-pcie.txt.
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+ compatible:
+ const: samsung,exynos5433-pcie
+
+ reg:
+ items:
+ - description: Data Bus Interface (DBI) registers.
+ - description: External Local Bus interface (ELBI) registers.
+ - description: PCIe configuration space region.
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: elbi
+ - const: config
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: PCIe bridge clock
+ - description: PCIe bus clock
+
+ clock-names:
+ items:
+ - const: pcie
+ - const: pcie_bus
+
+ phys:
+ maxItems: 1
+
+ vdd10-supply:
+ description:
+ Phandle to a regulator that provides 1.0V power to the PCIe block.
+
+ vdd18-supply:
+ description:
+ Phandle to a regulator that provides 1.8V power to the PCIe block.
+
+ num-lanes:
+ const: 1
+
+ num-viewport:
+ const: 3
+
+required:
+ - reg
+ - reg-names
+ - interrupts
+ - "#address-cells"
+ - "#size-cells"
+ - "#interrupt-cells"
+ - interrupt-map
+ - interrupt-map-mask
+ - ranges
+ - bus-range
+ - device_type
+ - num-lanes
+ - num-viewport
+ - clocks
+ - clock-names
+ - phys
+ - vdd10-supply
+ - vdd18-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/exynos5433.h>
+
+ pcie: pcie@15700000 {
+ compatible = "samsung,exynos5433-pcie";
+ reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, <0x0c000000 0x1000>;
+ reg-names = "dbi", "elbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>;
+ clock-names = "pcie", "pcie_bus";
+ phys = <&pcie_phy>;
+ pinctrl-0 = <&pcie_bus &pcie_wlanen>;
+ pinctrl-names = "default";
+ num-lanes = <1>;
+ num-viewport = <3>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>,
+ <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;
+ vdd10-supply = <&ldo6_reg>;
+ vdd18-supply = <&ldo7_reg>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+ };
+...
diff --git a/dts/Bindings/pci/samsung,exynos5440-pcie.txt b/dts/Bindings/pci/samsung,exynos5440-pcie.txt
deleted file mode 100644
index 651d957d10..0000000000
--- a/dts/Bindings/pci/samsung,exynos5440-pcie.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-* Samsung Exynos 5440 PCIe interface
-
-This PCIe host controller is based on the Synopsys DesignWare PCIe IP
-and thus inherits all the common properties defined in designware-pcie.txt.
-
-Required properties:
-- compatible: "samsung,exynos5440-pcie"
-- reg: base addresses and lengths of the PCIe controller,
-- reg-names : First name should be set to "elbi".
- And use the "config" instead of getting the configuration address space
- from "ranges".
- NOTE: When using the "config" property, reg-names must be set.
-- interrupts: A list of interrupt outputs for level interrupt,
- pulse interrupt, special interrupt.
-- phys: From PHY binding. Phandle for the generic PHY.
- Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
-
-For other common properties, refer to
- Documentation/devicetree/bindings/pci/designware-pcie.txt
-
-Example:
-
-SoC-specific DT Entry (with using PHY framework):
-
- pcie_phy0: pcie-phy@270000 {
- ...
- reg = <0x270000 0x1000>, <0x271000 0x40>;
- reg-names = "phy", "block";
- ...
- };
-
- pcie@290000 {
- compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
- reg = <0x290000 0x1000>, <0x40000000 0x1000>;
- reg-names = "elbi", "config";
- clocks = <&clock 28>, <&clock 27>;
- clock-names = "pcie", "pcie_bus";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- phys = <&pcie_phy0>;
- ranges = <0x81000000 0 0 0x60001000 0 0x00010000
- 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- num-lanes = <4>;
- };
-
-Board-specific DT Entry:
-
- pcie@290000 {
- reset-gpio = <&pin_ctrl 5 0>;
- };
-
- pcie@2a0000 {
- reset-gpio = <&pin_ctrl 22 0>;
- };
diff --git a/dts/Bindings/pci/ti,j721e-pci-ep.yaml b/dts/Bindings/pci/ti,j721e-pci-ep.yaml
index 3ae3e1a2d4..d06f0c4464 100644
--- a/dts/Bindings/pci/ti,j721e-pci-ep.yaml
+++ b/dts/Bindings/pci/ti,j721e-pci-ep.yaml
@@ -15,8 +15,14 @@ allOf:
properties:
compatible:
- enum:
- - ti,j721e-pcie-ep
+ oneOf:
+ - description: PCIe EP controller in J7200
+ items:
+ - const: ti,j7200-pcie-ep
+ - const: ti,j721e-pcie-ep
+ - description: PCIe EP controller in J721E
+ items:
+ - const: ti,j721e-pcie-ep
reg:
maxItems: 4
@@ -29,9 +35,12 @@ properties:
- const: mem
ti,syscon-pcie-ctrl:
- description: Phandle to the SYSCON entry required for configuring PCIe mode
- and link speed.
- $ref: /schemas/types.yaml#/definitions/phandle
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: Phandle to the SYSCON entry
+ - description: pcie_ctrl register offset within SYSCON
+ description: Specifier for configuring PCIe mode and link speed.
power-domains:
maxItems: 1
@@ -57,7 +66,6 @@ required:
- power-domains
- clocks
- clock-names
- - cdns,max-outbound-regions
- dma-coherent
- max-functions
- phys
@@ -80,13 +88,12 @@ examples:
<0x00 0x0d000000 0x00 0x00800000>,
<0x00 0x10000000 0x00 0x08000000>;
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
- ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
+ ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 239 1>;
clock-names = "fck";
- cdns,max-outbound-regions = <16>;
max-functions = /bits/ 8 <6>;
dma-coherent;
phys = <&serdes0_pcie_link>;
diff --git a/dts/Bindings/pci/ti,j721e-pci-host.yaml b/dts/Bindings/pci/ti,j721e-pci-host.yaml
index ee7a8eade3..0880a613ec 100644
--- a/dts/Bindings/pci/ti,j721e-pci-host.yaml
+++ b/dts/Bindings/pci/ti,j721e-pci-host.yaml
@@ -15,8 +15,14 @@ allOf:
properties:
compatible:
- enum:
- - ti,j721e-pcie-host
+ oneOf:
+ - description: PCIe controller in J7200
+ items:
+ - const: ti,j7200-pcie-host
+ - const: ti,j721e-pcie-host
+ - description: PCIe controller in J721E
+ items:
+ - const: ti,j721e-pcie-host
reg:
maxItems: 4
@@ -29,9 +35,12 @@ properties:
- const: cfg
ti,syscon-pcie-ctrl:
- description: Phandle to the SYSCON entry required for configuring PCIe mode
- and link speed.
- $ref: /schemas/types.yaml#/definitions/phandle
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: Phandle to the SYSCON entry
+ - description: pcie_ctrl register offset within SYSCON
+ description: Specifier for configuring PCIe mode and link speed.
power-domains:
maxItems: 1
@@ -48,7 +57,11 @@ properties:
const: 0x104c
device-id:
- const: 0xb00d
+ oneOf:
+ - items:
+ - const: 0xb00d
+ - items:
+ - const: 0xb00f
msi-map: true
@@ -90,7 +103,7 @@ examples:
<0x00 0x0d000000 0x00 0x00800000>,
<0x00 0x10000000 0x00 0x00001000>;
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
- ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
+ ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
diff --git a/dts/Bindings/perf/fsl-imx-ddr.yaml b/dts/Bindings/perf/fsl-imx-ddr.yaml
index 5aad9f4e0b..80a9238536 100644
--- a/dts/Bindings/perf/fsl-imx-ddr.yaml
+++ b/dts/Bindings/perf/fsl-imx-ddr.yaml
@@ -15,6 +15,9 @@ properties:
- enum:
- fsl,imx8-ddr-pmu
- fsl,imx8m-ddr-pmu
+ - fsl,imx8mq-ddr-pmu
+ - fsl,imx8mm-ddr-pmu
+ - fsl,imx8mn-ddr-pmu
- fsl,imx8mp-ddr-pmu
- items:
- enum:
diff --git a/dts/Bindings/phy/amlogic,axg-mipi-dphy.yaml b/dts/Bindings/phy/amlogic,axg-mipi-dphy.yaml
new file mode 100644
index 0000000000..be485f5008
--- /dev/null
+++ b/dts/Bindings/phy/amlogic,axg-mipi-dphy.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2020 BayLibre, SAS
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/amlogic,axg-mipi-dphy.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic AXG MIPI D-PHY
+
+maintainers:
+ - Neil Armstrong <narmstrong@baylibre.com>
+
+properties:
+ compatible:
+ enum:
+ - amlogic,axg-mipi-dphy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: pclk
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: phy
+
+ "#phy-cells":
+ const: 0
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ items:
+ - const: analog
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - phys
+ - phy-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@ff640000 {
+ compatible = "amlogic,axg-mipi-dphy";
+ reg = <0xff640000 0x100>;
+ clocks = <&clk_mipi_dsi_phy>;
+ clock-names = "pclk";
+ resets = <&reset_phy>;
+ reset-names = "phy";
+ phys = <&mipi_pcie_analog_dphy>;
+ phy-names = "analog";
+ #phy-cells = <0>;
+ };
diff --git a/dts/Bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml b/dts/Bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml
index 18c1ec5e19..4d01f3124e 100644
--- a/dts/Bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml
+++ b/dts/Bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml
@@ -9,27 +9,32 @@ title: Amlogic AXG shared MIPI/PCIE analog PHY
maintainers:
- Remi Pommarel <repk@triplefau.lt>
+description: |+
+ The Everything-Else Power Domains node should be the child of a syscon
+ node with the required property:
+
+ - compatible: Should be the following:
+ "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"
+
+ Refer to the the bindings described in
+ Documentation/devicetree/bindings/mfd/syscon.yaml
+
properties:
compatible:
const: amlogic,axg-mipi-pcie-analog-phy
- reg:
- maxItems: 1
-
"#phy-cells":
- const: 1
+ const: 0
required:
- compatible
- - reg
- "#phy-cells"
additionalProperties: false
examples:
- |
- mpphy: phy@0 {
+ mpphy: phy {
compatible = "amlogic,axg-mipi-pcie-analog-phy";
- reg = <0x0 0xc>;
- #phy-cells = <1>;
+ #phy-cells = <0>;
};
diff --git a/dts/Bindings/phy/brcm,sata-phy.yaml b/dts/Bindings/phy/brcm,sata-phy.yaml
new file mode 100644
index 0000000000..58c3ef8004
--- /dev/null
+++ b/dts/Bindings/phy/brcm,sata-phy.yaml
@@ -0,0 +1,148 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/brcm,sata-phy.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Broadcom SATA3 PHY
+
+maintainers:
+ - Florian Fainelli <f.fainelli@gmail.com>
+
+properties:
+ $nodename:
+ pattern: "^sata[-|_]phy(@.*)?$"
+
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - brcm,bcm7216-sata-phy
+ - brcm,bcm7425-sata-phy
+ - brcm,bcm7445-sata-phy
+ - brcm,bcm63138-sata-phy
+ - const: brcm,phy-sata3
+ - items:
+ - const: brcm,iproc-nsp-sata-phy
+ - items:
+ - const: brcm,iproc-ns2-sata-phy
+ - items:
+ - const: brcm,iproc-sr-sata-phy
+
+ reg:
+ minItems: 1
+ maxItems: 2
+
+ reg-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: phy
+ - const: phy-ctrl
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+patternProperties:
+ "^sata-phy@[0-9]+$":
+ type: object
+ description: |
+ Each port's PHY should be represented as a sub-node.
+
+ properties:
+ reg:
+ description: The SATA PHY port number
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ "brcm,enable-ssc":
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: |
+ Use spread spectrum clocking (SSC) on this port
+ This property is not applicable for "brcm,iproc-ns2-sata-phy",
+ "brcm,iproc-nsp-sata-phy" and "brcm,iproc-sr-sata-phy".
+
+ "brcm,rxaeq-mode":
+ $ref: /schemas/types.yaml#/definitions/string
+ description:
+ String that indicates the desired RX equalizer mode.
+ enum:
+ - off
+ - auto
+ - manual
+
+ "brcm,rxaeq-value":
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ When 'brcm,rxaeq-mode' is set to "manual", provides the RX
+ equalizer value that should be used.
+ minimum: 0
+ maximum: 63
+
+ "brcm,tx-amplitude-millivolt":
+ description: |
+ Transmit amplitude voltage in millivolt.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [400, 500, 600, 800]
+
+ required:
+ - reg
+ - "#phy-cells"
+
+ additionalProperties: false
+
+if:
+ properties:
+ compatible:
+ items:
+ const: brcm,iproc-ns2-sata-phy
+then:
+ properties:
+ reg:
+ maxItems: 2
+ reg-names:
+ items:
+ - const: "phy"
+ - const: "phy-ctrl"
+else:
+ properties:
+ reg:
+ maxItems: 1
+ reg-names:
+ maxItems: 1
+ items:
+ - const: "phy"
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+ - reg
+ - reg-names
+
+additionalProperties: false
+
+examples:
+ - |
+ sata_phy@f0458100 {
+ compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3";
+ reg = <0xf0458100 0x1e00>;
+ reg-names = "phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sata-phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ sata-phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+ };
diff --git a/dts/Bindings/phy/brcm-sata-phy.txt b/dts/Bindings/phy/brcm-sata-phy.txt
deleted file mode 100644
index c03ad21984..0000000000
--- a/dts/Bindings/phy/brcm-sata-phy.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-* Broadcom SATA3 PHY
-
-Required properties:
-- compatible: should be one or more of
- "brcm,bcm7216-sata-phy"
- "brcm,bcm7425-sata-phy"
- "brcm,bcm7445-sata-phy"
- "brcm,iproc-ns2-sata-phy"
- "brcm,iproc-nsp-sata-phy"
- "brcm,phy-sata3"
- "brcm,iproc-sr-sata-phy"
- "brcm,bcm63138-sata-phy"
-- address-cells: should be 1
-- size-cells: should be 0
-- reg: register ranges for the PHY PCB interface
-- reg-names: should be "phy" and "phy-ctrl"
- The "phy-ctrl" registers are only required for
- "brcm,iproc-ns2-sata-phy" and "brcm,iproc-sr-sata-phy".
-
-Sub-nodes:
- Each port's PHY should be represented as a sub-node.
-
-Sub-nodes required properties:
-- reg: the PHY number
-- phy-cells: generic PHY binding; must be 0
-
-Sub-nodes optional properties:
-- brcm,enable-ssc: use spread spectrum clocking (SSC) on this port
- This property is not applicable for "brcm,iproc-ns2-sata-phy",
- "brcm,iproc-nsp-sata-phy" and "brcm,iproc-sr-sata-phy".
-
-- brcm,rxaeq-mode: string that indicates the desired RX equalizer
- mode, possible values are:
- "off" (equivalent to not specifying the property)
- "auto"
- "manual" (brcm,rxaeq-value is used in that case)
-
-- brcm,rxaeq-value: when 'rxaeq-mode' is set to "manual", provides the RX
- equalizer value that should be used. Allowed range is 0..63.
-
-Example
- sata-phy@f0458100 {
- compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3";
- reg = <0xf0458100 0x1e00>, <0xf045804c 0x10>;
- reg-names = "phy";
- #address-cells = <1>;
- #size-cells = <0>;
-
- sata-phy@0 {
- reg = <0>;
- #phy-cells = <0>;
- };
-
- sata-phy@1 {
- reg = <1>;
- #phy-cells = <0>;
- };
- };
diff --git a/dts/Bindings/usb/ingenic,jz4770-phy.yaml b/dts/Bindings/phy/ingenic,phy-usb.yaml
index 2d61166ea5..0fd93d71fe 100644
--- a/dts/Bindings/usb/ingenic,jz4770-phy.yaml
+++ b/dts/Bindings/phy/ingenic,phy-usb.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: http://devicetree.org/schemas/usb/ingenic,jz4770-phy.yaml#
+$id: http://devicetree.org/schemas/phy/ingenic,phy-usb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ingenic SoCs USB PHY devicetree bindings
@@ -17,9 +17,11 @@ properties:
compatible:
enum:
- ingenic,jz4770-phy
+ - ingenic,jz4775-phy
- ingenic,jz4780-phy
- ingenic,x1000-phy
- ingenic,x1830-phy
+ - ingenic,x2000-phy
reg:
maxItems: 1
diff --git a/dts/Bindings/phy/intel,phy-keembay-usb.yaml b/dts/Bindings/phy/intel,phy-keembay-usb.yaml
new file mode 100644
index 0000000000..a217bb8ac5
--- /dev/null
+++ b/dts/Bindings/phy/intel,phy-keembay-usb.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/intel,phy-keembay-usb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Keem Bay USB PHY bindings
+
+maintainers:
+ - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
+
+properties:
+ compatible:
+ const: intel,keembay-usb-phy
+
+ reg:
+ items:
+ - description: USB APB CPR (clock, power, reset) register
+ - description: USB APB slave register
+
+ reg-names:
+ items:
+ - const: cpr-apb-base
+ - const: slv-apb-base
+
+ '#phy-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ usb-phy@20400000 {
+ compatible = "intel,keembay-usb-phy";
+ reg = <0x20400000 0x1c>,
+ <0x20480000 0xd0>;
+ reg-names = "cpr-apb-base", "slv-apb-base";
+ #phy-cells = <0>;
+ };
diff --git a/dts/Bindings/phy/marvell,mmp3-hsic-phy.yaml b/dts/Bindings/phy/marvell,mmp3-hsic-phy.yaml
index 00609ace67..ff255aa4cc 100644
--- a/dts/Bindings/phy/marvell,mmp3-hsic-phy.yaml
+++ b/dts/Bindings/phy/marvell,mmp3-hsic-phy.yaml
@@ -1,4 +1,4 @@
-# SPDX-License-Identifier: GPL-2.0-or-later
+# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
# Copyright 2019 Lubomir Rintel <lkundrak@v3.sk>
%YAML 1.2
---
@@ -18,27 +18,20 @@ properties:
maxItems: 1
description: base address of the device
- reset-gpios:
- maxItems: 1
- description: GPIO connected to reset
-
"#phy-cells":
const: 0
required:
- compatible
- reg
- - reset-gpios
- "#phy-cells"
additionalProperties: false
examples:
- |
- #include <dt-bindings/gpio/gpio.h>
hsic-phy@f0001800 {
compatible = "marvell,mmp3-hsic-phy";
reg = <0xf0001800 0x40>;
- reset-gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
#phy-cells = <0>;
};
diff --git a/dts/Bindings/phy/mediatek,mt7621-pci-phy.yaml b/dts/Bindings/phy/mediatek,mt7621-pci-phy.yaml
new file mode 100644
index 0000000000..0ccaded3f2
--- /dev/null
+++ b/dts/Bindings/phy/mediatek,mt7621-pci-phy.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/mediatek,mt7621-pci-phy.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Mediatek Mt7621 PCIe PHY Device Tree Bindings
+
+maintainers:
+ - Sergio Paracuellos <sergio.paracuellos@gmail.com>
+
+properties:
+ compatible:
+ const: mediatek,mt7621-pci-phy
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 1
+ description: selects if the phy is dual-ported
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ pcie0_phy: pcie-phy@1e149000 {
+ compatible = "mediatek,mt7621-pci-phy";
+ reg = <0x1e149000 0x0700>;
+ #phy-cells = <1>;
+ };
diff --git a/dts/Bindings/phy/phy-cadence-sierra.txt b/dts/Bindings/phy/phy-cadence-sierra.txt
deleted file mode 100644
index 03f5939d3d..0000000000
--- a/dts/Bindings/phy/phy-cadence-sierra.txt
+++ /dev/null
@@ -1,70 +0,0 @@
-Cadence Sierra PHY
------------------------
-
-Required properties:
-- compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform
- Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC.
-- resets: Must contain an entry for each in reset-names.
- See ../reset/reset.txt for details.
-- reset-names: Must include "sierra_reset" and "sierra_apb".
- "sierra_reset" must control the reset line to the PHY.
- "sierra_apb" must control the reset line to the APB PHY
- interface ("sierra_apb" is optional).
-- reg: register range for the PHY.
-- #address-cells: Must be 1
-- #size-cells: Must be 0
-
-Optional properties:
-- clocks: Must contain an entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
-- clock-names: Must contain "cmn_refclk_dig_div" and
- "cmn_refclk1_dig_div" for configuring the frequency of
- the clock to the lanes. "phy_clk" is deprecated.
-- cdns,autoconf: A boolean property whose presence indicates that the
- PHY registers will be configured by hardware. If not
- present, all sub-node optional properties must be
- provided.
-
-Sub-nodes:
- Each group of PHY lanes with a single master lane should be represented as
- a sub-node. Note that the actual configuration of each lane is determined by
- hardware strapping, and must match the configuration specified here.
-
-Sub-node required properties:
-- #phy-cells: Generic PHY binding; must be 0.
-- reg: The master lane number. This is the lowest numbered lane
- in the lane group.
-- resets: Must contain one entry which controls the reset line for the
- master lane of the sub-node.
- See ../reset/reset.txt for details.
-
-Sub-node optional properties:
-- cdns,num-lanes: Number of lanes in this group. From 1 to 4. The
- group is made up of consecutive lanes.
-- cdns,phy-type: Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on
- configuration of lanes.
-
-Example:
- pcie_phy4: pcie-phy@fd240000 {
- compatible = "cdns,sierra-phy-t0";
- reg = <0x0 0xfd240000 0x0 0x40000>;
- resets = <&phyrst 0>, <&phyrst 1>;
- reset-names = "sierra_reset", "sierra_apb";
- clocks = <&phyclock>;
- clock-names = "phy_clk";
- #address-cells = <1>;
- #size-cells = <0>;
- pcie0_phy0: pcie-phy@0 {
- reg = <0>;
- resets = <&phyrst 2>;
- cdns,num-lanes = <2>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_PCIE>;
- };
- pcie0_phy1: pcie-phy@2 {
- reg = <2>;
- resets = <&phyrst 4>;
- cdns,num-lanes = <1>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_PCIE>;
- };
diff --git a/dts/Bindings/phy/phy-cadence-sierra.yaml b/dts/Bindings/phy/phy-cadence-sierra.yaml
new file mode 100644
index 0000000000..d210843863
--- /dev/null
+++ b/dts/Bindings/phy/phy-cadence-sierra.yaml
@@ -0,0 +1,152 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Cadence Sierra PHY binding
+
+description:
+ This binding describes the Cadence Sierra PHY. Sierra PHY supports multilink
+ multiprotocol combinations including protocols such as PCIe, USB etc.
+
+maintainers:
+ - Swapnil Jakhade <sjakhade@cadence.com>
+ - Yuti Amonkar <yamonkar@cadence.com>
+
+properties:
+ compatible:
+ enum:
+ - cdns,sierra-phy-t0
+ - ti,sierra-phy-t0
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ resets:
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: Sierra PHY reset.
+ - description: Sierra APB reset. This is optional.
+
+ reset-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: sierra_reset
+ - const: sierra_apb
+
+ reg:
+ maxItems: 1
+ description:
+ Offset of the Sierra PHY configuration registers.
+
+ reg-names:
+ const: serdes
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: cmn_refclk_dig_div
+ - const: cmn_refclk1_dig_div
+
+ cdns,autoconf:
+ type: boolean
+ description:
+ A boolean property whose presence indicates that the PHY registers will be
+ configured by hardware. If not present, all sub-node optional properties
+ must be provided.
+
+patternProperties:
+ '^phy@[0-9a-f]$':
+ type: object
+ description:
+ Each group of PHY lanes with a single master lane should be represented as
+ a sub-node. Note that the actual configuration of each lane is determined
+ by hardware strapping, and must match the configuration specified here.
+ properties:
+ reg:
+ description:
+ The master lane number. This is the lowest numbered lane in the lane group.
+ minimum: 0
+ maximum: 15
+
+ resets:
+ minItems: 1
+ maxItems: 4
+ description:
+ Contains list of resets, one per lane, to get all the link lanes out of reset.
+
+ "#phy-cells":
+ const: 0
+
+ cdns,phy-type:
+ description:
+ Specifies the type of PHY for which the group of PHY lanes is used.
+ Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [2, 4]
+
+ cdns,num-lanes:
+ description:
+ Number of lanes in this group. The group is made up of consecutive lanes.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 16
+
+ required:
+ - reg
+ - resets
+ - "#phy-cells"
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+ - reg
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/phy/phy.h>
+
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ sierra-phy@fd240000 {
+ compatible = "cdns,sierra-phy-t0";
+ reg = <0x0 0xfd240000 0x0 0x40000>;
+ resets = <&phyrst 0>, <&phyrst 1>;
+ reset-names = "sierra_reset", "sierra_apb";
+ clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pcie0_phy0: phy@0 {
+ reg = <0>;
+ resets = <&phyrst 2>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ };
+ pcie0_phy1: phy@2 {
+ reg = <2>;
+ resets = <&phyrst 4>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ };
+ };
+ };
diff --git a/dts/Bindings/phy/phy-stm32-usbphyc.txt b/dts/Bindings/phy/phy-stm32-usbphyc.txt
deleted file mode 100644
index 725ae71ae6..0000000000
--- a/dts/Bindings/phy/phy-stm32-usbphyc.txt
+++ /dev/null
@@ -1,73 +0,0 @@
-STMicroelectronics STM32 USB HS PHY controller
-
-The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
-switch. It controls PHY configuration and status, and the UTMI+ switch that
-selects either OTG or HOST controller for the second PHY port. It also sets
-PLL configuration.
-
-USBPHYC
- |_ PLL
- |
- |_ PHY port#1 _________________ HOST controller
- | _ |
- | / 1|________________|
- |_ PHY port#2 ----| |________________
- | \_0| |
- |_ UTMI switch_______| OTG controller
-
-
-Phy provider node
-=================
-
-Required properties:
-- compatible: must be "st,stm32mp1-usbphyc"
-- reg: address and length of the usb phy control register set
-- clocks: phandle + clock specifier for the PLL phy clock
-- #address-cells: number of address cells for phys sub-nodes, must be <1>
-- #size-cells: number of size cells for phys sub-nodes, must be <0>
-
-Optional properties:
-- assigned-clocks: phandle + clock specifier for the PLL phy clock
-- assigned-clock-parents: the PLL phy clock parent
-- resets: phandle + reset specifier
-
-Required nodes: one sub-node per port the controller provides.
-
-Phy sub-nodes
-==============
-
-Required properties:
-- reg: phy port index
-- phy-supply: phandle to the regulator providing 3V3 power to the PHY,
- see phy-bindings.txt in the same directory.
-- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
-- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
-- #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY
- port#1 and must be <1> for PHY port#2, to select USB controller
-
-
-Example:
- usbphyc: usb-phy@5a006000 {
- compatible = "st,stm32mp1-usbphyc";
- reg = <0x5a006000 0x1000>;
- clocks = <&rcc_clk USBPHY_K>;
- resets = <&rcc_rst USBPHY_R>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- usbphyc_port0: usb-phy@0 {
- reg = <0>;
- phy-supply = <&vdd_usb>;
- vdda1v1-supply = <&reg11>;
- vdda1v8-supply = <&reg18>
- #phy-cells = <0>;
- };
-
- usbphyc_port1: usb-phy@1 {
- reg = <1>;
- phy-supply = <&vdd_usb>;
- vdda1v1-supply = <&reg11>;
- vdda1v8-supply = <&reg18>
- #phy-cells = <1>;
- };
- };
diff --git a/dts/Bindings/phy/phy-stm32-usbphyc.yaml b/dts/Bindings/phy/phy-stm32-usbphyc.yaml
new file mode 100644
index 0000000000..0ba61979b9
--- /dev/null
+++ b/dts/Bindings/phy/phy-stm32-usbphyc.yaml
@@ -0,0 +1,138 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 USB HS PHY controller binding
+
+description:
+
+ The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
+ switch. It controls PHY configuration and status, and the UTMI+ switch that
+ selects either OTG or HOST controller for the second PHY port. It also sets
+ PLL configuration.
+
+ USBPHYC
+ |_ PLL
+ |
+ |_ PHY port#1 _________________ HOST controller
+ | __ |
+ | / 1|________________|
+ |_ PHY port#2 ----| |________________
+ | \_0| |
+ |_ UTMI switch_______| OTG controller
+
+maintainers:
+ - Amelie Delaunay <amelie.delaunay@st.com>
+
+properties:
+ compatible:
+ const: st,stm32mp1-usbphyc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+#Required child nodes:
+
+patternProperties:
+ "^usb-phy@[0|1]$":
+ type: object
+ description:
+ Each port the controller provides must be represented as a sub-node.
+
+ properties:
+ reg:
+ description: phy port index.
+ maxItems: 1
+
+ phy-supply:
+ description: regulator providing 3V3 power supply to the PHY.
+
+ vdda1v1-supply:
+ description: regulator providing 1V1 power supply to the PLL block
+
+ vdda1v8-supply:
+ description: regulator providing 1V8 power supply to the PLL block
+
+ "#phy-cells":
+ enum: [ 0x0, 0x1 ]
+
+ allOf:
+ - if:
+ properties:
+ reg:
+ const: 0
+ then:
+ properties:
+ "#phy-cells":
+ const: 0
+ else:
+ properties:
+ "#phy-cells":
+ const: 1
+ description:
+ The value is used to select UTMI switch output.
+ 0 for OTG controller and 1 for Host controller.
+
+ required:
+ - reg
+ - phy-supply
+ - vdda1v1-supply
+ - vdda1v8-supply
+ - "#phy-cells"
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#address-cells"
+ - "#size-cells"
+ - usb-phy@0
+ - usb-phy@1
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/stm32mp1-clks.h>
+ #include <dt-bindings/reset/stm32mp1-resets.h>
+ usbphyc: usbphyc@5a006000 {
+ compatible = "st,stm32mp1-usbphyc";
+ reg = <0x5a006000 0x1000>;
+ clocks = <&rcc USBPHY_K>;
+ resets = <&rcc USBPHY_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbphyc_port0: usb-phy@0 {
+ reg = <0>;
+ phy-supply = <&vdd_usb>;
+ vdda1v1-supply = <&reg11>;
+ vdda1v8-supply = <&reg18>;
+ #phy-cells = <0>;
+ };
+
+ usbphyc_port1: usb-phy@1 {
+ reg = <1>;
+ phy-supply = <&vdd_usb>;
+ vdda1v1-supply = <&reg11>;
+ vdda1v8-supply = <&reg18>;
+ #phy-cells = <1>;
+ };
+ };
+...
diff --git a/dts/Bindings/phy/qcom,qmp-phy.yaml b/dts/Bindings/phy/qcom,qmp-phy.yaml
index 185cdea9cf..ec05db3746 100644
--- a/dts/Bindings/phy/qcom,qmp-phy.yaml
+++ b/dts/Bindings/phy/qcom,qmp-phy.yaml
@@ -31,6 +31,9 @@ properties:
- qcom,sdm845-qmp-usb3-uni-phy
- qcom,sm8150-qmp-ufs-phy
- qcom,sm8250-qmp-ufs-phy
+ - qcom,sm8250-qmp-gen3x1-pcie-phy
+ - qcom,sm8250-qmp-gen3x2-pcie-phy
+ - qcom,sm8250-qmp-modem-pcie-phy
reg:
items:
@@ -259,6 +262,9 @@ allOf:
enum:
- qcom,sdm845-qhp-pcie-phy
- qcom,sdm845-qmp-pcie-phy
+ - qcom,sm8250-qmp-gen3x1-pcie-phy
+ - qcom,sm8250-qmp-gen3x2-pcie-phy
+ - qcom,sm8250-qmp-modem-pcie-phy
then:
properties:
clocks:
diff --git a/dts/Bindings/phy/rockchip-emmc-phy.txt b/dts/Bindings/phy/rockchip-emmc-phy.txt
index e728786f21..00aa2d349e 100644
--- a/dts/Bindings/phy/rockchip-emmc-phy.txt
+++ b/dts/Bindings/phy/rockchip-emmc-phy.txt
@@ -16,6 +16,11 @@ Optional properties:
- drive-impedance-ohm: Specifies the drive impedance in Ohm.
Possible values are 33, 40, 50, 66 and 100.
If not set, the default value of 50 will be applied.
+ - enable-strobe-pulldown: Enable internal pull-down for the strobe line.
+ If not set, pull-down is not used.
+ - output-tapdelay-select: Specifies the phyctrl_otapdlysec register.
+ If not set, the register defaults to 0x4.
+ Maximum value 0xf.
Example:
diff --git a/dts/Bindings/phy/samsung,exynos-pcie-phy.yaml b/dts/Bindings/phy/samsung,exynos-pcie-phy.yaml
new file mode 100644
index 0000000000..ac0af40be5
--- /dev/null
+++ b/dts/Bindings/phy/samsung,exynos-pcie-phy.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,exynos-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series PCIe PHY Device Tree Bindings
+
+maintainers:
+ - Marek Szyprowski <m.szyprowski@samsung.com>
+ - Jaehoon Chung <jh80.chung@samsung.com>
+
+properties:
+ "#phy-cells":
+ const: 0
+
+ compatible:
+ const: samsung,exynos5433-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ samsung,pmu-syscon:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: phandle for PMU system controller interface, used to
+ control PMU registers bits for PCIe PHY
+
+ samsung,fsys-sysreg:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: phandle for FSYS sysreg interface, used to control
+ sysreg registers bits for PCIe PHY
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - samsung,pmu-syscon
+ - samsung,fsys-sysreg
+
+additionalProperties: false
+
+examples:
+ - |
+ pcie_phy: pcie-phy@15680000 {
+ compatible = "samsung,exynos5433-pcie-phy";
+ reg = <0x15680000 0x1000>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ samsung,fsys-sysreg = <&syscon_fsys>;
+ #phy-cells = <0>;
+ };
+...
diff --git a/dts/Bindings/phy/samsung-phy.txt b/dts/Bindings/phy/samsung-phy.txt
index 7510830a79..8f51aee911 100644
--- a/dts/Bindings/phy/samsung-phy.txt
+++ b/dts/Bindings/phy/samsung-phy.txt
@@ -47,6 +47,7 @@ Required properties:
- "samsung,exynos4210-usb2-phy"
- "samsung,exynos4x12-usb2-phy"
- "samsung,exynos5250-usb2-phy"
+ - "samsung,exynos5420-usb2-phy"
- "samsung,s5pv210-usb2-phy"
- reg : a list of registers used by phy driver
- first and obligatory is the location of phy modules registers
diff --git a/dts/Bindings/phy/ti,omap-usb2.yaml b/dts/Bindings/phy/ti,omap-usb2.yaml
index 83d5d0aceb..cbbf5e8b11 100644
--- a/dts/Bindings/phy/ti,omap-usb2.yaml
+++ b/dts/Bindings/phy/ti,omap-usb2.yaml
@@ -44,13 +44,13 @@ properties:
- const: refclk
syscon-phy-power:
- $ref: /schemas/types.yaml#definitions/phandle-array
+ $ref: /schemas/types.yaml#/definitions/phandle-array
description:
phandle/offset pair. Phandle to the system control module and
register offset to power on/off the PHY.
ctrl-module:
- $ref: /schemas/types.yaml#definitions/phandle
+ $ref: /schemas/types.yaml#/definitions/phandle
description:
(deprecated) phandle of the control module used by PHY driver
to power on the PHY. Use syscon-phy-power instead.
diff --git a/dts/Bindings/pinctrl/microchip,sparx5-sgpio.yaml b/dts/Bindings/pinctrl/microchip,sparx5-sgpio.yaml
new file mode 100644
index 0000000000..df0c83cb1c
--- /dev/null
+++ b/dts/Bindings/pinctrl/microchip,sparx5-sgpio.yaml
@@ -0,0 +1,161 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microsemi/Microchip Serial GPIO controller
+
+maintainers:
+ - Lars Povlsen <lars.povlsen@microchip.com>
+
+description: |
+ By using a serial interface, the SIO controller significantly extend
+ the number of available GPIOs with a minimum number of additional
+ pins on the device. The primary purpose of the SIO controllers is to
+ connect control signals from SFP modules and to act as an LED
+ controller.
+
+properties:
+ $nodename:
+ pattern: "^gpio@[0-9a-f]+$"
+
+ compatible:
+ enum:
+ - microchip,sparx5-sgpio
+ - mscc,ocelot-sgpio
+ - mscc,luton-sgpio
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ microchip,sgpio-port-ranges:
+ description: This is a sequence of tuples, defining intervals of
+ enabled ports in the serial input stream. The enabled ports must
+ match the hardware configuration in order for signals to be
+ properly written/read to/from the controller holding
+ registers. Being tuples, then number of arguments must be
+ even. The tuples mast be ordered (low, high) and are
+ inclusive.
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ items:
+ items:
+ - description: |
+ "low" indicates start bit number of range
+ minimum: 0
+ maximum: 31
+ - description: |
+ "high" indicates end bit number of range
+ minimum: 0
+ maximum: 31
+ minItems: 1
+ maxItems: 32
+
+ bus-frequency:
+ description: The sgpio controller frequency (Hz). This dictates
+ the serial bitstream speed, which again affects the latency in
+ getting control signals back and forth between external shift
+ registers. The speed must be no larger than half the system
+ clock, and larger than zero.
+ default: 12500000
+
+patternProperties:
+ "^gpio@[0-1]$":
+ type: object
+ properties:
+ compatible:
+ const: microchip,sparx5-sgpio-bank
+
+ reg:
+ description: |
+ The GPIO bank number. "0" is designates the input pin bank,
+ "1" the output bank.
+ maxItems: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ description: |
+ Specifies the pin (port and bit) and flags. Note that the
+ SGIO pin is defined by *2* numbers, a port number between 0
+ and 31, and a bit index, 0 to 3. The maximum bit number is
+ controlled indirectly by the "ngpios" property: (ngpios/32).
+ const: 3
+
+ interrupts:
+ description: Specifies the sgpio IRQ (in parent controller)
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ description:
+ Specifies the pin (port and bit) and flags, as defined in
+ defined in include/dt-bindings/interrupt-controller/irq.h
+ const: 3
+
+ ngpios:
+ description: The numbers of GPIO's exposed. This must be a
+ multiple of 32.
+ minimum: 32
+ maximum: 128
+
+ required:
+ - compatible
+ - reg
+ - gpio-controller
+ - '#gpio-cells'
+ - ngpios
+
+ additionalProperties: false
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - microchip,sgpio-port-ranges
+ - "#address-cells"
+ - "#size-cells"
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ sgpio2: gpio@1101059c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "microchip,sparx5-sgpio";
+ clocks = <&sys_clk>;
+ pinctrl-0 = <&sgpio2_pins>;
+ pinctrl-names = "default";
+ reg = <0x1101059c 0x100>;
+ microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>;
+ bus-frequency = <25000000>;
+ sgpio_in2: gpio@0 {
+ reg = <0>;
+ compatible = "microchip,sparx5-sgpio-bank";
+ gpio-controller;
+ #gpio-cells = <3>;
+ ngpios = <96>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+ sgpio_out2: gpio@1 {
+ compatible = "microchip,sparx5-sgpio-bank";
+ reg = <1>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ ngpios = <96>;
+ };
+ };
diff --git a/dts/Bindings/pinctrl/mscc,ocelot-pinctrl.txt b/dts/Bindings/pinctrl/mscc,ocelot-pinctrl.txt
index 0091244923..db99bd95d4 100644
--- a/dts/Bindings/pinctrl/mscc,ocelot-pinctrl.txt
+++ b/dts/Bindings/pinctrl/mscc,ocelot-pinctrl.txt
@@ -3,7 +3,8 @@ Microsemi Ocelot pin controller Device Tree Bindings
Required properties:
- compatible : Should be "mscc,ocelot-pinctrl",
- "mscc,jaguar2-pinctrl" or "microchip,sparx5-pinctrl"
+ "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl",
+ "mscc,luton-pinctrl" or "mscc,serval-pinctrl"
- reg : Address and length of the register set for the device
- gpio-controller : Indicates this device is a GPIO controller
- #gpio-cells : Must be 2.
diff --git a/dts/Bindings/pinctrl/nvidia,tegra194-pinmux.txt b/dts/Bindings/pinctrl/nvidia,tegra194-pinmux.txt
index 8763f448c3..90d38f7106 100644
--- a/dts/Bindings/pinctrl/nvidia,tegra194-pinmux.txt
+++ b/dts/Bindings/pinctrl/nvidia,tegra194-pinmux.txt
@@ -99,7 +99,7 @@ Example:
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
- nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
+ nvidia,io-hv = <TEGRA_PIN_ENABLE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
};
diff --git a/dts/Bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml b/dts/Bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
new file mode 100644
index 0000000000..e47ebf934d
--- /dev/null
+++ b/dts/Bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
+ Low Power Island (LPI) TLMM block
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description: |
+ This binding describes the Top Level Mode Multiplexer block found in the
+ LPASS LPI IP on most Qualcomm SoCs
+
+properties:
+ compatible:
+ const: qcom,sm8250-lpass-lpi-pinctrl
+
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ clocks:
+ items:
+ - description: LPASS Core voting clock
+ - description: LPASS Audio voting clock
+
+ clock-names:
+ items:
+ - const: core
+ - const: audio
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ description: Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+#PIN CONFIGURATION NODES
+patternProperties:
+ '-pins$':
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: "/schemas/pinctrl/pincfg-node.yaml"
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9])$"
+ minItems: 1
+ maxItems: 14
+
+ function:
+ enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,
+ qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,
+ dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,
+ i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,
+ dmic3_data, i2s2_data ]
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+ default: 2
+ description:
+ Selects the drive strength for the specified pins, in mA.
+
+ slew-rate:
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: |
+ 0: No adjustments
+ 1: Higher Slew rate (faster edges)
+ 2: Lower Slew rate (slower edges)
+ 3: Reserved (No adjustments)
+
+ bias-pull-down: true
+
+ bias-pull-up: true
+
+ bias-disable: true
+
+ output-high: true
+
+ output-low: true
+
+ required:
+ - pins
+ - function
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/sound/qcom,q6afe.h>
+ lpi_tlmm: pinctrl@33c0000 {
+ compatible = "qcom,sm8250-lpass-lpi-pinctrl";
+ reg = <0x33c0000 0x20000>,
+ <0x3550000 0x10000>;
+ clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "core", "audio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpi_tlmm 0 0 14>;
+ };
diff --git a/dts/Bindings/pinctrl/qcom,msm8953-pinctrl.yaml b/dts/Bindings/pinctrl/qcom,msm8953-pinctrl.yaml
new file mode 100644
index 0000000000..abe9f4c9b1
--- /dev/null
+++ b/dts/Bindings/pinctrl/qcom,msm8953-pinctrl.yaml
@@ -0,0 +1,167 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,msm8953-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. MSM8953 TLMM block
+
+maintainers:
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description: |
+ This binding describes the Top Level Mode Multiplexer block found in the
+ MSM8953 platform.
+
+properties:
+ compatible:
+ const: qcom,msm8953-pinctrl
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: Specifies the TLMM summary IRQ
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ description:
+ Specifies the PIN numbers and Flags, as defined in defined in
+ include/dt-bindings/interrupt-controller/irq.h
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ description: Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+#PIN CONFIGURATION NODES
+patternProperties:
+ '-pins$':
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: "/schemas/pinctrl/pincfg-node.yaml"
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
+ - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
+ sdc2_cmd, sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0,
+ qdsd_data1, qdsd_data2, qdsd_data3 ]
+ minItems: 1
+ maxItems: 16
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ enum: [ accel_int, adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1,
+ atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
+ atest_gpsadc_dtest0_native, atest_gpsadc_dtest1_native, atest_tsens,
+ atest_wlan0, atest_wlan1, bimc_dte0, bimc_dte1, blsp1_spi,
+ blsp3_spi, blsp6_spi, blsp7_spi, blsp_i2c1, blsp_i2c2, blsp_i2c3,
+ blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_spi1,
+ blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7,
+ blsp_spi8, blsp_uart2, blsp_uart4, blsp_uart5, blsp_uart6, cam0_ldo,
+ cam1_ldo, cam1_rst, cam1_standby, cam2_rst, cam2_standby, cam3_rst,
+ cam3_standby, cam_irq, cam_mclk, cap_int, cci_async, cci_i2c,
+ cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
+ cdc_pdm0, codec_int1, codec_int2, codec_reset, cri_trng, cri_trng0,
+ cri_trng1, dac_calib0, dac_calib1, dac_calib10, dac_calib11,
+ dac_calib12, dac_calib13, dac_calib14, dac_calib15, dac_calib16,
+ dac_calib17, dac_calib18, dac_calib19, dac_calib2, dac_calib20,
+ dac_calib21, dac_calib22, dac_calib23, dac_calib24, dac_calib25,
+ dac_calib3, dac_calib4, dac_calib5, dac_calib6, dac_calib7,
+ dac_calib8, dac_calib9, dbg_out, ddr_bist, dmic0_clk, dmic0_data,
+ ebi_cdc, ebi_ch0, ext_lpass, flash_strobe, fp_int, gcc_gp1_clk_a,
+ gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a,
+ gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, gpio, gsm0_tx, gsm1_tx,
+ gyro_int, hall_int, hdmi_int, key_focus, key_home, key_snapshot,
+ key_volp, ldo_en, ldo_update, lpass_slimbus, lpass_slimbus0,
+ lpass_slimbus1, m_voc, mag_int, mdp_vsync, mipi_dsi0, modem_tsync,
+ mss_lte, nav_pps, nav_pps_in_a, nav_pps_in_b, nav_tsync,
+ nfc_disable, nfc_dwl, nfc_irq, ois_sync, pa_indicator, pbs0, pbs1,
+ pbs2, pressure_int, pri_mi2s, pri_mi2s_mclk_a, pri_mi2s_mclk_b,
+ pri_mi2s_ws, prng_rosc, pwr_crypto_enabled_a, pwr_crypto_enabled_b,
+ pwr_down, pwr_modem_enabled_a, pwr_modem_enabled_b,
+ pwr_nav_enabled_a, pwr_nav_enabled_b, qdss_cti_trig_in_a0,
+ qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
+ qdss_cti_trig_out_a0, qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
+ qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b,
+ qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
+ qdss_tracedata_b, sd_write, sdcard_det, sec_mi2s, sec_mi2s_mclk_a,
+ sec_mi2s_mclk_b, smb_int, ss_switch, ssbi_wtr1, ts_resout,
+ ts_sample, ts_xvdd, tsens_max, uim1_clk, uim1_data, uim1_present,
+ uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
+ uim_batt, us_emitter, us_euro, wcss_bt, wcss_fm, wcss_wlan,
+ wcss_wlan0, wcss_wlan1, wcss_wlan2, wsa_en, wsa_io, wsa_irq ]
+
+ drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+ default: 2
+ description:
+ Selects the drive strength for the specified pins, in mA.
+
+ bias-pull-down: true
+
+ bias-pull-up: true
+
+ bias-disable: true
+
+ output-high: true
+
+ output-low: true
+
+ required:
+ - pins
+ - function
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,msm8953-pinctrl";
+ reg = <0x01000000 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 142>;
+
+ serial_default: serial-pins {
+ pins = "gpio4", "gpio5";
+ function = "blsp_uart2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
diff --git a/dts/Bindings/pinctrl/qcom,pmic-gpio.txt b/dts/Bindings/pinctrl/qcom,pmic-gpio.txt
index c3d1914381..7648ab00f4 100644
--- a/dts/Bindings/pinctrl/qcom,pmic-gpio.txt
+++ b/dts/Bindings/pinctrl/qcom,pmic-gpio.txt
@@ -29,6 +29,7 @@ PMIC's from Qualcomm.
"qcom,pm8150b-gpio"
"qcom,pm6150-gpio"
"qcom,pm6150l-gpio"
+ "qcom,pmx55-gpio"
And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio"
if the device is on an spmi bus or an ssbi bus respectively
@@ -110,6 +111,8 @@ to specify in a pin configuration subnode:
gpio1-gpio12 for pm8150l (hole on gpio7)
gpio1-gpio10 for pm6150
gpio1-gpio12 for pm6150l
+ gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10
+ and gpio11)
- function:
Usage: required
diff --git a/dts/Bindings/pinctrl/qcom,sc7280-pinctrl.yaml b/dts/Bindings/pinctrl/qcom,sc7280-pinctrl.yaml
new file mode 100644
index 0000000000..7d6a2ab10e
--- /dev/null
+++ b/dts/Bindings/pinctrl/qcom,sc7280-pinctrl.yaml
@@ -0,0 +1,158 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SC7280 TLMM block
+
+maintainers:
+ - Rajendra Nayak <rnayak@codeaurora.org>
+
+description: |
+ This binding describes the Top Level Mode Multiplexer block found in the
+ SC7280 platform.
+
+properties:
+ compatible:
+ const: qcom,sc7280-pinctrl
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: Specifies the TLMM summary IRQ
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ description:
+ Specifies the PIN numbers and Flags, as defined in defined in
+ include/dt-bindings/interrupt-controller/irq.h
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ description: Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ wakeup-parent:
+ maxItems: 1
+
+#PIN CONFIGURATION NODES
+patternProperties:
+ '-pins$':
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: "/schemas/pinctrl/pincfg-node.yaml"
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-4])$"
+ - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
+ sdc2_cmd, sdc2_data, ufs_reset ]
+ minItems: 1
+ maxItems: 16
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ enum: [ atest_char, atest_char0, atest_char1, atest_char2,
+ atest_char3, atest_usb0, atest_usb00, atest_usb01,
+ atest_usb02, atest_usb03, atest_usb1, atest_usb10,
+ atest_usb11, atest_usb12, atest_usb13, audio_ref,
+ cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,
+ cci_timer2, cci_timer3, cci_timer4, cmu_rng0, cmu_rng1,
+ cmu_rng2, cmu_rng3, coex_uart1, cri_trng, cri_trng0,
+ cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, dp_hot,
+ dp_lcd, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
+ gpio, host2wlan_sol, ibi_i3c, jitter_bist, lpass_slimbus,
+ mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3,
+ mdp_vsync4, mdp_vsync5, mi2s0_data0, mi2s0_data1, mi2s0_sck,
+ mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
+ mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mss_grfc0,
+ mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, mss_grfc2,
+ mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7,
+ mss_grfc8, mss_grfc9, nav_gpio0, nav_gpio1, nav_gpio2,
+ pa_indicator, pcie0_clkreqn, pcie1_clkreqn, phase_flag,
+ pll_bist, pll_bypassnl, pll_clk, pll_reset, pri_mi2s, prng_rosc,
+ qdss, qdss_cti, qlink0_enable, qlink0_request, qlink0_wmss,
+ qlink1_enable, qlink1_request, qlink1_wmss, qspi_clk, qspi_cs,
+ qspi_data, qup00, qup01, qup02, qup03, qup04, qup05, qup06, qup07,
+ qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
+ sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sd_write,
+ sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tsense_pwm1,
+ tsense_pwm2, uim0_clk, uim0_data, uim0_present, uim0_reset,
+ uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac,
+ usb_phy, vfr_0, vfr_1, vsense_trigger ]
+
+ drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+ default: 2
+ description:
+ Selects the drive strength for the specified pins, in mA.
+
+ bias-pull-down: true
+
+ bias-pull-up: true
+
+ bias-disable: true
+
+ output-high: true
+
+ output-low: true
+
+ required:
+ - pins
+ - function
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ tlmm: pinctrl@f000000 {
+ compatible = "qcom,sc7280-pinctrl";
+ reg = <0xf000000 0x1000000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 175>;
+ wakeup-parent = <&pdc>;
+
+ qup_uart5_default: qup-uart5-pins {
+ pins = "gpio46", "gpio47";
+ function = "qup13";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
diff --git a/dts/Bindings/pinctrl/qcom,sdx55-pinctrl.yaml b/dts/Bindings/pinctrl/qcom,sdx55-pinctrl.yaml
new file mode 100644
index 0000000000..112dd59ce7
--- /dev/null
+++ b/dts/Bindings/pinctrl/qcom,sdx55-pinctrl.yaml
@@ -0,0 +1,154 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,sdx55-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SDX55 TLMM block
+
+maintainers:
+ - Vinod Koul <vkoul@kernel.org>
+
+description: |
+ This binding describes the Top Level Mode Multiplexer block found in the
+ SDX55 platform.
+
+properties:
+ compatible:
+ const: qcom,sdx55-pinctrl
+
+ reg:
+ description: Specifies the base address and size of the TLMM register space
+ maxItems: 1
+
+ interrupts:
+ description: Specifies the TLMM summary IRQ
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ description: Specifies the PIN numbers and Flags, as defined in
+ include/dt-bindings/interrupt-controller/irq.h
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ description: Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ gpio-reserved-ranges:
+ maxItems: 1
+
+#PIN CONFIGURATION NODES
+patternProperties:
+ '-pins$':
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: "/schemas/pinctrl/pincfg-node.yaml"
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$"
+ - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
+ minItems: 1
+ maxItems: 36
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins. Functions are only valid for gpio pins.
+ enum: [ adsp_ext, atest, audio_ref, bimc_dte0, bimc_dte1, blsp_i2c1,
+ blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_spi1, blsp_spi2,
+ blsp_spi3, blsp_spi4, blsp_uart1, blsp_uart2, blsp_uart3,
+ blsp_uart4, char_exec, coex_uart, coex_uart2, cri_trng,
+ cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
+ ebi0_wrcdc, ebi2_a, ebi2_lcd, emac_gcc0, emac_gcc1,
+ emac_pps0, emac_pps1, ext_dbg, gcc_gp1, gcc_gp2, gcc_gp3,
+ gcc_plltest, gpio, i2s_mclk, jitter_bist, ldo_en, ldo_update,
+ mgpi_clk, m_voc, native_char, native_char0, native_char1,
+ native_char2, native_char3, native_tsens, native_tsense,
+ nav_gpio, pa_indicator, pcie_clkreq, pci_e, pll_bist, pll_ref,
+ pll_test, pri_mi2s, prng_rosc, qdss_cti, qdss_gpio,
+ qdss_gpio0, qdss_gpio1, qdss_gpio2, qdss_gpio3, qdss_gpio4,
+ qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9,
+ qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13,
+ qdss_gpio14, qdss_gpio15, qdss_stm0, qdss_stm1, qdss_stm2,
+ qdss_stm3, qdss_stm4, qdss_stm5, qdss_stm6, qdss_stm7,
+ qdss_stm8, qdss_stm9, qdss_stm10, qdss_stm11, qdss_stm12,
+ qdss_stm13, qdss_stm14, qdss_stm15, qdss_stm16, qdss_stm17,
+ qdss_stm18, qdss_stm19, qdss_stm20, qdss_stm21, qdss_stm22,
+ qdss_stm23, qdss_stm24, qdss_stm25, qdss_stm26, qdss_stm27,
+ qdss_stm28, qdss_stm29, qdss_stm30, qdss_stm31, qlink0_en,
+ qlink0_req, qlink0_wmss, qlink1_en, qlink1_req, qlink1_wmss,
+ spmi_coex, sec_mi2s, spmi_vgi, tgu_ch0, uim1_clk, uim1_data,
+ uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present,
+ uim2_reset, usb2phy_ac, vsense_trigger ]
+
+ drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+ default: 2
+ description:
+ Selects the drive strength for the specified pins, in mA.
+
+ bias-pull-down: true
+
+ bias-pull-up: true
+
+ bias-disable: true
+
+ output-high: true
+
+ output-low: true
+
+ required:
+ - pins
+ - function
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ tlmm: pinctrl@1f00000 {
+ compatible = "qcom,sdx55-pinctrl";
+ reg = <0x0f100000 0x300000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 108>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+
+ serial-pins {
+ pins = "gpio8", "gpio9";
+ function = "blsp_uart3";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+...
diff --git a/dts/Bindings/pinctrl/ralink,rt2880-pinmux.yaml b/dts/Bindings/pinctrl/ralink,rt2880-pinmux.yaml
new file mode 100644
index 0000000000..7dea3e26d9
--- /dev/null
+++ b/dts/Bindings/pinctrl/ralink,rt2880-pinmux.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/ralink,rt2880-pinmux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ralink rt2880 pinmux controller
+
+maintainers:
+ - Sergio Paracuellos <sergio.paracuellos@gmail.com>
+
+description:
+ The rt2880 pinmux can only set the muxing of pin groups. muxing indiviual pins
+ is not supported. There is no pinconf support.
+
+properties:
+ compatible:
+ enum:
+ - ralink,rt2880-pinmux
+
+ pinctrl-0:
+ description:
+ A phandle to the node containing the subnodes containing default
+ configurations. This is for pinctrl hogs.
+
+ pinctrl-names:
+ description:
+ A pinctrl state named "default" can be defined.
+ const: default
+
+required:
+ - compatible
+
+patternProperties:
+ '[a-z0-9_-]+':
+ if:
+ type: object
+ description: node for pinctrl.
+ $ref: "pinmux-node.yaml"
+ then:
+ properties:
+ groups:
+ description: Name of the pin group to use for the functions.
+ enum: [i2c, spi, uart1, uart2, uart3, rgmii1, rgmii2, mdio,
+ pcie, sdhci]
+ function:
+ description: The mux function to select
+ enum: [gpio, i2c, spi, uart1, uart2, uart3, rgmii1, rgmii2,
+ mdio, nand1, nand2, sdhci]
+
+additionalProperties: false
+
+examples:
+ # Pinmux controller node
+ - |
+ pinctrl {
+ compatible = "ralink,rt2880-pinmux";
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinctrl0 {
+ };
+
+ i2c_pins: i2c0 {
+ i2c0 {
+ groups = "i2c";
+ function = "i2c";
+ };
+ };
+ };
diff --git a/dts/Bindings/power/mediatek,power-controller.yaml b/dts/Bindings/power/mediatek,power-controller.yaml
new file mode 100644
index 0000000000..d14cb9bac8
--- /dev/null
+++ b/dts/Bindings/power/mediatek,power-controller.yaml
@@ -0,0 +1,293 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Power Domains Controller
+
+maintainers:
+ - Weiyi Lu <weiyi.lu@mediatek.com>
+ - Matthias Brugger <mbrugger@suse.com>
+
+description: |
+ Mediatek processors include support for multiple power domains which can be
+ powered up/down by software based on different application scenes to save power.
+
+ IP cores belonging to a power domain should contain a 'power-domains'
+ property that is a phandle for SCPSYS node representing the domain.
+
+properties:
+ $nodename:
+ const: power-controller
+
+ compatible:
+ enum:
+ - mediatek,mt8173-power-controller
+ - mediatek,mt8183-power-controller
+ - mediatek,mt8192-power-controller
+
+ '#power-domain-cells':
+ const: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+patternProperties:
+ "^power-domain@[0-9a-f]+$":
+ type: object
+ description: |
+ Represents the power domains within the power controller node as documented
+ in Documentation/devicetree/bindings/power/power-domain.yaml.
+
+ properties:
+
+ '#power-domain-cells':
+ description:
+ Must be 0 for nodes representing a single PM domain and 1 for nodes
+ providing multiple PM domains.
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ reg:
+ description: |
+ Power domain index. Valid values are defined in:
+ "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
+ "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
+ "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
+ maxItems: 1
+
+ clocks:
+ description: |
+ A number of phandles to clocks that need to be enabled during domain
+ power-up sequencing.
+
+ clock-names:
+ description: |
+ List of names of clocks, in order to match the power-up sequencing
+ for each power domain we need to group the clocks by name. BASIC
+ clocks need to be enabled before enabling the corresponding power
+ domain, and should not have a '-' in their name (i.e mm, mfg, venc).
+ SUSBYS clocks need to be enabled before releasing the bus protection,
+ and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
+
+ In order to follow properly the power-up sequencing, the clocks must
+ be specified by order, adding first the BASIC clocks followed by the
+ SUSBSYS clocks.
+
+ mediatek,infracfg:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the device containing the INFRACFG register range.
+
+ mediatek,smi:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the device containing the SMI register range.
+
+ patternProperties:
+ "^power-domain@[0-9a-f]+$":
+ type: object
+ description: |
+ Represents a power domain child within a power domain parent node.
+
+ properties:
+
+ '#power-domain-cells':
+ description:
+ Must be 0 for nodes representing a single PM domain and 1 for nodes
+ providing multiple PM domains.
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description: |
+ A number of phandles to clocks that need to be enabled during domain
+ power-up sequencing.
+
+ clock-names:
+ description: |
+ List of names of clocks, in order to match the power-up sequencing
+ for each power domain we need to group the clocks by name. BASIC
+ clocks need to be enabled before enabling the corresponding power
+ domain, and should not have a '-' in their name (i.e mm, mfg, venc).
+ SUSBYS clocks need to be enabled before releasing the bus protection,
+ and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
+
+ In order to follow properly the power-up sequencing, the clocks must
+ be specified by order, adding first the BASIC clocks followed by the
+ SUSBSYS clocks.
+
+ mediatek,infracfg:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the device containing the INFRACFG register range.
+
+ mediatek,smi:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the device containing the SMI register range.
+
+ patternProperties:
+ "^power-domain@[0-9a-f]+$":
+ type: object
+ description: |
+ Represents a power domain child within a power domain parent node.
+
+ properties:
+
+ '#power-domain-cells':
+ description:
+ Must be 0 for nodes representing a single PM domain and 1 for nodes
+ providing multiple PM domains.
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description: |
+ A number of phandles to clocks that need to be enabled during domain
+ power-up sequencing.
+
+ clock-names:
+ description: |
+ List of names of clocks, in order to match the power-up sequencing
+ for each power domain we need to group the clocks by name. BASIC
+ clocks need to be enabled before enabling the corresponding power
+ domain, and should not have a '-' in their name (i.e mm, mfg, venc).
+ SUSBYS clocks need to be enabled before releasing the bus protection,
+ and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
+
+ In order to follow properly the power-up sequencing, the clocks must
+ be specified by order, adding first the BASIC clocks followed by the
+ SUSBSYS clocks.
+
+ mediatek,infracfg:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the device containing the INFRACFG register range.
+
+ mediatek,smi:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the device containing the SMI register range.
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/power/mt8173-power.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ scpsys: syscon@10006000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0 0x10006000 0 0x1000>;
+
+ spm: power-controller {
+ compatible = "mediatek,mt8173-power-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ /* power domains of the SoC */
+ power-domain@MT8173_POWER_DOMAIN_VDEC {
+ reg = <MT8173_POWER_DOMAIN_VDEC>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>;
+ clock-names = "mm";
+ #power-domain-cells = <0>;
+ };
+ power-domain@MT8173_POWER_DOMAIN_VENC {
+ reg = <MT8173_POWER_DOMAIN_VENC>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>,
+ <&topckgen CLK_TOP_VENC_SEL>;
+ clock-names = "mm", "venc";
+ #power-domain-cells = <0>;
+ };
+ power-domain@MT8173_POWER_DOMAIN_ISP {
+ reg = <MT8173_POWER_DOMAIN_ISP>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>;
+ clock-names = "mm";
+ #power-domain-cells = <0>;
+ };
+ power-domain@MT8173_POWER_DOMAIN_MM {
+ reg = <MT8173_POWER_DOMAIN_MM>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>;
+ clock-names = "mm";
+ #power-domain-cells = <0>;
+ mediatek,infracfg = <&infracfg>;
+ };
+ power-domain@MT8173_POWER_DOMAIN_VENC_LT {
+ reg = <MT8173_POWER_DOMAIN_VENC_LT>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>,
+ <&topckgen CLK_TOP_VENC_LT_SEL>;
+ clock-names = "mm", "venclt";
+ #power-domain-cells = <0>;
+ };
+ power-domain@MT8173_POWER_DOMAIN_AUDIO {
+ reg = <MT8173_POWER_DOMAIN_AUDIO>;
+ #power-domain-cells = <0>;
+ };
+ power-domain@MT8173_POWER_DOMAIN_USB {
+ reg = <MT8173_POWER_DOMAIN_USB>;
+ #power-domain-cells = <0>;
+ };
+ power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
+ reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
+ clocks = <&clk26m>;
+ clock-names = "mfg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8173_POWER_DOMAIN_MFG_2D {
+ reg = <MT8173_POWER_DOMAIN_MFG_2D>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8173_POWER_DOMAIN_MFG {
+ reg = <MT8173_POWER_DOMAIN_MFG>;
+ #power-domain-cells = <0>;
+ mediatek,infracfg = <&infracfg>;
+ };
+ };
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/power/qcom,rpmpd.yaml b/dts/Bindings/power/qcom,rpmpd.yaml
index 8058955fb3..64825128ee 100644
--- a/dts/Bindings/power/qcom,rpmpd.yaml
+++ b/dts/Bindings/power/qcom,rpmpd.yaml
@@ -16,12 +16,16 @@ description:
properties:
compatible:
enum:
+ - qcom,msm8916-rpmpd
+ - qcom,msm8939-rpmpd
- qcom,msm8976-rpmpd
- qcom,msm8996-rpmpd
- qcom,msm8998-rpmpd
- qcom,qcs404-rpmpd
+ - qcom,sdm660-rpmpd
- qcom,sc7180-rpmhpd
- qcom,sdm845-rpmhpd
+ - qcom,sdx55-rpmhpd
- qcom,sm8150-rpmhpd
- qcom,sm8250-rpmhpd
diff --git a/dts/Bindings/power/reset/ocelot-reset.txt b/dts/Bindings/power/reset/ocelot-reset.txt
index 4d530d8154..c5de7b555f 100644
--- a/dts/Bindings/power/reset/ocelot-reset.txt
+++ b/dts/Bindings/power/reset/ocelot-reset.txt
@@ -7,7 +7,9 @@ The reset registers are both present in the MSCC vcoreiii MIPS and
microchip Sparx5 armv8 SoC's.
Required Properties:
- - compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset"
+
+ - compatible: "mscc,ocelot-chip-reset", "mscc,luton-chip-reset",
+ "mscc,jaguar2-chip-reset" or "microchip,sparx5-chip-reset"
Example:
reset@1070008 {
diff --git a/dts/Bindings/power/reset/regulator-poweroff.yaml b/dts/Bindings/power/reset/regulator-poweroff.yaml
new file mode 100644
index 0000000000..03bd1fa5a6
--- /dev/null
+++ b/dts/Bindings/power/reset/regulator-poweroff.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/reset/regulator-poweroff.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Force-disable power regulator to turn the power off.
+
+maintainers:
+ - Michael Klein <michael@fossekall.de>
+
+description: |
+ When the power-off handler is called, a power regulator is disabled by
+ calling regulator_force_disable(). If the power is still on and the
+ CPU still running after a 3000ms delay, a warning is emitted.
+
+properties:
+ compatible:
+ const: "regulator-poweroff"
+
+ cpu-supply:
+ description:
+ regulator to disable on power-down
+
+required:
+ - compatible
+ - cpu-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ regulator-poweroff {
+ compatible = "regulator-poweroff";
+ cpu-supply = <&reg_vcc1v2>;
+ };
+...
diff --git a/dts/Bindings/power/supply/cw2015_battery.yaml b/dts/Bindings/power/supply/cw2015_battery.yaml
index ee92e6a076..5fcdf58015 100644
--- a/dts/Bindings/power/supply/cw2015_battery.yaml
+++ b/dts/Bindings/power/supply/cw2015_battery.yaml
@@ -27,7 +27,7 @@ properties:
of this binary blob is kept secret by CellWise. The only way to obtain
it is to mail two batteries to a test facility of CellWise and receive
back a test report with the binary blob.
- $ref: /schemas/types.yaml#definitions/uint8-array
+ $ref: /schemas/types.yaml#/definitions/uint8-array
minItems: 64
maxItems: 64
diff --git a/dts/Bindings/powerpc/sleep.yaml b/dts/Bindings/powerpc/sleep.yaml
index 6494c7d08b..1b0936a5be 100644
--- a/dts/Bindings/powerpc/sleep.yaml
+++ b/dts/Bindings/powerpc/sleep.yaml
@@ -42,6 +42,6 @@ select: true
properties:
sleep:
- $ref: /schemas/types.yaml#definitions/phandle-array
+ $ref: /schemas/types.yaml#/definitions/phandle-array
additionalProperties: true
diff --git a/dts/Bindings/pwm/atmel-tcb-pwm.txt b/dts/Bindings/pwm/atmel-tcb-pwm.txt
deleted file mode 100644
index 985fcc65f8..0000000000
--- a/dts/Bindings/pwm/atmel-tcb-pwm.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-Atmel TCB PWM controller
-
-Required properties:
-- compatible: should be "atmel,tcb-pwm"
-- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of
- the cells format. The only third cell flag supported by this binding is
- PWM_POLARITY_INVERTED.
-- tc-block: The Timer Counter block to use as a PWM chip.
-
-Example:
-
-pwm {
- compatible = "atmel,tcb-pwm";
- #pwm-cells = <3>;
- tc-block = <1>;
-};
diff --git a/dts/Bindings/pwm/intel,keembay-pwm.yaml b/dts/Bindings/pwm/intel,keembay-pwm.yaml
new file mode 100644
index 0000000000..ff6880a02c
--- /dev/null
+++ b/dts/Bindings/pwm/intel,keembay-pwm.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Intel Corporation
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/intel,keembay-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Keem Bay PWM Device Tree Bindings
+
+maintainers:
+ - Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ enum:
+ - intel,keembay-pwm
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#pwm-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #define KEEM_BAY_A53_GPIO
+
+ pwm@203200a0 {
+ compatible = "intel,keembay-pwm";
+ reg = <0x203200a0 0xe8>;
+ clocks = <&scmi_clk KEEM_BAY_A53_GPIO>;
+ #pwm-cells = <2>;
+ };
diff --git a/dts/Bindings/pwm/intel,lgm-pwm.yaml b/dts/Bindings/pwm/intel,lgm-pwm.yaml
new file mode 100644
index 0000000000..11a6065361
--- /dev/null
+++ b/dts/Bindings/pwm/intel,lgm-pwm.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/intel,lgm-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LGM SoC PWM fan controller
+
+maintainers:
+ - Rahul Tanwar <rtanwar@maxlinear.com>
+
+properties:
+ compatible:
+ const: intel,lgm-pwm
+
+ reg:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 2
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ pwm: pwm@e0d00000 {
+ compatible = "intel,lgm-pwm";
+ reg = <0xe0d00000 0x30>;
+ #pwm-cells = <2>;
+ clocks = <&cgu0 126>;
+ resets = <&rcu0 0x30 21>;
+ };
diff --git a/dts/Bindings/pwm/pwm-mediatek.txt b/dts/Bindings/pwm/pwm-mediatek.txt
index 29adff59c4..25ed214473 100644
--- a/dts/Bindings/pwm/pwm-mediatek.txt
+++ b/dts/Bindings/pwm/pwm-mediatek.txt
@@ -7,6 +7,7 @@ Required properties:
- "mediatek,mt7623-pwm": found on mt7623 SoC.
- "mediatek,mt7628-pwm": found on mt7628 SoC.
- "mediatek,mt7629-pwm": found on mt7629 SoC.
+ - "mediatek,mt8183-pwm": found on mt8183 SoC.
- "mediatek,mt8516-pwm": found on mt8516 SoC.
- reg: physical base address and length of the controller's registers.
- #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
diff --git a/dts/Bindings/pwm/pwm-mtk-disp.txt b/dts/Bindings/pwm/pwm-mtk-disp.txt
index 0521957c25..902b271891 100644
--- a/dts/Bindings/pwm/pwm-mtk-disp.txt
+++ b/dts/Bindings/pwm/pwm-mtk-disp.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible: should be "mediatek,<name>-disp-pwm":
- "mediatek,mt2701-disp-pwm": found on mt2701 SoC.
- "mediatek,mt6595-disp-pwm": found on mt6595 SoC.
+ - "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm": found on mt8167 SoC.
- "mediatek,mt8173-disp-pwm": found on mt8173 SoC.
- reg: physical base address and length of the controller's registers.
- #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
diff --git a/dts/Bindings/regulator/anatop-regulator.yaml b/dts/Bindings/regulator/anatop-regulator.yaml
index e7b3abe303..0a66338c7e 100644
--- a/dts/Bindings/regulator/anatop-regulator.yaml
+++ b/dts/Bindings/regulator/anatop-regulator.yaml
@@ -59,7 +59,6 @@ properties:
description: u32 value representing regulator enable bit offset.
vin-supply:
- $ref: '/schemas/types.yaml#/definitions/phandle'
description: input supply phandle.
required:
diff --git a/dts/Bindings/regulator/dlg,da9121.yaml b/dts/Bindings/regulator/dlg,da9121.yaml
new file mode 100644
index 0000000000..6f2164f7bc
--- /dev/null
+++ b/dts/Bindings/regulator/dlg,da9121.yaml
@@ -0,0 +1,189 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/dlg,da9121.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Dialog Semiconductor DA9121 voltage regulator
+
+maintainers:
+ - Adam Ward <Adam.Ward.opensource@diasemi.com>
+
+description: |
+ Dialog Semiconductor DA9121 Single-channel 10A double-phase buck converter
+ Dialog Semiconductor DA9122 Double-channel 5A single-phase buck converter
+ Dialog Semiconductor DA9220 Double-channel 3A single-phase buck converter
+ Dialog Semiconductor DA9217 Single-channel 6A double-phase buck converter
+ Dialog Semiconductor DA9130 Single-channel 10A double-phase buck converter
+ Dialog Semiconductor DA9131 Double-channel 5A single-phase buck converter
+ Dialog Semiconductor DA9132 Double-channel 3A single-phase buck converter
+
+ Current limits
+
+ This is PER PHASE, and the current limit setting in the devices reflect
+ that with a maximum 10A limit. Allowing for transients at/near double
+ the rated current, this translates across the device range to per
+ channel figures as so...
+
+ | DA9121 DA9122 DA9220 DA9217 DA9140
+ | /DA9130 /DA9131 /DA9132
+ -----------------------------------------------------------------------------
+ Output current / channel | 10000000 5000000 3000000 6000000 40000000
+ Output current / phase | 5000000 5000000 3000000 3000000 9500000
+ -----------------------------------------------------------------------------
+ Min regulator-min-microvolt| 300000 300000 300000 300000 500000
+ Max regulator-max-microvolt| 1900000 1900000 1900000 1900000 1000000
+ Device hardware default | 1000000 1000000 1000000 1000000 1000000
+ -----------------------------------------------------------------------------
+ Min regulator-min-microamp | 7000000 3500000 3500000 7000000 26000000
+ Max regulator-max-microamp | 20000000 10000000 6000000 12000000 78000000
+ Device hardware default | 15000000 7500000 5500000 11000000 58000000
+
+properties:
+ $nodename:
+ pattern: "pmic@[0-9a-f]{1,2}"
+ compatible:
+ enum:
+ - dlg,da9121
+ - dlg,da9122
+ - dlg,da9220
+ - dlg,da9217
+ - dlg,da9130
+ - dlg,da9131
+ - dlg,da9132
+ - dlg,da9140
+
+ reg:
+ maxItems: 1
+ description: Specifies the I2C slave address.
+
+ interrupts:
+ maxItems: 1
+ description: IRQ line information.
+
+ dlg,irq-polling-delay-passive-ms:
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ minimum: 1000
+ maximum: 10000
+ description: |
+ Specify the polling period, measured in milliseconds, between interrupt status
+ update checks. Range 1000-10000 ms.
+
+ regulators:
+ type: object
+ $ref: regulator.yaml#
+ description: |
+ This node defines the settings for the BUCK. The content of the
+ sub-node is defined by the standard binding for regulators; see regulator.yaml.
+ The DA9121 regulator is bound using their names listed below
+ buck1 - BUCK1
+ buck2 - BUCK2 //DA9122, DA9220, DA9131, DA9132 only
+
+ patternProperties:
+ "^buck([1-2])$":
+ type: object
+ $ref: regulator.yaml#
+
+ properties:
+ regulator-mode:
+ maxItems: 1
+ description: Defined in include/dt-bindings/regulator/dlg,da9121-regulator.h
+
+ regulator-initial-mode:
+ maxItems: 1
+ description: Defined in include/dt-bindings/regulator/dlg,da9121-regulator.h
+
+ enable-gpios:
+ maxItems: 1
+ description: Specify a valid GPIO for platform control of the regulator
+
+ dlg,ripple-cancel:
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ description: |
+ Defined in include/dt-bindings/regulator/dlg,da9121-regulator.h
+ Only present on multi-channel devices (DA9122, DA9220, DA9131, DA9132)
+
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - regulators
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/regulator/dlg,da9121-regulator.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pmic@68 {
+ compatible = "dlg,da9121";
+ reg = <0x68>;
+
+ interrupt-parent = <&gpio6>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+
+ dlg,irq-polling-delay-passive-ms = <2000>;
+
+ regulators {
+ DA9121_BUCK1: buck1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-min-microamp = <7000000>;
+ regulator-max-microamp = <20000000>;
+ regulator-boot-on;
+ regulator-initial-mode = <DA9121_BUCK_MODE_AUTO>;
+ enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
+ };
+ };
+ };
+ };
+
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/regulator/dlg,da9121-regulator.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pmic@68 {
+ compatible = "dlg,da9122";
+ reg = <0x68>;
+
+ interrupt-parent = <&gpio6>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+
+ dlg,irq-polling-delay-passive-ms = <2000>;
+
+ regulators {
+ DA9122_BUCK1: buck1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-min-microamp = <3500000>;
+ regulator-max-microamp = <10000000>;
+ regulator-boot-on;
+ regulator-initial-mode = <DA9121_BUCK_MODE_AUTO>;
+ enable-gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>;
+ dlg,ripple-cancel = <DA9121_BUCK_RIPPLE_CANCEL_NONE>;
+ };
+ DA9122_BUCK2: buck2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-min-microamp = <3500000>;
+ regulator-max-microamp = <10000000>;
+ regulator-boot-on;
+ regulator-initial-mode = <DA9121_BUCK_MODE_AUTO>;
+ enable-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>;
+ dlg,ripple-cancel = <DA9121_BUCK_RIPPLE_CANCEL_NONE>;
+ };
+ };
+ };
+ };
+...
diff --git a/dts/Bindings/regulator/fixed-regulator.yaml b/dts/Bindings/regulator/fixed-regulator.yaml
index 92211f2b3b..d3d0dc13dd 100644
--- a/dts/Bindings/regulator/fixed-regulator.yaml
+++ b/dts/Bindings/regulator/fixed-regulator.yaml
@@ -26,12 +26,22 @@ if:
const: regulator-fixed-clock
required:
- clocks
+else:
+ if:
+ properties:
+ compatible:
+ contains:
+ const: regulator-fixed-domain
+ required:
+ - power-domains
+ - required-opps
properties:
compatible:
enum:
- regulator-fixed
- regulator-fixed-clock
+ - regulator-fixed-domain
regulator-name: true
@@ -46,6 +56,20 @@ properties:
is mandatory if compatible is chosen to regulator-fixed-clock.
maxItems: 1
+ power-domains:
+ description:
+ Power domain to use for enable control. This binding is only
+ available if the compatible is chosen to regulator-fixed-domain.
+ maxItems: 1
+
+ required-opps:
+ description:
+ Performance state to use for enable control. This binding is only
+ available if the compatible is chosen to regulator-fixed-domain. The
+ power-domain binding is mandatory if compatible is chosen to
+ regulator-fixed-domain.
+ maxItems: 1
+
startup-delay-us:
description: startup time in microseconds
$ref: /schemas/types.yaml#/definitions/uint32
@@ -89,4 +113,27 @@ examples:
gpio-open-drain;
vin-supply = <&parent_reg>;
};
+ reg_1v8_clk: regulator-1v8-clk {
+ compatible = "regulator-fixed-clock";
+ regulator-name = "1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ clocks = <&clock1>;
+ startup-delay-us = <70000>;
+ enable-active-high;
+ regulator-boot-on;
+ vin-supply = <&parent_reg>;
+ };
+ reg_1v8_domain: regulator-1v8-domain {
+ compatible = "regulator-fixed-domain";
+ regulator-name = "1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ power-domains = <&domain1>;
+ required-opps = <&domain1_state1>;
+ startup-delay-us = <70000>;
+ enable-active-high;
+ regulator-boot-on;
+ vin-supply = <&parent_reg>;
+ };
...
diff --git a/dts/Bindings/regulator/mcp16502-regulator.txt b/dts/Bindings/regulator/mcp16502-regulator.txt
index b8f843fa60..d86584ed4d 100644
--- a/dts/Bindings/regulator/mcp16502-regulator.txt
+++ b/dts/Bindings/regulator/mcp16502-regulator.txt
@@ -10,7 +10,7 @@ Required properties:
name. The content of each sub-node is defined by the
standard binding for regulators; see regulator.txt.
-Regualtors of MCP16502 PMIC:
+Regulators of MCP16502 PMIC:
1) VDD_IO - Buck (1.2 - 3.7 V)
2) VDD_DDR - Buck (0.6 - 1.85 V)
3) VDD_CORE - Buck (0.6 - 1.85 V)
diff --git a/dts/Bindings/regulator/nxp,pf8x00-regulator.yaml b/dts/Bindings/regulator/nxp,pf8x00-regulator.yaml
new file mode 100644
index 0000000000..a6c259ce97
--- /dev/null
+++ b/dts/Bindings/regulator/nxp,pf8x00-regulator.yaml
@@ -0,0 +1,211 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/nxp,pf8x00-regulator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP PF8100/PF8121A/PF8200 PMIC regulators
+
+maintainers:
+ - Jagan Teki <jagan@amarulasolutions.com>
+ - Troy Kisky <troy.kisky@boundarydevices.com>
+
+description: |
+ PF8100/PF8121A/PF8200 is a PMIC designed for highperformance consumer
+ applications. It features seven high efficiency buck converters, four
+ linear and one vsnvs regulators. It has built-in one time programmable
+ fuse bank for device configurations.
+
+properties:
+ compatible:
+ enum:
+ - nxp,pf8x00
+
+ reg:
+ maxItems: 1
+
+ regulators:
+ type: object
+ description: |
+ list of regulators provided by this controller
+
+ patternProperties:
+ "^ldo[1-4]$":
+ type: object
+ $ref: regulator.yaml#
+ description:
+ Properties for single LDO regulator.
+
+ properties:
+ regulator-name:
+ pattern: "^ldo[1-4]$"
+ description:
+ should be "ldo1", ..., "ldo4"
+
+ unevaluatedProperties: false
+
+ "^buck[1-7]$":
+ type: object
+ $ref: regulator.yaml#
+ description:
+ Properties for single BUCK regulator.
+
+ properties:
+ regulator-name:
+ pattern: "^buck[1-7]$"
+ description:
+ should be "buck1", ..., "buck7"
+
+ nxp,ilim-ma:
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ minimum: 2100
+ maximum: 4500
+ description:
+ BUCK regulators current limit in mA.
+
+ Listed current limits in mA are,
+ 2100 (default)
+ 2600
+ 3000
+ 4500
+
+ nxp,phase-shift:
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ minimum: 45
+ maximum: 0
+ description:
+ BUCK regulators phase shift control in degrees.
+
+ Listed phase shift control values in degrees are,
+ 45
+ 90
+ 135
+ 180
+ 225
+ 270
+ 315
+ 0 (default)
+
+ unevaluatedProperties: false
+
+ "^vsnvs$":
+ type: object
+ $ref: regulator.yaml#
+ description:
+ Properties for single VSNVS regulator.
+
+ properties:
+ regulator-name:
+ pattern: "^vsnvs$"
+ description:
+ should be "vsnvs"
+
+ unevaluatedProperties: false
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - regulators
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic@8 {
+ compatible = "nxp,pf8x00";
+ reg = <0x08>;
+
+ regulators {
+ reg_ldo1: ldo1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <1500000>;
+ };
+
+ reg_ldo2: ldo2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <1500000>;
+ };
+
+ reg_ldo3: ldo3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <1500000>;
+ };
+
+ reg_ldo4: ldo4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <1500000>;
+ };
+
+ reg_buck1: buck1 {
+ nxp,ilim-ma = <4500>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <400000>;
+ };
+
+ reg_buck2: buck2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <400000>;
+ };
+
+ reg_buck3: buck3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <400000>;
+ };
+
+ reg_buck4: buck4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <400000>;
+ };
+
+ reg_buck5: buck5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <400000>;
+ };
+
+ reg_buck6: buck6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <400000>;
+ };
+
+ reg_buck7: buck7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ };
+
+ reg_vsnvs: vsnvs {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ };
+ };
+ };
+ };
diff --git a/dts/Bindings/regulator/qcom,rpmh-regulator.txt b/dts/Bindings/regulator/qcom,rpmh-regulator.txt
index 97c3e0b761..b8f0b7809c 100644
--- a/dts/Bindings/regulator/qcom,rpmh-regulator.txt
+++ b/dts/Bindings/regulator/qcom,rpmh-regulator.txt
@@ -26,10 +26,13 @@ Supported regulator node names:
PM8009: smps1 - smps2, ldo1 - ldo7
PM8150: smps1 - smps10, ldo1 - ldo18
PM8150L: smps1 - smps8, ldo1 - ldo11, bob, flash, rgb
+ PM8350: smps1 - smps12, ldo1 - ldo10,
+ PM8350C: smps1 - smps10, ldo1 - ldo13, bob
PM8998: smps1 - smps13, ldo1 - ldo28, lvs1 - lvs2
PMI8998: bob
PM6150: smps1 - smps5, ldo1 - ldo19
PM6150L: smps1 - smps8, ldo1 - ldo11, bob
+ PMX55: smps1 - smps7, ldo1 - ldo16
========================
First Level Nodes - PMIC
@@ -43,10 +46,13 @@ First Level Nodes - PMIC
"qcom,pm8009-rpmh-regulators"
"qcom,pm8150-rpmh-regulators"
"qcom,pm8150l-rpmh-regulators"
+ "qcom,pm8350-rpmh-regulators"
+ "qcom,pm8350c-rpmh-regulators"
"qcom,pm8998-rpmh-regulators"
"qcom,pmi8998-rpmh-regulators"
"qcom,pm6150-rpmh-regulators"
"qcom,pm6150l-rpmh-regulators"
+ "qcom,pmx55-rpmh-regulators"
- qcom,pmic-id
Usage: required
diff --git a/dts/Bindings/regulator/rohm,bd71837-regulator.yaml b/dts/Bindings/regulator/rohm,bd71837-regulator.yaml
index f5e31196a6..1941b36cf1 100644
--- a/dts/Bindings/regulator/rohm,bd71837-regulator.yaml
+++ b/dts/Bindings/regulator/rohm,bd71837-regulator.yaml
@@ -105,6 +105,54 @@ patternProperties:
PMIC hardware state machine.
type: boolean
+ # Setups where regulator (especially the buck8) output voltage is scaled
+ # by adding external connection where some other regulator output is
+ # connected to feedback-pin (over suitable resistors) is getting popular
+ # amongst users of BD71837. (This allows for example scaling down the
+ # buck8 voltages to suit lover GPU voltages for projects where buck8 is
+ # (ab)used to supply power for GPU.
+ #
+ # So we allow describing this external connection from DT and scale the
+ # voltages accordingly. This is what the connection should look like:
+ #
+ # |---------------|
+ # | buck 8 |-------+----->Vout
+ # | | |
+ # |---------------| |
+ # | |
+ # | |
+ # +-------+--R2----+
+ # |
+ # R1
+ # |
+ # V FB-pull-up
+ #
+ # Here the buck output is sifted according to formula:
+ #
+ # Vout_o = Vo - (Vpu - Vo)*R2/R1
+ # Linear_step = step_orig*(R1+R2)/R1
+ #
+ # where:
+ # Vout_o is adjusted voltage output at vsel reg value 0
+ # Vo is original voltage output at vsel reg value 0
+ # Vpu is the pull-up voltage V FB-pull-up in the picture
+ # R1 and R2 are resistor values.
+
+ rohm,fb-pull-up-microvolt:
+ description:
+ Feedback-pin has pull-up connection to adjust voltage range. This is
+ the used pull-up voltage before R1.
+
+ rohm,feedback-pull-up-r1-ohms:
+ description:
+ Feedback-pin has pull-up connection to adjust voltage range. This is
+ the used R1 resistor.
+
+ rohm,feedback-pull-up-r2-ohms:
+ description:
+ Feedback-pin has pull-up connection to adjust voltage range. This is
+ the used R2 resistor.
+
required:
- regulator-name
diff --git a/dts/Bindings/regulator/rohm,bd71847-regulator.yaml b/dts/Bindings/regulator/rohm,bd71847-regulator.yaml
index eeac32cd15..a1b8063738 100644
--- a/dts/Bindings/regulator/rohm,bd71847-regulator.yaml
+++ b/dts/Bindings/regulator/rohm,bd71847-regulator.yaml
@@ -99,6 +99,55 @@ patternProperties:
Enable/Disable control of this regulator must be left to the
PMIC hardware state machine.
type: boolean
+
+ # Setups where regulator (especially the buck8) output voltage is scaled
+ # by adding external connection where some other regulator output is
+ # connected to feedback-pin (over suitable resistors) is getting popular
+ # amongst users of BD71837. (This allows for example scaling down the
+ # buck8 voltages to suit lover GPU voltages for projects where buck8 is
+ # (ab)used to supply power for GPU.
+ #
+ # So we allow describing this external connection from DT and scale the
+ # voltages accordingly. This is what the connection should look like:
+ #
+ # |---------------|
+ # | buck 8 |-------+----->Vout
+ # | | |
+ # |---------------| |
+ # | |
+ # | |
+ # +-------+--R2----+
+ # |
+ # R1
+ # |
+ # V FB-pull-up
+ #
+ # Here the buck output is sifted according to formula:
+ #
+ # Vout_o = Vo - (Vpu - Vo)*R2/R1
+ # Linear_step = step_orig*(R1+R2)/R1
+ #
+ # where:
+ # Vout_o is adjusted voltage output at vsel reg value 0
+ # Vo is original voltage output at vsel reg value 0
+ # Vpu is the pull-up voltage V FB-pull-up in the picture
+ # R1 and R2 are resistor values.
+
+ rohm,fb-pull-up-microvolt:
+ description:
+ Feedback-pin has pull-up connection to adjust voltage range. This is
+ the used pull-up voltage before R1.
+
+ rohm,feedback-pull-up-r1-ohms:
+ description:
+ Feedback-pin has pull-up connection to adjust voltage range. This is
+ the used R1 resistor.
+
+ rohm,feedback-pull-up-r2-ohms:
+ description:
+ Feedback-pin has pull-up connection to adjust voltage range. This is
+ the used R2 resistor.
+
required:
- regulator-name
diff --git a/dts/Bindings/remoteproc/qcom,q6v5.txt b/dts/Bindings/remoteproc/qcom,q6v5.txt
index 1f9a62e13e..7ccd5534b0 100644
--- a/dts/Bindings/remoteproc/qcom,q6v5.txt
+++ b/dts/Bindings/remoteproc/qcom,q6v5.txt
@@ -113,8 +113,8 @@ should be referenced as follows:
For the compatible strings below the following supplies are required:
"qcom,q6v5-pil"
"qcom,msm8916-mss-pil",
-- cx-supply:
-- mx-supply:
+- cx-supply: (deprecated, use power domain instead)
+- mx-supply: (deprecated, use power domain instead)
- pll-supply:
Usage: required
Value type: <phandle>
@@ -123,9 +123,9 @@ For the compatible strings below the following supplies are required:
For the compatible string below the following supplies are required:
"qcom,msm8974-mss-pil"
-- cx-supply:
+- cx-supply: (deprecated, use power domain instead)
- mss-supply:
-- mx-supply:
+- mx-supply: (deprecated, use power domain instead)
- pll-supply:
Usage: required
Value type: <phandle>
@@ -149,11 +149,11 @@ For the compatible string below the following supplies are required:
Usage: required
Value type: <stringlist>
Definition: The power-domains needed depend on the compatible string:
- qcom,q6v5-pil:
qcom,ipq8074-wcss-pil:
+ no power-domain names required
+ qcom,q6v5-pil:
qcom,msm8916-mss-pil:
qcom,msm8974-mss-pil:
- no power-domain names required
qcom,msm8996-mss-pil:
qcom,msm8998-mss-pil:
must be "cx", "mx"
diff --git a/dts/Bindings/remoteproc/qcom,wcnss-pil.txt b/dts/Bindings/remoteproc/qcom,wcnss-pil.txt
index d420f84ddf..cc0b7fc1c2 100644
--- a/dts/Bindings/remoteproc/qcom,wcnss-pil.txt
+++ b/dts/Bindings/remoteproc/qcom,wcnss-pil.txt
@@ -34,14 +34,25 @@ on the Qualcomm WCNSS core.
Definition: should be "wdog", "fatal", optionally followed by "ready",
"handover", "stop-ack"
-- vddmx-supply:
-- vddcx-supply:
+- vddmx-supply: (deprecated for qcom,pronto-v1/2-pil)
+- vddcx-supply: (deprecated for qcom,pronto-v1/2-pil)
- vddpx-supply:
Usage: required
Value type: <phandle>
Definition: reference to the regulators to be held on behalf of the
booting of the WCNSS core
+- power-domains:
+ Usage: required (for qcom,pronto-v1/2-pil)
+ Value type: <phandle>
+ Definition: reference to the power domains to be held on behalf of the
+ booting of the WCNSS core
+
+- power-domain-names:
+ Usage: required (for qcom,pronto-v1/2-pil)
+ Value type: <stringlist>
+ Definition: must be "cx", "mx"
+
- qcom,smem-states:
Usage: optional
Value type: <prop-encoded-array>
@@ -111,8 +122,9 @@ pronto@fb204000 {
<&wcnss_smp2p_slave 3 0>;
interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
- vddmx-supply = <&pm8841_s1>;
- vddcx-supply = <&pm8841_s2>;
+ power-domains = <&rpmpd MSM8974_VDDCX>, <&rpmpd MSM8974_VDDMX>;
+ power-domain-names = "cx", "mx";
+
vddpx-supply = <&pm8941_s3>;
qcom,smem-states = <&wcnss_smp2p_out 0>;
diff --git a/dts/Bindings/remoteproc/st,stm32-rproc.yaml b/dts/Bindings/remoteproc/st,stm32-rproc.yaml
index 4ffa25268f..a1171dfba0 100644
--- a/dts/Bindings/remoteproc/st,stm32-rproc.yaml
+++ b/dts/Bindings/remoteproc/st,stm32-rproc.yaml
@@ -38,9 +38,6 @@ properties:
st,syscfg-tz:
description:
Reference to the system configuration which holds the RCC trust zone mode
- - Phandle of syscon block.
- - The offset of the RCC trust zone mode register.
- - The field mask of the RCC trust zone mode.
$ref: "/schemas/types.yaml#/definitions/phandle-array"
maxItems: 1
@@ -91,9 +88,19 @@ properties:
$ref: "/schemas/types.yaml#/definitions/phandle-array"
description: |
Reference to the system configuration which holds the remote
- 1st cell: phandle to syscon block
- 2nd cell: register offset containing the deep sleep setting
- 3rd cell: register bitmask for the deep sleep bit
+ maxItems: 1
+
+ st,syscfg-m4-state:
+ $ref: "/schemas/types.yaml#/definitions/phandle-array"
+ description: |
+ Reference to the tamp register which exposes the Cortex-M4 state.
+ maxItems: 1
+
+ st,syscfg-rsc-tbl:
+ $ref: "/schemas/types.yaml#/definitions/phandle-array"
+ description: |
+ Reference to the tamp register which references the Cortex-M4
+ resource table address.
maxItems: 1
st,auto-boot:
@@ -122,6 +129,8 @@ examples:
resets = <&rcc MCU_R>;
st,syscfg-holdboot = <&rcc 0x10C 0x1>;
st,syscfg-tz = <&rcc 0x000 0x1>;
+ st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
+ st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
};
...
diff --git a/dts/Bindings/remoteproc/ti,k3-r5f-rproc.yaml b/dts/Bindings/remoteproc/ti,k3-r5f-rproc.yaml
index 4069f0f5e8..d905d61450 100644
--- a/dts/Bindings/remoteproc/ti,k3-r5f-rproc.yaml
+++ b/dts/Bindings/remoteproc/ti,k3-r5f-rproc.yaml
@@ -32,6 +32,7 @@ properties:
enum:
- ti,am654-r5fss
- ti,j721e-r5fss
+ - ti,j7200-r5fss
power-domains:
description: |
@@ -95,6 +96,7 @@ patternProperties:
enum:
- ti,am654-r5f
- ti,j721e-r5f
+ - ti,j7200-r5f
reg:
items:
diff --git a/dts/Bindings/remoteproc/ti,pru-rproc.yaml b/dts/Bindings/remoteproc/ti,pru-rproc.yaml
new file mode 100644
index 0000000000..63071eef16
--- /dev/null
+++ b/dts/Bindings/remoteproc/ti,pru-rproc.yaml
@@ -0,0 +1,214 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/remoteproc/ti,pru-rproc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI Programmable Realtime Unit (PRU) cores
+
+maintainers:
+ - Suman Anna <s-anna@ti.com>
+
+description: |
+ Each Programmable Real-Time Unit and Industrial Communication Subsystem
+ (PRU-ICSS or PRUSS) has two 32-bit load/store RISC CPU cores called
+ Programmable Real-Time Units (PRUs), each represented by a node. Each PRU
+ core has a dedicated Instruction RAM, Control and Debug register sets, and
+ use the Data RAMs present within the PRU-ICSS for code execution.
+
+ The K3 SoCs containing ICSSG v1.0 (eg: AM65x SR1.0) also have two Auxiliary
+ PRU cores called RTUs with slightly different IP integration. The K3 SoCs
+ containing the revised ICSSG v1.1 (eg: J721E, AM65x SR2.0) have an extra two
+ auxiliary Transmit PRU cores called Tx_PRUs that augment the PRUs. Each RTU
+ or Tx_PRU core can also be used independently like a PRU, or alongside a
+ corresponding PRU core to provide/implement auxiliary functionality/support.
+
+ Each PRU, RTU or Tx_PRU core node should be defined as a child node of the
+ corresponding PRU-ICSS node. Each node can optionally be rendered inactive by
+ using the standard DT string property, "status".
+
+ Please see the overall PRU-ICSS bindings document for additional details
+ including a complete example,
+ Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml
+
+properties:
+ compatible:
+ enum:
+ - ti,am3356-pru # for AM335x SoC family (AM3356+ SoCs only)
+ - ti,am4376-pru # for AM437x SoC family (AM4376+ SoCs only)
+ - ti,am5728-pru # for AM57xx SoC family
+ - ti,k2g-pru # for 66AK2G SoC family
+ - ti,am654-pru # for PRUs in K3 AM65x SoC family
+ - ti,am654-rtu # for RTUs in K3 AM65x SoC family
+ - ti,am654-tx-pru # for Tx_PRUs in K3 AM65x SR2.0 SoCs
+ - ti,j721e-pru # for PRUs in K3 J721E SoC family
+ - ti,j721e-rtu # for RTUs in K3 J721E SoC family
+ - ti,j721e-tx-pru # for Tx_PRUs in K3 J721E SoC family
+
+ reg:
+ items:
+ - description: Address and Size of the PRU Instruction RAM
+ - description: Address and Size of the PRU CTRL sub-module registers
+ - description: Address and Size of the PRU Debug sub-module registers
+
+ reg-names:
+ items:
+ - const: iram
+ - const: control
+ - const: debug
+
+ firmware-name:
+ description: |
+ Should contain the name of the default firmware image
+ file located on the firmware search path.
+
+if:
+ properties:
+ compatible:
+ enum:
+ - ti,am654-rtu
+ - ti,j721e-rtu
+then:
+ properties:
+ $nodename:
+ pattern: "^rtu@[0-9a-f]+$"
+else:
+ if:
+ properties:
+ compatible:
+ enum:
+ - ti,am654-tx-pru
+ - ti,j721e-tx-pru
+ then:
+ properties:
+ $nodename:
+ pattern: "^txpru@[0-9a-f]+"
+ else:
+ properties:
+ $nodename:
+ pattern: "^pru@[0-9a-f]+$"
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - firmware-name
+
+additionalProperties: false
+
+examples:
+ - |
+ /* AM33xx PRU-ICSS */
+ pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */
+ compatible = "ti,sysc-pruss", "ti,sysc";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x300000 0x80000>;
+
+ pruss: pruss@0 {
+ compatible = "ti,am3356-pruss";
+ reg = <0x0 0x80000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pruss_mem: memories@0 {
+ reg = <0x0 0x2000>,
+ <0x2000 0x2000>,
+ <0x10000 0x3000>;
+ reg-names = "dram0", "dram1", "shrdram2";
+ };
+
+ pru0: pru@34000 {
+ compatible = "ti,am3356-pru";
+ reg = <0x34000 0x2000>,
+ <0x22000 0x400>,
+ <0x22400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am335x-pru0-fw";
+ };
+
+ pru1: pru@38000 {
+ compatible = "ti,am3356-pru";
+ reg = <0x38000 0x2000>,
+ <0x24000 0x400>,
+ <0x24400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am335x-pru1-fw";
+ };
+ };
+ };
+
+ - |
+ /* AM65x SR2.0 ICSSG */
+ #include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+ icssg0: icssg@b000000 {
+ compatible = "ti,am654-icssg";
+ reg = <0xb000000 0x80000>;
+ power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xb000000 0x80000>;
+
+ icssg0_mem: memories@0 {
+ reg = <0x0 0x2000>,
+ <0x2000 0x2000>,
+ <0x10000 0x10000>;
+ reg-names = "dram0", "dram1", "shrdram2";
+ };
+
+ pru0_0: pru@34000 {
+ compatible = "ti,am654-pru";
+ reg = <0x34000 0x4000>,
+ <0x22000 0x100>,
+ <0x22400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-pru0_0-fw";
+ };
+
+ rtu0_0: rtu@4000 {
+ compatible = "ti,am654-rtu";
+ reg = <0x4000 0x2000>,
+ <0x23000 0x100>,
+ <0x23400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-rtu0_0-fw";
+ };
+
+ tx_pru0_0: txpru@a000 {
+ compatible = "ti,am654-tx-pru";
+ reg = <0xa000 0x1800>,
+ <0x25000 0x100>,
+ <0x25400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-txpru0_0-fw";
+ };
+
+ pru0_1: pru@38000 {
+ compatible = "ti,am654-pru";
+ reg = <0x38000 0x4000>,
+ <0x24000 0x100>,
+ <0x24400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-pru0_1-fw";
+ };
+
+ rtu0_1: rtu@6000 {
+ compatible = "ti,am654-rtu";
+ reg = <0x6000 0x2000>,
+ <0x23800 0x100>,
+ <0x23c00 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-rtu0_1-fw";
+ };
+
+ tx_pru0_1: txpru@c000 {
+ compatible = "ti,am654-tx-pru";
+ reg = <0xc000 0x1800>,
+ <0x25800 0x100>,
+ <0x25c00 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am65x-txpru0_1-fw";
+ };
+ };
diff --git a/dts/Bindings/reset/brcm,bcm6345-reset.yaml b/dts/Bindings/reset/brcm,bcm6345-reset.yaml
new file mode 100644
index 0000000000..560cf6522c
--- /dev/null
+++ b/dts/Bindings/reset/brcm,bcm6345-reset.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/brcm,bcm6345-reset.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: BCM6345 reset controller
+
+description: This document describes the BCM6345 reset controller.
+
+maintainers:
+ - Álvaro Fernández Rojas <noltari@gmail.com>
+
+properties:
+ compatible:
+ const: brcm,bcm6345-reset
+
+ reg:
+ maxItems: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ reset-controller@10000010 {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0x10000010 0x4>;
+ #reset-cells = <1>;
+ };
diff --git a/dts/Bindings/reset/snps,dw-reset.txt b/dts/Bindings/reset/snps,dw-reset.txt
index f94f911dd9..0c241d4aae 100644
--- a/dts/Bindings/reset/snps,dw-reset.txt
+++ b/dts/Bindings/reset/snps,dw-reset.txt
@@ -23,7 +23,7 @@ example:
#reset-cells = <1>;
};
- dw_rst_2: reset-controller@1000 {i
+ dw_rst_2: reset-controller@1000 {
compatible = "snps,dw-low-reset";
reg = <0x1000 0x8>;
#reset-cells = <1>;
diff --git a/dts/Bindings/rtc/rtc.yaml b/dts/Bindings/rtc/rtc.yaml
index 8acd2de3de..d30dc045aa 100644
--- a/dts/Bindings/rtc/rtc.yaml
+++ b/dts/Bindings/rtc/rtc.yaml
@@ -63,6 +63,11 @@ properties:
description:
Enables wake up of host system on alarm.
+ reset-source:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ The RTC is able to reset the machine.
+
additionalProperties: true
...
diff --git a/dts/Bindings/serial/8250.yaml b/dts/Bindings/serial/8250.yaml
index c1d4c196f0..f54cae9ff7 100644
--- a/dts/Bindings/serial/8250.yaml
+++ b/dts/Bindings/serial/8250.yaml
@@ -126,7 +126,7 @@ properties:
maxItems: 1
current-speed:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description: The current active speed of the UART.
reg-offset:
@@ -154,7 +154,7 @@ properties:
Set to indicate that the port does not implement loopback test mode.
fifo-size:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description: The fifo size of the UART.
auto-flow-control:
@@ -165,7 +165,7 @@ properties:
property.
tx-threshold:
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
description: |
Specify the TX FIFO low water indication for parts with programmable
TX FIFO thresholds.
diff --git a/dts/Bindings/serial/litex,liteuart.yaml b/dts/Bindings/serial/litex,liteuart.yaml
new file mode 100644
index 0000000000..c4f1f489dc
--- /dev/null
+++ b/dts/Bindings/serial/litex,liteuart.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/litex,liteuart.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LiteUART serial controller
+
+maintainers:
+ - Karol Gugala <kgugala@antmicro.com>
+ - Mateusz Holenko <mholenko@antmicro.com>
+
+description: |
+ LiteUART serial controller is a part of the LiteX FPGA SoC builder. It supports
+ multiple CPU architectures, currently including e.g. OpenRISC and RISC-V.
+
+properties:
+ compatible:
+ const: litex,liteuart
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ uart0: serial@e0001800 {
+ compatible = "litex,liteuart";
+ reg = <0xe0001800 0x100>;
+ interrupts = <2>;
+ };
diff --git a/dts/Bindings/serial/omap_serial.txt b/dts/Bindings/serial/omap_serial.txt
index dcba86b0a0..c2db8cabf2 100644
--- a/dts/Bindings/serial/omap_serial.txt
+++ b/dts/Bindings/serial/omap_serial.txt
@@ -1,6 +1,7 @@
OMAP UART controller
Required properties:
+- compatible : should be "ti,am64-uart", "ti,am654-uart" for AM64 controllers
- compatible : should be "ti,j721e-uart", "ti,am654-uart" for J721E controllers
- compatible : should be "ti,am654-uart" for AM654 controllers
- compatible : should be "ti,omap2-uart" for OMAP2 controllers
diff --git a/dts/Bindings/serial/renesas,scif.yaml b/dts/Bindings/serial/renesas,scif.yaml
index eda3d2c6bd..672158906c 100644
--- a/dts/Bindings/serial/renesas,scif.yaml
+++ b/dts/Bindings/serial/renesas,scif.yaml
@@ -60,6 +60,7 @@ properties:
- renesas,scif-r8a77980 # R-Car V3H
- renesas,scif-r8a77990 # R-Car E3
- renesas,scif-r8a77995 # R-Car D3
+ - renesas,scif-r8a779a0 # R-Car V3U
- const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G2
- const: renesas,scif # generic SCIF compatible UART
diff --git a/dts/Bindings/serial/sifive-serial.yaml b/dts/Bindings/serial/sifive-serial.yaml
index 92283f693d..3ac5c7ff27 100644
--- a/dts/Bindings/serial/sifive-serial.yaml
+++ b/dts/Bindings/serial/sifive-serial.yaml
@@ -17,7 +17,9 @@ allOf:
properties:
compatible:
items:
- - const: sifive,fu540-c000-uart
+ - enum:
+ - sifive,fu540-c000-uart
+ - sifive,fu740-c000-uart
- const: sifive,uart0
description:
diff --git a/dts/Bindings/soc/litex/litex,soc-controller.yaml b/dts/Bindings/soc/litex/litex,soc-controller.yaml
new file mode 100644
index 0000000000..c8b57c7fd0
--- /dev/null
+++ b/dts/Bindings/soc/litex/litex,soc-controller.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+# Copyright 2020 Antmicro <www.antmicro.com>
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/litex/litex,soc-controller.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: LiteX SoC Controller driver
+
+description: |
+ This is the SoC Controller driver for the LiteX SoC Builder.
+ Its purpose is to verify LiteX CSR (Control&Status Register) access
+ operations and provide functions for other drivers to read/write CSRs
+ and to check if those accessors are ready to be used.
+
+maintainers:
+ - Karol Gugala <kgugala@antmicro.com>
+ - Mateusz Holenko <mholenko@antmicro.com>
+
+properties:
+ compatible:
+ const: litex,soc-controller
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ soc_ctrl0: soc-controller@f0000000 {
+ compatible = "litex,soc-controller";
+ reg = <0xf0000000 0xc>;
+ status = "okay";
+ };
+
+...
diff --git a/dts/Bindings/soc/mediatek/devapc.yaml b/dts/Bindings/soc/mediatek/devapc.yaml
new file mode 100644
index 0000000000..31e4d3c339
--- /dev/null
+++ b/dts/Bindings/soc/mediatek/devapc.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# # Copyright 2020 MediaTek Inc.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/mediatek/devapc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: MediaTek Device Access Permission Control driver
+
+description: |
+ MediaTek bus fabric provides TrustZone security support and data
+ protection to prevent slaves from being accessed by unexpected masters.
+ The security violation is logged and sent to the processor for further
+ analysis and countermeasures.
+
+maintainers:
+ - Neal Liu <neal.liu@mediatek.com>
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt6779-devapc
+
+ reg:
+ description: The base address of devapc register bank
+ maxItems: 1
+
+ interrupts:
+ description: A single interrupt specifier
+ maxItems: 1
+
+ clocks:
+ description: Contains module clock source and clock names
+ maxItems: 1
+
+ clock-names:
+ description: Names of the clocks list in clocks property
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt6779-clk.h>
+
+ devapc: devapc@10207000 {
+ compatible = "mediatek,mt6779-devapc";
+ reg = <0x10207000 0x1000>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg_ao CLK_INFRA_DEVICE_APC>;
+ clock-names = "devapc-infra-clock";
+ };
diff --git a/dts/Bindings/soc/microchip/atmel,at91rm9200-tcb.yaml b/dts/Bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
index 55fffae05d..597d67fba9 100644
--- a/dts/Bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
+++ b/dts/Bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
@@ -59,6 +59,7 @@ patternProperties:
items:
- enum:
- atmel,tcb-timer
+ - atmel,tcb-pwm
- microchip,tcb-capture
reg:
description:
@@ -68,10 +69,35 @@ patternProperties:
minItems: 1
maxItems: 3
+ required:
+ - compatible
+ - reg
+
+ "^pwm@[0-2]$":
+ description: The timer block channels that are used as PWMs.
+ $ref: ../../pwm/pwm.yaml#
+ type: object
+ properties:
+ compatible:
+ const: atmel,tcb-pwm
+ reg:
+ description:
+ TCB channel to use for this PWM.
+ enum: [ 0, 1, 2 ]
+
+ "#pwm-cells":
+ description:
+ The only third cell flag supported by this binding is
+ PWM_POLARITY_INVERTED.
+ const: 3
required:
- compatible
- reg
+ - "#pwm-cells"
+
+ additionalProperties: false
+
allOf:
- if:
@@ -158,7 +184,13 @@ examples:
compatible = "atmel,tcb-timer";
reg = <1>;
};
- };
+
+ pwm@2 {
+ compatible = "atmel,tcb-pwm";
+ reg = <2>;
+ #pwm-cells = <3>;
+ };
+ };
/* TCB0 Capture with QDEC: */
timer@f800c000 {
compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
diff --git a/dts/Bindings/soc/ti/k3-ringacc.yaml b/dts/Bindings/soc/ti/k3-ringacc.yaml
index c3c595e235..ddea3d4197 100644
--- a/dts/Bindings/soc/ti/k3-ringacc.yaml
+++ b/dts/Bindings/soc/ti/k3-ringacc.yaml
@@ -55,7 +55,7 @@ properties:
description: TI-SCI RM subtype for GP ring range
ti,sci:
- $ref: /schemas/types.yaml#definitions/phandle-array
+ $ref: /schemas/types.yaml#/definitions/phandle-array
description: phandle on TI-SCI compatible System controller node
ti,sci-dev-id:
diff --git a/dts/Bindings/soc/xilinx/xlnx,vcu-settings.yaml b/dts/Bindings/soc/xilinx/xlnx,vcu-settings.yaml
new file mode 100644
index 0000000000..cb245f4002
--- /dev/null
+++ b/dts/Bindings/soc/xilinx/xlnx,vcu-settings.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/xilinx/xlnx,vcu-settings.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx VCU Settings
+
+maintainers:
+ - Michael Tretter <kernel@pengutronix.de>
+
+description: |
+ The Xilinx VCU Settings provides information about the configuration of the
+ video codec unit.
+
+properties:
+ compatible:
+ items:
+ - const: xlnx,vcu-settings
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ fpga {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ xlnx_vcu: vcu@a0041000 {
+ compatible = "xlnx,vcu-settings", "syscon";
+ reg = <0x0 0xa0041000 0x0 0x1000>;
+ };
+ };
+
+...
diff --git a/dts/Bindings/soc/xilinx/xlnx,vcu.txt b/dts/Bindings/soc/xilinx/xlnx,vcu.txt
index 6786d6715d..2417b13ba4 100644
--- a/dts/Bindings/soc/xilinx/xlnx,vcu.txt
+++ b/dts/Bindings/soc/xilinx/xlnx,vcu.txt
@@ -12,10 +12,7 @@ Required properties:
- compatible: shall be one of:
"xlnx,vcu"
"xlnx,vcu-logicoreip-1.0"
-- reg, reg-names: There are two sets of registers need to provide.
- 1. vcu slcr
- 2. Logicore
- reg-names should contain name for the each register sequence.
+- reg : The base offset and size of the VCU_PL_SLCR register space.
- clocks: phandle for aclk and pll_ref clocksource
- clock-names: The identification string, "aclk", is always required for
the axi clock. "pll_ref" is required for pll.
@@ -23,9 +20,7 @@ Example:
xlnx_vcu: vcu@a0040000 {
compatible = "xlnx,vcu-logicoreip-1.0";
- reg = <0x0 0xa0040000 0x0 0x1000>,
- <0x0 0xa0041000 0x0 0x1000>;
- reg-names = "vcu_slcr", "logicore";
+ reg = <0x0 0xa0040000 0x0 0x1000>;
clocks = <&si570_1>, <&clkc 71>;
clock-names = "pll_ref", "aclk";
};
diff --git a/dts/Bindings/sound/adi,adau1372.yaml b/dts/Bindings/sound/adi,adau1372.yaml
new file mode 100644
index 0000000000..701449311f
--- /dev/null
+++ b/dts/Bindings/sound/adi,adau1372.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/adi,adau1372.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+
+title: Analog Devices ADAU1372 CODEC
+
+maintainers:
+ - Alexandre Belloni <alexandre.belloni@bootlin.om>
+
+description: |
+ Analog Devices ADAU1372 four inputs and two outputs codec.
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1372.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,adau1372
+
+ reg:
+ maxItems: 1
+
+ "#sound-dai-cells":
+ const: 0
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: "mclk"
+
+ powerdown-gpios:
+ description: GPIO used for hardware power-down.
+ maxItems: 1
+
+required:
+ - "#sound-dai-cells"
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ audio-codec@3c {
+ compatible = "adi,adau1372";
+ reg = <0x3c>;
+ #sound-dai-cells = <0>;
+ clock-names = "mclk";
+ clocks = <&adau1372z_xtal>;
+ };
+ };
+
+ adau1372z_xtal: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12288000>;
+ };
+...
+
diff --git a/dts/Bindings/sound/adi,adau1977.txt b/dts/Bindings/sound/adi,adau1977.txt
deleted file mode 100644
index 37f8aad012..0000000000
--- a/dts/Bindings/sound/adi,adau1977.txt
+++ /dev/null
@@ -1,61 +0,0 @@
-Analog Devices ADAU1977/ADAU1978/ADAU1979
-
-Datasheets:
-https://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1977.pdf
-https://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1978.pdf
-https://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1979.pdf
-
-This driver supports both the I2C and SPI bus.
-
-Required properties:
- - compatible: Should contain one of the following:
- "adi,adau1977"
- "adi,adau1978"
- "adi,adau1979"
-
- - AVDD-supply: analog power supply for the device, please consult
- Documentation/devicetree/bindings/regulator/regulator.txt
-
-Optional properties:
- - reset-gpios: the reset pin for the chip, for more details consult
- Documentation/devicetree/bindings/gpio/gpio.txt
-
- - DVDD-supply: supply voltage for the digital core, please consult
- Documentation/devicetree/bindings/regulator/regulator.txt
-
-- adi,micbias: configures the voltage setting for the MICBIAS pin.
- Select 0/1/2/3/4/5/6/7/8 to specify MICBIAS voltage
- 5V/5.5V/6V/6.5V/7V/7.5V/8V/8.5V/9V
- If not specified the default value will be "7" meaning 8.5 Volts.
- This property is only valid for the ADAU1977
-
-For required properties on SPI, please consult
-Documentation/devicetree/bindings/spi/spi-bus.txt
-
-Required properties on I2C:
-
- - reg: The i2c address. Value depends on the state of ADDR0
- and ADDR1, as wired in hardware.
-
-Examples:
-
- adau1977_spi: adau1977@0 {
- compatible = "adi,adau1977";
- spi-max-frequency = <600000>;
-
- AVDD-supply = <&regulator>;
- DVDD-supply = <&regulator_digital>;
-
- adi,micbias = <3>;
- reset-gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
- };
-
- adau1977_i2c: adau1977@11 {
- compatible = "adi,adau1977";
- reg = <0x11>;
-
- AVDD-supply = <&regulator>;
- DVDD-supply = <&regulator_digital>;
-
- reset-gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
- };
diff --git a/dts/Bindings/sound/adi,adau1977.yaml b/dts/Bindings/sound/adi,adau1977.yaml
new file mode 100644
index 0000000000..b80454ad97
--- /dev/null
+++ b/dts/Bindings/sound/adi,adau1977.yaml
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/adi,adau1977.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices ADAU1977/ADAU1978/ADAU1979 Quad ADC with Diagnostics
+
+maintainers:
+ - Lars-Peter Clausen <lars@metafoo.de>
+ - Bogdan Togorean <bogdan.togorean@analog.com>
+
+description: |
+ Analog Devices ADAU1977 and similar quad ADC with Diagnostics
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1977.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1978.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1979.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,adau1977
+ - adi,adau1978
+ - adi,adau1979
+
+ reg:
+ maxItems: 1
+
+ "#sound-dai-cells":
+ const: 0
+
+ reset-gpios:
+ maxItems: 1
+
+ spi-max-frequency: true
+
+ AVDD-supply:
+ description: Analog power support for the device.
+
+ DVDD-supply:
+ description: Supply voltage for digital core.
+
+ adi,micbias:
+ description: |
+ Configures the voltage setting for the MICBIAS pin.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3, 4, 5, 6, 7, 8]
+ default: 7
+
+required:
+ - reg
+ - compatible
+ - AVDD-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ adau1977_spi: adau1977@0 {
+ compatible = "adi,adau1977";
+ reg = <0>;
+ spi-max-frequency = <600000>;
+
+ AVDD-supply = <&regulator>;
+ DVDD-supply = <&regulator_digital>;
+
+ reset-gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+
+ adi,micbias = <3>;
+ };
+ };
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ adau1977_i2c: adau1977@11 {
+ compatible = "adi,adau1977";
+ reg = <0x11>;
+
+ AVDD-supply = <&regulator>;
+ DVDD-supply = <&regulator_digital>;
+
+ reset-gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+ };
+ };
diff --git a/dts/Bindings/sound/allwinner,sun4i-a10-codec.yaml b/dts/Bindings/sound/allwinner,sun4i-a10-codec.yaml
index be390accdd..dd47fef985 100644
--- a/dts/Bindings/sound/allwinner,sun4i-a10-codec.yaml
+++ b/dts/Bindings/sound/allwinner,sun4i-a10-codec.yaml
@@ -57,7 +57,7 @@ properties:
A list of the connections between audio components. Each entry
is a pair of strings, the first being the connection's sink, the
second being the connection's source.
- $ref: /schemas/types.yaml#definitions/non-unique-string-array
+ $ref: /schemas/types.yaml#/definitions/non-unique-string-array
minItems: 2
maxItems: 18
items:
diff --git a/dts/Bindings/sound/allwinner,sun4i-a10-i2s.yaml b/dts/Bindings/sound/allwinner,sun4i-a10-i2s.yaml
index 112ae00d63..a16e37b01e 100644
--- a/dts/Bindings/sound/allwinner,sun4i-a10-i2s.yaml
+++ b/dts/Bindings/sound/allwinner,sun4i-a10-i2s.yaml
@@ -24,6 +24,7 @@ properties:
- items:
- const: allwinner,sun50i-a64-i2s
- const: allwinner,sun8i-h3-i2s
+ - const: allwinner,sun50i-h6-i2s
reg:
maxItems: 1
@@ -59,6 +60,7 @@ allOf:
- allwinner,sun8i-a83t-i2s
- allwinner,sun8i-h3-i2s
- allwinner,sun50i-a64-codec-i2s
+ - allwinner,sun50i-h6-i2s
then:
required:
@@ -68,7 +70,9 @@ allOf:
properties:
compatible:
contains:
- const: allwinner,sun8i-a83t-i2s
+ enum:
+ - allwinner,sun8i-a83t-i2s
+ - allwinner,sun8i-h3-i2s
then:
properties:
diff --git a/dts/Bindings/sound/audio-graph-card.txt b/dts/Bindings/sound/audio-graph-card.txt
deleted file mode 100644
index d5f6919a2d..0000000000
--- a/dts/Bindings/sound/audio-graph-card.txt
+++ /dev/null
@@ -1,337 +0,0 @@
-Audio Graph Card:
-
-Audio Graph Card specifies audio DAI connections of SoC <-> codec.
-It is based on common bindings for device graphs.
-see ${LINUX}/Documentation/devicetree/bindings/graph.txt
-
-Basically, Audio Graph Card property is same as Simple Card.
-see ${LINUX}/Documentation/devicetree/bindings/sound/simple-card.yaml
-
-Below are same as Simple-Card.
-
-- label
-- widgets
-- routing
-- dai-format
-- frame-master
-- bitclock-master
-- bitclock-inversion
-- frame-inversion
-- mclk-fs
-- hp-det-gpio
-- mic-det-gpio
-- dai-tdm-slot-num
-- dai-tdm-slot-width
-- clocks / system-clock-frequency
-
-Required properties:
-
-- compatible : "audio-graph-card";
-- dais : list of CPU DAI port{s}
-
-Optional properties:
-- pa-gpios: GPIO used to control external amplifier.
-
------------------------
-Example: Single DAI case
------------------------
-
- sound_card {
- compatible = "audio-graph-card";
-
- dais = <&cpu_port>;
- };
-
- dai-controller {
- ...
- cpu_port: port {
- cpu_endpoint: endpoint {
- remote-endpoint = <&codec_endpoint>;
-
- dai-format = "left_j";
- ...
- };
- };
- };
-
- audio-codec {
- ...
- port {
- codec_endpoint: endpoint {
- remote-endpoint = <&cpu_endpoint>;
- };
- };
- };
-
------------------------
-Example: Multi DAI case
------------------------
-
- sound-card {
- compatible = "audio-graph-card";
-
- label = "sound-card";
-
- dais = <&cpu_port0
- &cpu_port1
- &cpu_port2>;
- };
-
- audio-codec@0 {
- ...
- port {
- codec0_endpoint: endpoint {
- remote-endpoint = <&cpu_endpoint0>;
- };
- };
- };
-
- audio-codec@1 {
- ...
- port {
- codec1_endpoint: endpoint {
- remote-endpoint = <&cpu_endpoint1>;
- };
- };
- };
-
- audio-codec@2 {
- ...
- port {
- codec2_endpoint: endpoint {
- remote-endpoint = <&cpu_endpoint2>;
- };
- };
- };
-
- dai-controller {
- ...
- ports {
- cpu_port0: port@0 {
- cpu_endpoint0: endpoint {
- remote-endpoint = <&codec0_endpoint>;
-
- dai-format = "left_j";
- ...
- };
- };
- cpu_port1: port@1 {
- cpu_endpoint1: endpoint {
- remote-endpoint = <&codec1_endpoint>;
-
- dai-format = "i2s";
- ...
- };
- };
- cpu_port2: port@2 {
- cpu_endpoint2: endpoint {
- remote-endpoint = <&codec2_endpoint>;
-
- dai-format = "i2s";
- ...
- };
- };
- };
- };
-
-
------------------------
-Example: Sampling Rate Conversion
------------------------
-
- sound_card {
- compatible = "audio-graph-card";
-
- label = "sound-card";
- prefix = "codec";
- routing = "codec Playback", "DAI0 Playback",
- "DAI0 Capture", "codec Capture";
- convert-rate = <48000>;
-
- dais = <&cpu_port>;
- };
-
- audio-codec {
- ...
- port {
- codec_endpoint: endpoint {
- remote-endpoint = <&cpu_endpoint>;
- };
- };
- };
-
- dai-controller {
- ...
- cpu_port: port {
- cpu_endpoint: endpoint {
- remote-endpoint = <&codec_endpoint>;
-
- dai-format = "left_j";
- ...
- };
- };
- };
-
------------------------
-Example: 2 CPU 1 Codec (Mixing)
------------------------
-
- sound_card {
- compatible = "audio-graph-card";
-
- label = "sound-card";
- routing = "codec Playback", "DAI0 Playback",
- "codec Playback", "DAI1 Playback",
- "DAI0 Capture", "codec Capture";
-
- dais = <&cpu_port>;
- };
-
- audio-codec {
- ...
-
- audio-graph-card,prefix = "codec";
- audio-graph-card,convert-rate = <48000>;
- port {
- reg = <0>;
- codec_endpoint0: endpoint@0 {
- remote-endpoint = <&cpu_endpoint0>;
- };
- codec_endpoint1: endpoint@1 {
- remote-endpoint = <&cpu_endpoint1>;
- };
- };
- };
-
- dai-controller {
- ...
- cpu_port: port {
- cpu_endpoint0: endpoint@0 {
- remote-endpoint = <&codec_endpoint0>;
-
- dai-format = "left_j";
- ...
- };
- cpu_endpoint1: endpoint@1 {
- remote-endpoint = <&codec_endpoint1>;
-
- dai-format = "left_j";
- ...
- };
- };
- };
-
------------------------
-Example: Multi DAI with DPCM
------------------------
-
- CPU0 ------ ak4613
- CPU1 ------ HDMI
- CPU2 ------ PCM3168A-p /* DPCM 1ch/2ch */
- CPU3 --/ /* DPCM 3ch/4ch */
- CPU4 --/ /* DPCM 5ch/6ch */
- CPU5 --/ /* DPCM 7ch/8ch */
- CPU6 ------ PCM3168A-c
-
- sound_card: sound {
- compatible = "audio-graph-card";
-
- label = "sound-card";
-
- routing = "pcm3168a Playback", "DAI2 Playback",
- "pcm3168a Playback", "DAI3 Playback",
- "pcm3168a Playback", "DAI4 Playback",
- "pcm3168a Playback", "DAI5 Playback";
-
- dais = <&snd_port0 /* ak4613 */
- &snd_port1 /* HDMI0 */
- &snd_port2 /* pcm3168a playback */
- &snd_port3 /* pcm3168a capture */
- >;
- };
-
- ak4613: codec@10 {
- ...
- port {
- ak4613_endpoint: endpoint {
- remote-endpoint = <&rsnd_endpoint0>;
- };
- };
- };
-
- pcm3168a: audio-codec@44 {
- ...
- audio-graph-card,prefix = "pcm3168a";
- audio-graph-card,convert-channels = <8>; /* TDM Split */
- ports {
- port@0 {
- reg = <0>;
- pcm3168a_endpoint_p1: endpoint@1 {
- remote-endpoint = <&rsnd_endpoint2>;
- ...
- };
- pcm3168a_endpoint_p2: endpoint@2 {
- remote-endpoint = <&rsnd_endpoint3>;
- ...
- };
- pcm3168a_endpoint_p3: endpoint@3 {
- remote-endpoint = <&rsnd_endpoint4>;
- ...
- };
- pcm3168a_endpoint_p4: endpoint@4 {
- remote-endpoint = <&rsnd_endpoint5>;
- ...
- };
- };
- port@1 {
- reg = <1>;
- pcm3168a_endpoint_c: endpoint {
- remote-endpoint = <&rsnd_endpoint6>;
- ...
- };
- };
- };
- };
-
- &sound {
- ports {
- snd_port0: port@0 {
- rsnd_endpoint0: endpoint {
- remote-endpoint = <&ak4613_endpoint>;
- ...
- };
- };
- snd_port1: port@1 {
- rsnd_endpoint1: endpoint {
- remote-endpoint = <&dw_hdmi0_snd_in>;
- ...
- };
- };
- snd_port2: port@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- rsnd_endpoint2: endpoint@2 {
- remote-endpoint = <&pcm3168a_endpoint_p1>;
- ...
- };
- rsnd_endpoint3: endpoint@3 {
- remote-endpoint = <&pcm3168a_endpoint_p2>;
- ...
- };
- rsnd_endpoint4: endpoint@4 {
- remote-endpoint = <&pcm3168a_endpoint_p3>;
- ...
- };
- rsnd_endpoint5: endpoint@5 {
- remote-endpoint = <&pcm3168a_endpoint_p4>;
- ...
- };
- };
- snd_port3: port@6 {
- rsnd_endpoint6: endpoint {
- remote-endpoint = <&pcm3168a_endpoint_c>;
- ...
- };
- };
- };
- };
diff --git a/dts/Bindings/sound/audio-graph-card.yaml b/dts/Bindings/sound/audio-graph-card.yaml
new file mode 100644
index 0000000000..109e55f9e5
--- /dev/null
+++ b/dts/Bindings/sound/audio-graph-card.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/audio-graph-card.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Audio Graph Card Device Tree Bindings
+
+maintainers:
+ - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+
+allOf:
+ - $ref: /schemas/sound/audio-graph.yaml#
+
+properties:
+ compatible:
+ enum:
+ - audio-graph-card
+ - audio-graph-scu-card
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ sound {
+ compatible = "audio-graph-card";
+
+ dais = <&cpu_port_a>;
+ };
+
+ cpu {
+ /*
+ * dai-controller own settings
+ */
+
+ port {
+ cpu_endpoint: endpoint {
+ remote-endpoint = <&codec_endpoint>;
+ dai-format = "left_j";
+ };
+ };
+ };
+
+ codec {
+ /*
+ * codec own settings
+ */
+
+ port {
+ codec_endpoint: endpoint {
+ remote-endpoint = <&cpu_endpoint>;
+ };
+ };
+ };
diff --git a/dts/Bindings/sound/audio-graph-port.yaml b/dts/Bindings/sound/audio-graph-port.yaml
new file mode 100644
index 0000000000..2005014161
--- /dev/null
+++ b/dts/Bindings/sound/audio-graph-port.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/audio-graph-port.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Audio Graph Card 'port' Node Bindings
+
+maintainers:
+ - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+
+select: false
+
+properties:
+ port:
+ description: single OF-Graph subnode
+ type: object
+ properties:
+ reg:
+ maxItems: 1
+ prefix:
+ description: "device name prefix"
+ $ref: /schemas/types.yaml#/definitions/string
+ convert-rate:
+ description: CPU to Codec rate convert.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ convert-channels:
+ description: CPU to Codec rate channels.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ patternProperties:
+ "^endpoint(@[0-9a-f]+)?":
+ type: object
+ properties:
+ remote-endpoint:
+ maxItems: 1
+ mclk-fs:
+ description: |
+ Multiplication factor between stream rate and codec mclk.
+ When defined, mclk-fs property defined in dai-link sub nodes are
+ ignored.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ frame-inversion:
+ description: dai-link uses frame clock inversion
+ $ref: /schemas/types.yaml#/definitions/flag
+ bitclock-inversion:
+ description: dai-link uses bit clock inversion
+ $ref: /schemas/types.yaml#/definitions/flag
+ frame-master:
+ description: Indicates dai-link frame master.
+ $ref: /schemas/types.yaml#/definitions/phandle
+ bitclock-master:
+ description: Indicates dai-link bit clock master
+ $ref: /schemas/types.yaml#/definitions/phandle
+ dai-format:
+ description: audio format.
+ items:
+ enum:
+ - i2s
+ - right_j
+ - left_j
+ - dsp_a
+ - dsp_b
+ - ac97
+ - pdm
+ - msb
+ - lsb
+ convert-rate:
+ description: CPU to Codec rate convert.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ convert-channels:
+ description: CPU to Codec rate channels.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ required:
+ - remote-endpoint
+
+ ports:
+ description: multi OF-Graph subnode
+ type: object
+ patternProperties:
+ "^port(@[0-9a-f]+)?":
+ $ref: "#/properties/port"
+
+additionalProperties: true
diff --git a/dts/Bindings/sound/audio-graph.yaml b/dts/Bindings/sound/audio-graph.yaml
new file mode 100644
index 0000000000..4b46794e51
--- /dev/null
+++ b/dts/Bindings/sound/audio-graph.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/audio-graph.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Audio Graph Device Tree Bindings
+
+maintainers:
+ - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+
+properties:
+ dais:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ label:
+ maxItems: 1
+ prefix:
+ description: "device name prefix"
+ $ref: /schemas/types.yaml#/definitions/string
+ routing:
+ description: |
+ A list of the connections between audio components.
+ Each entry is a pair of strings, the first being the
+ connection's sink, the second being the connection's source.
+ $ref: /schemas/types.yaml#/definitions/non-unique-string-array
+ widgets:
+ description: User specified audio sound widgets.
+ $ref: /schemas/types.yaml#/definitions/non-unique-string-array
+ convert-rate:
+ description: CPU to Codec rate convert.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ convert-channels:
+ description: CPU to Codec rate channels.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ pa-gpios:
+ maxItems: 1
+ hp-det-gpio:
+ maxItems: 1
+ mic-det-gpio:
+ maxItems: 1
+
+required:
+ - dais
+
+additionalProperties: true
diff --git a/dts/Bindings/sound/fsl,aud2htx.yaml b/dts/Bindings/sound/fsl,aud2htx.yaml
new file mode 100644
index 0000000000..aa4be71707
--- /dev/null
+++ b/dts/Bindings/sound/fsl,aud2htx.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/fsl,aud2htx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP Audio Subsystem to HDMI RTX Subsystem Controller
+
+maintainers:
+ - Shengjiu Wang <shengjiu.wang@nxp.com>
+
+properties:
+ compatible:
+ const: fsl,imx8mp-aud2htx
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Peripheral clock
+
+ clock-names:
+ items:
+ - const: bus
+
+ dmas:
+ items:
+ - description: DMA controller phandle and request line for TX
+
+ dma-names:
+ items:
+ - const: tx
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - dmas
+ - dma-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/imx8mp-clock.h>
+
+ aud2htx: aud2htx@30cb0000 {
+ compatible = "fsl,imx8mp-aud2htx";
+ reg = <0x30cb0000 0x10000>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG>;
+ clock-names = "bus";
+ dmas = <&sdma2 26 2 0>;
+ dma-names = "tx";
+ power-domains = <&audiomix_pd>;
+ };
diff --git a/dts/Bindings/sound/fsl,spdif.yaml b/dts/Bindings/sound/fsl,spdif.yaml
index 2ac671f5cb..50449b6d10 100644
--- a/dts/Bindings/sound/fsl,spdif.yaml
+++ b/dts/Bindings/sound/fsl,spdif.yaml
@@ -20,6 +20,7 @@ properties:
- fsl,imx35-spdif
- fsl,vf610-spdif
- fsl,imx6sx-spdif
+ - fsl,imx8qm-spdif
reg:
maxItems: 1
diff --git a/dts/Bindings/sound/fsl,xcvr.yaml b/dts/Bindings/sound/fsl,xcvr.yaml
new file mode 100644
index 0000000000..223b8ea693
--- /dev/null
+++ b/dts/Bindings/sound/fsl,xcvr.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/fsl,xcvr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP Audio Transceiver (XCVR) Controller
+
+maintainers:
+ - Viorel Suman <viorel.suman@nxp.com>
+
+description: |
+ NXP XCVR (Audio Transceiver) is a on-chip functional module
+ that allows CPU to receive and transmit digital audio via
+ HDMI2.1 eARC, HDMI1.4 ARC and SPDIF.
+
+properties:
+ $nodename:
+ pattern: "^xcvr@.*"
+
+ compatible:
+ enum:
+ - fsl,imx8mp-xcvr
+
+ reg:
+ items:
+ - description: 20K RAM for code and data
+ - description: registers space
+ - description: RX FIFO address
+ - description: TX FIFO address
+
+ reg-names:
+ items:
+ - const: ram
+ - const: regs
+ - const: rxfifo
+ - const: txfifo
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Peripheral clock
+ - description: PHY clock
+ - description: SPBA clock
+ - description: PLL clock
+
+ clock-names:
+ items:
+ - const: ipg
+ - const: phy
+ - const: spba
+ - const: pll_ipg
+
+ dmas:
+ items:
+ - description: DMA controller phandle and request line for RX
+ - description: DMA controller phandle and request line for TX
+
+ dma-names:
+ items:
+ - const: rx
+ - const: tx
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - clocks
+ - clock-names
+ - dmas
+ - dma-names
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/imx8mp-clock.h>
+ #include <dt-bindings/reset/imx8mp-reset.h>
+
+ xcvr: xcvr@30cc0000 {
+ compatible = "fsl,imx8mp-xcvr";
+ reg = <0x30cc0000 0x800>,
+ <0x30cc0800 0x400>,
+ <0x30cc0c00 0x080>,
+ <0x30cc0e00 0x080>;
+ reg-names = "ram", "regs", "rxfifo", "txfifo";
+ interrupts = <0x0 128 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_IPG>,
+ <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_PHY>,
+ <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>,
+ <&audiomix_clk IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>;
+ clock-names = "ipg", "phy", "spba", "pll_ipg";
+ dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>;
+ dma-names = "rx", "tx";
+ resets = <&audiomix_reset 0>;
+ };
diff --git a/dts/Bindings/sound/fsl-asoc-card.txt b/dts/Bindings/sound/fsl-asoc-card.txt
index f339be62e7..90d9e9d816 100644
--- a/dts/Bindings/sound/fsl-asoc-card.txt
+++ b/dts/Bindings/sound/fsl-asoc-card.txt
@@ -40,6 +40,8 @@ The compatible list for this generic sound card currently:
"fsl,imx-audio-tlv320aic32x4"
+ "fsl,imx-audio-si476x"
+
Required properties:
- compatible : Contains one of entries in the compatible list.
diff --git a/dts/Bindings/sound/google,sc7180-trogdor.yaml b/dts/Bindings/sound/google,sc7180-trogdor.yaml
new file mode 100644
index 0000000000..5095b780e2
--- /dev/null
+++ b/dts/Bindings/sound/google,sc7180-trogdor.yaml
@@ -0,0 +1,138 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/google,sc7180-trogdor.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google SC7180-Trogdor ASoC sound card driver
+
+maintainers:
+ - Rohit kumar <rohitkr@codeaurora.org>
+ - Cheng-Yi Chiang <cychiang@chromium.org>
+
+description:
+ This binding describes the SC7180 sound card which uses LPASS for audio.
+
+properties:
+ compatible:
+ enum:
+ - google,sc7180-trogdor
+ - google,sc7180-coachz
+
+ audio-routing:
+ $ref: /schemas/types.yaml#/definitions/non-unique-string-array
+ description:
+ A list of the connections between audio components. Each entry is a
+ pair of strings, the first being the connection's sink, the second
+ being the connection's source.
+
+ model:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: User specified audio sound card name
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ dmic-gpios:
+ maxItems: 1
+ description: GPIO for switching between DMICs
+
+patternProperties:
+ "^dai-link(@[0-9])?$":
+ description:
+ Each subnode represents a dai link. Subnodes of each dai links would be
+ cpu/codec dais.
+
+ type: object
+
+ properties:
+ link-name:
+ description: Indicates dai-link name and PCM stream name.
+ $ref: /schemas/types.yaml#/definitions/string
+ maxItems: 1
+
+ reg:
+ description: dai link address.
+
+ cpu:
+ description: Holds subnode which indicates cpu dai.
+ type: object
+ properties:
+ sound-dai: true
+
+ codec:
+ description: Holds subnode which indicates codec dai.
+ type: object
+ properties:
+ sound-dai: true
+
+ required:
+ - link-name
+ - cpu
+ - codec
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - model
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+
+ - |
+ sound {
+ compatible = "google,sc7180-trogdor";
+ model = "sc7180-rt5682-max98357a-2mic";
+
+ audio-routing =
+ "Headphone Jack", "HPOL",
+ "Headphone Jack", "HPOR";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dmic-gpios = <&tlmm 86 0>;
+
+ dai-link@0 {
+ link-name = "MultiMedia0";
+ reg = <0>;
+ cpu {
+ sound-dai = <&lpass_cpu 0>;
+ };
+
+ codec {
+ sound-dai = <&alc5682 0>;
+ };
+ };
+
+ dai-link@1 {
+ link-name = "MultiMedia1";
+ reg = <1>;
+ cpu {
+ sound-dai = <&lpass_cpu 1>;
+ };
+
+ codec {
+ sound-dai = <&max98357a>;
+ };
+ };
+
+ dai-link@2 {
+ link-name = "MultiMedia2";
+ reg = <2>;
+ cpu {
+ sound-dai = <&lpass_hdmi 0>;
+ };
+
+ codec {
+ sound-dai = <&msm_dp>;
+ };
+ };
+ };
diff --git a/dts/Bindings/sound/imx-audio-hdmi.yaml b/dts/Bindings/sound/imx-audio-hdmi.yaml
new file mode 100644
index 0000000000..d5474f83ac
--- /dev/null
+++ b/dts/Bindings/sound/imx-audio-hdmi.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/imx-audio-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX audio complex with HDMI
+
+maintainers:
+ - Shengjiu Wang <shengjiu.wang@nxp.com>
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx-audio-hdmi
+ - fsl,imx-audio-sii902x
+
+ model:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: User specified audio sound card name
+
+ audio-cpu:
+ description: The phandle of an CPU DAI controller
+
+ hdmi-out:
+ description: |
+ This is a boolean property. If present, the transmitting function
+ of HDMI will be enabled, indicating there's a physical HDMI out
+ connector or jack on the board or it's connecting to some other IP
+ block, such as an HDMI encoder or display-controller.
+
+ hdmi-in:
+ description: |
+ This is a boolean property. If present, the receiving function of
+ HDMI will be enabled, indicating there is a physical HDMI in
+ connector/jack on the board.
+
+required:
+ - compatible
+ - model
+ - audio-cpu
+
+additionalProperties: false
+
+examples:
+ - |
+ sound-hdmi {
+ compatible = "fsl,imx-audio-hdmi";
+ model = "audio-hdmi";
+ audio-cpu = <&aud2htx>;
+ hdmi-out;
+ };
diff --git a/dts/Bindings/sound/marvell,mmp-sspa.yaml b/dts/Bindings/sound/marvell,mmp-sspa.yaml
index 6d20a24a2a..234f64a321 100644
--- a/dts/Bindings/sound/marvell,mmp-sspa.yaml
+++ b/dts/Bindings/sound/marvell,mmp-sspa.yaml
@@ -9,6 +9,9 @@ title: Marvel SSPA Digital Audio Interface Bindings
maintainers:
- Lubomir Rintel <lkundrak@v3.sk>
+allOf:
+ - $ref: audio-graph-port.yaml#
+
properties:
$nodename:
pattern: "^audio-controller(@.*)?$"
@@ -58,29 +61,9 @@ properties:
type: object
properties:
- remote-endpoint: true
-
- frame-master:
- type: boolean
- description: SoC generates the frame clock
-
- bitclock-master:
- type: boolean
- description: SoC generates the bit clock
-
dai-format:
- $ref: /schemas/types.yaml#/definitions/string
- description: The digital audio format
const: i2s
- required:
- - remote-endpoint
-
- required:
- - endpoint
-
- additionalProperties: false
-
required:
- "#sound-dai-cells"
- compatible
@@ -112,8 +95,6 @@ examples:
port {
endpoint {
remote-endpoint = <&rt5631_0>;
- frame-master;
- bitclock-master;
dai-format = "i2s";
};
};
diff --git a/dts/Bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml b/dts/Bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml
new file mode 100644
index 0000000000..bf8c8ba250
--- /dev/null
+++ b/dts/Bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/mt8192-mt6359-rt1015-rt5682.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek MT8192 with MT6359, RT1015 and RT5682 ASoC sound card driver
+
+maintainers:
+ - Jiaxin Yu <jiaxin.yu@mediatek.com>
+ - Shane Chien <shane.chien@mediatek.com>
+
+description:
+ This binding describes the MT8192 sound card.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8192_mt6359_rt1015_rt5682
+ - mediatek,mt8192_mt6359_rt1015p_rt5682
+
+ mediatek,platform:
+ $ref: "/schemas/types.yaml#/definitions/phandle"
+ description: The phandle of MT8192 ASoC platform.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - mediatek,platform
+
+examples:
+ - |
+
+ sound: mt8192-sound {
+ compatible = "mediatek,mt8192_mt6359_rt1015_rt5682";
+ mediatek,platform = <&afe>;
+ pinctrl-names = "aud_clk_mosi_off",
+ "aud_clk_mosi_on";
+ pinctrl-0 = <&aud_clk_mosi_off>;
+ pinctrl-1 = <&aud_clk_mosi_on>;
+ };
+
+...
diff --git a/dts/Bindings/sound/nau8315.txt b/dts/Bindings/sound/nau8315.txt
new file mode 100644
index 0000000000..6eaec46f38
--- /dev/null
+++ b/dts/Bindings/sound/nau8315.txt
@@ -0,0 +1,18 @@
+Nuvoton NAU8315 Mono Class-D Amplifier
+
+Required properties:
+- compatible : "nuvoton,nau8315"
+
+Optional properties:
+- enable-gpios : GPIO specifier for the chip's device enable input(EN) pin.
+ If this option is not specified then driver does not manage
+ the pin state (e.g. chip is always on).
+
+Example:
+
+#include <dt-bindings/gpio/gpio.h>
+
+nau8315 {
+ compatible = "nuvoton,nau8315";
+ enable-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+};
diff --git a/dts/Bindings/sound/nvidia,tegra30-hda.txt b/dts/Bindings/sound/nvidia,tegra30-hda.txt
deleted file mode 100644
index 21cd310963..0000000000
--- a/dts/Bindings/sound/nvidia,tegra30-hda.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-NVIDIA Tegra30 HDA controller
-
-Required properties:
-- compatible : For Tegra30, must contain "nvidia,tegra30-hda". Otherwise,
- must contain '"nvidia,<chip>-hda", "nvidia,tegra30-hda"', where <chip> is
- tegra114, tegra124, or tegra132.
-- reg : Should contain the HDA registers location and length.
-- interrupts : The interrupt from the HDA controller.
-- clocks : Must contain an entry for each required entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
-- clock-names : Must include the following entries: hda, hda2hdmi, hda2codec_2x
-- resets : Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-- reset-names : Must include the following entries: hda, hda2hdmi, hda2codec_2x
-
-Optional properties:
-- nvidia,model : The user-visible name of this sound complex. Since the property
- is optional, legacy boards can use default name provided in hda driver.
-
-Example:
-
-hda@70030000 {
- compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
- reg = <0x0 0x70030000 0x0 0x10000>;
- interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA124_CLK_HDA>,
- <&tegra_car TEGRA124_CLK_HDA2HDMI>,
- <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
- clock-names = "hda", "hda2hdmi", "hda2codec_2x";
- resets = <&tegra_car 125>, /* hda */
- <&tegra_car 128>, /* hda2hdmi */
- <&tegra_car 111>; /* hda2codec_2x */
- reset-names = "hda", "hda2hdmi", "hda2codec_2x";
- nvidia,model = "jetson-tk1-hda";
-};
diff --git a/dts/Bindings/sound/nvidia,tegra30-hda.yaml b/dts/Bindings/sound/nvidia,tegra30-hda.yaml
new file mode 100644
index 0000000000..b55775e21d
--- /dev/null
+++ b/dts/Bindings/sound/nvidia,tegra30-hda.yaml
@@ -0,0 +1,110 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/nvidia,tegra30-hda.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra HDA controller
+
+description: |
+ The High Definition Audio (HDA) block provides a serial interface to
+ audio codec. It supports multiple input and output streams.
+
+maintainers:
+ - Thierry Reding <treding@nvidia.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+ $nodename:
+ pattern: "^hda@[0-9a-f]*$"
+
+ compatible:
+ oneOf:
+ - const: nvidia,tegra30-hda
+ - items:
+ - enum:
+ - nvidia,tegra194-hda
+ - nvidia,tegra186-hda
+ - nvidia,tegra210-hda
+ - nvidia,tegra124-hda
+ - const: nvidia,tegra30-hda
+ - items:
+ - const: nvidia,tegra132-hda
+ - const: nvidia,tegra124-hda
+ - const: nvidia,tegra30-hda
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: The interrupt from the HDA controller
+ maxItems: 1
+
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: hda
+ - const: hda2hdmi
+ - const: hda2codec_2x
+
+ resets:
+ maxItems: 3
+
+ reset-names:
+ items:
+ - const: hda
+ - const: hda2hdmi
+ - const: hda2codec_2x
+
+ power-domains:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: dma-mem
+ - const: write
+
+ iommus:
+ maxItems: 1
+
+ nvidia,model:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: |
+ The user-visible name of this sound complex. If this property is
+ not specified then boards can use default name provided in hda driver.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include<dt-bindings/clock/tegra124-car-common.h>
+ #include<dt-bindings/interrupt-controller/arm-gic.h>
+
+ hda@70030000 {
+ compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
+ reg = <0x70030000 0x10000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA124_CLK_HDA>,
+ <&tegra_car TEGRA124_CLK_HDA2HDMI>,
+ <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
+ clock-names = "hda", "hda2hdmi", "hda2codec_2x";
+ resets = <&tegra_car 125>, /* hda */
+ <&tegra_car 128>, /* hda2hdmi */
+ <&tegra_car 111>; /* hda2codec_2x */
+ reset-names = "hda", "hda2hdmi", "hda2codec_2x";
+ nvidia,model = "jetson-tk1-hda";
+ };
+
+...
diff --git a/dts/Bindings/sound/qcom,lpass-va-macro.yaml b/dts/Bindings/sound/qcom,lpass-va-macro.yaml
new file mode 100644
index 0000000000..679b49cbe3
--- /dev/null
+++ b/dts/Bindings/sound/qcom,lpass-va-macro.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/qcom,lpass-va-macro.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LPASS(Low Power Audio Subsystem) VA Macro audio codec DT bindings
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+properties:
+ compatible:
+ const: qcom,sm8250-lpass-va-macro
+
+ reg:
+ maxItems: 1
+
+ "#sound-dai-cells":
+ const: 1
+
+ '#clock-cells':
+ const: 0
+
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: mclk
+ - const: core
+ - const: dcodec
+
+ clock-output-names:
+ items:
+ - const: fsgen
+
+ qcom,dmic-sample-rate:
+ description: dmic sample rate
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ vdd-micb-supply:
+ description: phandle to voltage regulator of MIC Bias
+
+required:
+ - compatible
+ - reg
+ - "#sound-dai-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/sound/qcom,q6afe.h>
+ codec@3370000 {
+ compatible = "qcom,sm8250-lpass-va-macro";
+ reg = <0x3370000 0x1000>;
+ #sound-dai-cells = <1>;
+ #clock-cells = <0>;
+ clocks = <&aoncc 0>,
+ <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "mclk", "core", "dcodec";
+ clock-output-names = "fsgen";
+ qcom,dmic-sample-rate = <600000>;
+ vdd-micb-supply = <&vreg_s4a_1p8>;
+ };
diff --git a/dts/Bindings/sound/qcom,lpass-wsa-macro.yaml b/dts/Bindings/sound/qcom,lpass-wsa-macro.yaml
new file mode 100644
index 0000000000..435b019a1e
--- /dev/null
+++ b/dts/Bindings/sound/qcom,lpass-wsa-macro.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/qcom,lpass-wsa-macro.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LPASS(Low Power Audio Subsystem) VA Macro audio codec DT bindings
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+properties:
+ compatible:
+ const: qcom,sm8250-lpass-wsa-macro
+
+ reg:
+ maxItems: 1
+
+ "#sound-dai-cells":
+ const: 1
+
+ '#clock-cells':
+ const: 0
+
+ clocks:
+ maxItems: 5
+
+ clock-names:
+ items:
+ - const: mclk
+ - const: npl
+ - const: macro
+ - const: dcodec
+ - const: fsgen
+
+ clock-output-names:
+ items:
+ - const: mclk
+
+ qcom,dmic-sample-rate:
+ description: dmic sample rate
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ vdd-micb-supply:
+ description: phandle to voltage regulator of MIC Bias
+
+required:
+ - compatible
+ - reg
+ - "#sound-dai-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/sound/qcom,q6afe.h>
+ codec@3240000 {
+ compatible = "qcom,sm8250-lpass-wsa-macro";
+ reg = <0x3240000 0x1000>;
+ #sound-dai-cells = <1>;
+ #clock-cells = <0>;
+ clocks = <&audiocc 1>,
+ <&audiocc 0>,
+ <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&vamacro>;
+ clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
+ clock-output-names = "mclk";
+ };
diff --git a/dts/Bindings/sound/qcom,sm8250.yaml b/dts/Bindings/sound/qcom,sm8250.yaml
new file mode 100644
index 0000000000..72ad9ab918
--- /dev/null
+++ b/dts/Bindings/sound/qcom,sm8250.yaml
@@ -0,0 +1,159 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/qcom,sm8250.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies Inc. SM8250 ASoC sound card driver
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description:
+ This bindings describes SC8250 SoC based sound cards
+ which uses LPASS internal codec for audio.
+
+properties:
+ compatible:
+ oneOf:
+ - const: qcom,sm8250-sndcard
+ - const: qcom,qrb5165-rb5-sndcard
+
+ audio-routing:
+ $ref: /schemas/types.yaml#/definitions/non-unique-string-array
+ description:
+ A list of the connections between audio components. Each entry is a
+ pair of strings, the first being the connection's sink, the second
+ being the connection's source. Valid names could be power supplies,
+ MicBias of codec and the jacks on the board.
+
+ model:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: User visible long sound card name
+
+patternProperties:
+ ".*-dai-link$":
+ description:
+ Each subnode represents a dai link. Subnodes of each dai links would be
+ cpu/codec dais.
+
+ type: object
+
+ properties:
+ link-name:
+ description: Indicates dai-link name and PCM stream name.
+ $ref: /schemas/types.yaml#/definitions/string
+ maxItems: 1
+
+ cpu:
+ description: Holds subnode which indicates cpu dai.
+ type: object
+ properties:
+ sound-dai: true
+
+ platform:
+ description: Holds subnode which indicates platform dai.
+ type: object
+ properties:
+ sound-dai: true
+
+ codec:
+ description: Holds subnode which indicates codec dai.
+ type: object
+ properties:
+ sound-dai: true
+
+ required:
+ - link-name
+ - cpu
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - model
+
+additionalProperties: false
+
+examples:
+
+ - |
+ #include <dt-bindings/sound/qcom,q6afe.h>
+ #include <dt-bindings/sound/qcom,q6asm.h>
+ sound {
+ compatible = "qcom,qrb5165-rb5-sndcard";
+ model = "Qualcomm-qrb5165-RB5-WSA8815-Speakers-DMIC0";
+ audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "VA DMIC0", "vdd-micb",
+ "VA DMIC1", "vdd-micb",
+ "MM_DL1", "MultiMedia1 Playback",
+ "MM_DL2", "MultiMedia2 Playback",
+ "MultiMedia3 Capture", "MM_UL3";
+
+ mm1-dai-link {
+ link-name = "MultiMedia0";
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
+ };
+ };
+
+ mm2-dai-link {
+ link-name = "MultiMedia2";
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
+ };
+ };
+
+ mm3-dai-link {
+ link-name = "MultiMedia3";
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
+ };
+ };
+
+ hdmi-dai-link {
+ link-name = "HDMI Playback";
+ cpu {
+ sound-dai = <&q6afedai TERTIARY_MI2S_RX>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&lt9611_codec 0>;
+ };
+ };
+
+ wsa-dai-link {
+ link-name = "WSA Playback";
+ cpu {
+ sound-dai = <&q6afedai WSA_CODEC_DMA_RX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&wsamacro>;
+ };
+ };
+
+ va-dai-link {
+ link-name = "VA Capture";
+ cpu {
+ sound-dai = <&q6afedai VA_CODEC_DMA_TX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&vamacro 0>;
+ };
+ };
+ };
diff --git a/dts/Bindings/sound/renesas,rsnd.txt b/dts/Bindings/sound/renesas,rsnd.txt
index b39743d3f7..b731f16aea 100644
--- a/dts/Bindings/sound/renesas,rsnd.txt
+++ b/dts/Bindings/sound/renesas,rsnd.txt
@@ -253,523 +253,3 @@ This is example of TDM 6ch.
Driver can automatically switches TDM <-> stereo mode in this case.
see "Example: simple sound card for TDM"
-
-=============================================
-Required properties:
-=============================================
-
-- compatible : "renesas,rcar_sound-<soctype>", fallbacks
- "renesas,rcar_sound-gen1" if generation1, and
- "renesas,rcar_sound-gen2" if generation2 (or RZ/G1)
- "renesas,rcar_sound-gen3" if generation3 (or RZ/G2)
- Examples with soctypes are:
- - "renesas,rcar_sound-r8a7742" (RZ/G1H)
- - "renesas,rcar_sound-r8a7743" (RZ/G1M)
- - "renesas,rcar_sound-r8a7744" (RZ/G1N)
- - "renesas,rcar_sound-r8a7745" (RZ/G1E)
- - "renesas,rcar_sound-r8a77470" (RZ/G1C)
- - "renesas,rcar_sound-r8a774a1" (RZ/G2M)
- - "renesas,rcar_sound-r8a774b1" (RZ/G2N)
- - "renesas,rcar_sound-r8a774c0" (RZ/G2E)
- - "renesas,rcar_sound-r8a774e1" (RZ/G2H)
- - "renesas,rcar_sound-r8a7778" (R-Car M1A)
- - "renesas,rcar_sound-r8a7779" (R-Car H1)
- - "renesas,rcar_sound-r8a7790" (R-Car H2)
- - "renesas,rcar_sound-r8a7791" (R-Car M2-W)
- - "renesas,rcar_sound-r8a7793" (R-Car M2-N)
- - "renesas,rcar_sound-r8a7794" (R-Car E2)
- - "renesas,rcar_sound-r8a7795" (R-Car H3)
- - "renesas,rcar_sound-r8a7796" (R-Car M3-W)
- - "renesas,rcar_sound-r8a77965" (R-Car M3-N)
- - "renesas,rcar_sound-r8a77990" (R-Car E3)
- - "renesas,rcar_sound-r8a77995" (R-Car D3)
-- reg : Should contain the register physical address.
- required register is
- SRU/ADG/SSI if generation1
- SRU/ADG/SSIU/SSI/AUDIO-DMAC-periperi if generation2/generation3
- Select extended AUDIO-DMAC-periperi address if SoC has it,
- otherwise select normal AUDIO-DMAC-periperi address.
-- reg-names : Should contain the register names.
- scu/adg/ssi if generation1
- scu/adg/ssiu/ssi/audmapp if generation2/generation3
-- rcar_sound,ssi : Should contain SSI feature.
- The number of SSI subnode should be same as HW.
- see below for detail.
-- rcar_sound,ssiu : Should contain SSIU feature.
- The number of SSIU subnode should be same as HW.
- see below for detail.
-- rcar_sound,src : Should contain SRC feature.
- The number of SRC subnode should be same as HW.
- see below for detail.
-- rcar_sound,ctu : Should contain CTU feature.
- The number of CTU subnode should be same as HW.
- see below for detail.
-- rcar_sound,mix : Should contain MIX feature.
- The number of MIX subnode should be same as HW.
- see below for detail.
-- rcar_sound,dvc : Should contain DVC feature.
- The number of DVC subnode should be same as HW.
- see below for detail.
-- rcar_sound,dai : DAI contents.
- The number of DAI subnode should be same as HW.
- see below for detail.
-- #sound-dai-cells : it must be 0 if your system is using single DAI
- it must be 1 if your system is using multi DAI
-- clocks : References to SSI/SRC/MIX/CTU/DVC/AUDIO_CLK clocks.
-- clock-names : List of necessary clock names.
- "ssi-all", "ssi.X", "src.X", "mix.X", "ctu.X",
- "dvc.X", "clk_a", "clk_b", "clk_c", "clk_i"
-
-Optional properties:
-- #clock-cells : it must be 0 if your system has audio_clkout
- it must be 1 if your system has audio_clkout0/1/2/3
-- clock-frequency : for all audio_clkout0/1/2/3
-- clkout-lr-asynchronous : boolean property. it indicates that audio_clkoutn
- is asynchronizes with lr-clock.
-- resets : References to SSI resets.
-- reset-names : List of valid reset names.
- "ssi-all", "ssi.X"
-
-SSI subnode properties:
-- interrupts : Should contain SSI interrupt for PIO transfer
-- shared-pin : if shared clock pin
-- pio-transfer : use PIO transfer mode
-- no-busif : BUSIF is not ussed when [mem -> SSI] via DMA case
-- dma : Should contain Audio DMAC entry
-- dma-names : SSI case "rx" (=playback), "tx" (=capture)
- Deprecated: see SSIU subnode properties
- SSIU case "rxu" (=playback), "txu" (=capture)
-
-SSIU subnode properties:
-- dma : Should contain Audio DMAC entry
-- dma-names : "rx" (=playback), "tx" (=capture)
-
-SRC subnode properties:
-- dma : Should contain Audio DMAC entry
-- dma-names : "rx" (=playback), "tx" (=capture)
-
-DVC subnode properties:
-- dma : Should contain Audio DMAC entry
-- dma-names : "tx" (=playback/capture)
-
-DAI subnode properties:
-- playback : list of playback modules
-- capture : list of capture modules
-
-
-=============================================
-Example:
-=============================================
-
-rcar_sound: sound@ec500000 {
- #sound-dai-cells = <1>;
- compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2";
- reg = <0 0xec500000 0 0x1000>, /* SCU */
- <0 0xec5a0000 0 0x100>, /* ADG */
- <0 0xec540000 0 0x1000>, /* SSIU */
- <0 0xec541000 0 0x1280>, /* SSI */
- <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
- reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
-
- clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
- <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
- <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
- <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
- <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
- <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
- <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
- <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
- <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
- <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
- <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
- <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
- <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
- clock-names = "ssi-all",
- "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
- "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
- "src.9", "src.8", "src.7", "src.6", "src.5",
- "src.4", "src.3", "src.2", "src.1", "src.0",
- "dvc.0", "dvc.1",
- "clk_a", "clk_b", "clk_c", "clk_i";
-
- rcar_sound,dvc {
- dvc0: dvc-0 {
- dmas = <&audma0 0xbc>;
- dma-names = "tx";
- };
- dvc1: dvc-1 {
- dmas = <&audma0 0xbe>;
- dma-names = "tx";
- };
- };
-
- rcar_sound,mix {
- mix0: mix-0 { };
- mix1: mix-1 { };
- };
-
- rcar_sound,ctu {
- ctu00: ctu-0 { };
- ctu01: ctu-1 { };
- ctu02: ctu-2 { };
- ctu03: ctu-3 { };
- ctu10: ctu-4 { };
- ctu11: ctu-5 { };
- ctu12: ctu-6 { };
- ctu13: ctu-7 { };
- };
-
- rcar_sound,src {
- src0: src-0 {
- interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x85>, <&audma1 0x9a>;
- dma-names = "rx", "tx";
- };
- src1: src-1 {
- interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x87>, <&audma1 0x9c>;
- dma-names = "rx", "tx";
- };
- src2: src-2 {
- interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x89>, <&audma1 0x9e>;
- dma-names = "rx", "tx";
- };
- src3: src-3 {
- interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8b>, <&audma1 0xa0>;
- dma-names = "rx", "tx";
- };
- src4: src-4 {
- interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8d>, <&audma1 0xb0>;
- dma-names = "rx", "tx";
- };
- src5: src-5 {
- interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x8f>, <&audma1 0xb2>;
- dma-names = "rx", "tx";
- };
- src6: src-6 {
- interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x91>, <&audma1 0xb4>;
- dma-names = "rx", "tx";
- };
- src7: src-7 {
- interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x93>, <&audma1 0xb6>;
- dma-names = "rx", "tx";
- };
- src8: src-8 {
- interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x95>, <&audma1 0xb8>;
- dma-names = "rx", "tx";
- };
- src9: src-9 {
- interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x97>, <&audma1 0xba>;
- dma-names = "rx", "tx";
- };
- };
-
- rcar_sound,ssiu {
- ssiu00: ssiu-0 {
- dmas = <&audma0 0x15>, <&audma1 0x16>;
- dma-names = "rx", "tx";
- };
- ssiu01: ssiu-1 {
- dmas = <&audma0 0x35>, <&audma1 0x36>;
- dma-names = "rx", "tx";
- };
-
- ...
-
- ssiu95: ssiu-49 {
- dmas = <&audma0 0xA5>, <&audma1 0xA6>;
- dma-names = "rx", "tx";
- };
- ssiu96: ssiu-50 {
- dmas = <&audma0 0xA7>, <&audma1 0xA8>;
- dma-names = "rx", "tx";
- };
- ssiu97: ssiu-51 {
- dmas = <&audma0 0xA9>, <&audma1 0xAA>;
- dma-names = "rx", "tx";
- };
- };
-
- rcar_sound,ssi {
- ssi0: ssi-0 {
- interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x01>, <&audma1 0x02>;
- dma-names = "rx", "tx";
- };
- ssi1: ssi-1 {
- interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x03>, <&audma1 0x04>;
- dma-names = "rx", "tx";
- };
-
- ...
-
- ssi8: ssi-8 {
- interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x11>, <&audma1 0x12>;
- dma-names = "rx", "tx";
- };
- ssi9: ssi-9 {
- interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x13>, <&audma1 0x14>;
- dma-names = "rx", "tx";
- };
- };
-
- rcar_sound,dai {
- dai0 {
- playback = <&ssi5 &src5>;
- capture = <&ssi6>;
- };
- dai1 {
- playback = <&ssi3>;
- };
- dai2 {
- capture = <&ssi4>;
- };
- dai3 {
- playback = <&ssi7>;
- };
- dai4 {
- capture = <&ssi8>;
- };
- };
-};
-
-=============================================
-Example: simple sound card
-=============================================
-
- rsnd_ak4643: sound {
- compatible = "simple-audio-card";
-
- simple-audio-card,format = "left_j";
- simple-audio-card,bitclock-master = <&sndcodec>;
- simple-audio-card,frame-master = <&sndcodec>;
-
- sndcpu: simple-audio-card,cpu {
- sound-dai = <&rcar_sound>;
- };
-
- sndcodec: simple-audio-card,codec {
- sound-dai = <&ak4643>;
- clocks = <&audio_clock>;
- };
- };
-
-&rcar_sound {
- pinctrl-0 = <&sound_pins &sound_clk_pins>;
- pinctrl-names = "default";
-
- /* Single DAI */
- #sound-dai-cells = <0>;
-
-
- rcar_sound,dai {
- dai0 {
- playback = <&ssi0 &src2 &dvc0>;
- capture = <&ssi1 &src3 &dvc1>;
- };
- };
-};
-
-&ssi1 {
- shared-pin;
-};
-
-=============================================
-Example: simple sound card for Asynchronous mode
-=============================================
-
-sound {
- compatible = "simple-scu-audio-card";
- ...
- /*
- * SRC Asynchronous mode setting
- * Playback:
- * All input data will be converted to 48kHz
- * Capture:
- * Inputed 48kHz data will be converted to
- * system specified Hz
- */
- simple-audio-card,convert-rate = <48000>;
- ...
- simple-audio-card,cpu {
- sound-dai = <&rcar_sound>;
- };
- simple-audio-card,codec {
- ...
- };
-};
-
-=============================================
-Example: simple sound card for channel convert
-=============================================
-
-sound {
- compatible = "simple-scu-audio-card";
- ...
- /*
- * CTU setting
- * All input data will be converted to 2ch
- * as output data
- */
- simple-audio-card,convert-channels = <2>;
- ...
- simple-audio-card,cpu {
- sound-dai = <&rcar_sound>;
- };
- simple-audio-card,codec {
- ...
- };
-};
-
-=============================================
-Example: simple sound card for MIXer
-=============================================
-
-sound {
- compatible = "simple-scu-audio-card";
- ...
- simple-audio-card,cpu@0 {
- sound-dai = <&rcar_sound 0>;
- };
- simple-audio-card,cpu@1 {
- sound-dai = <&rcar_sound 1>;
- };
- simple-audio-card,codec {
- ...
- };
-};
-
-&rcar_sound {
- ...
- rcar_sound,dai {
- dai0 {
- playback = <&src1 &ctu02 &mix0 &dvc0 &ssi0>;
- };
- dai1 {
- playback = <&src2 &ctu03 &mix0 &dvc0 &ssi0>;
- };
- };
-};
-
-=============================================
-Example: simple sound card for TDM
-=============================================
-
-rsnd_tdm: sound {
- compatible = "simple-audio-card";
-
- simple-audio-card,format = "left_j";
- simple-audio-card,bitclock-master = <&sndcodec>;
- simple-audio-card,frame-master = <&sndcodec>;
-
- sndcpu: simple-audio-card,cpu {
- sound-dai = <&rcar_sound>;
- dai-tdm-slot-num = <6>;
- };
-
- sndcodec: simple-audio-card,codec {
- sound-dai = <&xxx>;
- };
-};
-
-=============================================
-Example: simple sound card for TDM Split
-=============================================
-
-sound_card: sound {
- compatible = "audio-graph-scu-card";
- prefix = "xxxx";
- routing = "xxxx Playback", "DAI0 Playback",
- "xxxx Playback", "DAI1 Playback",
- "xxxx Playback", "DAI2 Playback",
- "xxxx Playback", "DAI3 Playback";
- convert-channels = <8>; /* TDM Split */
-
- dais = <&rsnd_port0 /* playback ch1/ch2 */
- &rsnd_port1 /* playback ch3/ch4 */
- &rsnd_port2 /* playback ch5/ch6 */
- &rsnd_port3 /* playback ch7/ch8 */
- >;
-};
-
-audio-codec {
- ...
- port {
- codec_0: endpoint@1 {
- remote-endpoint = <&rsnd_ep0>;
- };
- codec_1: endpoint@2 {
- remote-endpoint = <&rsnd_ep1>;
- };
- codec_2: endpoint@3 {
- remote-endpoint = <&rsnd_ep2>;
- };
- codec_3: endpoint@4 {
- remote-endpoint = <&rsnd_ep3>;
- };
- };
-};
-
-&rcar_sound {
- ...
- ports {
- rsnd_port0: port@0 {
- rsnd_ep0: endpoint {
- remote-endpoint = <&codec_0>;
- ...
- playback = <&ssiu30 &ssi3>;
- };
- };
- rsnd_port1: port@1 {
- rsnd_ep1: endpoint {
- remote-endpoint = <&codec_1>;
- ...
- playback = <&ssiu31 &ssi3>;
- };
- };
- rsnd_port2: port@2 {
- rsnd_ep2: endpoint {
- remote-endpoint = <&codec_2>;
- ...
- playback = <&ssiu32 &ssi3>;
- };
- };
- rsnd_port3: port@3 {
- rsnd_ep3: endpoint {
- remote-endpoint = <&codec_3>;
- ...
- playback = <&ssiu33 &ssi3>;
- };
- };
- };
-};
-
-=============================================
-Example: simple sound card for Multi channel
-=============================================
-
-&rcar_sound {
- pinctrl-0 = <&sound_pins &sound_clk_pins>;
- pinctrl-names = "default";
-
- /* Single DAI */
- #sound-dai-cells = <0>;
-
-
- rcar_sound,dai {
- dai0 {
- playback = <&ssi0 &ssi1 &ssi2 &src0 &dvc0>;
- };
- };
-};
diff --git a/dts/Bindings/sound/renesas,rsnd.yaml b/dts/Bindings/sound/renesas,rsnd.yaml
new file mode 100644
index 0000000000..0fd37aa849
--- /dev/null
+++ b/dts/Bindings/sound/renesas,rsnd.yaml
@@ -0,0 +1,447 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/renesas,rsnd.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car Sound Driver Device Tree Bindings
+
+maintainers:
+ - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+
+properties:
+
+ compatible:
+ oneOf:
+ # for Gen1 SoC
+ - items:
+ - enum:
+ - renesas,rcar_sound-r8a7778 # R-Car M1A
+ - renesas,rcar_sound-r8a7779 # R-Car H1
+ - enum:
+ - renesas,rcar_sound-gen1
+ # for Gen2 SoC
+ - items:
+ - enum:
+ - renesas,rcar_sound-r8a7742 # RZ/G1H
+ - renesas,rcar_sound-r8a7743 # RZ/G1M
+ - renesas,rcar_sound-r8a7744 # RZ/G1N
+ - renesas,rcar_sound-r8a7745 # RZ/G1E
+ - renesas,rcar_sound-r8a77470 # RZ/G1C
+ - renesas,rcar_sound-r8a7790 # R-Car H2
+ - renesas,rcar_sound-r8a7791 # R-Car M2-W
+ - renesas,rcar_sound-r8a7793 # R-Car M2-N
+ - renesas,rcar_sound-r8a7794 # R-Car E2
+ - enum:
+ - renesas,rcar_sound-gen2
+ # for Gen3 SoC
+ - items:
+ - enum:
+ - renesas,rcar_sound-r8a774a1 # RZ/G2M
+ - renesas,rcar_sound-r8a774b1 # RZ/G2N
+ - renesas,rcar_sound-r8a774c0 # RZ/G2E
+ - renesas,rcar_sound-r8a774e1 # RZ/G2H
+ - renesas,rcar_sound-r8a7795 # R-Car H3
+ - renesas,rcar_sound-r8a7796 # R-Car M3-W
+ - renesas,rcar_sound-r8a77961 # R-Car M3-W+
+ - renesas,rcar_sound-r8a77965 # R-Car M3-N
+ - renesas,rcar_sound-r8a77990 # R-Car E3
+ - renesas,rcar_sound-r8a77995 # R-Car D3
+ - enum:
+ - renesas,rcar_sound-gen3
+ # for Generic
+ - items:
+ - enum:
+ - renesas,rcar_sound-gen1
+ - renesas,rcar_sound-gen2
+ - renesas,rcar_sound-gen3
+
+ reg:
+ minItems: 1
+ maxItems: 5
+
+ reg-names:
+ minItems: 1
+ maxItems: 5
+
+ "#sound-dai-cells":
+ description: |
+ it must be 0 if your system is using single DAI
+ it must be 1 if your system is using multi DAIs
+ enum: [0, 1]
+
+ "#clock-cells":
+ description: |
+ it must be 0 if your system has audio_clkout
+ it must be 1 if your system has audio_clkout0/1/2/3
+ enum: [0, 1]
+
+ clock-frequency:
+ description: for audio_clkout0/1/2/3
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+ clkout-lr-asynchronous:
+ description: audio_clkoutn is asynchronizes with lr-clock.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ power-domains: true
+
+ resets:
+ maxItems: 11
+
+ reset-names:
+ maxItems: 11
+
+ clocks:
+ description: References to SSI/SRC/MIX/CTU/DVC/AUDIO_CLK clocks.
+ minItems: 1
+ maxItems: 31
+
+ clock-names:
+ description: List of necessary clock names.
+ minItems: 1
+ maxItems: 31
+ items:
+ oneOf:
+ - const: ssi-all
+ - pattern: '^ssi\.[0-9]$'
+ - pattern: '^src\.[0-9]$'
+ - pattern: '^mix\.[0-1]$'
+ - pattern: '^ctu\.[0-1]$'
+ - pattern: '^dvc\.[0-1]$'
+ - pattern: '^clk_(a|b|c|i)$'
+
+ port: true
+
+# use patternProperties to avoid naming "xxx,yyy" issue
+patternProperties:
+ "^rcar_sound,dvc$":
+ description: DVC subnode.
+ type: object
+ patternProperties:
+ "^dvc-[0-1]$":
+ type: object
+ properties:
+ dmas:
+ maxItems: 1
+ dma-names:
+ const: "tx"
+ required:
+ - dmas
+ - dma-names
+ additionalProperties: false
+
+ "^rcar_sound,mix$":
+ description: MIX subnode.
+ type: object
+ patternProperties:
+ "^mix-[0-1]$":
+ type: object
+ # no properties
+ additionalProperties: false
+
+ "^rcar_sound,ctu$":
+ description: CTU subnode.
+ type: object
+ patternProperties:
+ "^ctu-[0-7]$":
+ type: object
+ # no properties
+ additionalProperties: false
+
+ "^rcar_sound,src$":
+ description: SRC subnode.
+ type: object
+ patternProperties:
+ "^src-[0-9]$":
+ type: object
+ properties:
+ interrupts:
+ maxItems: 1
+ dmas:
+ maxItems: 2
+ dma-names:
+ allOf:
+ - items:
+ enum:
+ - tx
+ - rx
+ required:
+ - interrupts
+ - dmas
+ - dma-names
+ additionalProperties: false
+
+ "^rcar_sound,ssiu$":
+ description: SSIU subnode.
+ type: object
+ patternProperties:
+ "^ssiu-[0-9]+$":
+ type: object
+ properties:
+ dmas:
+ maxItems: 2
+ dma-names:
+ allOf:
+ - items:
+ enum:
+ - tx
+ - rx
+ required:
+ - dmas
+ - dma-names
+ additionalProperties: false
+
+ "^rcar_sound,ssi$":
+ description: SSI subnode.
+ type: object
+ patternProperties:
+ "^ssi-[0-9]$":
+ type: object
+ properties:
+ interrupts:
+ maxItems: 1
+ dmas:
+ minItems: 2
+ maxItems: 4
+ dma-names:
+ allOf:
+ - items:
+ enum:
+ - tx
+ - rx
+ - txu # if no ssiu node
+ - rxu # if no ssiu node
+
+ shared-pin:
+ description: shared clock pin
+ $ref: /schemas/types.yaml#/definitions/flag
+ pio-transfer:
+ description: PIO transfer mode
+ $ref: /schemas/types.yaml#/definitions/flag
+ no-busif:
+ description: BUSIF is not used when [mem -> SSI] via DMA case
+ $ref: /schemas/types.yaml#/definitions/flag
+ required:
+ - interrupts
+ - dmas
+ - dma-names
+ additionalProperties: false
+
+ # For DAI base
+ "^rcar_sound,dai$":
+ description: DAI subnode.
+ type: object
+ patternProperties:
+ "^dai([0-9]+)?$":
+ type: object
+ properties:
+ playback:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ capture:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ anyOf:
+ - required:
+ - playback
+ - required:
+ - capture
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - "#sound-dai-cells"
+
+allOf:
+ - $ref: audio-graph.yaml#
+ - $ref: audio-graph-port.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,rcar_sound-gen1
+ then:
+ properties:
+ reg:
+ maxItems: 3
+ reg-names:
+ maxItems: 3
+ items:
+ enum:
+ - scu
+ - ssi
+ - adg
+ else:
+ properties:
+ reg:
+ maxItems: 5
+ reg-names:
+ maxItems: 5
+ items:
+ enum:
+ - scu
+ - adg
+ - ssiu
+ - ssi
+ - audmapp
+
+additionalProperties: false
+
+examples:
+ - |
+ rcar_sound: sound@ec500000 {
+ #sound-dai-cells = <1>;
+ compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
+ reg = <0xec500000 0x1000>, /* SCU */
+ <0xec5a0000 0x100>, /* ADG */
+ <0xec540000 0x1000>, /* SSIU */
+ <0xec541000 0x1280>, /* SSI */
+ <0xec740000 0x200>; /* Audio DMAC peri peri*/
+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+ clocks = <&mstp10_clks 1005>, /* SSI-ALL */
+ <&mstp10_clks 1006>, <&mstp10_clks 1007>, /* SSI9, SSI8 */
+ <&mstp10_clks 1008>, <&mstp10_clks 1009>, /* SSI7, SSI6 */
+ <&mstp10_clks 1010>, <&mstp10_clks 1011>, /* SSI5, SSI4 */
+ <&mstp10_clks 1012>, <&mstp10_clks 1013>, /* SSI3, SSI2 */
+ <&mstp10_clks 1014>, <&mstp10_clks 1015>, /* SSI1, SSI0 */
+ <&mstp10_clks 1022>, <&mstp10_clks 1023>, /* SRC9, SRC8 */
+ <&mstp10_clks 1024>, <&mstp10_clks 1025>, /* SRC7, SRC6 */
+ <&mstp10_clks 1026>, <&mstp10_clks 1027>, /* SRC5, SRC4 */
+ <&mstp10_clks 1028>, <&mstp10_clks 1029>, /* SRC3, SRC2 */
+ <&mstp10_clks 1030>, <&mstp10_clks 1031>, /* SRC1, SRC0 */
+ <&mstp10_clks 1020>, <&mstp10_clks 1021>, /* MIX1, MIX0 */
+ <&mstp10_clks 1020>, <&mstp10_clks 1021>, /* CTU1, CTU0 */
+ <&mstp10_clks 1019>, <&mstp10_clks 1018>, /* DVC0, DVC1 */
+ <&audio_clk_a>, <&audio_clk_b>, /* CLKA, CLKB */
+ <&audio_clk_c>, <&audio_clk_i>; /* CLKC, CLKI */
+
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8",
+ "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4",
+ "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "src.9", "src.8",
+ "src.7", "src.6",
+ "src.5", "src.4",
+ "src.3", "src.2",
+ "src.1", "src.0",
+ "mix.1", "mix.0",
+ "ctu.1", "ctu.0",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b",
+ "clk_c", "clk_i";
+
+ rcar_sound,dvc {
+ dvc0: dvc-0 {
+ dmas = <&audma0 0xbc>;
+ dma-names = "tx";
+ };
+ dvc1: dvc-1 {
+ dmas = <&audma0 0xbe>;
+ dma-names = "tx";
+ };
+ };
+
+ rcar_sound,mix {
+ mix0: mix-0 { };
+ mix1: mix-1 { };
+ };
+
+ rcar_sound,ctu {
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
+ };
+
+ rcar_sound,src {
+ src0: src-0 {
+ status = "disabled";
+ };
+ src1: src-1 {
+ interrupts = <0 353 0>;
+ dmas = <&audma0 0x87>, <&audma1 0x9c>;
+ dma-names = "rx", "tx";
+ };
+ /* skip after src-2 */
+ };
+
+ rcar_sound,ssiu {
+ ssiu00: ssiu-0 {
+ dmas = <&audma0 0x15>, <&audma1 0x16>;
+ dma-names = "rx", "tx";
+ };
+ ssiu01: ssiu-1 {
+ dmas = <&audma0 0x35>, <&audma1 0x36>;
+ dma-names = "rx", "tx";
+ };
+ /* skip after ssiu-2 */
+ };
+
+ rcar_sound,ssi {
+ ssi0: ssi-0 {
+ interrupts = <0 370 1>;
+ dmas = <&audma0 0x01>, <&audma1 0x02>;
+ dma-names = "rx", "tx";
+ };
+ ssi1: ssi-1 {
+ interrupts = <0 371 1>;
+ dmas = <&audma0 0x03>, <&audma1 0x04>;
+ dma-names = "rx", "tx";
+ };
+ /* skip other ssi-2 */
+ };
+
+ /* DAI base */
+ rcar_sound,dai {
+ dai0 {
+ playback = <&ssi5 &src5>;
+ capture = <&ssi6>;
+ };
+ dai1 {
+ playback = <&ssi3>;
+ };
+ dai2 {
+ capture = <&ssi4>;
+ };
+ dai3 {
+ playback = <&ssi7>;
+ };
+ dai4 {
+ capture = <&ssi8>;
+ };
+ };
+
+ /* assume audio-graph */
+ port {
+ rsnd_endpoint: endpoint {
+ remote-endpoint = <&codec_endpoint>;
+
+ dai-format = "left_j";
+ bitclock-master = <&rsnd_endpoint0>;
+ frame-master = <&rsnd_endpoint0>;
+
+ playback = <&ssi0 &src0 &dvc0>;
+ capture = <&ssi1 &src1 &dvc1>;
+ };
+ };
+ };
+
+
+ /* assume audio-graph */
+ codec {
+ port {
+ codec_endpoint: endpoint {
+ remote-endpoint = <&rsnd_endpoint>;
+ };
+ };
+ };
diff --git a/dts/Bindings/sound/rt5682.txt b/dts/Bindings/sound/rt5682.txt
index 707fa98d13..9c5fadb6ac 100644
--- a/dts/Bindings/sound/rt5682.txt
+++ b/dts/Bindings/sound/rt5682.txt
@@ -44,6 +44,8 @@ Optional properties:
- realtek,dmic-delay-ms : Set the delay time (ms) for the requirement of
the particular DMIC.
+- realtek,dmic-clk-driving-high : Set the high drving of the DMIC clock out.
+
Pins on the device (for linking into audio routes) for RT5682:
* DMIC L1
diff --git a/dts/Bindings/sound/simple-audio-mux.yaml b/dts/Bindings/sound/simple-audio-mux.yaml
new file mode 100644
index 0000000000..5986d1fcbb
--- /dev/null
+++ b/dts/Bindings/sound/simple-audio-mux.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/simple-audio-mux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Simple Audio Multiplexer
+
+maintainers:
+ - Alexandre Belloni <aleandre.belloni@bootlin.com>
+
+description: |
+ Simple audio multiplexers are driven using gpios, allowing to select which of
+ their input line is connected to the output line.
+
+properties:
+ compatible:
+ const: simple-audio-mux
+
+ mux-gpios:
+ description: |
+ GPIOs used to select the input line.
+
+ sound-name-prefix:
+ $ref: /schemas/types.yaml#/definitions/string
+ description:
+ Used as prefix for sink/source names of the component. Must be a
+ unique string among multiple instances of the same component.
+
+required:
+ - compatible
+ - mux-gpios
+
+additionalProperties: false
+
+examples:
+ - |
+ mux {
+ compatible = "simple-audio-mux";
+ mux-gpios = <&gpio 3 0>;
+ };
diff --git a/dts/Bindings/sound/simple-card.yaml b/dts/Bindings/sound/simple-card.yaml
index 35e6690202..45fd9fd9eb 100644
--- a/dts/Bindings/sound/simple-card.yaml
+++ b/dts/Bindings/sound/simple-card.yaml
@@ -13,13 +13,11 @@ definitions:
frame-master:
description: Indicates dai-link frame master.
- $ref: /schemas/types.yaml#/definitions/phandle-array
- maxItems: 1
+ $ref: /schemas/types.yaml#/definitions/phandle
bitclock-master:
description: Indicates dai-link bit clock master
- $ref: /schemas/types.yaml#/definitions/phandle-array
- maxItems: 1
+ $ref: /schemas/types.yaml#/definitions/phandle
frame-inversion:
description: dai-link uses frame clock inversion
diff --git a/dts/Bindings/sound/st,stm32-adfsdm.txt b/dts/Bindings/sound/st,stm32-adfsdm.txt
deleted file mode 100644
index 864f5b00b0..0000000000
--- a/dts/Bindings/sound/st,stm32-adfsdm.txt
+++ /dev/null
@@ -1,63 +0,0 @@
-STMicroelectronics Audio Digital Filter Sigma Delta modulators(DFSDM)
-
-The DFSDM allows PDM microphones capture through SPI interface. The Audio
-interface is seems as a sub block of the DFSDM device.
-For details on DFSDM bindings refer to ../iio/adc/st,stm32-dfsdm-adc.txt
-
-Required properties:
- - compatible: "st,stm32h7-dfsdm-dai".
-
- - #sound-dai-cells : Must be equal to 0
-
- - io-channels : phandle to iio dfsdm instance node.
-
-Example of a sound card using audio DFSDM node.
-
- sound_card {
- compatible = "audio-graph-card";
-
- dais = <&cpu_port>;
- };
-
- dfsdm: dfsdm@40017000 {
- compatible = "st,stm32h7-dfsdm";
- reg = <0x40017000 0x400>;
- clocks = <&rcc DFSDM1_CK>;
- clock-names = "dfsdm";
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- dfsdm_adc0: filter@0 {
- compatible = "st,stm32-dfsdm-dmic";
- reg = <0>;
- interrupts = <110>;
- dmas = <&dmamux1 101 0x400 0x00>;
- dma-names = "rx";
- st,adc-channels = <1>;
- st,adc-channel-names = "dmic0";
- st,adc-channel-types = "SPI_R";
- st,adc-channel-clk-src = "CLKOUT";
- st,filter-order = <5>;
-
- dfsdm_dai0: dfsdm-dai {
- compatible = "st,stm32h7-dfsdm-dai";
- #sound-dai-cells = <0>;
- io-channels = <&dfsdm_adc0 0>;
- cpu_port: port {
- dfsdm_endpoint: endpoint {
- remote-endpoint = <&dmic0_endpoint>;
- };
- };
- };
- };
-
- dmic0: dmic@0 {
- compatible = "dmic-codec";
- #sound-dai-cells = <0>;
- port {
- dmic0_endpoint: endpoint {
- remote-endpoint = <&dfsdm_endpoint>;
- };
- };
- };
diff --git a/dts/Bindings/sound/st,stm32-sai.txt b/dts/Bindings/sound/st,stm32-sai.txt
deleted file mode 100644
index c42b91e525..0000000000
--- a/dts/Bindings/sound/st,stm32-sai.txt
+++ /dev/null
@@ -1,107 +0,0 @@
-STMicroelectronics STM32 Serial Audio Interface (SAI).
-
-The SAI interface (Serial Audio Interface) offers a wide set of audio protocols
-as I2S standards, LSB or MSB-justified, PCM/DSP, TDM, and AC'97.
-The SAI contains two independent audio sub-blocks. Each sub-block has
-its own clock generator and I/O lines controller.
-
-Required properties:
- - compatible: Should be "st,stm32f4-sai" or "st,stm32h7-sai"
- - reg: Base address and size of SAI common register set.
- - clocks: Must contain phandle and clock specifier pairs for each entry
- in clock-names.
- - clock-names: Must contain "pclk" "x8k" and "x11k"
- "pclk": Clock which feeds the peripheral bus interface.
- Mandatory for "st,stm32h7-sai" compatible.
- Not used for "st,stm32f4-sai" compatible.
- "x8k": SAI parent clock for sampling rates multiple of 8kHz.
- "x11k": SAI parent clock for sampling rates multiple of 11.025kHz.
- - interrupts: cpu DAI interrupt line shared by SAI sub-blocks
-
-Optional properties:
- - resets: Reference to a reset controller asserting the SAI
-
-SAI subnodes:
-Two subnodes corresponding to SAI sub-block instances A et B can be defined.
-Subnode can be omitted for unsused sub-block.
-
-SAI subnodes required properties:
- - compatible: Should be "st,stm32-sai-sub-a" or "st,stm32-sai-sub-b"
- for SAI sub-block A or B respectively.
- - reg: Base address and size of SAI sub-block register set.
- - clocks: Must contain one phandle and clock specifier pair
- for sai_ck which feeds the internal clock generator.
- If the SAI shares a master clock, with another SAI set as MCLK
- clock provider, SAI provider phandle must be specified here.
- - clock-names: Must contain "sai_ck".
- Must also contain "MCLK", if SAI shares a master clock,
- with a SAI set as MCLK clock provider.
- - dmas: see Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
- - dma-names: identifier string for each DMA request line
- "tx": if sai sub-block is configured as playback DAI
- "rx": if sai sub-block is configured as capture DAI
- - pinctrl-names: should contain only value "default"
- - pinctrl-0: see Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
-
-SAI subnodes Optional properties:
- - st,sync: specify synchronization mode.
- By default SAI sub-block is in asynchronous mode.
- This property sets SAI sub-block as slave of another SAI sub-block.
- Must contain the phandle and index of the sai sub-block providing
- the synchronization.
- - st,iec60958: support S/PDIF IEC6958 protocol for playback
- IEC60958 protocol is not available for capture.
- By default, custom protocol is assumed, meaning that protocol is
- configured according to protocol defined in related DAI link node,
- such as i2s, left justified, right justified, dsp and pdm protocols.
- Note: ac97 protocol is not supported by SAI driver
- - #clock-cells: should be 0. This property must be present if the SAI device
- is a master clock provider, according to clocks bindings, described in
- Documentation/devicetree/bindings/clock/clock-bindings.txt.
-
-The device node should contain one 'port' child node with one child 'endpoint'
-node, according to the bindings defined in Documentation/devicetree/bindings/
-graph.txt.
-
-Example:
-sound_card {
- compatible = "audio-graph-card";
- dais = <&sai1b_port>;
-};
-
-sai1: sai1@40015800 {
- compatible = "st,stm32h7-sai";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x40015800 0x400>;
- reg = <0x40015800 0x4>;
- clocks = <&rcc SAI1_CK>, <&rcc PLL1_Q>, <&rcc PLL2_P>;
- clock-names = "pclk", "x8k", "x11k";
- interrupts = <87>;
-
- sai1a: audio-controller@40015804 {
- compatible = "st,stm32-sai-sub-a";
- reg = <0x4 0x1C>;
- clocks = <&rcc SAI1_CK>;
- clock-names = "sai_ck";
- dmas = <&dmamux1 1 87 0x400 0x0>;
- dma-names = "tx";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sai1a>;
-
- sai1b_port: port {
- cpu_endpoint: endpoint {
- remote-endpoint = <&codec_endpoint>;
- format = "i2s";
- };
- };
- };
-};
-
-audio-codec {
- codec_port: port {
- codec_endpoint: endpoint {
- remote-endpoint = <&cpu_endpoint>;
- };
- };
-};
diff --git a/dts/Bindings/sound/st,stm32-sai.yaml b/dts/Bindings/sound/st,stm32-sai.yaml
new file mode 100644
index 0000000000..f2443b6512
--- /dev/null
+++ b/dts/Bindings/sound/st,stm32-sai.yaml
@@ -0,0 +1,200 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/st,stm32-sai.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 Serial Audio Interface (SAI)
+
+maintainers:
+ - Olivier Moysan <olivier.moysan@st.com>
+
+description:
+ The SAI interface (Serial Audio Interface) offers a wide set of audio
+ protocols as I2S standards, LSB or MSB-justified, PCM/DSP, TDM, and AC'97.
+ The SAI contains two independent audio sub-blocks. Each sub-block has
+ its own clock generator and I/O lines controller.
+
+properties:
+ compatible:
+ enum:
+ - st,stm32f4-sai
+ - st,stm32h7-sai
+
+ reg:
+ items:
+ - description: Base address and size of SAI common register set.
+ - description: Base address and size of SAI identification register set.
+ minItems: 1
+ maxItems: 2
+
+ ranges:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ maxItems: 3
+
+required:
+ - compatible
+ - reg
+ - ranges
+ - "#address-cells"
+ - "#size-cells"
+ - clocks
+ - clock-names
+
+patternProperties:
+ "^audio-controller@[0-9a-f]+$":
+ type: object
+ description:
+ Two subnodes corresponding to SAI sub-block instances A et B
+ can be defined. Subnode can be omitted for unsused sub-block.
+
+ properties:
+ compatible:
+ description: Compatible for SAI sub-block A or B.
+ pattern: "st,stm32-sai-sub-[ab]"
+
+ "#sound-dai-cells":
+ const: 0
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: sai_ck clock feeding the internal clock generator.
+ - description: MCLK clock from a SAI set as master clock provider.
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: sai_ck
+ - const: MCLK
+ minItems: 1
+ maxItems: 2
+
+ dmas:
+ maxItems: 1
+
+ dma-names:
+ description: |
+ rx: SAI sub-block is configured as a capture DAI.
+ tx: SAI sub-block is configured as a playback DAI.
+ enum: [ rx, tx ]
+
+ st,sync:
+ description:
+ Configure the SAI sub-block as slave of another SAI sub-block.
+ By default SAI sub-block is in asynchronous mode.
+ Must contain the phandle and index of the SAI sub-block providing
+ the synchronization.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/phandle-array
+ - maxItems: 1
+
+ st,iec60958:
+ description:
+ If set, support S/PDIF IEC6958 protocol for playback.
+ IEC60958 protocol is not available for capture.
+ By default, custom protocol is assumed, meaning that protocol is
+ configured according to protocol defined in related DAI link node,
+ such as i2s, left justified, right justified, dsp and pdm protocols.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/flag
+
+ "#clock-cells":
+ description: Configure the SAI device as master clock provider.
+ const: 0
+
+ required:
+ - compatible
+ - "#sound-dai-cells"
+ - reg
+ - clocks
+ - clock-names
+ - dmas
+ - dma-names
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: st,stm32f4-sai
+
+ - then:
+ properties:
+ clocks:
+ items:
+ - description: x8k, SAI parent clock for sampling rates multiple of 8kHz.
+ - description: x11k, SAI parent clock for sampling rates multiple of 11.025kHz.
+
+ clock-names:
+ items:
+ - const: x8k
+ - const: x11k
+
+ - else:
+ properties:
+ clocks:
+ items:
+ - description: pclk feeds the peripheral bus interface.
+ - description: x8k, SAI parent clock for sampling rates multiple of 8kHz.
+ - description: x11k, SAI parent clock for sampling rates multiple of 11.025kHz.
+
+ clock-names:
+ items:
+ - const: pclk
+ - const: x8k
+ - const: x11k
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/stm32mp1-clks.h>
+ #include <dt-bindings/reset/stm32mp1-resets.h>
+ sai2: sai@4400b000 {
+ compatible = "st,stm32h7-sai";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4400b000 0x400>;
+ reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
+ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
+ clock-names = "pclk", "x8k", "x11k";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>;
+ pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>;
+ status = "okay";
+
+ sai2a: audio-controller@4400b004 {
+ #sound-dai-cells = <0>;
+ compatible = "st,stm32-sai-sub-a";
+ reg = <0x4 0x1c>;
+ dmas = <&dmamux1 89 0x400 0x01>;
+ dma-names = "tx";
+ clocks = <&rcc SAI2_K>;
+ clock-names = "sai_ck";
+ status = "okay";
+ };
+ };
+
+...
diff --git a/dts/Bindings/spi/snps,dw-apb-ssi.yaml b/dts/Bindings/spi/snps,dw-apb-ssi.yaml
index 99ed9b416e..4825157cd9 100644
--- a/dts/Bindings/spi/snps,dw-apb-ssi.yaml
+++ b/dts/Bindings/spi/snps,dw-apb-ssi.yaml
@@ -65,6 +65,8 @@ properties:
const: baikal,bt1-ssi
- description: Baikal-T1 System Boot SPI Controller
const: baikal,bt1-sys-ssi
+ - description: Canaan Kendryte K210 SoS SPI Controller
+ const: canaan,k210-spi
reg:
minItems: 1
diff --git a/dts/Bindings/spi/spi-controller.yaml b/dts/Bindings/spi/spi-controller.yaml
index 1b56d5e40f..5f50581010 100644
--- a/dts/Bindings/spi/spi-controller.yaml
+++ b/dts/Bindings/spi/spi-controller.yaml
@@ -42,6 +42,33 @@ properties:
cs2 : &gpio1 1 0
cs3 : &gpio1 2 0
+ The second flag of a gpio descriptor can be GPIO_ACTIVE_HIGH (0)
+ or GPIO_ACTIVE_LOW(1). Legacy device trees often use 0.
+
+ There is a special rule set for combining the second flag of an
+ cs-gpio with the optional spi-cs-high flag for SPI slaves.
+
+ Each table entry defines how the CS pin is to be physically
+ driven (not considering potential gpio inversions by pinmux):
+
+ device node | cs-gpio | CS pin state active | Note
+ ================+===============+=====================+=====
+ spi-cs-high | - | H |
+ - | - | L |
+ spi-cs-high | ACTIVE_HIGH | H |
+ - | ACTIVE_HIGH | L | 1
+ spi-cs-high | ACTIVE_LOW | H | 2
+ - | ACTIVE_LOW | L |
+
+ Notes:
+ 1) Should print a warning about polarity inversion.
+ Here it would be wise to avoid and define the gpio as
+ ACTIVE_LOW.
+ 2) Should print a warning about polarity inversion
+ because ACTIVE_LOW is overridden by spi-cs-high.
+ Should be generally avoided and be replaced by
+ spi-cs-high + ACTIVE_HIGH.
+
num-cs:
$ref: /schemas/types.yaml#/definitions/uint32
description:
diff --git a/dts/Bindings/spi/spi-sifive.yaml b/dts/Bindings/spi/spi-sifive.yaml
index 56dcf1d35d..6e7e394fc1 100644
--- a/dts/Bindings/spi/spi-sifive.yaml
+++ b/dts/Bindings/spi/spi-sifive.yaml
@@ -17,15 +17,17 @@ allOf:
properties:
compatible:
items:
- - const: sifive,fu540-c000-spi
+ - enum:
+ - sifive,fu540-c000-spi
+ - sifive,fu740-c000-spi
- const: sifive,spi0
description:
Should be "sifive,<chip>-spi" and "sifive,spi<version>".
Supported compatible strings are -
- "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated
- onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive
- SPI v0 IP block with no chip integration tweaks.
+ "sifive,fu540-c000-spi" and "sifive,fu740-c000-spi" for the SiFive SPI v0
+ as integrated onto the SiFive FU540 and FU740 chip resp, and "sifive,spi0"
+ for the SiFive SPI v0 IP block with no chip integration tweaks.
Please refer to sifive-blocks-ip-versioning.txt for details
SPI RTL that corresponds to the IP block version numbers can be found here -
diff --git a/dts/Bindings/submitting-patches.rst b/dts/Bindings/submitting-patches.rst
index 0aab2b3f16..68129ff099 100644
--- a/dts/Bindings/submitting-patches.rst
+++ b/dts/Bindings/submitting-patches.rst
@@ -25,7 +25,8 @@ I. For patch submitters
make dt_binding_check
- See ../writing-schema.rst for more details about schema and tools setup.
+ See Documentation/devicetree/writing-schema.rst for more details about
+ schema and tools setup.
3) DT binding files should be dual licensed. The preferred license tag is
(GPL-2.0-only OR BSD-2-Clause).
diff --git a/dts/Bindings/thermal/mediatek-thermal.txt b/dts/Bindings/thermal/mediatek-thermal.txt
index 1e249c42fa..5c7e7bdd02 100644
--- a/dts/Bindings/thermal/mediatek-thermal.txt
+++ b/dts/Bindings/thermal/mediatek-thermal.txt
@@ -14,18 +14,19 @@ Required properties:
- "mediatek,mt2712-thermal" : For MT2712 family of SoCs
- "mediatek,mt7622-thermal" : For MT7622 SoC
- "mediatek,mt8183-thermal" : For MT8183 family of SoCs
+ - "mediatek,mt8516-thermal", "mediatek,mt2701-thermal : For MT8516 family of SoCs
- reg: Address range of the thermal controller
- interrupts: IRQ for the thermal controller
- clocks, clock-names: Clocks needed for the thermal controller. required
clocks are:
"therm": Main clock needed for register access
"auxadc": The AUXADC clock
-- resets: Reference to the reset controller controlling the thermal controller.
- mediatek,auxadc: A phandle to the AUXADC which the thermal controller uses
- mediatek,apmixedsys: A phandle to the APMIXEDSYS controller.
- #thermal-sensor-cells : Should be 0. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for a description.
Optional properties:
+- resets: Reference to the reset controller controlling the thermal controller.
- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If
unspecified default values shall be used.
- nvmem-cell-names: Should be "calibration-data"
diff --git a/dts/Bindings/thermal/rcar-gen3-thermal.yaml b/dts/Bindings/thermal/rcar-gen3-thermal.yaml
index f386f2a7c0..b33a76eeac 100644
--- a/dts/Bindings/thermal/rcar-gen3-thermal.yaml
+++ b/dts/Bindings/thermal/rcar-gen3-thermal.yaml
@@ -26,13 +26,16 @@ properties:
- renesas,r8a77961-thermal # R-Car M3-W+
- renesas,r8a77965-thermal # R-Car M3-N
- renesas,r8a77980-thermal # R-Car V3H
+ - renesas,r8a779a0-thermal # R-Car V3U
+
reg:
minItems: 2
- maxItems: 3
+ maxItems: 4
items:
- description: TSC1 registers
- description: TSC2 registers
- description: TSC3 registers
+ - description: TSC4 registers
interrupts:
items:
@@ -55,12 +58,22 @@ properties:
required:
- compatible
- reg
- - interrupts
- clocks
- power-domains
- resets
- "#thermal-sensor-cells"
+if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,r8a779a0-thermal
+then:
+ required:
+ - interrupts
+
additionalProperties: false
examples:
diff --git a/dts/Bindings/thermal/rcar-thermal.yaml b/dts/Bindings/thermal/rcar-thermal.yaml
index 7e9557ac0e..927de79ab4 100644
--- a/dts/Bindings/thermal/rcar-thermal.yaml
+++ b/dts/Bindings/thermal/rcar-thermal.yaml
@@ -62,25 +62,35 @@ properties:
"#thermal-sensor-cells":
const: 0
-if:
- properties:
- compatible:
- contains:
- enum:
- - renesas,thermal-r8a73a4 # R-Mobile APE6
- - renesas,thermal-r8a7779 # R-Car H1
-then:
- required:
- - compatible
- - reg
-else:
- required:
- - compatible
- - reg
- - interrupts
- - clocks
- - power-domains
- - resets
+required:
+ - compatible
+ - reg
+
+allOf:
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,thermal-r8a73a4 # R-Mobile APE6
+ - renesas,thermal-r8a7779 # R-Car H1
+ then:
+ required:
+ - resets
+ - '#thermal-sensor-cells'
+
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: renesas,thermal-r8a7779 # R-Car H1
+ then:
+ required:
+ - interrupts
+ - clocks
+ - power-domains
additionalProperties: false
diff --git a/dts/Bindings/timer/renesas,tmu.txt b/dts/Bindings/timer/renesas,tmu.txt
deleted file mode 100644
index 29159f4e65..0000000000
--- a/dts/Bindings/timer/renesas,tmu.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-* Renesas R-Mobile/R-Car Timer Unit (TMU)
-
-The TMU is a 32-bit timer/counter with configurable clock inputs and
-programmable compare match.
-
-Channels share hardware resources but their counter and compare match value
-are independent. The TMU hardware supports up to three channels.
-
-Required Properties:
-
- - compatible: must contain one or more of the following:
- - "renesas,tmu-r8a7740" for the r8a7740 TMU
- - "renesas,tmu-r8a774a1" for the r8a774A1 TMU
- - "renesas,tmu-r8a774b1" for the r8a774B1 TMU
- - "renesas,tmu-r8a774c0" for the r8a774C0 TMU
- - "renesas,tmu-r8a7778" for the r8a7778 TMU
- - "renesas,tmu-r8a7779" for the r8a7779 TMU
- - "renesas,tmu-r8a77970" for the r8a77970 TMU
- - "renesas,tmu-r8a77980" for the r8a77980 TMU
- - "renesas,tmu" for any TMU.
- This is a fallback for the above renesas,tmu-* entries
-
- - reg: base address and length of the registers block for the timer module.
-
- - interrupts: interrupt-specifier for the timer, one per channel.
-
- - clocks: a list of phandle + clock-specifier pairs, one for each entry
- in clock-names.
- - clock-names: must contain "fck" for the functional clock.
-
-Optional Properties:
-
- - #renesas,channels: number of channels implemented by the timer, must be 2
- or 3 (if not specified the value defaults to 3).
-
-
-Example: R8A7779 (R-Car H1) TMU0 node
-
- tmu0: timer@ffd80000 {
- compatible = "renesas,tmu-r8a7779", "renesas,tmu";
- reg = <0xffd80000 0x30>;
- interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
- <0 33 IRQ_TYPE_LEVEL_HIGH>,
- <0 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
- clock-names = "fck";
-
- #renesas,channels = <3>;
- };
diff --git a/dts/Bindings/timer/renesas,tmu.yaml b/dts/Bindings/timer/renesas,tmu.yaml
new file mode 100644
index 0000000000..c54188731a
--- /dev/null
+++ b/dts/Bindings/timer/renesas,tmu.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/renesas,tmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Mobile/R-Car Timer Unit (TMU)
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+ - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+
+description:
+ The TMU is a 32-bit timer/counter with configurable clock inputs and
+ programmable compare match.
+
+ Channels share hardware resources but their counter and compare match value
+ are independent. The TMU hardware supports up to three channels.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,tmu-r8a7740 # R-Mobile A1
+ - renesas,tmu-r8a774a1 # RZ/G2M
+ - renesas,tmu-r8a774b1 # RZ/G2N
+ - renesas,tmu-r8a774c0 # RZ/G2E
+ - renesas,tmu-r8a774e1 # RZ/G2H
+ - renesas,tmu-r8a7778 # R-Car M1A
+ - renesas,tmu-r8a7779 # R-Car H1
+ - renesas,tmu-r8a77970 # R-Car V3M
+ - renesas,tmu-r8a77980 # R-Car V3H
+ - const: renesas,tmu
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 2
+ maxItems: 3
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: fck
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ '#renesas,channels':
+ description:
+ Number of channels implemented by the timer.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 2, 3 ]
+ default: 3
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+
+if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,tmu-r8a7740
+ - renesas,tmu-r8a7778
+ - renesas,tmu-r8a7779
+then:
+ required:
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7779-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7779-sysc.h>
+ tmu0: timer@ffd80000 {
+ compatible = "renesas,tmu-r8a7779", "renesas,tmu";
+ reg = <0xffd80000 0x30>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
+ #renesas,channels = <3>;
+ };
diff --git a/dts/Bindings/timer/snps,dw-apb-timer.yaml b/dts/Bindings/timer/snps,dw-apb-timer.yaml
index 2fc617377e..d65faf289a 100644
--- a/dts/Bindings/timer/snps,dw-apb-timer.yaml
+++ b/dts/Bindings/timer/snps,dw-apb-timer.yaml
@@ -38,13 +38,6 @@ properties:
clock-frequency: true
- clock-freq:
- $ref: "/schemas/types.yaml#/definitions/uint32"
- description: |
- Has the same meaning as the 'clock-frequency' property - timer clock
- frequency in HZ, but is defined only for the backwards compatibility
- with the picoxcell platform.
-
additionalProperties: false
required:
diff --git a/dts/Bindings/trivial-devices.yaml b/dts/Bindings/trivial-devices.yaml
index ab623ba930..bdc2dc3181 100644
--- a/dts/Bindings/trivial-devices.yaml
+++ b/dts/Bindings/trivial-devices.yaml
@@ -30,6 +30,12 @@ properties:
- ad,ad7414
# ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems
- ad,adm9240
+ # Analog Devices ADP5585 Keypad Decoder and I/O Expansion
+ - adi,adp5585
+ # Analog Devices ADP5585 Keypad Decoder and I/O Expansion with support for Row5
+ - adi,adp5585-02
+ # Analog Devices ADP5589 Keypad Decoder and I/O Expansion
+ - adi,adp5589
# +/-1C TDM Extended Temp Range I.C
- adi,adt7461
# +/-1C TDM Extended Temp Range I.C
@@ -44,6 +50,8 @@ properties:
- atmel,atsha204a
# i2c h/w elliptic curve crypto module
- atmel,atecc508a
+ # Bosch Sensortec pressure, temperature, humididty and VOC sensor
+ - bosch,bme680
# CM32181: Ambient Light Sensor
- capella,cm32181
# CM3232: Ambient Light Sensor
@@ -60,6 +68,8 @@ properties:
- dallas,ds4510
# Digital Thermometer and Thermostat
- dallas,ds75
+ # 1/4 Brick DC/DC Regulated Power Module
+ - delta,q54sj108a2
# Devantech SRF02 ultrasonic ranger in I2C mode
- devantech,srf02
# Devantech SRF08 ultrasonic ranger
@@ -70,6 +80,12 @@ properties:
- dlg,da9053
# DA9063: system PMIC for quad-core application processors
- dlg,da9063
+ # DMARD05: 3-axis I2C Accelerometer
+ - domintech,dmard05
+ # DMARD06: 3-axis I2C Accelerometer
+ - domintech,dmard06
+ # DMARD05: 3-axis I2C Accelerometer
+ - domintech,dmard07
# DMARD09: 3-axis Accelerometer
- domintech,dmard09
# DMARD10: 3-axis Accelerometer
@@ -108,20 +124,22 @@ properties:
- isil,isl68137
# 5 Bit Programmable, Pulse-Width Modulator
- maxim,ds1050
- # 10-bit 8 channels 300ks/s SPI ADC with temperature sensor
- - maxim,max1027
- # 10-bit 12 channels 300ks/s SPI ADC with temperature sensor
- - maxim,max1029
- # 10-bit 16 channels 300ks/s SPI ADC with temperature sensor
- - maxim,max1031
- # 12-bit 8 channels 300ks/s SPI ADC with temperature sensor
- - maxim,max1227
- # 12-bit 12 channels 300ks/s SPI ADC with temperature sensor
- - maxim,max1229
- # 12-bit 16 channels 300ks/s SPI ADC with temperature sensor
- - maxim,max1231
+ # 10 kOhm digital potentiometer with I2C interface
+ - maxim,ds1803-010
+ # 50 kOhm digital potentiometer with I2C interface
+ - maxim,ds1803-050
+ # 100 kOhm digital potentiometer with I2C interface
+ - maxim,ds1803-100
# Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
- maxim,max1237
+ # 10-bit 10 kOhm linear programable voltage divider
+ - maxim,max5481
+ # 10-bit 50 kOhm linear programable voltage divider
+ - maxim,max5482
+ # 10-bit 10 kOhm linear programable variable resistor
+ - maxim,max5483
+ # 10-bit 50 kOhm linear programable variable resistor
+ - maxim,max5484
# PECI-to-I2C translator for PECI-to-SMBus/I2C protocol conversion
- maxim,max6621
# 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
@@ -130,8 +148,24 @@ properties:
- maxim,max31730
# mCube 3-axis 8-bit digital accelerometer
- mcube,mc3230
+ # MEMSIC magnetometer
+ - memsic,mmc35240
# MEMSIC 2-axis 8-bit digital accelerometer
- memsic,mxc6225
+ # Measurement Specialities I2C temperature and humidity sensor
+ - meas,htu21
+ # Measurement Specialities I2C pressure and temperature sensor
+ - meas,ms5637
+ # Measurement Specialities I2C pressure and temperature sensor
+ - meas,ms5805
+ # Measurement Specialities I2C pressure and temperature sensor
+ - meas,ms5837
+ # Measurement Specialities temp and humidity part of ms8607 device
+ - meas,ms8607-humidity
+ # Measurement Specialities temp and pressure part of ms8607 device
+ - meas,ms8607-temppressure
+ # Measurement Specialties temperature sensor
+ - meas,tsys01
# Microchip differential I2C ADC, 1 Channel, 18 bit
- microchip,mcp3421
# Microchip differential I2C ADC, 2 Channel, 18 bit
@@ -172,134 +206,6 @@ properties:
- microchip,mcp4019-503
# Microchip 7-bit Single I2C Digital POT (100k)
- microchip,mcp4019-104
- # Microchip 7-bit Single I2C Digital Potentiometer (5k)
- - microchip,mcp4531-502
- # Microchip 7-bit Single I2C Digital Potentiometer (10k)
- - microchip,mcp4531-103
- # Microchip 7-bit Single I2C Digital Potentiometer (50k)
- - microchip,mcp4531-503
- # Microchip 7-bit Single I2C Digital Potentiometer (100k)
- - microchip,mcp4531-104
- # Microchip 7-bit Single I2C Digital Potentiometer (5k)
- - microchip,mcp4532-502
- # Microchip 7-bit Single I2C Digital Potentiometer (10k)
- - microchip,mcp4532-103
- # Microchip 7-bit Single I2C Digital Potentiometer (50k)
- - microchip,mcp4532-503
- # Microchip 7-bit Single I2C Digital Potentiometer (100k)
- - microchip,mcp4532-104
- # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (5k)
- - microchip,mcp4541-502
- # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (10k)
- - microchip,mcp4541-103
- # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (50k)
- - microchip,mcp4541-503
- # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (100k)
- - microchip,mcp4541-104
- # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (5k)
- - microchip,mcp4542-502
- # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (10k)
- - microchip,mcp4542-103
- # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (50k)
- - microchip,mcp4542-503
- # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (100k)
- - microchip,mcp4542-104
- # Microchip 8-bit Single I2C Digital Potentiometer (5k)
- - microchip,mcp4551-502
- # Microchip 8-bit Single I2C Digital Potentiometer (10k)
- - microchip,mcp4551-103
- # Microchip 8-bit Single I2C Digital Potentiometer (50k)
- - microchip,mcp4551-503
- # Microchip 8-bit Single I2C Digital Potentiometer (100k)
- - microchip,mcp4551-104
- # Microchip 8-bit Single I2C Digital Potentiometer (5k)
- - microchip,mcp4552-502
- # Microchip 8-bit Single I2C Digital Potentiometer (10k)
- - microchip,mcp4552-103
- # Microchip 8-bit Single I2C Digital Potentiometer (50k)
- - microchip,mcp4552-503
- # Microchip 8-bit Single I2C Digital Potentiometer (100k)
- - microchip,mcp4552-104
- # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (5k)
- - microchip,mcp4561-502
- # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (10k)
- - microchip,mcp4561-103
- # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (50k)
- - microchip,mcp4561-503
- # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (100k)
- - microchip,mcp4561-104
- # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (5k)
- - microchip,mcp4562-502
- # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (10k)
- - microchip,mcp4562-103
- # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (50k)
- - microchip,mcp4562-503
- # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (100k)
- - microchip,mcp4562-104
- # Microchip 7-bit Dual I2C Digital Potentiometer (5k)
- - microchip,mcp4631-502
- # Microchip 7-bit Dual I2C Digital Potentiometer (10k)
- - microchip,mcp4631-103
- # Microchip 7-bit Dual I2C Digital Potentiometer (50k)
- - microchip,mcp4631-503
- # Microchip 7-bit Dual I2C Digital Potentiometer (100k)
- - microchip,mcp4631-104
- # Microchip 7-bit Dual I2C Digital Potentiometer (5k)
- - microchip,mcp4632-502
- # Microchip 7-bit Dual I2C Digital Potentiometer (10k)
- - microchip,mcp4632-103
- # Microchip 7-bit Dual I2C Digital Potentiometer (50k)
- - microchip,mcp4632-503
- # Microchip 7-bit Dual I2C Digital Potentiometer (100k)
- - microchip,mcp4632-104
- # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (5k)
- - microchip,mcp4641-502
- # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (10k)
- - microchip,mcp4641-103
- # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (50k)
- - microchip,mcp4641-503
- # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (100k)
- - microchip,mcp4641-104
- # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (5k)
- - microchip,mcp4642-502
- # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (10k)
- - microchip,mcp4642-103
- # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (50k)
- - microchip,mcp4642-503
- # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (100k)
- - microchip,mcp4642-104
- # Microchip 8-bit Dual I2C Digital Potentiometer (5k)
- - microchip,mcp4651-502
- # Microchip 8-bit Dual I2C Digital Potentiometer (10k)
- - microchip,mcp4651-103
- # Microchip 8-bit Dual I2C Digital Potentiometer (50k)
- - microchip,mcp4651-503
- # Microchip 8-bit Dual I2C Digital Potentiometer (100k)
- - microchip,mcp4651-104
- # Microchip 8-bit Dual I2C Digital Potentiometer (5k)
- - microchip,mcp4652-502
- # Microchip 8-bit Dual I2C Digital Potentiometer (10k)
- - microchip,mcp4652-103
- # Microchip 8-bit Dual I2C Digital Potentiometer (50k)
- - microchip,mcp4652-503
- # Microchip 8-bit Dual I2C Digital Potentiometer (100k)
- - microchip,mcp4652-104
- # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (5k)
- - microchip,mcp4661-502
- # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (10k)
- - microchip,mcp4661-103
- # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (50k)
- - microchip,mcp4661-503
- # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (100k)
- - microchip,mcp4661-104
- # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (5k)
- - microchip,mcp4662-502
- # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (10k)
- - microchip,mcp4662-103
- # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (50k)
- - microchip,mcp4662-503
- # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (100k)
- - microchip,mcp4662-104
# PWM Fan Speed Controller With Fan Fault Detection
- microchip,tc654
# PWM Fan Speed Controller With Fan Fault Detection
@@ -336,8 +242,14 @@ properties:
- plx,pex8648
# Pulsedlight LIDAR range-finding sensor
- pulsedlight,lidar-lite-v2
+ # Renesas ISL29501 time-of-flight sensor
+ - renesas,isl29501
# S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power)
- samsung,24ad0xd1
+ # Sensirion low power multi-pixel gas sensor with I2C interface
+ - sensirion,sgpc3
+ # Sensirion multi-pixel gas sensor with I2C interface
+ - sensirion,sgp30
# SGX Sensortech VZ89X Sensors
- sgx,vz89x
# Relative Humidity and Temperature Sensors
@@ -350,12 +262,18 @@ properties:
- st,24c256
# Ambient Light Sensor with SMBUS/Two Wire Serial Interface
- taos,tsl2550
- # 8-Channels, 12-bit ADC
- - ti,ads7828
- # 8-Channels, 8-bit ADC
- - ti,ads7830
# Temperature Monitoring and Fan Control
- ti,amc6821
+ # Temperature and humidity sensor with i2c interface
+ - ti,hdc1000
+ # Temperature and humidity sensor with i2c interface
+ - ti,hdc1008
+ # Temperature and humidity sensor with i2c interface
+ - ti,hdc1010
+ # Temperature and humidity sensor with i2c interface
+ - ti,hdc1050
+ # Temperature and humidity sensor with i2c interface
+ - ti,hdc1080
# Temperature sensor with 2-wire interface
- ti,lm73
# Temperature sensor with integrated fan control
diff --git a/dts/Bindings/usb/brcm,usb-pinmap.yaml b/dts/Bindings/usb/brcm,usb-pinmap.yaml
new file mode 100644
index 0000000000..ffa148b9ea
--- /dev/null
+++ b/dts/Bindings/usb/brcm,usb-pinmap.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/brcm,usb-pinmap.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom USB pin map Controller Device Tree Bindings
+
+maintainers:
+ - Al Cooper <alcooperx@gmail.com>
+
+properties:
+ compatible:
+ items:
+ - const: brcm,usb-pinmap
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+ description: Interrupt for signals mirrored to out-gpios.
+
+ in-gpios:
+ description: Array of one or two GPIO pins used for input signals.
+
+ brcm,in-functions:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ description: Array of input signal names, one per gpio in in-gpios.
+
+ brcm,in-masks:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: Array of enable and mask pairs, one per gpio in-gpios.
+
+ out-gpios:
+ description: Array of one GPIO pin used for output signals.
+
+ brcm,out-functions:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ description: Array of output signal names, one per gpio in out-gpios.
+
+ brcm,out-masks:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: Array of enable, value, changed and clear masks, one
+ per gpio in out-gpios.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+dependencies:
+ in-gpios: [ interrupts ]
+
+examples:
+ - |
+ usb_pinmap: usb-pinmap@22000d0 {
+ compatible = "brcm,usb-pinmap";
+ reg = <0x22000d0 0x4>;
+ in-gpios = <&gpio 18 0>, <&gpio 19 0>;
+ brcm,in-functions = "VBUS", "PWRFLT";
+ brcm,in-masks = <0x8000 0x40000 0x10000 0x80000>;
+ out-gpios = <&gpio 20 0>;
+ brcm,out-functions = "PWRON";
+ brcm,out-masks = <0x20000 0x800000 0x400000 0x200000>;
+ interrupts = <0x0 0xb2 0x4>;
+ };
+
+...
diff --git a/dts/Bindings/usb/cdns,usb3.yaml b/dts/Bindings/usb/cdns,usb3.yaml
index d6af2794d4..a407e1143c 100644
--- a/dts/Bindings/usb/cdns,usb3.yaml
+++ b/dts/Bindings/usb/cdns,usb3.yaml
@@ -26,16 +26,21 @@ properties:
- const: dev
interrupts:
+ minItems: 3
items:
- description: OTG/DRD controller interrupt
- description: XHCI host controller interrupt
- description: Device controller interrupt
+ - description: interrupt used to wake up core, e.g when usbcmd.rs is
+ cleared by xhci core, this interrupt is optional
interrupt-names:
+ minItems: 3
items:
- const: host
- const: peripheral
- const: otg
+ - const: wakeup
dr_mode:
enum: [host, otg, peripheral]
diff --git a/dts/Bindings/usb/maxim,max33359.yaml b/dts/Bindings/usb/maxim,max33359.yaml
new file mode 100644
index 0000000000..93a19eda61
--- /dev/null
+++ b/dts/Bindings/usb/maxim,max33359.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/usb/maxim,max33359.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Maxim TCPCI Type-C PD controller DT bindings
+
+maintainers:
+ - Badhri Jagan Sridharan <badhri@google.com>
+
+description: Maxim TCPCI Type-C PD controller
+
+properties:
+ compatible:
+ enum:
+ - maxim,max33359
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ connector:
+ type: object
+ $ref: ../connector/usb-connector.yaml#
+ description:
+ Properties for usb c connector.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - connector
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/usb/pd.h>
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ maxtcpc@25 {
+ compatible = "maxim,max33359";
+ reg = <0x25>;
+ interrupt-parent = <&gpa8>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+
+ connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ data-role = "dual";
+ power-role = "dual";
+ try-power-role = "sink";
+ self-powered;
+ op-sink-microwatt = <2600000>;
+ new-source-frs-typec-current = <FRS_5V_1P5A>;
+ source-pdos = <PDO_FIXED(5000, 900,
+ PDO_FIXED_SUSPEND |
+ PDO_FIXED_USB_COMM |
+ PDO_FIXED_DATA_SWAP |
+ PDO_FIXED_DUAL_ROLE)>;
+ sink-pdos = <PDO_FIXED(5000, 3000,
+ PDO_FIXED_USB_COMM |
+ PDO_FIXED_DATA_SWAP |
+ PDO_FIXED_DUAL_ROLE)
+ PDO_FIXED(9000, 2000, 0)>;
+ };
+ };
+ };
+...
diff --git a/dts/Bindings/usb/renesas,usb-xhci.yaml b/dts/Bindings/usb/renesas,usb-xhci.yaml
index 0f078bd0a3..22603256dd 100644
--- a/dts/Bindings/usb/renesas,usb-xhci.yaml
+++ b/dts/Bindings/usb/renesas,usb-xhci.yaml
@@ -51,7 +51,6 @@ properties:
maxItems: 1
phy-names:
- maxItems: 1
items:
- const: usb
diff --git a/dts/Bindings/usb/renesas,usbhs.yaml b/dts/Bindings/usb/renesas,usbhs.yaml
index 737c1f47b7..54c361d4a7 100644
--- a/dts/Bindings/usb/renesas,usbhs.yaml
+++ b/dts/Bindings/usb/renesas,usbhs.yaml
@@ -74,11 +74,8 @@ properties:
phys:
maxItems: 1
- items:
- - description: phandle + phy specifier pair.
phy-names:
- maxItems: 1
items:
- const: usb
diff --git a/dts/Bindings/usb/st,stusb160x.yaml b/dts/Bindings/usb/st,stusb160x.yaml
new file mode 100644
index 0000000000..9a51efa9d1
--- /dev/null
+++ b/dts/Bindings/usb/st,stusb160x.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/usb/st,stusb160x.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: STMicroelectronics STUSB160x Type-C controller bindings
+
+maintainers:
+ - Amelie Delaunay <amelie.delaunay@st.com>
+
+properties:
+ compatible:
+ enum:
+ - st,stusb1600
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ vdd-supply:
+ description: main power supply (4.1V-22V)
+
+ vsys-supply:
+ description: low power supply (3.0V-5.5V)
+
+ vconn-supply:
+ description: power supply (2.7V-5.5V) used to supply VConn on CC pin in
+ source or dual power role
+
+ connector:
+ type: object
+
+ allOf:
+ - $ref: ../connector/usb-connector.yaml
+
+ properties:
+ compatible:
+ const: usb-c-connector
+
+ power-role: true
+
+ typec-power-opmode: true
+
+ required:
+ - compatible
+
+required:
+ - compatible
+ - reg
+ - connector
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ typec: stusb1600@28 {
+ compatible = "st,stusb1600";
+ reg = <0x28>;
+ vdd-supply = <&vbus_drd>;
+ vsys-supply = <&vdd_usb>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpioi>;
+
+ typec_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ data-role = "dual";
+ typec-power-opmode = "default";
+
+ port {
+ typec_con_ep: endpoint {
+ remote-endpoint = <&usbotg_hs_ep>;
+ };
+ };
+ };
+ };
+ };
+...
diff --git a/dts/Bindings/vendor-prefixes.yaml b/dts/Bindings/vendor-prefixes.yaml
index 2735be1a84..041ae90b0d 100644
--- a/dts/Bindings/vendor-prefixes.yaml
+++ b/dts/Bindings/vendor-prefixes.yaml
@@ -16,7 +16,7 @@ properties: {}
patternProperties:
# Prefixes which are not vendors, but followed the pattern
# DO NOT ADD NEW PROPERTIES TO THIS LIST
- "^(at25|devbus|dmacap|dsa|exynos|fsi[ab]|gpio-fan|gpio|gpmc|hdmi|i2c-gpio),.*": true
+ "^(at25|bm|devbus|dmacap|dsa|exynos|fsi[ab]|gpio-fan|gpio-key|gpio|gpmc|hdmi|i2c-gpio),.*": true
"^(keypad|m25p|max8952|max8997|max8998|mpmc),.*": true
"^(pinctrl-single|#pinctrl-single|PowerPC),.*": true
"^(pl022|pxa-mmc|rcar_sound|rotary-encoder|s5m8767|sdhci),.*": true
@@ -25,10 +25,14 @@ patternProperties:
# Keep list in alphabetical order.
"^70mai,.*":
description: 70mai Co., Ltd.
+ "^abb,.*":
+ description: ABB
"^abilis,.*":
description: Abilis Systems
"^abracon,.*":
description: Abracon Corporation
+ "^abt,.*":
+ description: ShenZhen Asia Better Technology Ltd.
"^acer,.*":
description: Acer Inc.
"^acme,.*":
@@ -65,6 +69,8 @@ patternProperties:
description: AlphaScale Integrated Circuits Systems, Inc.
"^alps,.*":
description: Alps Electric Co., Ltd.
+ "^alt,.*":
+ description: Altus-Escon-Company BV
"^altr,.*":
description: Altera Corp.
"^amarula,.*":
@@ -79,6 +85,8 @@ patternProperties:
description: Shenzhen Amediatech Technology Co., Ltd
"^amlogic,.*":
description: Amlogic, Inc.
+ "^ampere,.*":
+ description: Ampere Computing LLC
"^ampire,.*":
description: Ampire Co., Ltd.
"^ams,.*":
@@ -179,6 +187,8 @@ patternProperties:
description: CALAO Systems SAS
"^calxeda,.*":
description: Calxeda
+ "^canaan,.*":
+ description: Canaan, Inc.
"^caninos,.*":
description: Caninos Loucos Program
"^capella,.*":
@@ -315,10 +325,14 @@ patternProperties:
description: Einfochips
"^elan,.*":
description: Elan Microelectronic Corp.
+ "^element14,.*":
+ description: Element14 (A Premier Farnell Company)
"^elgin,.*":
description: Elgin S/A.
"^elida,.*":
description: Shenzhen Elida Technology Co., Ltd.
+ "^elimo,.*":
+ description: Elimo Engineering Ltd.
"^embest,.*":
description: Shenzhen Embest Technology Co., Ltd.
"^emlid,.*":
@@ -377,6 +391,8 @@ patternProperties:
description: Shenzhen Feixin Photoelectic Co., Ltd
"^feiyang,.*":
description: Shenzhen Fly Young Technology Co.,LTD.
+ "^fii,.*":
+ description: Foxconn Industrial Internet
"^firefly,.*":
description: Firefly
"^focaltech,.*":
@@ -441,6 +457,8 @@ patternProperties:
description: HiDeep Inc.
"^himax,.*":
description: Himax Technologies, Inc.
+ "^hirschmann,.*":
+ description: Hirschmann Automation and Control GmbH
"^hisilicon,.*":
description: Hisilicon Limited.
"^hit,.*":
@@ -451,6 +469,8 @@ patternProperties:
description: Holt Integrated Circuits, Inc.
"^honeywell,.*":
description: Honeywell
+ "^honestar,.*":
+ description: Honestar Technologies Co., Ltd.
"^hoperun,.*":
description: Jiangsu HopeRun Software Co., Ltd.
"^hp,.*":
@@ -553,6 +573,8 @@ patternProperties:
description: Kionix, Inc.
"^kobo,.*":
description: Rakuten Kobo Inc.
+ "^kobol,.*":
+ description: Kobol Innovations Pte. Ltd.
"^koe,.*":
description: Kaohsiung Opto-Electronics Inc.
"^kontron,.*":
@@ -601,6 +623,8 @@ patternProperties:
description: Linux-specific binding
"^linx,.*":
description: Linx Technologies
+ "^litex,.*":
+ description: LiteX SoC builder
"^lltc,.*":
description: Linear Technology Corporation
"^logicpd,.*":
@@ -655,6 +679,8 @@ patternProperties:
description: MEMSIC Inc.
"^menlo,.*":
description: Menlo Systems GmbH
+ "^mentor,.*":
+ description: Mentor Graphics
"^meraki,.*":
description: Cisco Meraki, LLC
"^merrii,.*":
@@ -669,6 +695,8 @@ patternProperties:
description: Micron Technology Inc.
"^microsoft,.*":
description: Microsoft Corporation
+ "^microsys,.*":
+ description: MicroSys Electronics GmbH
"^mikroe,.*":
description: MikroElektronika d.o.o.
"^mikrotik,.*":
@@ -681,6 +709,8 @@ patternProperties:
description: MiraMEMS Sensing Technology Co., Ltd.
"^mitsubishi,.*":
description: Mitsubishi Electric Corporation
+ "^modtronix,.*":
+ description: Modtronix Engineering
"^mosaixtech,.*":
description: Mosaix Technologies, Inc.
"^motorola,.*":
@@ -760,6 +790,8 @@ patternProperties:
description: NXP Semiconductors
"^oceanic,.*":
description: Oceanic Systems (UK) Ltd.
+ "^oct,.*":
+ description: Octavo Systems LLC
"^okaya,.*":
description: Okaya Electric America, Inc.
"^oki,.*":
@@ -792,6 +824,8 @@ patternProperties:
description: Ortus Technology Co., Ltd.
"^osddisplays,.*":
description: OSD Displays
+ "^ouya,.*":
+ description: Ouya Inc.
"^overkiz,.*":
description: Overkiz SAS
"^ovti,.*":
@@ -894,6 +928,8 @@ patternProperties:
description: iMX6 Rex Project
"^rervision,.*":
description: Shenzhen Rervision Technology Co., Ltd.
+ "^revotics,.*":
+ description: Revolution Robotics, Inc. (Revotics)
"^richtek,.*":
description: Richtek Technology Corporation
"^ricoh,.*":
@@ -1053,6 +1089,8 @@ patternProperties:
description: Trusted Computing Group
"^tcl,.*":
description: Toby Churchill Ltd.
+ "^tdo,.*":
+ description: Shangai Top Display Optoelectronics Co., Ltd
"^technexion,.*":
description: TechNexion
"^technologic,.*":
@@ -1097,7 +1135,7 @@ patternProperties:
"^tpo,.*":
description: TPO
"^tq,.*":
- description: TQ Systems GmbH
+ description: TQ-Systems GmbH
"^tronfy,.*":
description: Tronfy
"^tronsmart,.*":
@@ -1140,12 +1178,16 @@ patternProperties:
description: Vamrs Ltd.
"^variscite,.*":
description: Variscite Ltd.
+ "^vdl,.*":
+ description: Van der Laan b.v.
"^via,.*":
description: VIA Technologies, Inc.
"^videostrong,.*":
description: Videostrong Technology Co., Ltd.
"^virtio,.*":
description: Virtual I/O Device Specification, developed by the OASIS consortium
+ "^virtual,.*":
+ description: Used for virtual device without specific vendor.
"^vishay,.*":
description: Vishay Intertechnology, Inc
"^vitesse,.*":
@@ -1210,6 +1252,8 @@ patternProperties:
description: Shenzhen Xunlong Software CO.,Limited
"^xylon,.*":
description: Xylon
+ "^yes-optoelectronics,.*":
+ description: Yes Optoelectronics Co.,Ltd.
"^ylm,.*":
description: Shenzhen Yangliming Electronic Technology Co., Ltd.
"^yna,.*":
diff --git a/dts/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/dts/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
index e8f2263761..5ac607de8b 100644
--- a/dts/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
+++ b/dts/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
@@ -22,6 +22,9 @@ properties:
- const: allwinner,sun50i-a64-wdt
- const: allwinner,sun6i-a31-wdt
- items:
+ - const: allwinner,sun50i-a100-wdt
+ - const: allwinner,sun6i-a31-wdt
+ - items:
- const: allwinner,sun50i-h6-wdt
- const: allwinner,sun6i-a31-wdt
- items:
diff --git a/dts/Bindings/watchdog/fsl-imx-wdt.yaml b/dts/Bindings/watchdog/fsl-imx-wdt.yaml
index 991b4e3348..fb7695515b 100644
--- a/dts/Bindings/watchdog/fsl-imx-wdt.yaml
+++ b/dts/Bindings/watchdog/fsl-imx-wdt.yaml
@@ -18,10 +18,26 @@ properties:
- const: fsl,imx21-wdt
- items:
- enum:
+ - fsl,imx25-wdt
+ - fsl,imx27-wdt
+ - fsl,imx31-wdt
+ - fsl,imx35-wdt
+ - fsl,imx50-wdt
+ - fsl,imx51-wdt
+ - fsl,imx53-wdt
+ - fsl,imx6q-wdt
+ - fsl,imx6sl-wdt
+ - fsl,imx6sll-wdt
+ - fsl,imx6sx-wdt
+ - fsl,imx6ul-wdt
+ - fsl,imx7d-wdt
- fsl,imx8mm-wdt
- fsl,imx8mn-wdt
- fsl,imx8mp-wdt
- fsl,imx8mq-wdt
+ - fsl,ls1012a-wdt
+ - fsl,ls1043a-wdt
+ - fsl,vf610-wdt
- const: fsl,imx21-wdt
reg:
diff --git a/dts/Bindings/watchdog/snps,dw-wdt.yaml b/dts/Bindings/watchdog/snps,dw-wdt.yaml
index d9fc7bb851..f7ee9229c2 100644
--- a/dts/Bindings/watchdog/snps,dw-wdt.yaml
+++ b/dts/Bindings/watchdog/snps,dw-wdt.yaml
@@ -14,7 +14,15 @@ maintainers:
properties:
compatible:
- const: snps,dw-wdt
+ oneOf:
+ - const: snps,dw-wdt
+ - items:
+ - enum:
+ - rockchip,rk3066-wdt
+ - rockchip,rk3188-wdt
+ - rockchip,rk3288-wdt
+ - rockchip,rk3368-wdt
+ - const: snps,dw-wdt
reg:
maxItems: 1