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-rw-r--r--dts/src/arc/axc003.dtsi8
1 files changed, 8 insertions, 0 deletions
diff --git a/dts/src/arc/axc003.dtsi b/dts/src/arc/axc003.dtsi
index 4e6e9f57e7..dc91c663bc 100644
--- a/dts/src/arc/axc003.dtsi
+++ b/dts/src/arc/axc003.dtsi
@@ -35,6 +35,14 @@
reg = <0x80 0x10>, <0x100 0x10>;
#clock-cells = <0>;
clocks = <&input_clk>;
+
+ /*
+ * Set initial core pll output frequency to 90MHz.
+ * It will be applied at the core pll driver probing
+ * on early boot.
+ */
+ assigned-clocks = <&core_clk>;
+ assigned-clock-rates = <90000000>;
};
core_intc: archs-intc@cpu {