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-rw-r--r--dts/src/arc/axc003_idu.dtsi23
-rw-r--r--dts/src/arc/haps_hs_idu.dts11
-rw-r--r--dts/src/arc/nsim_hs_idu.dts15
-rw-r--r--dts/src/arc/nsimosci_hs_idu.dts21
-rw-r--r--dts/src/arc/vdk_axc003_idu.dtsi13
-rw-r--r--dts/src/arc/vdk_axs10x_mb.dtsi26
6 files changed, 40 insertions, 69 deletions
diff --git a/dts/src/arc/axc003_idu.dtsi b/dts/src/arc/axc003_idu.dtsi
index 3d6cfa32bf..695f9fa199 100644
--- a/dts/src/arc/axc003_idu.dtsi
+++ b/dts/src/arc/axc003_idu.dtsi
@@ -40,18 +40,7 @@
compatible = "snps,archs-idu-intc";
interrupt-controller;
interrupt-parent = <&core_intc>;
-
- /*
- * <hwirq distribution>
- * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
- */
- #interrupt-cells = <2>;
-
- /*
- * upstream irqs to core intc - downstream these are
- * "COMMON" irq 0,1..
- */
- interrupts = <24 25>;
+ #interrupt-cells = <1>;
};
/*
@@ -73,12 +62,7 @@
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&idu_intc>;
-
- /*
- * cmn irq 1 -> cpu irq 25
- * Distribute to cpu0 only
- */
- interrupts = <1 1>;
+ interrupts = <1>;
};
};
@@ -119,8 +103,7 @@
reg = < 0xe0012000 0x200 >;
interrupt-controller;
interrupt-parent = <&idu_intc>;
- interrupts = <0 1>; /* cmn irq 0 -> cpu irq 24
- distribute to cpu0 only */
+ interrupts = <0>;
};
memory {
diff --git a/dts/src/arc/haps_hs_idu.dts b/dts/src/arc/haps_hs_idu.dts
index 65204b4c0f..215cddd0b6 100644
--- a/dts/src/arc/haps_hs_idu.dts
+++ b/dts/src/arc/haps_hs_idu.dts
@@ -47,18 +47,13 @@
compatible = "snps,archs-intc";
interrupt-controller;
#interrupt-cells = <1>;
-/* interrupts = <16 17 18 19 20 21 22 23 24 25>; */
};
idu_intc: idu-interrupt-controller {
compatible = "snps,archs-idu-intc";
interrupt-controller;
interrupt-parent = <&core_intc>;
- /* <hwirq distribution>
- distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 */
- #interrupt-cells = <2>;
- interrupts = <24 25 26 27 28 29 30 31>;
-
+ #interrupt-cells = <1>;
};
uart0: serial@f0000000 {
@@ -66,9 +61,7 @@
compatible = "ns16550a";
reg = <0xf0000000 0x2000>;
interrupt-parent = <&idu_intc>;
- /* interrupts = <0 1>; DEST=1*/
- /* interrupts = <0 2>; DEST=2*/
- interrupts = <0 0>; /* RR*/
+ interrupts = <0>;
clock-frequency = <50000000>;
baud = <115200>;
reg-shift = <2>;
diff --git a/dts/src/arc/nsim_hs_idu.dts b/dts/src/arc/nsim_hs_idu.dts
index 48434d7c44..4f98ebf71f 100644
--- a/dts/src/arc/nsim_hs_idu.dts
+++ b/dts/src/arc/nsim_hs_idu.dts
@@ -46,25 +46,14 @@
compatible = "snps,archs-idu-intc";
interrupt-controller;
interrupt-parent = <&core_intc>;
-
- /*
- * <hwirq distribution>
- * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
- */
- #interrupt-cells = <2>;
-
- /*
- * upstream irqs to core intc - downstream these are
- * "COMMON" irq 0,1..
- */
- interrupts = <24 25 26 27 28 29 30 31>;
+ #interrupt-cells = <1>;
};
arcuart0: serial@c0fc1000 {
compatible = "snps,arc-uart";
reg = <0xc0fc1000 0x100>;
interrupt-parent = <&idu_intc>;
- interrupts = <0 0>;
+ interrupts = <0>;
clock-frequency = <80000000>;
current-speed = <115200>;
status = "okay";
diff --git a/dts/src/arc/nsimosci_hs_idu.dts b/dts/src/arc/nsimosci_hs_idu.dts
index cbf65b6cc7..5052917d4a 100644
--- a/dts/src/arc/nsimosci_hs_idu.dts
+++ b/dts/src/arc/nsimosci_hs_idu.dts
@@ -43,33 +43,20 @@
compatible = "snps,archs-intc";
interrupt-controller;
#interrupt-cells = <1>;
-/* interrupts = <16 17 18 19 20 21 22 23 24 25>; */
};
idu_intc: idu-interrupt-controller {
compatible = "snps,archs-idu-intc";
interrupt-controller;
interrupt-parent = <&core_intc>;
-
- /*
- * <hwirq distribution>
- * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
- */
- #interrupt-cells = <2>;
-
- /*
- * upstream irqs to core intc - downstream these are
- * "COMMON" irq 0,1..
- */
- interrupts = <24 25 26 27 28 29 30 31>;
+ #interrupt-cells = <1>;
};
uart0: serial@f0000000 {
compatible = "ns8250";
reg = <0xf0000000 0x2000>;
interrupt-parent = <&idu_intc>;
- interrupts = <0 0>; /* cmn irq 0 -> cpu irq 24
- RR distribute to all cpus */
+ interrupts = <0>;
clock-frequency = <3686400>;
baud = <115200>;
reg-shift = <2>;
@@ -93,7 +80,7 @@
ps2: ps2@f9001000 {
compatible = "snps,arc_ps2";
reg = <0xf9000400 0x14>;
- interrupts = <3 0>;
+ interrupts = <3>;
interrupt-parent = <&idu_intc>;
interrupt-names = "arc_ps2_irq";
};
@@ -102,7 +89,7 @@
compatible = "ezchip,nps-mgt-enet";
reg = <0xf0003000 0x44>;
interrupt-parent = <&idu_intc>;
- interrupts = <1 2>;
+ interrupts = <1>;
};
arcpct0: pct {
diff --git a/dts/src/arc/vdk_axc003_idu.dtsi b/dts/src/arc/vdk_axc003_idu.dtsi
index 82214cd7ba..28956f9a9f 100644
--- a/dts/src/arc/vdk_axc003_idu.dtsi
+++ b/dts/src/arc/vdk_axc003_idu.dtsi
@@ -41,14 +41,7 @@
compatible = "snps,archs-idu-intc";
interrupt-controller;
interrupt-parent = <&core_intc>;
-
- /*
- * <hwirq distribution>
- * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
- */
- #interrupt-cells = <2>;
-
- interrupts = <24 25 26 27>;
+ #interrupt-cells = <1>;
};
debug_uart: dw-apb-uart@0x5000 {
@@ -56,7 +49,7 @@
reg = <0x5000 0x100>;
clock-frequency = <2403200>;
interrupt-parent = <&idu_intc>;
- interrupts = <2 0>;
+ interrupts = <2>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
@@ -70,7 +63,7 @@
reg = < 0xe0012000 0x200 >;
interrupt-controller;
interrupt-parent = <&idu_intc>;
- interrupts = < 0 0 >;
+ interrupts = <0>;
};
memory {
diff --git a/dts/src/arc/vdk_axs10x_mb.dtsi b/dts/src/arc/vdk_axs10x_mb.dtsi
index 99498a4b42..f0df59b23e 100644
--- a/dts/src/arc/vdk_axs10x_mb.dtsi
+++ b/dts/src/arc/vdk_axs10x_mb.dtsi
@@ -23,6 +23,12 @@
#clock-cells = <0>;
};
+ mmcclk: mmcclk {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ #clock-cells = <0>;
+ };
+
pguclk: pguclk {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -94,5 +100,25 @@
interrupts = <5>;
interrupt-names = "arc_ps2_irq";
};
+
+ mmc@0x15000 {
+ compatible = "snps,dw-mshc";
+ reg = <0x15000 0x400>;
+ num-slots = <1>;
+ fifo-depth = <1024>;
+ card-detect-delay = <200>;
+ clocks = <&apbclk>, <&mmcclk>;
+ clock-names = "biu", "ciu";
+ interrupts = <7>;
+ bus-width = <4>;
+ };
+
+ /* Embedded Vision subsystem UIO mappings; only relevant for EV VDK */
+ uio_ev: uio@0xD0000000 {
+ compatible = "generic-uio";
+ reg = <0xD0000000 0x2000 0xD1000000 0x2000 0x90000000 0x10000000 0xC0000000 0x10000000>;
+ reg-names = "ev_gsa", "ev_ctrl", "ev_shared_mem", "ev_code_mem";
+ interrupts = <23>;
+ };
};
};
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-19 19:22:50 +0000