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-rw-r--r--dts/src/arc/axc001.dtsi2
-rw-r--r--dts/src/arc/axc003.dtsi13
-rw-r--r--dts/src/arc/axc003_idu.dtsi13
-rw-r--r--dts/src/arc/axs10x_mb.dtsi1
-rw-r--r--dts/src/arc/hsdk.dts189
-rw-r--r--dts/src/arc/nsim_hs.dts2
-rw-r--r--dts/src/arc/vdk_axs10x_mb.dtsi1
7 files changed, 211 insertions, 10 deletions
diff --git a/dts/src/arc/axc001.dtsi b/dts/src/arc/axc001.dtsi
index a380ffa1a4..fdc266504a 100644
--- a/dts/src/arc/axc001.dtsi
+++ b/dts/src/arc/axc001.dtsi
@@ -99,7 +99,7 @@
memory {
device_type = "memory";
- /* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */
+ /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
reg = <0x0 0x80000000 0x0 0x1b000000>; /* (512 - 32) MiB */
};
diff --git a/dts/src/arc/axc003.dtsi b/dts/src/arc/axc003.dtsi
index cc9239ef8d..4e6e9f57e7 100644
--- a/dts/src/arc/axc003.dtsi
+++ b/dts/src/arc/axc003.dtsi
@@ -24,10 +24,17 @@
ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
- core_clk: core_clk {
+ input_clk: input-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <90000000>;
+ clock-frequency = <33333333>;
+ };
+
+ core_clk: core-clk@80 {
+ compatible = "snps,axs10x-arc-pll-clock";
+ reg = <0x80 0x10>, <0x100 0x10>;
+ #clock-cells = <0>;
+ clocks = <&input_clk>;
};
core_intc: archs-intc@cpu {
@@ -102,7 +109,7 @@
memory {
device_type = "memory";
- /* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */
+ /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */
0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */
};
diff --git a/dts/src/arc/axc003_idu.dtsi b/dts/src/arc/axc003_idu.dtsi
index 4ebb2170ab..63954a8b01 100644
--- a/dts/src/arc/axc003_idu.dtsi
+++ b/dts/src/arc/axc003_idu.dtsi
@@ -24,10 +24,17 @@
ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
- core_clk: core_clk {
+ input_clk: input-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <100000000>;
+ clock-frequency = <33333333>;
+ };
+
+ core_clk: core-clk@80 {
+ compatible = "snps,axs10x-arc-pll-clock";
+ reg = <0x80 0x10>, <0x100 0x10>;
+ #clock-cells = <0>;
+ clocks = <&input_clk>;
};
core_intc: archs-intc@cpu {
@@ -108,7 +115,7 @@
memory {
device_type = "memory";
- /* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */
+ /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */
0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */
};
diff --git a/dts/src/arc/axs10x_mb.dtsi b/dts/src/arc/axs10x_mb.dtsi
index 0ff7e07edc..2367a67c5f 100644
--- a/dts/src/arc/axs10x_mb.dtsi
+++ b/dts/src/arc/axs10x_mb.dtsi
@@ -101,7 +101,6 @@
mmc@0x15000 {
compatible = "altr,socfpga-dw-mshc";
reg = < 0x15000 0x400 >;
- num-slots = < 1 >;
fifo-depth = < 16 >;
card-detect-delay = < 200 >;
clocks = <&apbclk>, <&mmcclk>;
diff --git a/dts/src/arc/hsdk.dts b/dts/src/arc/hsdk.dts
new file mode 100644
index 0000000000..229d13adbc
--- /dev/null
+++ b/dts/src/arc/hsdk.dts
@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Device Tree for ARC HS Development Kit
+ */
+/dts-v1/;
+
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ model = "snps,hsdk";
+ compatible = "snps,hsdk";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen {
+ bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "snps,archs38";
+ reg = <0>;
+ clocks = <&core_clk>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "snps,archs38";
+ reg = <1>;
+ clocks = <&core_clk>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "snps,archs38";
+ reg = <2>;
+ clocks = <&core_clk>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "snps,archs38";
+ reg = <3>;
+ clocks = <&core_clk>;
+ };
+ };
+
+ core_clk: core-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <500000000>;
+ };
+
+ cpu_intc: cpu-interrupt-controller {
+ compatible = "snps,archs-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ idu_intc: idu-interrupt-controller {
+ compatible = "snps,archs-idu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&cpu_intc>;
+ };
+
+ arcpct: pct {
+ compatible = "snps,archs-pct";
+ };
+
+ /* TIMER0 with interrupt for clockevent */
+ timer {
+ compatible = "snps,arc-timer";
+ interrupts = <16>;
+ interrupt-parent = <&cpu_intc>;
+ clocks = <&core_clk>;
+ };
+
+ /* 64-bit Global Free Running Counter */
+ gfrc {
+ compatible = "snps,archs-timer-gfrc";
+ clocks = <&core_clk>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&idu_intc>;
+
+ ranges = <0x00000000 0xf0000000 0x10000000>;
+
+ serial: serial@5000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x5000 0x100>;
+ clock-frequency = <33330000>;
+ interrupts = <6>;
+ baud = <115200>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+
+ gmacclk: gmacclk {
+ compatible = "fixed-clock";
+ clock-frequency = <400000000>;
+ #clock-cells = <0>;
+ };
+
+ mmcclk_ciu: mmcclk-ciu {
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ #clock-cells = <0>;
+ };
+
+ mmcclk_biu: mmcclk-biu {
+ compatible = "fixed-clock";
+ clock-frequency = <400000000>;
+ #clock-cells = <0>;
+ };
+
+ ethernet@8000 {
+ #interrupt-cells = <1>;
+ compatible = "snps,dwmac";
+ reg = <0x8000 0x2000>;
+ interrupts = <10>;
+ interrupt-names = "macirq";
+ phy-mode = "rgmii";
+ snps,pbl = <32>;
+ clocks = <&gmacclk>;
+ clock-names = "stmmaceth";
+ phy-handle = <&phy0>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+ };
+ };
+
+ ohci@60000 {
+ compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
+ reg = <0x60000 0x100>;
+ interrupts = <15>;
+ };
+
+ ehci@40000 {
+ compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
+ reg = <0x40000 0x100>;
+ interrupts = <15>;
+ };
+
+ mmc@a000 {
+ compatible = "altr,socfpga-dw-mshc";
+ reg = <0xa000 0x400>;
+ num-slots = <1>;
+ fifo-depth = <16>;
+ card-detect-delay = <200>;
+ clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
+ clock-names = "biu", "ciu";
+ interrupts = <12>;
+ bus-width = <4>;
+ };
+ };
+
+ memory@80000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>; /* 1 GiB */
+ };
+};
diff --git a/dts/src/arc/nsim_hs.dts b/dts/src/arc/nsim_hs.dts
index 3772c40c24..8d787b251f 100644
--- a/dts/src/arc/nsim_hs.dts
+++ b/dts/src/arc/nsim_hs.dts
@@ -18,7 +18,7 @@
memory {
device_type = "memory";
- /* CONFIG_LINUX_LINK_BASE needs to match low mem start */
+ /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MB low mem */
0x1 0x00000000 0x0 0x40000000>; /* 1 GB highmem */
};
diff --git a/dts/src/arc/vdk_axs10x_mb.dtsi b/dts/src/arc/vdk_axs10x_mb.dtsi
index 459fc656b7..48bb4b4cd2 100644
--- a/dts/src/arc/vdk_axs10x_mb.dtsi
+++ b/dts/src/arc/vdk_axs10x_mb.dtsi
@@ -104,7 +104,6 @@
mmc@0x15000 {
compatible = "snps,dw-mshc";
reg = <0x15000 0x400>;
- num-slots = <1>;
fifo-depth = <1024>;
card-detect-delay = <200>;
clocks = <&apbclk>, <&mmcclk>;
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-19 17:27:30 +0000