diff options
Diffstat (limited to 'dts/src/arm/am43xx-clocks.dtsi')
-rw-r--r-- | dts/src/arm/am43xx-clocks.dtsi | 883 |
1 files changed, 0 insertions, 883 deletions
diff --git a/dts/src/arm/am43xx-clocks.dtsi b/dts/src/arm/am43xx-clocks.dtsi deleted file mode 100644 index 314fc5975a..0000000000 --- a/dts/src/arm/am43xx-clocks.dtsi +++ /dev/null @@ -1,883 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for AM43xx clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&scm_clocks { - sys_clkin_ck: sys_clkin_ck@40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>; - ti,bit-shift = <31>; - reg = <0x0040>; - }; - - crystal_freq_sel_ck: crystal_freq_sel_ck@40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; - ti,bit-shift = <29>; - reg = <0x0040>; - }; - - sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; - ti,bit-shift = <22>; - reg = <0x0040>; - }; - - adc_tsc_fck: adc_tsc_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dcan0_fck: dcan0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dcan1_fck: dcan1_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - mcasp0_fck: mcasp0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - mcasp1_fck: mcasp1_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - smartreflex0_fck: smartreflex0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - smartreflex1_fck: smartreflex1_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - sha0_fck: sha0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - aes0_fck: aes0_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - rng_fck: rng_fck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - ehrpwm0_tbclk: ehrpwm0_tbclk@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <0>; - reg = <0x0664>; - }; - - ehrpwm1_tbclk: ehrpwm1_tbclk@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <1>; - reg = <0x0664>; - }; - - ehrpwm2_tbclk: ehrpwm2_tbclk@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <2>; - reg = <0x0664>; - }; - - ehrpwm3_tbclk: ehrpwm3_tbclk@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <4>; - reg = <0x0664>; - }; - - ehrpwm4_tbclk: ehrpwm4_tbclk@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <5>; - reg = <0x0664>; - }; - - ehrpwm5_tbclk: ehrpwm5_tbclk@664 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l4ls_gclk>; - ti,bit-shift = <6>; - reg = <0x0664>; - }; -}; -&prcm_clocks { - clk_32768_ck: clk_32768_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - clk_rc32k_ck: clk_rc32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - virt_19200000_ck: virt_19200000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <19200000>; - }; - - virt_24000000_ck: virt_24000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - virt_25000000_ck: virt_25000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - virt_26000000_ck: virt_26000000_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - tclkin_ck: tclkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - }; - - dpll_core_ck: dpll_core_ck@2d20 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-core-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>; - }; - - dpll_core_x2_ck: dpll_core_x2_ck { - #clock-cells = <0>; - compatible = "ti,am3-dpll-x2-clock"; - clocks = <&dpll_core_ck>; - }; - - dpll_core_m4_ck: dpll_core_m4_ck@2d38 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2d38>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_m5_ck: dpll_core_m5_ck@2d3c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2d3c>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_core_m6_ck: dpll_core_m6_ck@2d40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2d40>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_mpu_ck: dpll_mpu_ck@2d60 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>; - }; - - dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_mpu_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2d70>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - mpu_periphclk: mpu_periphclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_mpu_m2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - dpll_ddr_ck: dpll_ddr_ck@2da0 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>; - }; - - dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_ddr_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2db0>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_disp_ck: dpll_disp_ck@2e20 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>; - }; - - dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_disp_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2e30>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - ti,set-rate-parent; - }; - - dpll_per_ck: dpll_per_ck@2de0 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-j-type-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>; - }; - - dpll_per_m2_ck: dpll_per_m2_ck@2df0 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_per_ck>; - ti,max-div = <127>; - ti,autoidle-shift = <8>; - reg = <0x2df0>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <4>; - }; - - clk_24mhz: clk_24mhz { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <8>; - }; - - clkdiv32k_ck: clkdiv32k_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_24mhz>; - clock-mult = <1>; - clock-div = <732>; - }; - - clkdiv32k_ick: clkdiv32k_ick@2a38 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkdiv32k_ck>; - ti,bit-shift = <8>; - reg = <0x2a38>; - }; - - sysclk_div: sysclk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - pruss_ocp_gclk: pruss_ocp_gclk@4248 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sysclk_div>, <&dpll_disp_m2_ck>; - reg = <0x4248>; - }; - - clk_32k_tpm_ck: clk_32k_tpm_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - timer1_fck: timer1_fck@4200 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>; - reg = <0x4200>; - }; - - timer2_fck: timer2_fck@4204 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x4204>; - }; - - timer3_fck: timer3_fck@4208 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x4208>; - }; - - timer4_fck: timer4_fck@420c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x420c>; - }; - - timer5_fck: timer5_fck@4210 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x4210>; - }; - - timer6_fck: timer6_fck@4214 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x4214>; - }; - - timer7_fck: timer7_fck@4218 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; - reg = <0x4218>; - }; - - wdt1_fck: wdt1_fck@422c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; - reg = <0x422c>; - }; - - l3_gclk: l3_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sysclk_div>; - clock-mult = <1>; - clock-div = <2>; - }; - - l4hs_gclk: l4hs_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l3s_gclk: l3s_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_div2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - l4ls_gclk: l4ls_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m4_div2_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - cpsw_125mhz_gclk: cpsw_125mhz_gclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m5_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@4238 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>; - reg = <0x4238>; - }; - - dpll_clksel_mac_clk: dpll_clksel_mac_clk@4234 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_core_m5_ck>; - reg = <0x4234>; - ti,bit-shift = <2>; - ti,dividers = <2>, <5>; - }; - - clk_32k_mosc_ck: clk_32k_mosc_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@4240 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>; - reg = <0x4240>; - }; - - mmc_clk: mmc_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@423c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sysclk_div>, <&dpll_per_m2_ck>; - ti,bit-shift = <1>; - reg = <0x423c>; - }; - - gfx_fck_div_ck: gfx_fck_div_ck@423c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&gfx_fclk_clksel_ck>; - reg = <0x423c>; - ti,max-div = <2>; - }; - - disp_clk: disp_clk@4244 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; - reg = <0x4244>; - ti,set-rate-parent; - }; - - dpll_extdev_ck: dpll_extdev_ck@2e60 { - #clock-cells = <0>; - compatible = "ti,am3-dpll-clock"; - clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>; - }; - - dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_extdev_ck>; - ti,max-div = <127>; - ti,autoidle-shift = <8>; - reg = <0x2e70>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - mux_synctimer32k_ck: mux_synctimer32k_ck@4230 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>; - reg = <0x4230>; - }; - - timer8_fck: timer8_fck@421c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; - reg = <0x421c>; - }; - - timer9_fck: timer9_fck@4220 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; - reg = <0x4220>; - }; - - timer10_fck: timer10_fck@4224 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; - reg = <0x4224>; - }; - - timer11_fck: timer11_fck@4228 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; - reg = <0x4228>; - }; - - cpsw_50m_clkdiv: cpsw_50m_clkdiv { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_core_m5_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - cpsw_5m_clkdiv: cpsw_5m_clkdiv { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&cpsw_50m_clkdiv>; - clock-mult = <1>; - clock-div = <10>; - }; - - dpll_ddr_x2_ck: dpll_ddr_x2_ck { - #clock-cells = <0>; - compatible = "ti,am3-dpll-x2-clock"; - clocks = <&dpll_ddr_ck>; - }; - - dpll_ddr_m4_ck: dpll_ddr_m4_ck@2db8 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_ddr_x2_ck>; - ti,max-div = <31>; - ti,autoidle-shift = <8>; - reg = <0x2db8>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; - }; - - dpll_per_clkdcoldo: dpll_per_clkdcoldo@2e14 { - #clock-cells = <0>; - compatible = "ti,fixed-factor-clock"; - clocks = <&dpll_per_ck>; - ti,clock-mult = <1>; - ti,clock-div = <1>; - ti,autoidle-shift = <8>; - reg = <0x2e14>; - ti,invert-autoidle-bit; - }; - - dll_aging_clk_div: dll_aging_clk_div@4250 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkin_ck>; - reg = <0x4250>; - ti,dividers = <8>, <16>, <32>; - }; - - div_core_25m_ck: div_core_25m_ck { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sysclk_div>; - clock-mult = <1>; - clock-div = <8>; - }; - - func_12m_clk: func_12m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_per_m2_ck>; - clock-mult = <1>; - clock-div = <16>; - }; - - vtp_clk_div: vtp_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&sys_clkin_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - - usbphy_32khz_clkmux: usbphy_32khz_clkmux@4260 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; - reg = <0x4260>; - }; - - usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&usbphy_32khz_clkmux>; - ti,bit-shift = <8>; - reg = <0x2a40>; - }; - - usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&usbphy_32khz_clkmux>; - ti,bit-shift = <8>; - reg = <0x2a48>; - }; - - clkout1_osc_div_ck: clkout1-osc-div-ck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sys_clkin_ck>; - ti,bit-shift = <20>; - ti,max-div = <4>; - reg = <0x4100>; - }; - - clkout1_src2_mux_ck: clkout1-src2-mux-ck { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>, - <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>, - <&dpll_mpu_m2_ck>; - reg = <0x4100>; - }; - - clkout1_src2_pre_div_ck: clkout1-src2-pre-div-ck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&clkout1_src2_mux_ck>; - ti,bit-shift = <4>; - ti,max-div = <8>; - reg = <0x4100>; - }; - - clkout1_src2_post_div_ck: clkout1-src2-post-div-ck { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&clkout1_src2_pre_div_ck>; - ti,bit-shift = <8>; - ti,max-div = <32>; - ti,index-power-of-two; - reg = <0x4100>; - }; - - clkout1_mux_ck: clkout1-mux-ck { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>, - <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>; - ti,bit-shift = <16>; - reg = <0x4100>; - }; - - clkout1_ck: clkout1-ck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkout1_mux_ck>; - ti,bit-shift = <23>; - reg = <0x4100>; - }; -}; - -&prcm { - wkup_cm: wkup-cm@2800 { - compatible = "ti,omap4-cm"; - reg = <0x2800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2800 0x400>; - - l3s_tsc_clkctrl: l3s-tsc-clkctrl@120 { - compatible = "ti,clkctrl"; - reg = <0x120 0x4>; - #clock-cells = <2>; - }; - - l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@228 { - compatible = "ti,clkctrl"; - reg = <0x228 0xc>; - #clock-cells = <2>; - }; - - l4_wkup_clkctrl: l4-wkup-clkctrl@220 { - compatible = "ti,clkctrl"; - reg = <0x220 0x4>, <0x328 0x44>; - #clock-cells = <2>; - }; - - }; - - mpu_cm: mpu-cm@8300 { - compatible = "ti,omap4-cm"; - reg = <0x8300 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x8300 0x100>; - - mpu_clkctrl: mpu-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - gfx_l3_cm: gfx-l3-cm@8400 { - compatible = "ti,omap4-cm"; - reg = <0x8400 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x8400 0x100>; - - gfx_l3_clkctrl: gfx-l3-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - l4_rtc_cm: l4-rtc-cm@8500 { - compatible = "ti,omap4-cm"; - reg = <0x8500 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x8500 0x100>; - - l4_rtc_clkctrl: l4-rtc-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x4>; - #clock-cells = <2>; - }; - }; - - per_cm: per-cm@8800 { - compatible = "ti,omap4-cm"; - reg = <0x8800 0xc00>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x8800 0xc00>; - - l3_clkctrl: l3-clkctrl@20 { - compatible = "ti,clkctrl"; - reg = <0x20 0x3c>, <0x78 0x2c>; - #clock-cells = <2>; - }; - - l3s_clkctrl: l3s-clkctrl@68 { - compatible = "ti,clkctrl"; - reg = <0x68 0xc>, <0x220 0x4c>; - #clock-cells = <2>; - }; - - pruss_ocp_clkctrl: pruss-ocp-clkctrl@320 { - compatible = "ti,clkctrl"; - reg = <0x320 0x4>; - #clock-cells = <2>; - }; - - l4ls_clkctrl: l4ls-clkctrl@420 { - compatible = "ti,clkctrl"; - reg = <0x420 0x1a4>; - #clock-cells = <2>; - }; - - emif_clkctrl: emif-clkctrl@720 { - compatible = "ti,clkctrl"; - reg = <0x720 0x4>; - #clock-cells = <2>; - }; - - dss_clkctrl: dss-clkctrl@a20 { - compatible = "ti,clkctrl"; - reg = <0xa20 0x4>; - #clock-cells = <2>; - }; - - cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@b20 { - compatible = "ti,clkctrl"; - reg = <0xb20 0x4>; - #clock-cells = <2>; - }; - - }; -}; |