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diff --git a/dts/src/arm/armada-370-xp.dtsi b/dts/src/arm/armada-370-xp.dtsi
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-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
- *
- * Copyright (C) 2012 Marvell
- *
- * Lior Amsalem <alior@marvell.com>
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- * Ben Dooks <ben.dooks@codethink.co.uk>
- *
- * This file contains the definitions that are common to the Armada
- * 370 and Armada XP SoC.
- */
-
-#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
-
-/ {
- model = "Marvell Armada 370 and XP SoC";
- compatible = "marvell,armada-370-xp";
-
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- cpu@0 {
- compatible = "marvell,sheeva-v7";
- device_type = "cpu";
- reg = <0>;
- };
- };
-
- pmu {
- compatible = "arm,cortex-a9-pmu";
- interrupts-extended = <&mpic 3>;
- };
-
- soc {
- #address-cells = <2>;
- #size-cells = <1>;
- controller = <&mbusc>;
- interrupt-parent = <&mpic>;
- pcie-mem-aperture = <0xf8000000 0x7e00000>;
- pcie-io-aperture = <0xffe00000 0x100000>;
-
- devbus_bootcs: devbus-bootcs {
- compatible = "marvell,mvebu-devbus";
- reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
- ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- devbus_cs0: devbus-cs0 {
- compatible = "marvell,mvebu-devbus";
- reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
- ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- devbus_cs1: devbus-cs1 {
- compatible = "marvell,mvebu-devbus";
- reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
- ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- devbus_cs2: devbus-cs2 {
- compatible = "marvell,mvebu-devbus";
- reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
- ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- devbus_cs3: devbus-cs3 {
- compatible = "marvell,mvebu-devbus";
- reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
- ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- internal-regs {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
-
- rtc: rtc@10300 {
- compatible = "marvell,orion-rtc";
- reg = <0x10300 0x20>;
- interrupts = <50>;
- };
-
- i2c0: i2c@11000 {
- compatible = "marvell,mv64xxx-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <31>;
- timeout-ms = <1000>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- i2c1: i2c@11100 {
- compatible = "marvell,mv64xxx-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <32>;
- timeout-ms = <1000>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- uart0: serial@12000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x12000 0x100>;
- reg-shift = <2>;
- interrupts = <41>;
- reg-io-width = <1>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- uart1: serial@12100 {
- compatible = "snps,dw-apb-uart";
- reg = <0x12100 0x100>;
- reg-shift = <2>;
- interrupts = <42>;
- reg-io-width = <1>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- pinctrl: pin-ctrl@18000 {
- reg = <0x18000 0x38>;
- };
-
- coredivclk: corediv-clock@18740 {
- compatible = "marvell,armada-370-corediv-clock";
- reg = <0x18740 0xc>;
- #clock-cells = <1>;
- clocks = <&mainpll>;
- clock-output-names = "nand";
- };
-
- mbusc: mbus-controller@20000 {
- compatible = "marvell,mbus-controller";
- reg = <0x20000 0x100>, <0x20180 0x20>,
- <0x20250 0x8>;
- };
-
- mpic: interrupt-controller@20a00 {
- compatible = "marvell,mpic";
- #interrupt-cells = <1>;
- #size-cells = <1>;
- interrupt-controller;
- msi-controller;
- };
-
- coherencyfab: coherency-fabric@20200 {
- compatible = "marvell,coherency-fabric";
- reg = <0x20200 0xb0>, <0x21010 0x1c>;
- };
-
- timer: timer@20300 {
- reg = <0x20300 0x30>, <0x21040 0x30>;
- interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
- };
-
- watchdog: watchdog@20300 {
- reg = <0x20300 0x34>, <0x20704 0x4>;
- };
-
- cpurst: cpurst@20800 {
- compatible = "marvell,armada-370-cpu-reset";
- reg = <0x20800 0x8>;
- };
-
- pmsu: pmsu@22000 {
- compatible = "marvell,armada-370-pmsu";
- reg = <0x22000 0x1000>;
- };
-
- usb0: usb@50000 {
- compatible = "marvell,orion-ehci";
- reg = <0x50000 0x500>;
- interrupts = <45>;
- status = "disabled";
- };
-
- usb1: usb@51000 {
- compatible = "marvell,orion-ehci";
- reg = <0x51000 0x500>;
- interrupts = <46>;
- status = "disabled";
- };
-
- eth0: ethernet@70000 {
- reg = <0x70000 0x4000>;
- interrupts = <8>;
- clocks = <&gateclk 4>;
- status = "disabled";
- };
-
- mdio: mdio@72004 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,orion-mdio";
- reg = <0x72004 0x4>;
- clocks = <&gateclk 4>;
- };
-
- eth1: ethernet@74000 {
- reg = <0x74000 0x4000>;
- interrupts = <10>;
- clocks = <&gateclk 3>;
- status = "disabled";
- };
-
- sata: sata@a0000 {
- compatible = "marvell,armada-370-sata";
- reg = <0xa0000 0x5000>;
- interrupts = <55>;
- clocks = <&gateclk 15>, <&gateclk 30>;
- clock-names = "0", "1";
- status = "disabled";
- };
-
- nand_controller: nand-controller@d0000 {
- compatible = "marvell,armada370-nand-controller";
- reg = <0xd0000 0x54>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <113>;
- clocks = <&coredivclk 0>;
- status = "disabled";
- };
-
- sdio: mvsdio@d4000 {
- compatible = "marvell,orion-sdio";
- reg = <0xd4000 0x200>;
- interrupts = <54>;
- clocks = <&gateclk 17>;
- bus-width = <4>;
- cap-sdio-irq;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- status = "disabled";
- };
- };
-
- spi0: spi@10600 {
- reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
- <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
- <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
- <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
- <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
- <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
- <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
- <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
- <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <0>;
- interrupts = <30>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- spi1: spi@10680 {
- reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x28>, /* control */
- <MBUS_ID(0x01, 0x1a) 0 0xffffffff>, /* CS0 */
- <MBUS_ID(0x01, 0x5a) 0 0xffffffff>, /* CS1 */
- <MBUS_ID(0x01, 0x9a) 0 0xffffffff>, /* CS2 */
- <MBUS_ID(0x01, 0xda) 0 0xffffffff>, /* CS3 */
- <MBUS_ID(0x01, 0x1b) 0 0xffffffff>, /* CS4 */
- <MBUS_ID(0x01, 0x5b) 0 0xffffffff>, /* CS5 */
- <MBUS_ID(0x01, 0x9b) 0 0xffffffff>, /* CS6 */
- <MBUS_ID(0x01, 0xdb) 0 0xffffffff>; /* CS7 */
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <1>;
- interrupts = <92>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
- };
-
- clocks {
- /* 2 GHz fixed main PLL */
- mainpll: mainpll {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <2000000000>;
- };
- };
- };
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