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-rw-r--r--dts/src/arm/gemini-sq201.dts159
1 files changed, 159 insertions, 0 deletions
diff --git a/dts/src/arm/gemini-sq201.dts b/dts/src/arm/gemini-sq201.dts
index e5cf9d1..3787cf3 100644
--- a/dts/src/arm/gemini-sq201.dts
+++ b/dts/src/arm/gemini-sq201.dts
@@ -55,6 +55,75 @@
};
};
+ mdio0: mdio {
+ compatible = "virtual,mdio-gpio";
+ /* Uses MDC and MDIO */
+ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
+ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* This is a Marvell 88E1111 ethernet transciever */
+ phy0: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
+
+ spi {
+ compatible = "spi-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* Check pin collisions */
+ gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+ gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
+ num-chipselects = <1>;
+
+ switch@0 {
+ compatible = "vitesse,vsc7395";
+ reg = <0>;
+ /* Specified for 2.5 MHz or below */
+ spi-max-frequency = <2500000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ };
+ vsc: port@6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <&gmac1>;
+ phy-mode = "rgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
+ };
+
+
soc {
flash@30000000 {
/*
@@ -108,6 +177,7 @@
/*
* gpio0fgrp cover line 18 used by reset button
* gpio0ggrp cover line 20 used by info LED
+ * gpio0hgrp cover line 21, 22 used by MDIO for Marvell PHY
* gpio0kgrp cover line 31 used by USB LED
*/
gpio0_default_pins: pinctrl-gpio0 {
@@ -115,9 +185,76 @@
function = "gpio0";
groups = "gpio0fgrp",
"gpio0ggrp",
+ "gpio0hgrp",
"gpio0kgrp";
};
};
+ /*
+ * gpio0dgrp cover lines used by the SPI
+ * to the Vitesse G5x chip.
+ */
+ gpio1_default_pins: pinctrl-gpio1 {
+ mux {
+ function = "gpio1";
+ groups = "gpio1dgrp";
+ };
+ };
+ pinctrl-gmii {
+ mux {
+ function = "gmii";
+ groups = "gmii_gmac0_grp", "gmii_gmac1_grp";
+ };
+ /* Settings come from memory dump in PLATO */
+ conf0 {
+ pins = "V8 GMAC0 RXDV";
+ skew-delay = <0>;
+ };
+ conf1 {
+ pins = "Y7 GMAC0 RXC";
+ skew-delay = <15>;
+ };
+ conf2 {
+ pins = "T8 GMAC0 TXEN";
+ skew-delay = <7>;
+ };
+ conf3 {
+ pins = "U8 GMAC0 TXC";
+ skew-delay = <10>;
+ };
+ conf4 {
+ pins = "T10 GMAC1 RXDV";
+ skew-delay = <7>;
+ };
+ conf5 {
+ pins = "Y11 GMAC1 RXC";
+ skew-delay = <8>;
+ };
+ conf6 {
+ pins = "W11 GMAC1 TXEN";
+ skew-delay = <7>;
+ };
+ conf7 {
+ pins = "V11 GMAC1 TXC";
+ skew-delay = <5>;
+ };
+ conf8 {
+ /* The data lines all have default skew */
+ pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1",
+ "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3",
+ "T7 GMAC0 TXD0", "U6 GMAC0 TXD1",
+ "V7 GMAC0 TXD2", "U7 GMAC0 TXD3",
+ "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1",
+ "T11 GMAC1 RXD2", "W12 GMAC1 RXD3",
+ "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1",
+ "W10 GMAC1 TXD2", "T9 GMAC1 TXD3";
+ skew-delay = <7>;
+ };
+ /* Set up drive strength on GMAC0 and GMAC1 to 16 mA */
+ conf9 {
+ groups = "gmii_gmac0_grp", "gmii_gmac1_grp";
+ drive-strength = <16>;
+ };
+ };
};
};
@@ -132,6 +269,11 @@
pinctrl-0 = <&gpio0_default_pins>;
};
+ gpio1: gpio@4e000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio1_default_pins>;
+ };
+
pci@50000000 {
status = "okay";
interrupt-map-mask = <0xf800 0 0 7>;
@@ -154,6 +296,23 @@
<0x6000 0 0 4 &pci_intc 2>;
};
+ ethernet@60000000 {
+ status = "okay";
+
+ ethernet-port@0 {
+ phy-mode = "rgmii";
+ phy-handle = <&phy0>;
+ };
+ ethernet-port@1 {
+ phy-mode = "rgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+
ata@63000000 {
status = "okay";
};