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-rw-r--r--dts/src/arm/imx6dl.dtsi392
1 files changed, 0 insertions, 392 deletions
diff --git a/dts/src/arm/imx6dl.dtsi b/dts/src/arm/imx6dl.dtsi
deleted file mode 100644
index 008312ee0c..0000000000
--- a/dts/src/arm/imx6dl.dtsi
+++ /dev/null
@@ -1,392 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright 2013 Freescale Semiconductor, Inc.
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include "imx6dl-pinfunc.h"
-#include "imx6qdl.dtsi"
-
-/ {
- aliases {
- i2c3 = &i2c4;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a9";
- device_type = "cpu";
- reg = <0>;
- next-level-cache = <&L2>;
- operating-points = <
- /* kHz uV */
- 996000 1250000
- 792000 1175000
- 396000 1150000
- >;
- fsl,soc-operating-points = <
- /* ARM kHz SOC-PU uV */
- 996000 1175000
- 792000 1175000
- 396000 1175000
- >;
- clock-latency = <61036>; /* two CLK32 periods */
- #cooling-cells = <2>;
- clocks = <&clks IMX6QDL_CLK_ARM>,
- <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
- <&clks IMX6QDL_CLK_STEP>,
- <&clks IMX6QDL_CLK_PLL1_SW>,
- <&clks IMX6QDL_CLK_PLL1_SYS>;
- clock-names = "arm", "pll2_pfd2_396m", "step",
- "pll1_sw", "pll1_sys";
- arm-supply = <&reg_arm>;
- pu-supply = <&reg_pu>;
- soc-supply = <&reg_soc>;
- };
-
- cpu@1 {
- compatible = "arm,cortex-a9";
- device_type = "cpu";
- reg = <1>;
- next-level-cache = <&L2>;
- operating-points = <
- /* kHz uV */
- 996000 1250000
- 792000 1175000
- 396000 1150000
- >;
- fsl,soc-operating-points = <
- /* ARM kHz SOC-PU uV */
- 996000 1175000
- 792000 1175000
- 396000 1175000
- >;
- clock-latency = <61036>; /* two CLK32 periods */
- #cooling-cells = <2>;
- clocks = <&clks IMX6QDL_CLK_ARM>,
- <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
- <&clks IMX6QDL_CLK_STEP>,
- <&clks IMX6QDL_CLK_PLL1_SW>,
- <&clks IMX6QDL_CLK_PLL1_SYS>;
- clock-names = "arm", "pll2_pfd2_396m", "step",
- "pll1_sw", "pll1_sys";
- arm-supply = <&reg_arm>;
- pu-supply = <&reg_pu>;
- soc-supply = <&reg_soc>;
- };
- };
-
- soc {
- ocram: sram@900000 {
- compatible = "mmio-sram";
- reg = <0x00900000 0x20000>;
- clocks = <&clks IMX6QDL_CLK_OCRAM>;
- };
-
- aips1: aips-bus@2000000 {
- iomuxc: iomuxc@20e0000 {
- compatible = "fsl,imx6dl-iomuxc";
- };
-
- pxp: pxp@20f0000 {
- reg = <0x020f0000 0x4000>;
- interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- epdc: epdc@20f4000 {
- reg = <0x020f4000 0x4000>;
- interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- aips2: aips-bus@2100000 {
- i2c4: i2c@21f8000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
- reg = <0x021f8000 0x4000>;
- interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6DL_CLK_I2C4>;
- status = "disabled";
- };
- };
- };
-
- capture-subsystem {
- compatible = "fsl,imx-capture-subsystem";
- ports = <&ipu1_csi0>, <&ipu1_csi1>;
- };
-
- display-subsystem {
- compatible = "fsl,imx-display-subsystem";
- ports = <&ipu1_di0>, <&ipu1_di1>;
- };
-};
-
-&gpio1 {
- gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>,
- <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>,
- <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>,
- <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>,
- <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>,
- <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>,
- <&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
-};
-
-&gpio2 {
- gpio-ranges = <&iomuxc 0 161 8>, <&iomuxc 8 208 8>, <&iomuxc 16 74 1>,
- <&iomuxc 17 73 1>, <&iomuxc 18 72 1>, <&iomuxc 19 71 1>,
- <&iomuxc 20 70 1>, <&iomuxc 21 69 1>, <&iomuxc 22 68 1>,
- <&iomuxc 23 79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>,
- <&iomuxc 28 113 4>;
-};
-
-&gpio3 {
- gpio-ranges = <&iomuxc 0 97 2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
- <&iomuxc 16 81 16>;
-};
-
-&gpio4 {
- gpio-ranges = <&iomuxc 5 136 1>, <&iomuxc 6 145 1>, <&iomuxc 7 150 1>,
- <&iomuxc 8 146 1>, <&iomuxc 9 151 1>, <&iomuxc 10 147 1>,
- <&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>,
- <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16 39 7>,
- <&iomuxc 23 56 1>, <&iomuxc 24 61 7>, <&iomuxc 31 46 1>;
-};
-
-&gpio5 {
- gpio-ranges = <&iomuxc 0 120 1>, <&iomuxc 2 77 1>, <&iomuxc 4 76 1>,
- <&iomuxc 5 47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>,
- <&iomuxc 19 36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>,
- <&iomuxc 22 29 6>, <&iomuxc 28 19 4>;
-};
-
-&gpio6 {
- gpio-ranges = <&iomuxc 0 23 6>, <&iomuxc 6 75 1>, <&iomuxc 7 156 1>,
- <&iomuxc 8 155 1>, <&iomuxc 9 170 1>, <&iomuxc 10 169 1>,
- <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>,
- <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>,
- <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>,
- <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31 78 1>;
-};
-
-&gpio7 {
- gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc 1 201 1>, <&iomuxc 2 196 1>,
- <&iomuxc 3 195 1>, <&iomuxc 4 197 4>, <&iomuxc 8 205 1>,
- <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;
-};
-
-&gpr {
- ipu1_csi0_mux {
- compatible = "video-mux";
- mux-controls = <&mux 0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- ipu1_csi0_mux_from_mipi_vc0: endpoint {
- remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- ipu1_csi0_mux_from_mipi_vc1: endpoint {
- remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
- };
- };
-
- port@2 {
- reg = <2>;
-
- ipu1_csi0_mux_from_mipi_vc2: endpoint {
- remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
- };
- };
-
- port@3 {
- reg = <3>;
-
- ipu1_csi0_mux_from_mipi_vc3: endpoint {
- remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
- };
- };
-
- port@4 {
- reg = <4>;
-
- ipu1_csi0_mux_from_parallel_sensor: endpoint {
- };
- };
-
- port@5 {
- reg = <5>;
-
- ipu1_csi0_mux_to_ipu1_csi0: endpoint {
- remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
- };
- };
- };
-
- ipu1_csi1_mux {
- compatible = "video-mux";
- mux-controls = <&mux 1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- ipu1_csi1_mux_from_mipi_vc0: endpoint {
- remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- ipu1_csi1_mux_from_mipi_vc1: endpoint {
- remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
- };
- };
-
- port@2 {
- reg = <2>;
-
- ipu1_csi1_mux_from_mipi_vc2: endpoint {
- remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
- };
- };
-
- port@3 {
- reg = <3>;
-
- ipu1_csi1_mux_from_mipi_vc3: endpoint {
- remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
- };
- };
-
- port@4 {
- reg = <4>;
-
- ipu1_csi1_mux_from_parallel_sensor: endpoint {
- };
- };
-
- port@5 {
- reg = <5>;
-
- ipu1_csi1_mux_to_ipu1_csi1: endpoint {
- remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
- };
- };
- };
-};
-
-&gpt {
- compatible = "fsl,imx6dl-gpt";
-};
-
-&hdmi {
- compatible = "fsl,imx6dl-hdmi";
-};
-
-&ipu1_csi1 {
- ipu1_csi1_from_ipu1_csi1_mux: endpoint {
- remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
- };
-};
-
-&ldb {
- clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
- <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
- <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
- clock-names = "di0_pll", "di1_pll",
- "di0_sel", "di1_sel",
- "di0", "di1";
-};
-
-&mipi_csi {
- port@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi_vc0_to_ipu1_csi0_mux: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
- };
-
- mipi_vc0_to_ipu1_csi1_mux: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
- };
- };
-
- port@2 {
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi_vc1_to_ipu1_csi0_mux: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
- };
-
- mipi_vc1_to_ipu1_csi1_mux: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
- };
- };
-
- port@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi_vc2_to_ipu1_csi0_mux: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
- };
-
- mipi_vc2_to_ipu1_csi1_mux: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
- };
- };
-
- port@4 {
- reg = <4>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi_vc3_to_ipu1_csi0_mux: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
- };
-
- mipi_vc3_to_ipu1_csi1_mux: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
- };
- };
-};
-
-&mux {
- mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
- <0x34 0x00000038>, /* IPU_CSI1_MUX */
- <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
- <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
- <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
- <0x28 0x00000003>, /* DCIC1_MUX_CTL */
- <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
-};
-
-&vpu {
- compatible = "fsl,imx6dl-vpu", "cnm,coda960";
-};
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-19 04:10:54 +0000