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Diffstat (limited to 'dts/src/arm/imx6qdl.dtsi')
-rw-r--r--dts/src/arm/imx6qdl.dtsi18
1 files changed, 15 insertions, 3 deletions
diff --git a/dts/src/arm/imx6qdl.dtsi b/dts/src/arm/imx6qdl.dtsi
index fe17a34..b3a77bc 100644
--- a/dts/src/arm/imx6qdl.dtsi
+++ b/dts/src/arm/imx6qdl.dtsi
@@ -4,6 +4,7 @@
// Copyright 2011 Linaro Ltd.
#include <dt-bindings/clock/imx6qdl-clock.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
@@ -279,6 +280,7 @@
ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
num-lanes = <1>;
+ num-viewport = <4>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
@@ -833,6 +835,14 @@
status = "disabled";
};
+ snvs_pwrkey: snvs-powerkey {
+ compatible = "fsl,sec-v4.0-pwrkey";
+ regmap = <&snvs>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ linux,keycode = <KEY_POWER>;
+ wakeup-source;
+ };
+
snvs_lpgpr: snvs-lpgpr {
compatible = "fsl,imx6q-snvs-lpgpr";
};
@@ -918,7 +928,7 @@
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
reg = <0x020ec000 0x4000>;
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_SDMA>,
+ clocks = <&clks IMX6QDL_CLK_IPG>,
<&clks IMX6QDL_CLK_SDMA>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
@@ -1129,14 +1139,16 @@
reg = <0x021ac000 0x4000>;
};
- mmdc0: mmdc@21b0000 { /* MMDC0 */
+ mmdc0: memory-controller@21b0000 { /* MMDC0 */
compatible = "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
};
- mmdc1: mmdc@21b4000 { /* MMDC1 */
+ mmdc1: memory-controller@21b4000 { /* MMDC1 */
+ compatible = "fsl,imx6q-mmdc";
reg = <0x021b4000 0x4000>;
+ status = "disabled";
};
weim: weim@21b8000 {